Upgrading exception processing method and device

Abstract

The invention provides an upgrading exception processing method and device, and the method comprises the steps: determining the verification failure of upgrading data of a target processor, and obtaining an exceptional data segment in the upgrading data; detecting the target processor based on the abnormal data segment, and judging whether the abnormal data segment can cause interaction abnormity between the target processor and external equipment or not; in response to the situation that the abnormal data segment does not cause abnormal interaction between the target processor and the external equipment, carrying out rollback on the abnormal data segment to obtain a corresponding first data segment; or, in response to the situation that the abnormal data segment can cause interaction abnormity of the target processor and the external equipment, repairing the abnormal data segment to obtain a second data segment; and upgrading a target processor based on the first data segment or the second data segment. The success rate of processor upgrading can be improved, and normal operation of the processor is ensured.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a method and apparatus for processing upgrade anomalies. Background Art

[0002] In the related art, when a processor upgrade fails, repeated attempts are usually made for repair. However, this repair method does not fundamentally solve the problem of processor upgrade failure, which poses a potential hazard to the normal operation of the processor. Summary of the Invention

[0003] This application aims to at least solve one of the technical problems in the related art to some extent.

[0004] In a first aspect, this application provides a method for processing upgrade anomalies, including: determining that the upgrade data verification of a target processor fails, and obtaining an abnormal data segment in the upgrade data; detecting the target processor based on the abnormal data segment, and determining whether the abnormal data segment will cause abnormal interaction between the target processor and an external device; in response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, rolling back the abnormal data segment to obtain a corresponding first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, repairing the abnormal data segment to obtain a second data segment; upgrading the target processor based on the first data segment or the second data segment.

[0005] In an implementation, the obtaining of the abnormal data segment in the upgrade data includes: obtaining a data segment with failed verification in the upgrade data as a data segment to be identified; performing level analysis and frequency analysis on the data segment to be identified to obtain the signal level and signal frequency of the signal corresponding to the data segment to be identified; determining whether the signal level meets a first preset condition and whether the signal frequency meets a second preset condition; determining that the signal level does not meet the first preset condition and / or the signal frequency does not meet the second preset condition, performing level calibration and / or frequency calibration on the signal to be identified to obtain a calibrated signal; performing signal verification on the calibrated signal; and determining that the calibrated signal fails the verification, and taking the data segment to be identified as the abnormal data segment.

[0006] In one implementation, detecting the target processor based on the abnormal data segment and determining whether the abnormal data segment will cause abnormal interaction between the target processor and an external device includes: generating setting information based on the abnormal data segment; sending the setting information to the target processor; in response to obtaining feedback information of the target processor, determining whether the abnormal data segment will cause abnormal interaction between the target processor and the external device based on the feedback information; or, in response to not obtaining the feedback information of the target processor, determining that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0007] In one implementation, reverting the abnormal data segment to obtain a corresponding first data segment includes: obtaining at least one historical upgrade data; comparing the historical upgrade data with the abnormal data segment and the at least one historical upgrade data to obtain the first data segment corresponding to the abnormal data segment.

[0008] In one implementation, repairing the abnormal data segment to obtain a second data segment includes: obtaining a second functional block having a coupling relationship with a first functional block corresponding to the abnormal data segment; obtaining a data segment corresponding to the second functional block; combining the abnormal data segment and the data segment corresponding to the second functional block into a first data unit; performing multiple repairs on the first data unit to obtain multiple candidate data units; performing exclusive OR on the multiple candidate data units to obtain a candidate data segment, and verifying the candidate data segment; in response to passing the verification, using the candidate second data segment as the second data segment; or, in response to failing the verification, returning to execute the step of performing multiple repairs on the first data unit to obtain multiple candidate data units.

[0009] In an alternative implementation, each candidate data unit is obtained through the following steps: Step 1: Obtaining a data link signal in the target processor as status data; Step 2: Obtaining a first remainder unit by calculating the remainder of the first data unit based on the status data; Step 3: Performing exclusive OR on the first remainder unit and the first data unit to obtain a second data unit; Step 4: Obtaining a second remainder unit by calculating the remainder of the second data unit based on the status data; Step 5: In response to the second remainder unit being zero, using the second data unit as the candidate data unit; or, in response to the second remainder unit not being zero, performing exclusive OR on the second data unit based on the second remainder unit to obtain a third data unit, and using the third data unit as the new second data unit and returning to execute Step 4.

[0010] In an alternative implementation, the method further includes: obtaining the data position corresponding to the first data unit; after the target processor is upgraded again, obtaining the corresponding target data unit from the newly upgraded data after the re-upgrade based on the data position; performing a functional simulation comparison between the first data unit and the target data unit to obtain functional deviation information; obtaining a target data code from the upgrade data based on the functional deviation information; and using the target data code to replace the corresponding data in the target processor.

[0011] In a second aspect, the present application provides a device for processing upgrade anomalies, the device including: a first processing module configured to determine that the upgrade data verification of the target processor fails and obtain an abnormal data segment in the upgrade data; a second processing module configured to detect the target processor based on the abnormal data segment and determine whether the abnormal data segment will cause abnormal interaction between the target processor and an external device; a third processing module configured to, in response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, roll back the abnormal data segment to obtain a corresponding first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, repair the abnormal data segment to obtain a second data segment; and a fourth processing module configured to upgrade the target processor based on the first data segment or the second data segment.

[0012] In one implementation, the first processing module is configured to: obtain the data segment with failed verification in the upgrade data as a data segment to be identified; perform level analysis and frequency analysis on the data segment to be identified to obtain the signal level and signal frequency of the signal corresponding to the data segment to be identified; determine whether the signal level meets a first preset condition and whether the signal frequency meets a second preset condition; determine that the signal level does not meet the first preset condition and / or the signal frequency does not meet the second preset condition, perform level calibration and / or frequency calibration on the signal to be identified to obtain a calibrated signal; perform signal verification on the calibrated signal; and determine that the calibrated signal fails the verification, and use the data segment to be identified as the abnormal data segment.

[0013] In one implementation, the second processing module is configured to: generate setting information based on the abnormal data segment; send the setting information to the target processor; in response to obtaining the feedback information of the target processor, determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device based on the feedback information; or, in response to not obtaining the feedback information of the target processor, determine that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0014] In one implementation, the third processing module is configured to: obtain at least one piece of historical upgrade data; compare the historical upgrade data with the abnormal data segment and the at least one piece of historical upgrade data to obtain the first data segment corresponding to the abnormal data segment.

[0015] In one implementation, the third processing module is configured to: obtain a second functional block having a coupling relationship with the first functional block corresponding to the abnormal data segment; obtain the data segment corresponding to the second functional block; combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit; perform multiple repairs on the first data unit to obtain multiple candidate data units; perform exclusive OR on the multiple candidate data units to obtain a candidate data segment, and verify the candidate data segment; in response to passing the verification, use the candidate second data segment as the second data segment; or, in response to failing the verification, return to execute the step of performing multiple repairs on the first data unit to obtain multiple candidate data units.

[0016] In one implementation, the third processing module is configured to execute the following steps: Step 1: Obtain the data link signal in the target processor as status data; Step 2: Obtain a first remainder unit by calculating the remainder of the first data unit based on the status data; Step 3: Perform exclusive OR on the first remainder unit and the first data unit to obtain a second data unit; Step 4: Obtain a second remainder unit by calculating the remainder of the second data unit based on the status data; Step 5: In response to the second remainder unit being zero, use the second data unit as the candidate data unit; or, in response to the second remainder unit not being zero, perform exclusive OR on the second data unit based on the second remainder unit to obtain a third data unit, and use the third data unit as the new second data unit and return to execute Step 4.

[0017] In an alternative implementation, the third processing module is further configured to: obtain the data position corresponding to the first data unit; after the target processor is upgraded again, obtain the corresponding target data unit from the newly upgraded data based on the data position; perform functional simulation comparison between the first data unit and the target data unit to obtain functional deviation information; obtain a target data code from the upgrade data based on the functional deviation information; use the target data code to replace the corresponding data in the target processor.

[0018] In a third aspect, the present application provides an electronic device, including: at least one target processor; and a memory communicatively connected to the at least one target processor; wherein the memory stores instructions executable by the at least one target processor, and when the instructions are executed by the at least one target processor, the at least one target processor is enabled to execute the method for handling upgrade exceptions as described in the first aspect.

[0019] In a fourth aspect, the present application provides a computer-readable storage medium for storing instructions that, when executed, implement the method as described in the first aspect.

[0020] In a fifth aspect, the present application provides a computer program product including a computer program that, when executed by a target processor, implements the steps of the method for handling upgrade exceptions as described in the first aspect.

[0021] The method, apparatus, device, and storage medium for handling upgrade exceptions provided by the present application can, when an exception occurs during the upgrade of a target processor, perform a logical function analysis based on an exception data segment to determine whether the exception data segment will cause an interaction exception between the target processor and an external device. If the exception data segment does not cause an interaction exception between the target processor and the external device, the exception data segment is rolled back to obtain a first data segment. If the exception data segment causes an interaction exception between the target processor and the external device, the exception data segment is repaired to obtain a second data segment, and the target processor is upgraded based on the first data segment or the second data segment. This can improve the success rate of processor upgrade and ensure the normal operation of the processor.

[0022] The additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be understood through the practice of the present application. Description of the Drawings

[0023] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, where: Figure 1 is a schematic flowchart of a method for handling upgrade exceptions provided by an embodiment of the present application; Figure 2 is a schematic flowchart of another method for handling upgrade exceptions provided by an embodiment of the present application; Figure 3 is a schematic flowchart of yet another method for handling upgrade exceptions provided by an embodiment of the present application; Figure 4 is a schematic diagram of an analysis process of an exception data segment provided by an embodiment of the present application; Figure 5 is a schematic flowchart of yet another method for handling upgrade exceptions provided by an embodiment of the present application; Figure 6 It is an example diagram of a data segment rollback repair algorithm provided by an embodiment of the present application; Figure 7 It is a schematic flowchart of another method for handling upgrade exceptions provided by an embodiment of the present application; Figure 8 It is a schematic flowchart of an abnormal data repair process provided by an embodiment of the present application; Figure 9 It is an example diagram of another abnormal data repair process provided by an embodiment of the present application; Figure 10 It is a schematic diagram of a solution for handling upgrade exceptions provided by an embodiment of the present application; Figure 11 It is a schematic structural diagram of a device for handling upgrade exceptions provided by an embodiment of the present application; Figure 12 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0024] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as a limitation of the present application.

[0025] The method and device for handling upgrade exceptions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0026] It should be noted that the method for handling upgrade exceptions provided by the embodiments of the present application can be applied to a first processor connected to a target processor.

[0027] Figure 1 It is a schematic flowchart of a method for handling upgrade exceptions provided by an embodiment of the present application. As Figure 1 shown, the method may include but is not limited to the following steps: Step S101: Determine that the upgrade data verification of the target processor fails, and obtain the abnormal data segment in the upgrade data.

[0028] Exemplarily, the above target processor may be a programmable logic controller device.

[0029] Exemplarily, during the data verification in the process of firmware upgrade of the target processor, if it is detected that there is a data error, the abnormal data segment in the upgrade data is obtained according to the position of the error data.

[0030] Exemplarily, taking the target processor as a CPLD (Complex Programmable Logic Device), the first processor can be a CPU (Central Processing Unit) connected to the CPLD.

[0031] Exemplarily, taking the target processor as a CPLD, the CPLD can be the CPLD in the storage device.

[0032] Exemplarily, when the processor detects abnormal data during data verification of the upgrade data, obtain the information related to the abnormal data fed back by the processor, locate the position of the abnormal data through the information related to the abnormal data, check the difference between the abnormal data and the expected data, determine the number of bits of the abnormal data, and extract the abnormal data segment from the upgrade data based on the number of bits of the abnormal data.

[0033] Exemplarily, the data signals between the response bit of the previous signal in the field where the abnormal data appears and the end bit of this data segment can be extracted as the abnormal data segment.

[0034] Step S102: Detect based on the abnormal data segment and determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0035] Exemplarily, taking the target processor as a CPLD, perform a logical function analysis on the abnormal data segment to determine whether the implementation of the function corresponding to the abnormal data segment requires dependence on the pins on the CPLD, or whether the function affected by the abnormal data segment is only an internal function of the CPLD; if the implementation of the function corresponding to the abnormal data segment requires dependence on the pins on the CPLD, it is determined that the abnormal data segment will cause abnormal interaction between the target processor and the external device; if the function affected by the abnormal data segment is only an internal function of the CPLD, it is determined that the abnormal data segment will not cause abnormal interaction between the target processor and the external device.

[0036] Exemplarily, determine the function of the abnormal data in the upgrade data (for example, communication parameters, protocol fields, buffer data), and analyze whether the abnormal data will cause abnormal communication between the processor and the external device in combination with the interface protocol specification (for example, whether it will cause the baud rate configuration to exceed the device support range, CRC checksum generation logic error); by means of simulation, compare the communication data streams of the upgrade data containing abnormal data and the normal upgrade data to determine whether observing the abnormal data will cause phenomena such as communication timeout and frame parsing failure, so as to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0037] Exemplarily, taking the target processor as a programmable logic controller as an example, the logical function of the abnormal data segment is analyzed to determine whether the abnormal data segment causes coupling anomalies between different functional blocks in the processor. If the abnormal data segment causes coupling anomalies between different functional blocks in the processor, it is determined that the abnormal data segment will cause abnormal interaction between the target processor and external devices.

[0038] It should be noted that if two functional blocks are physically connected in hardware logic, the two functional blocks are functional blocks with a coupling relationship; or, if there is data coupling between two functional blocks in the data processing flow, the two functional blocks are functional blocks with a coupling relationship.

[0039] Step S103: In response to the abnormal data segment not causing abnormal interaction between the target processor and external devices, roll back the abnormal data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and external devices, repair the abnormal data segment to obtain a second data segment.

[0040] Exemplarily, in response to the abnormal data segment not causing abnormal interaction between the target processor and external devices, obtain the first data segment corresponding to the abnormal data segment from the historical upgrade data corresponding to the last successful upgrade of the processor.

[0041] In some optional implementations, the historical upgrade data can be stored in a memory connected to the first processor.

[0042] Exemplarily, in response to the abnormal data segment causing abnormal interaction between the target processor and external devices, repair the abnormal data segment to obtain a second data segment.

[0043] Step S104: Upgrade the target processor based on the first data segment or the second data segment.

[0044] Exemplarily, taking the case where the abnormal data segment does not cause abnormal interaction between the target processor and external devices as an example, replace the abnormal data segment in the upgrade data of the target processor with the first data segment, and import the replaced upgrade data into the target processor to upgrade the target processor.

[0045] Exemplarily, taking the case where the abnormal data segment does not cause abnormal interaction between the target processor and external devices as an example, replace the abnormal data segment in the upgrade data of the target processor with the second data segment, and import the replaced upgrade data into the target processor to upgrade the target processor.

[0046] By implementing the embodiments of the present application, when an abnormality occurs in the upgrade of the target processor, logical function analysis can be performed based on the abnormal data segment to determine whether the abnormal data segment will cause abnormal interaction between the target processor and external devices. If the abnormal data segment does not affect the normal interaction between the target processor and external devices, the abnormal data segment is rolled back to obtain the first data segment. If the abnormal data segment affects the normal interaction between the target processor and external devices, the abnormal data segment is repaired to obtain the second data segment, and the target processor is upgraded based on the first data segment or the second data segment. This can improve the success rate of processor upgrade and ensure the normal operation of the processor.

[0047] In some embodiments, when it is determined that an abnormality occurs during the upgrade process of the target processor, the abnormal data in the upgrade data can be analyzed to obtain the abnormal data segment in the upgrade data. As an example, please refer to Figure 2 , Figure 2 which is a schematic flowchart of another method for handling upgrade abnormalities provided by the embodiments of the present application. As shown in Figure 2 , the method may include but is not limited to the following steps: Step S201: Determine that the verification of the upgrade data of the target processor fails, and obtain the data segment with verification failure in the upgrade data as the data segment to be identified.

[0048] Exemplarily, determine that the verification of the upgrade data of the target processor is abnormal, obtain the data position of the abnormal data, and obtain the corresponding data segment from the upgrade data according to the above data position as the data segment to be identified.

[0049] It should be noted that the data position of the abnormal data is at least one, and the data segment to be identified is at least one.

[0050] Step S202: Perform level analysis and frequency analysis on the data segment to be identified to obtain the signal level and signal frequency of the signal corresponding to the data segment to be identified.

[0051] Exemplarily, perform level analysis on the data segment to be identified to obtain the signal level value of the signal corresponding to the data segment to be identified, and perform frequency analysis on the data segment to be identified to obtain the signal frequency of the signal corresponding to the data segment to be identified.

[0052] Step S203: Determine whether the signal level meets the first preset condition, and determine whether the signal frequency meets the second preset condition.

[0053] As an example, taking the signal level including a high level value as an example, if the high level value is less than or equal to the preset high level threshold, it is determined that the level value does not meet the first preset condition.

[0054] As an example, taking the signal level including a low level value as an example, if the low level value is greater than or equal to a preset low level threshold, it is determined that the level value does not meet the first preset condition.

[0055] As an example, taking the signal level including a high level value and a low level value as an example, if the high level value is less than or equal to a preset high level threshold and the low level value is greater than or equal to a preset low level threshold, it is determined that the level value does not meet the first preset condition.

[0056] As an example, if the signal frequency is greater than or equal to a preset frequency threshold, it is determined that the signal frequency does not meet the second preset condition.

[0057] Step S204: Determine that the signal level does not meet the first preset condition and / or the signal frequency does not meet the second preset condition, perform level calibration and / or frequency calibration on the signal to be recognized, and obtain a calibrated signal.

[0058] Exemplarily, determine that the signal level does not meet the first preset condition, perform level calibration on the signal to be recognized, and obtain a calibrated signal.

[0059] Exemplarily, determine that the signal frequency does not meet the second preset condition, perform frequency calibration on the signal to be recognized, and obtain a calibrated signal.

[0060] Exemplarily, determine that the signal level does not meet the first preset condition and the signal frequency does not meet the second preset condition, perform level calibration and frequency calibration on the signal level, and obtain a calibrated signal.

[0061] Step S205: Perform signal verification on the calibrated signal.

[0062] Exemplarily, compare and verify the calibrated signal with a preset standard signal.

[0063] Step S206: Determine that the calibrated signal fails the verification, and regard the data segment to be recognized as an abnormal data segment.

[0064] Step S207: Based on the abnormal data segment, perform detection to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0065] In the embodiments of the present application, step S207 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0066] Step S208: In response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, perform a rollback on the abnormal data segment to obtain a first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, perform a repair on the abnormal data segment to obtain a second data segment.

[0067] In the embodiments of the present application, step S208 can be implemented in any one of the embodiments of the present application, and the embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0068] Step S209: Upgrade the target processor based on the first data segment or the second data segment.

[0069] In the embodiments of the present application, step S209 can be implemented in any one of the embodiments of the present application, and the embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0070] By implementing the embodiments of the present application, when an exception occurs during the upgrade of the target processor, the data segment where the exception occurs can be obtained as the data segment to be recognized, so as to analyze the data segment to be recognized to determine whether the data segment to be recognized is an abnormal data segment that needs to be processed. Thereby reducing the upgrade failure caused by signal quality and timing problems, and improving the processing efficiency of the target processor upgrade exception.

[0071] In some embodiments, information can be sent to the target processor to determine the influence range of the abnormal data segment according to the feedback information of the target processor. As an example, please refer to Figure 3 , Figure 3 is a flowchart of another method for processing upgrade exceptions provided by the embodiments of the present application. As shown in Figure 3 shown, the method can include but is not limited to the following steps: Step S301: Determine that the upgrade data verification of the target processor fails, and obtain the abnormal data segment in the upgrade data.

[0072] In the embodiments of the present application, step S301 can be implemented in any one of the embodiments of the present application, and the embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0073] Step S302: Obtain the setting information corresponding to the abnormal data segment in the upgrade data.

[0074] Step S303: Send the setting information to the target processor.

[0075] Exemplarily, perform resource band identification on the target processor resources occupied by the setting information, determine the unit for the in-band resources of the first processor to interact with the target processor, and send the setting information to the target processor through this unit.

[0076] Step S304: In response to obtaining the feedback information of the target processor, determine whether the abnormal data segment will cause the target processor to interact abnormally with external devices based on the feedback information; or, in response to not obtaining the feedback information of the target processor, determine that the abnormal data segment will cause the target processor to interact abnormally with external devices.

[0077] It is understandable that after the target processor receives the setting information, if the target processor can recognize the setting information, it will feedback corresponding feedback information, which includes the affected pins and the execution status of related functions judged by the target processor in combination with the pin signal status; if the unit that receives the feedback information is the same as the unit that sends the setting information, it is determined that the abnormal data segment will not cause abnormal interaction between the target processor and the external device; if the unit that receives the feedback information is different from the unit that sends the setting information, it is determined that the abnormal data segment will cause abnormal interaction between the target processor and the external device; if the target processor cannot recognize the setting information, it will not feedback corresponding feedback information, which means that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0078] Step S305: In response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, roll back the abnormal data segment to obtain a first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, repair the abnormal data segment to obtain a second data segment.

[0079] In the embodiments of the present application, step S305 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not limit this and will not elaborate further.

[0080] Step S306: Upgrade the target processor based on the first data segment or the second data segment.

[0081] In the embodiments of the present application, step S306 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not limit this and will not elaborate further.

[0082] By implementing the embodiments of the present application, the influence range of the abnormal data segment can be determined according to the feedback of the target processor on the setting information, and corresponding processing can be performed according to the influence range, which can improve the processing efficiency of abnormal target processor upgrades.

[0083] As an example, please refer to Figure 4 , Figure 4 which is a schematic diagram of an abnormal data segment analysis process provided by the embodiments of the present application. As shown in Figure 4 , when an error occurs during the verification process, key error information is extracted and recognized. After retrieving and recognizing the error code set for the verified error code, the impact of the resulting error code point on the overall function can be confirmed.

[0084] In one implementation, when the abnormal data segment only affects the implementation of the corresponding target function, the abnormal data segment can be rolled back. As an example, please refer to Figure 5 ,Figure 5 It is a schematic flowchart of another method for handling upgrade exceptions provided by an embodiment of the present application. As Figure 5 shown, the method may include but is not limited to the following steps: Step S501: Determine that the upgrade data verification of the target processor fails, and obtain the abnormal data segment in the upgrade data.

[0085] In the embodiments of the present application, step S501 can be implemented in any one of the embodiments of the present application, and the embodiments of the present application do not limit this and will not be elaborated further.

[0086] Step S502: Based on the abnormal data segment, detect whether the abnormal data segment will cause abnormal interaction between the target processor and external devices.

[0087] In the embodiments of the present application, step S502 can be implemented in any one of the embodiments of the present application, and the embodiments of the present application do not limit this and will not be elaborated further.

[0088] Step S503: In response to the abnormal data segment not causing abnormal interaction between the target processor and external devices, obtain at least one piece of historical upgrade data.

[0089] Exemplarily, in response to the abnormal data segment not causing abnormal interaction between the target processor and external devices, obtain the historical upgrade data used during at least one historical upgrade process of the target processor.

[0090] Step S504: Compare the historical upgrade data with the abnormal data segment and at least one piece of historical upgrade data to obtain the first data segment corresponding to the abnormal data segment.

[0091] Exemplarily, taking the target processor as a CPLD as an example, according to the pins corresponding to the abnormal data segment and the corresponding target function, compare with the historical firmware data of the CPLD, select the target historical firmware data that contains the data segment corresponding to the target function most recently, and use the data segment corresponding to the target function in the target historical firmware data as the historical data segment corresponding to the abnormal data segment.

[0092] In some embodiments, the historical upgrade data can be quickly compared with the abnormal data segment and at least one piece of historical upgrade data through hardware acceleration to obtain the historical data segment corresponding to the abnormal data segment, so as to improve the processing efficiency of the abnormal data segment.

[0093] Exemplarily, taking the case where the first processor includes multiple cores as an example, the resource occupancy rates of the multiple cores are sorted, and the core with the lowest current occupancy rate is extracted. This core is used for data verification. The abnormal data segment is used as a retrieval point and compared with the data as an error correction code during data verification. The historical upgrade data is used as the information code for data verification operations. The remainder obtained by dividing the entire information code by the verification code is used as the verification bit in data verification, and the remainder is used as the input for core division processing. The divided core will extract the error code position information corresponding to the remainder after each verification, and obtain the data segment corresponding to the remainder as the historical data segment.

[0094] Step S505: Upgrade the target processor based on the first data segment.

[0095] In the embodiments of the present application, step S505 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0096] By implementing the embodiments of the present application, when the abnormal data segment does not cause abnormal coupling functions in the target processor, the target data segment corresponding to the abnormal data segment in the most recent historical upgrade data can be used to replace the abnormal data segment, so as to upgrade the target processor based on the replaced upgrade data. It can quickly solve the upgrade anomalies with a small impact range and improve the success rate of target processor generation.

[0097] Please refer to Figure 6 , Figure 6 which is an example diagram of a data segment rollback repair algorithm provided by the embodiments of the present application. As Figure 6 shown, if it is confirmed that the current data segment will affect the configuration of a single CPLD IO pin and the realization of the target function, but will not be coupled to other function points, the local rollback algorithm is adopted to automatically roll back the data segment corresponding to the target function to the previous version, and while masking the error code point, verification is performed to ensure that the verification error code will not cause an abnormality in CPLD upgrade.

[0098] In one implementation, when the abnormal data segment affects the coupling between different functions, the abnormal data segment can be repaired. As an example, please refer to Figure 7 , Figure 7 which is a flowchart of another method for handling upgrade anomalies provided by the embodiments of the present application. As Figure 7 shown, the method may include but is not limited to the following steps: Step S701: Determine that the upgrade data verification of the target processor fails, and obtain the abnormal data segment in the upgrade data.

[0099] In the embodiments of the present application, step S701 can be implemented in any one of the embodiments of the present application, and the embodiments of the present application do not limit this and will not elaborate further.

[0100] Step S702: Detect based on the abnormal data segment, and determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0101] In the embodiments of the present application, step S702 can be implemented in any one of the embodiments of the present application, and the embodiments of the present application do not limit this and will not elaborate further.

[0102] Step S703: In response to the abnormal data segment causing abnormal interaction between the target processor and the external device, obtain the second functional block that has a coupling relationship with the first functional block corresponding to the abnormal data segment in the upgrade data.

[0103] Wherein, in the embodiments of the present application, the above-mentioned second functional block is at least one.

[0104] Step S704: Obtain the data segment corresponding to the second functional block.

[0105] Step S705: Combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit.

[0106] Exemplarily, the first functional block and the second functional block are combined in the form of a function package to combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit.

[0107] Step S706: Repair the first data unit multiple times to obtain multiple candidate data units.

[0108] Exemplarily, use the check code pre-embedded in the upgrade data to repair the first data unit to obtain multiple candidate data units.

[0109] In one implementation, each candidate data unit is obtained through the following steps: Step A1: Obtain the data link signal in the target processor as status data.

[0110] Step A2: Obtain the first remainder unit by obtaining the remainder of the first data unit based on the status data.

[0111] Step A3: XOR the first remainder unit with the first data unit to obtain a second data unit.

[0112] Step A4: Obtain the second remainder unit by obtaining the remainder of the second data unit based on the status data.

[0113] Step A5: In response to the second remainder unit being zero, use the second data unit as the candidate data unit. Alternatively, in response to the second remainder unit not being zero, perform an exclusive OR operation on the second data unit based on the second remainder unit to obtain a third data unit, and return the third data unit as the new second data unit to execute Step A4.

[0114] Step S707: Perform an exclusive OR operation on multiple candidate data units to obtain a candidate second data segment.

[0115] Exemplarily, perform an exclusive OR operation on the data codes at the same positions in multiple candidate data units to obtain a candidate repair data unit.

[0116] Step S708: In response to the verification passing, use the candidate second data segment as the second data segment; or, in response to the verification failing, return to execute the step of performing multiple repairs on the first data unit to obtain multiple candidate data units.

[0117] Exemplarily, use the candidate repair data unit to replace the corresponding data in the upgrade data, and perform data verification on the new upgrade data obtained after replacement. If the data verification passes, it is determined that the repair is successful; if the data verification fails, return to execute Step S707.

[0118] Step S709: Upgrade the target processor based on the second data segment.

[0119] In the embodiments of the present application, Step S709 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0120] By implementing the embodiments of the present application, when an abnormal data segment affects the coupling between different functions of the target processor, the abnormal data segment can be repaired. Then, upgrade the target processor based on the repaired data segment. This can improve the success rate of upgrading the target processor.

[0121] As an example, please refer to Figure 8 , Figure 8 which is a schematic diagram of an abnormal data repair process provided by the embodiments of the present application. As shown in Figure 8 , when it is confirmed that the error code will affect the function of a single IO pin and will be coupled to the entire functional module, the error code can be repeatedly repaired on the basis of CRC verification. After each repair is completed, perform a measurement on the repair result until no abnormality occurs during the measurement process. Then, perform an upgrade based on the upgrade data after the repair is completed. And record the abnormal situations that occur during the measurement process. After the recording is completed, uniformly integrate the current recorded value and the repair content into the repair factor of the CPLD unit, and execute the loop of the functional module again until no abnormality occurs during the measurement process, then the loop verification process is completed.

[0122] In some embodiments, the above method may further include the following steps: obtaining the data position corresponding to the first data unit; after the CPLD is upgraded again, obtaining the corresponding target data unit from the newly upgraded data after the re-upgrade based on the data position; performing a functional simulation comparison between the first data unit and the target data unit to obtain functional deviation information; obtaining the target data code from the upgrade data based on the functional deviation information; and replacing the corresponding data in the target processor based on the target data code.

[0123] Exemplarily, after the repair is completed, record the start position and end position of the error code unit. According to the start position and end position, compare the error code units before and after modification to obtain the repair point information of the current error code unit, and save the repair point information. After the next successful upgrade of the target processor, obtain the corresponding target data code from the upgrade data used for the successful upgrade according to the above repair point information, perform a functional simulation operation on the data code and the error code inside the target processor to obtain the target register with different register assignments and the corresponding target data code position, obtain the corresponding target data code from the upgrade data according to the target data code position, generate a data patch based on the target data code, and import the data patch into the target processor.

[0124] In some embodiments, the above method further includes: obtaining coupling function change information; decoupling the first functional block and the second functional block based on the coupling function change information.

[0125] Exemplarily, for the change in the coupling function involved in the repair, decouple the repaired functional block, combine the functional blocks involved in the change in the overall repaired data code, combine the functional blocks not involved in the change during the repair process, and place the repaired error code unit and the functional block involved in the change at the forefront of the storage address in the storage unit.

[0126] In one implementation, the data patch can be generated based on the target data code through the following steps: first, split the data code at the abnormal position and the data code corresponding to the coupling function in the target data code to obtain the abnormal unit module and the coupling function module. Each module includes a position code for indicating the position of the data code to be replaced and the modified data code, and integrate the two modules to generate a data patch and import it into the upgrade module of the target processor to repair the target processor.

[0127] By implementing the embodiments of the present application, after the target processor is upgraded again, the change in the data code during the repair process of the abnormal data segment can be repaired to ensure the stable operation of the processor.

[0128] As an example, please refer to Figure 9 , Figure 9 is an example diagram of another abnormal data repair process provided by the embodiments of the present application. As shown in Figure 9As shown in the figure, there are differences in the functional implementation of the CPLD program obtained through cyclic redundancy check compared with the previous one. Through the error location recording and analysis algorithm, the repair points in the current cyclic redundancy check and rollback check processes are recorded. After the next successful CPLD upgrade, the modified positions of the CPLD repaired this time are improved in the form of patches. Finally, the modified CPLD is consistent with the normal CPLD in terms of function and implementation method, ensuring the normal operation of the storage device.

[0129] As an example, please refer to Figure 10 , Figure 10 which is a schematic diagram of a processing solution for upgrade exceptions provided by an embodiment of the present application. As Figure 10 shown, for the processor upgrade failure caused by verification failure, first, through the error code analysis of the verification failure process, it is judged whether the error code affects other logical functions of the processor except the failure location. If it only affects a single function at the failure location, the data at the error code location is rolled back to the previous version through the rollback algorithm for function repair. If it is judged that other logical functions are affected, through the cyclic redundancy check algorithm, the functions coupled in phase with the function corresponding to the error code are repaired together. After the repair is completed, the current upgrade can proceed normally; and through the error location recording and analysis algorithm, the verification and repair points are recorded. After the next successful CPLD upgrade, the modified positions of the CPLD repaired this time are repaired in the form of patches, so as to ensure that there is no difference in function and reliability between the final CPLD version and the normal version.

[0130] Please refer to Figure 11 , Figure 11 which is a schematic structural diagram of a processing device for upgrade exceptions provided by an embodiment of the present application. As Figure 11 shown, the device 1100 includes: a first processing module 1101, configured to determine that the upgrade data verification of the target processor fails and obtain an abnormal data segment in the upgrade data; a second processing module 1102, configured to detect based on the abnormal data segment and judge whether the abnormal data segment will cause the target processor to interact abnormally with an external device; a third processing module 1103, configured to, in response to the abnormal data segment not causing the target processor to interact abnormally with the external device, roll back the abnormal data segment to obtain a corresponding first data segment; or, in response to the abnormal data segment causing the target processor to interact abnormally with the external device, repair the abnormal data segment to obtain a second data segment; a fourth processing module 1104, configured to upgrade the target processor based on the first data segment or the second data segment.

[0131] In one implementation, the first processing module 1101 is configured to: obtain the data segment with failed verification in the upgrade data as the data segment to be recognized; perform level analysis and frequency analysis on the data segment to be recognized, and obtain the signal level and signal frequency of the signal corresponding to the data segment to be recognized; determine whether the signal level meets a first preset condition, and determine whether the signal frequency meets a second preset condition; determine that the signal level does not meet the first preset condition and / or the signal frequency does not meet the second preset condition, perform level calibration and / or frequency calibration on the signal to be recognized, and obtain a calibrated signal; perform signal verification on the calibrated signal; determine that the calibrated signal fails the verification, and use the data segment to be recognized as the abnormal data segment.

[0132] In one implementation, the second processing module 1102 is configured to: generate setting information based on the abnormal data segment; send the setting information to the target processor; in response to obtaining the feedback information of the target processor, determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device based on the feedback information; or, in response to not obtaining the feedback information of the target processor, determine that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0133] In one implementation, the third processing module 1103 is configured to: obtain at least one historical upgrade data; compare the historical upgrade data with the abnormal data segment and the at least one historical upgrade data to obtain the first data segment corresponding to the abnormal data segment.

[0134] In one implementation, the third processing module 1103 is configured to: obtain a second functional block having a coupling relationship with the first functional block corresponding to the abnormal data segment in the upgrade data; obtain the data segment corresponding to the second functional block; combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit; obtain the data link signal in the target processor as the status data; perform multiple repairs on the first data unit based on the status data to obtain multiple candidate data units; perform exclusive OR on the multiple candidate data units to obtain a candidate data segment, and verify the candidate data segment; in response to passing the verification, use the candidate second data segment as the second data segment; or, in response to failing the verification, return to execute the step of performing multiple repairs on the first data unit to obtain multiple candidate data units.

[0135] In an alternative implementation, the third processing module 1103 is configured to perform the following steps: Step 1: Obtain a data link signal in the target processor as status data; Step 2: Obtain a first remainder unit by calculating the remainder of the first data unit based on the status data; Step 3: Exclusive-OR the first remainder unit with the first data unit to obtain a second data unit; Step 4: Obtain a second remainder unit by calculating the remainder of the second data unit based on the status data; Step 5: In response to the second remainder unit being zero, use the second data unit as a candidate data unit; or, in response to the second remainder unit not being zero, exclusive-OR the second data unit based on the second remainder unit to obtain a third data unit, and return the third data unit as the new second data unit to execute Step 4.

[0136] In an alternative implementation, the third processing module 1103 is further configured to: obtain the data position corresponding to the first data unit; after the target processor is upgraded again, obtain the corresponding target data unit from the newly upgraded data after the re-upgrade based on the data position; obtain function deviation information based on functional simulation and comparison between the first data unit and the target data unit; obtain a target data code from the upgrade data based on the function deviation information; and use the target data code to replace the corresponding data in the target processor.

[0137] Through the device according to the embodiments of the present application, when an abnormality occurs during the upgrade of the target processor, logical function analysis can be performed based on the abnormal data segment to determine whether the abnormal data segment will cause the target processor to interact abnormally with external devices. If the abnormal data segment does not cause the target processor to interact abnormally with external devices, the abnormal data segment is rolled back to obtain a first data segment. If the abnormal data segment causes the target processor to interact abnormally with external devices, the abnormal data segment is repaired to obtain a second data segment, and the target processor is upgraded based on the first data segment or the second data segment. This can improve the success rate of processor upgrade and ensure the normal operation of the processor.

[0138] It should be noted that the foregoing explanation of the embodiments of the method for handling upgrade abnormalities also applies to the device for handling upgrade abnormalities in this embodiment, and will not be elaborated here.

[0139] To implement the above embodiments, the present application also proposes an electronic device. Please refer to Figure 12 , Figure 12 which is a schematic structural diagram of the electronic device provided by the embodiments of the present application. As Figure 12 shown, the electronic device 1200 includes: a target processor 1201, and a memory 1202 communicatively connected to the target processor 1201; the memory 1202 stores computer-executable instructions; the target processor 1201 executes the computer-executable instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0140] To implement the above embodiments, the present application further provides a computer-readable storage medium storing computer-executable instructions, which are used to implement the method provided in the foregoing embodiments when executed by a target processor.

[0141] To implement the above embodiments, the present application further provides a computer program product including a computer program, which implements the method provided in the foregoing embodiments when executed by a target processor.

[0142] Wherein, in the description of the present application, unless otherwise specified, " / " means "or". For example, A / B may mean A or B; herein, "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone.

[0143] In the description of the foregoing embodiments, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without conflict, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0144] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0145] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a customized logic function or process. The scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0146] The logic and / or steps represented in the flowchart or otherwise described herein can, for example, be considered as a definable sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a target processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in conjunction with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: electrical connection parts with one or more wirings (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber devices, and portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing if necessary, and then stored in a computer memory.

[0147] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or combinations thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0148] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above-described embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0149] In addition, each functional unit in various embodiments of the present application may be integrated into one processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0150] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A method for handling upgrade exceptions, characterized in that, Including: Determine that the upgrade data verification of the target processor fails, and obtain the abnormal data segment in the upgrade data; Detect the target processor based on the abnormal data segment, and determine whether the abnormal data segment will cause abnormal interaction between the target processor and external devices; In response to the abnormal data segment not causing abnormal interaction between the target processor and external devices, roll back the abnormal data segment to obtain the corresponding first data segment; Alternatively, in response to the abnormal data segment causing abnormal interaction between the target processor and external devices, repair the abnormal data segment to obtain a second data segment; Upgrade the target processor based on the first data segment or the second data segment.

2. The method according to claim 1, characterized in that The obtaining the abnormal data segment in the upgrade data includes: Obtain the data segment with failed verification in the upgrade data as the data segment to be identified; Perform level analysis and frequency analysis on the data segment to be identified, and obtain the signal level and signal frequency of the signal corresponding to the data segment to be identified; Determine whether the signal level meets a first preset condition, and determine whether the signal frequency meets a second preset condition; Determine that the signal level does not meet the first preset condition and / or the signal frequency does not meet the second preset condition, perform level calibration and / or frequency calibration on the signal to be identified, and obtain a calibrated signal; Perform signal verification on the calibrated signal; Determine that the calibrated signal fails the verification, and use the data segment to be identified as the abnormal data segment.

3. The method according to claim 1, characterized in that, The detecting the target processor based on the abnormal data segment and determining whether the abnormal data segment will cause abnormal interaction between the target processor and external devices includes: Generate setting information based on the abnormal data segment; Send the setting information to the target processor; In response to obtaining the feedback information of the target processor, determine whether the abnormal data segment will cause abnormal interaction between the target processor and external devices based on the feedback information; or, in response to not obtaining the feedback information of the target processor, determine that the abnormal data segment will cause abnormal interaction between the target processor and external devices.

4. The method according to claim 1, characterized in that, The rolling back the abnormal data segment to obtain the corresponding first data segment includes: Obtain at least one historical upgrade data; Compare the historical upgrade data with the abnormal data segment and the at least one historical upgrade data, and obtain the first data segment corresponding to the abnormal data segment.

5. The method according to claim 1, wherein The repairing the abnormal data segment to obtain a second data segment includes: Obtain a second functional block that has a coupling relationship with the first functional block corresponding to the abnormal data segment; Obtain the data segment corresponding to the second functional block; Combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit; Repair the first data unit multiple times to obtain multiple candidate data units; Perform exclusive OR on the multiple candidate data units to obtain a candidate data segment, and verify the candidate data segment; In response to successful verification, use the candidate data segment as the second data segment; or, in response to failed verification, return to the step of performing multiple repairs on the first data unit to obtain multiple candidate data units.

6. The method according to claim 5, characterized in that, Each of the candidate data units is obtained through the following steps: Step 1: Obtain the data link signal in the target processor as status data; Step 2: Calculate the remainder of the first data unit based on the status data to obtain a first remainder unit; Step 3: Exclusive-OR the first remainder unit with the first data unit to obtain a second data unit; Step 4: Calculate the remainder of the second data unit based on the status data to obtain a second remainder unit; Step 5: In response to the second remainder unit being zero, use the second data unit as the candidate data unit; or, in response to the second remainder unit not being zero, exclusive-OR the second data unit based on the second remainder unit to obtain a third data unit, and use the third data unit as the new second data unit and return to execute Step 4.

7. The method according to claim 5, wherein The method further includes: Obtain the data position corresponding to the first data unit; After the target processor is upgraded again, obtain the corresponding target data unit from the newly upgraded data based on the data position; Perform functional simulation comparison between the first data unit and the target data unit to obtain functional deviation information; Obtain the target data code from the upgrade data based on the functional deviation information; Use the target data code to replace the corresponding data in the target processor.

8. A processing device for upgrade exceptions, characterized in that, Includes: A first processing module, configured to determine that the upgrade data verification of the target processor fails and obtain the abnormal data segment in the upgrade data; A second processing module, configured to detect the target processor based on the abnormal data segment and determine whether the abnormal data segment will cause abnormal interaction between the target processor and external devices; A third processing module, configured to, in response to the abnormal data segment not causing abnormal interaction between the target processor and external devices, roll back the abnormal data segment to obtain the corresponding first data segment; Or, in response to the abnormal data segment causing abnormal interaction between the target processor and external devices, repair the abnormal data segment to obtain a second data segment; A fourth processing module, configured to upgrade the target processor based on the first data segment or the second data segment.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which when executed by the target processor are used to implement the method according to any one of claims 1 to 7.

10. A computer program product, characterized in that, Includes a computer program, which when executed by a processor implements the method according to any one of claims 1 to 7.

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