Upgrade abnormality processing method and device

Abstract

The present application proposes a method and device for handling upgrade anomalies, wherein the method includes: determining that the upgrade data verification of the target processor fails, obtaining an abnormal data segment in the upgrade data; detecting the target processor based on the abnormal data segment, and judging whether the abnormal data segment will cause abnormal interaction between the target processor and an external device; in response to the abnormal data segment not causing abnormal interaction between the target processor and an external device, rolling back the abnormal data segment to obtain a corresponding first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and an external device, repairing the abnormal data segment to obtain a second data segment; and upgrading the target processor based on the first data segment or the second data segment. This can improve the success rate of processor upgrades and ensure the normal operation of the processor.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and device for handling upgrade anomalies. Background Art

[0002] In the related art, when a processor upgrade fails, it is usually repaired by repeated attempts. This repair method does not fundamentally solve the problem of processor upgrade failure, and brings hidden dangers to the normal operation of the processor. Summary of the Invention

[0003] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0004] In a first aspect, the present application proposes a method for handling upgrade exceptions, the method comprising: determining that upgrade data verification of a target processor has failed, and obtaining an abnormal data segment in the upgrade data; detecting the target processor based on the abnormal data segment, and determining whether the abnormal data segment will cause abnormal interaction between the target processor and an external device; in response to the abnormal data segment not causing abnormal interaction between the target processor and an external device, rolling back the abnormal data segment to obtain a corresponding first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and an external device, repairing the abnormal data segment to obtain a second data segment; and upgrading the target processor based on the first data segment or the second data segment.

[0005] In one implementation, obtaining the abnormal data segment in the upgraded data includes: obtaining the data segment that fails verification in the upgraded data as the data segment to be identified; performing level analysis and frequency analysis on the data segment to be identified to obtain the signal level and signal frequency of the signal to be identified corresponding to the data segment to be identified; judging whether the signal level meets a first preset condition, and judging whether the signal frequency meets a second preset condition; determining that the signal level does not meet the first preset condition and / or the signal frequency does not meet the second preset condition, performing level calibration and / or frequency calibration on the signal to be identified to obtain a calibration signal; performing signal verification on the calibration signal; determining that the calibration signal fails the verification, and treating the data segment to be identified as the abnormal data segment.

[0006] In one implementation, the detecting the target processor based on the abnormal data segment and determining whether the abnormal data segment will cause abnormal interaction between the target processor and an external device includes: generating set information based on the abnormal data segment; sending the set information to the target processor; in response to feedback information obtained from the target processor, determining based on the feedback information whether the abnormal data segment will cause abnormal interaction between the target processor and the external device; or, in response to not obtaining feedback information from the target processor, determining that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0007] In one implementation, rolling back the abnormal data segment to obtain the corresponding first data segment includes: obtaining at least one historical upgrade data; comparing the historical upgrade data with the abnormal data segment and the at least one historical upgrade data to obtain the first data segment corresponding to the abnormal data segment.

[0008] In one implementation, the repairing of the abnormal data segment to obtain the second data segment includes: obtaining a second functional block that is coupled to the first functional block corresponding to the abnormal data segment; obtaining a data segment corresponding to the second functional block; combining the abnormal data segment and the data segment corresponding to the second functional block into a first data unit; repairing the first data unit multiple times to obtain multiple candidate data units; performing XOR on the multiple candidate data units to obtain candidate data segments, and verifying the candidate data segments; in response to passing the verification, using the candidate second data segment as the second data segment; or, in response to failing the verification, returning to the step of repairing the first data unit multiple times to obtain multiple candidate data units.

[0009] In an optional implementation, each candidate data unit is obtained through the following steps: Step 1: Acquire the data link signal in the target processor as status data; Step 2: Calculate the remainder of the first data unit based on the status data to obtain a first remainder unit; Step 3: XOR the first remainder unit with the first data unit to obtain a second data unit; Step 4: Calculate the remainder of the second data unit based on the status data to obtain a second remainder unit; Step 5: In response to the second remainder unit being zero, use the second data unit as the candidate data unit; or, in response to the second remainder unit being not zero, XOR the second data unit based on the second remainder unit to obtain a third data unit, and return the third data unit as a new second data unit to execute step 4.

[0010] In an optional implementation, the method further includes: obtaining the data position corresponding to the first data unit; after the target processor is upgraded again, obtaining the corresponding target data unit from the newly upgraded data based on the data position; performing a functional simulation comparison between the first data unit and the target data unit to obtain functional deviation information; obtaining a target data code from the upgraded data based on the functional deviation information; and using the target data code to replace the corresponding data in the target processor.

[0011] In a second aspect, the present application proposes a device for processing upgrade exceptions, the device comprising: a first processing module, for determining that the upgrade data verification of the target processor has failed, and obtaining an abnormal data segment in the upgrade data; a second processing module, for detecting the target processor based on the abnormal data segment, and determining whether the abnormal data segment will cause abnormal interaction between the target processor and an external device; a third processing module, for rolling back the abnormal data segment in response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, and obtaining a corresponding first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, repairing the abnormal data segment to obtain a second data segment; and a fourth processing module, for upgrading the target processor based on the first data segment or the second data segment.

[0012] In one implementation, the first processing module is used to: obtain a data segment in the upgrade data that fails verification as a data segment to be identified; perform level analysis and frequency analysis on the data segment to be identified to obtain a signal level and signal frequency of a signal to be identified corresponding to the data segment to be identified; determine whether the signal level meets a first preset condition, and determine whether the signal frequency meets a second preset condition; determine that the signal level does not meet the first preset condition and / or the signal frequency does not meet the second preset condition, perform level calibration and / or frequency calibration on the signal to be identified to obtain a calibration signal; perform signal verification on the calibration signal; determine that the calibration signal fails the verification, and use the data segment to be identified as the abnormal data segment.

[0013] In one implementation, the second processing module is used to: generate set information based on the abnormal data segment; send the set information to the target processor; in response to obtaining feedback information from the target processor, determine based on the feedback information whether the abnormal data segment will cause abnormal interaction between the target processor and the external device; or, in response to not obtaining feedback information from the target processor, determine that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0014] In one implementation, the third processing module is configured to: obtain at least one historical upgrade data; and compare the historical upgrade data with the abnormal data segment and the at least one historical upgrade data to obtain the first data segment corresponding to the abnormal data segment.

[0015] In one implementation, the third processing module is used to: obtain a second functional block that is coupled to the first functional block corresponding to the abnormal data segment; obtain a data segment corresponding to the second functional block; combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit; repair the first data unit multiple times to obtain multiple candidate data units; perform XOR on the multiple candidate data units to obtain candidate data segments, and verify the candidate data segments; in response to the verification passing, use the candidate second data segment as the second data segment; or, in response to the verification failing, return to the step of repairing the first data unit multiple times to obtain multiple candidate data units.

[0016] In one implementation, the third processing module is used to perform the following steps: Step 1: Acquire the data link signal in the target processor as status data; Step 2: Calculate the remainder of the first data unit based on the status data to obtain a first remainder unit; Step 3: XOR the first remainder unit with the first data unit to obtain a second data unit; Step 4: Calculate the remainder of the second data unit based on the status data to obtain a second remainder unit; Step 5: In response to the second remainder unit being zero, use the second data unit as the candidate data unit; or, in response to the second remainder unit being not zero, XOR the second data unit based on the second remainder unit to obtain a third data unit, and return the third data unit as a new second data unit to execute step 4.

[0017] In an optional implementation, the third processing module is also used to: obtain the data position corresponding to the first data unit; after the target processor is upgraded again, obtain the corresponding target data unit from the newly upgraded data based on the data position; perform functional simulation comparison between the first data unit and the target data unit to obtain functional deviation information; obtain target data code from the upgraded data based on the functional deviation information; and use the target data code to replace the corresponding data in the target processor.

[0018] In a third aspect, the present application proposes an electronic device comprising: at least one target processor; and a memory communicatively connected to the at least one target processor; wherein the memory stores instructions executable by the at least one target processor, and the instructions are executed by the at least one target processor so that the at least one target processor can execute the method for handling upgraded exceptions as described in the first aspect.

[0019] In a fourth aspect, the present application proposes a computer-readable storage medium for storing instructions, which, when executed, enables the method described in the first aspect to be implemented.

[0020] In a fifth aspect, the present application proposes a computer program product, comprising a computer program, which, when executed by a target processor, implements the steps of the method for handling an upgrade exception as described in the first aspect.

[0021] The upgrade exception processing method, apparatus, device and storage medium provided by the present application can perform a logical function analysis based on the abnormal data segment when an abnormality occurs during the target processor upgrade to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device. If the abnormal data segment does not cause abnormal interaction between the target processor and the external device, the abnormal data segment is rolled back to obtain the first data segment. If the abnormal data segment causes abnormal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain the second data segment, and the target processor is upgraded based on the first data segment or the second data segment. This can improve the success rate of processor upgrades and ensure the normal operation of the processor.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0024] Figure 1 This is a flowchart of a method for handling upgrade exceptions provided in an embodiment of the present application;

[0025] Figure 2 This is a flowchart of another method for handling upgrade exceptions provided in an embodiment of the present application;

[0026] Figure 3 This is a flowchart of another method for handling upgrade exceptions provided in an embodiment of the present application;

[0027] Figure 4 This is a schematic diagram of an abnormal data segment analysis process provided by an embodiment of the present application;

[0028] Figure 5 This is a flowchart of another method for handling upgrade exceptions provided in an embodiment of the present application;

[0029] Figure 6 This is an example diagram of a data segment rollback repair algorithm provided by an embodiment of the present application;

[0030] Figure 7 This is a flowchart of another method for handling upgrade exceptions provided in an embodiment of the present application;

[0031] Figure 8 This is a schematic diagram of an abnormal data repair process provided by an embodiment of the present application;

[0032] Figure 9 This is an example diagram of another abnormal data repair process provided by an embodiment of the present application;

[0033] Figure 10 This is a schematic diagram of a solution for handling upgrade exceptions provided in an embodiment of the present application;

[0034] Figure 11 This is a structural diagram of a device for handling upgrade exceptions provided in an embodiment of the present application;

[0035] Figure 12 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0037] The following describes a method and apparatus for handling upgrade anomalies according to an embodiment of the present application with reference to the accompanying drawings.

[0038] It should be noted that the upgrade exception processing method provided in the embodiment of the present application can be applied to the first processor connected to the target processor.

[0039] Figure 1 This is a flowchart of a method for handling upgrade exceptions provided by an embodiment of the present application. Figure 1 As shown, the method may include but is not limited to the following steps:

[0040] Step S101: determining that the upgrade data verification of the target processor fails, and obtaining an abnormal data segment in the upgrade data.

[0041] Exemplarily, the target processor may be a programmable logic control device.

[0042] For example, when data verification is performed during the firmware upgrade process of the target processor, if a data error is detected, an abnormal data segment in the upgrade data is obtained according to the location of the erroneous data.

[0043] For example, taking the target processor as a CPLD (Complex Programmable Logic Device), the first processor may be a CPU (Central Processing Unit) connected to the CPLD.

[0044] Exemplarily, taking the target processor as a CPLD as an example, the CPLD may be a CPLD in a storage device.

[0045] Exemplarily, when the processor detects abnormal data when performing data verification on the upgraded data, the processor obtains information related to the abnormal data fed back by the processor, locates the position of the abnormal data through the information related to the abnormal data, checks the difference between the abnormal data and the expected data, determines the number of bits of the abnormal data, and extracts the abnormal data segment from the upgraded data based on the number of bits of the abnormal data.

[0046] Exemplarily, the data signal between the response bit of the previous signal of the abnormal data occurrence field and the end bit of the current data segment can be extracted as the abnormal data segment.

[0047] Step S102: performing detection based on the abnormal data segment to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0048] For example, taking the target processor as a CPLD, a logical function analysis is performed on the abnormal data segment to determine whether the implementation of the function corresponding to the abnormal data segment needs to rely on the pins on the CPLD, or whether the function affected by the abnormal data segment is only the internal function of the CPLD; if the implementation of the function corresponding to the abnormal data segment needs to rely on the pins on the CPLD, it is determined that the abnormal data segment will cause abnormal interaction between the target processor and the external device; if the function affected by the abnormal data segment is only the internal function of the CPLD, it is determined that the abnormal data segment will not cause abnormal interaction between the target processor and the external device.

[0049] Exemplarily, determine the function of the abnormal data in the upgrade data (for example, communication parameters, protocol fields, buffer data), and analyze in combination with the interface protocol specification whether the abnormal data will cause abnormal communication between the processor and the external device (for example, whether it will cause the baud rate configuration to exceed the device support range, or the CRC check code to generate logical errors); through simulation, compare the communication data stream of the upgrade data containing abnormal data with that of the normal upgrade data, and determine whether observing the abnormal data will cause communication timeouts, frame parsing failures, etc., so as to judge whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0050] For example, taking the target processor as a programmable logic controller, a logical function analysis is performed on the abnormal data segment to determine whether the abnormal data segment causes abnormal coupling between different functional blocks in the processor. If the abnormal data segment causes abnormal coupling between different functional blocks in the processor, it is determined that the abnormal data segment will cause abnormal interaction between the target processor and external devices.

[0051] It should be noted that if two functional blocks are interconnected in hardware logic, the two functional blocks are functional blocks with a coupling relationship; or if two functional blocks have data coupling in the data processing flow, the two functional blocks are functional blocks with a coupling relationship.

[0052] Step S103: In response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, the abnormal data segment is rolled back; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain a second data segment.

[0053] Exemplarily, in response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, a first data segment corresponding to the abnormal data segment is obtained from historical upgrade data corresponding to the last successful upgrade of the processor.

[0054] In some optional implementations, the historical upgrade data may be stored in a memory connected to the first processor.

[0055] Exemplarily, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain a second data segment.

[0056] Step S104: upgrading the target processor based on the first data segment or the second data segment.

[0057] Exemplarily, taking the example that the abnormal data segment will not cause abnormal interaction between the target processor and the external device, the abnormal data segment in the upgrade data of the target processor is replaced with the first data segment, and the replaced upgrade data is imported into the target processor to upgrade the target processor.

[0058] Exemplarily, taking the example that the abnormal data segment will not cause abnormal interaction between the target processor and the external device, the abnormal data segment in the upgrade data of the target processor is replaced with a second data segment, and the replaced upgrade data is imported into the target processor to upgrade the target processor.

[0059] By implementing the embodiments of the present application, when an exception occurs during the upgrade of the target processor, a logical function analysis can be performed based on the abnormal data segment to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device. If the abnormal data segment does not affect the normal interaction between the target processor and the external device, the abnormal data segment is rolled back to obtain the first data segment. If the abnormal data segment affects the normal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain the second data segment, and the target processor is upgraded based on the first data segment or the second data segment. This can improve the success rate of the processor upgrade and ensure the normal operation of the processor.

[0060] In some embodiments, when it is determined that an abnormality occurs during the upgrade process of the target processor, the data in which the abnormality occurs can be analyzed to obtain an abnormal data segment in the upgrade data. As an example, see Figure 2 , Figure 2 This is a flow chart of another method for handling upgrade exceptions provided by an embodiment of the present application. Figure 2 As shown, the method may include but is not limited to the following steps:

[0061] Step S201: determining that the upgrade data of the target processor fails to be verified, and obtaining a data segment in the upgrade data that fails to be verified as a data segment to be identified.

[0062] Exemplarily, it is determined that an abnormality occurs in the verification of the target processor upgrade data, the data location of the abnormal data is obtained, and a corresponding data segment is obtained from the upgrade data according to the data location as the data segment to be identified.

[0063] It should be noted that there is at least one data location where abnormal data occurs and at least one data segment to be identified.

[0064] Step S202: performing level analysis and frequency analysis on the data segment to be identified, and obtaining the signal level and signal frequency of the signal to be identified corresponding to the data segment to be identified.

[0065] Exemplarily, based on the data segment to be identified, the level analysis is performed on the data segment to be identified, and the signal level value of the signal to be identified is obtained by the data segment to be identified. Furthermore, the frequency analysis is performed on the data segment to be identified, and the signal frequency of the signal to be identified is obtained by the data segment to be identified.

[0066] Step S203: determining whether the signal level satisfies a first preset condition, and determining whether the signal frequency satisfies a second preset condition.

[0067] As an example, taking the case where the signal level includes a high level value, if the high level value is less than or equal to a preset high level threshold, it is determined that the level value does not meet the first preset condition.

[0068] As an example, taking the case where the signal level includes a low level value, if the low level value is greater than or equal to a preset low level threshold, it is determined that the level value does not meet the first preset condition.

[0069] As an example, taking the signal level including a high level value and a low level value, if the high level value is less than or equal to the preset high level threshold and the low level value is greater than or equal to the preset low level threshold, it is determined that the level value does not meet the first preset condition.

[0070] As an example, if the signal frequency is greater than or equal to a preset frequency threshold, it is determined that the signal frequency does not meet the second preset condition.

[0071] Step S204: determining that the signal level does not satisfy the first preset condition and / or the signal frequency does not satisfy the second preset condition, performing level calibration and / or frequency calibration on the signal to be identified to obtain a calibration signal.

[0072] Exemplarily, it is determined that the signal level does not meet the first preset condition, and a level calibration is performed on the signal to be identified to obtain a calibration signal.

[0073] Exemplarily, it is determined that the signal frequency does not meet the second preset condition, and frequency calibration is performed on the signal to be identified to obtain a calibration signal.

[0074] Exemplarily, it is determined that the signal level does not meet the first preset condition and the signal frequency does not meet the second preset condition, and level calibration and frequency calibration are performed on the signal level to obtain a calibration signal.

[0075] Step S205: perform signal verification on the calibration signal.

[0076] Exemplarily, the calibration signal is compared and verified with a preset standard signal.

[0077] Step S206: determining that the calibration signal fails verification, and treating the data segment to be identified as an abnormal data segment.

[0078] Step S207: performing detection based on the abnormal data segment to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0079] In the embodiment of the present application, step S207 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0080] Step S208: In response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, the abnormal data segment is rolled back to obtain the first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain the second data segment.

[0081] In the embodiment of the present application, step S208 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0082] Step S209: upgrading the target processor based on the first data segment or the second data segment.

[0083] In the embodiment of the present application, step S209 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0084] By implementing the embodiments of the present application, when an exception occurs during a target processor upgrade, the data segment with the exception can be obtained as a data segment to be identified, and the data segment to be identified can be analyzed to determine whether the data segment to be identified is an abnormal data segment that needs to be processed. This reduces upgrade failures caused by signal quality and timing issues and improves the efficiency of handling target processor upgrade exceptions.

[0085] In some embodiments, information may be sent to the target processor to determine the impact range of the abnormal data segment based on the feedback information from the target processor. As an example, see Figure 3 , Figure 3 This is a flow chart of another method for handling upgrade exceptions provided by the embodiment of the present application. Figure 3 As shown, the method may include but is not limited to the following steps:

[0086] Step S301: determining that the upgrade data verification of the target processor fails, and obtaining an abnormal data segment in the upgrade data.

[0087] In the embodiment of the present application, step S301 can be implemented in any of the ways in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0088] Step S302: Acquire the setting information corresponding to the abnormal data segment in the upgrade data.

[0089] Step S303: Sending setting information to the target processor.

[0090] Exemplarily, resource band identification is performed on the target processor resources occupied by the setting information, a unit through which the in-band resources of the first processor interact with the target processor is determined, and the setting information is sent to the target processor through the unit.

[0091] Step S304: In response to obtaining feedback information from the target processor, determine based on the feedback information whether the abnormal data segment will cause abnormal interaction between the target processor and the external device; or, in response to not obtaining feedback information from the target processor, determine that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0092] It can be understood that after the target processor receives the set information, if the target processor can recognize the set information, it will feedback corresponding feedback information, which includes the affected pins and the execution status of the relevant functions of the target processor determined in combination with the pin signal status; if the unit receiving the feedback information is the same as the unit sending the set information, it is determined that the abnormal data segment will not cause abnormal interaction between the target processor and the external device; if the unit receiving the feedback information is different from the unit sending the set information, it is determined that the abnormal data segment will cause abnormal interaction between the target processor and the external device; if the target processor cannot recognize the set information, it will not feedback corresponding feedback information, which means that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0093] Step S305: In response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, the abnormal data segment is rolled back to obtain the first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain the second data segment.

[0094] In the embodiment of the present application, step S305 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0095] Step S306: upgrading the target processor based on the first data segment or the second data segment.

[0096] In the embodiment of the present application, step S306 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0097] By implementing the embodiments of the present application, the impact range of the abnormal data segment can be determined based on the target processor's feedback on the set information, and corresponding processing can be performed based on the impact range. This can improve the efficiency of handling abnormalities in the target processor upgrade.

[0098] As an example, see Figure 4 , Figure 4 This is a schematic diagram of an abnormal data segment analysis process provided by an embodiment of the present application. Figure 4As shown, when errors occur during the verification process, key information of the errors is extracted and identified. By performing error set retrieval and error set identification on the verified errors, the impact of the resulting error points on the overall function can be confirmed.

[0099] In one implementation, when the abnormal data segment only affects the implementation of the corresponding target function, the abnormal data segment can be rolled back. As an example, see Figure 5 , Figure 5 This is a flow chart of another method for handling upgrade exceptions provided by the embodiment of the present application. Figure 5 As shown, the method may include but is not limited to the following steps:

[0100] Step S501: determining that the upgrade data verification of the target processor fails, and obtaining an abnormal data segment in the upgrade data.

[0101] In the embodiment of the present application, step S501 can be implemented in any of the ways in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0102] Step S502: performing detection based on the abnormal data segment to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0103] In the embodiment of the present application, step S502 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0104] Step S503: In response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, obtaining at least one historical upgrade data.

[0105] Exemplarily, in response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, historical upgrade data used in at least one historical upgrade process of the target processor is acquired.

[0106] Step S504: Compare the historical upgrade data with the abnormal data segment and at least one historical upgrade data to obtain a first data segment corresponding to the abnormal data segment.

[0107] For example, taking the target processor as CPLD, the historical firmware data of the CPLD can be compared based on the pin corresponding to the abnormal data segment and the corresponding target function, and the most recent target historical firmware data containing the data segment corresponding to the target function is selected, and the data segment corresponding to the target function in the target historical firmware data is used as the historical data segment corresponding to the abnormal data segment.

[0108] In some embodiments, the historical upgrade data can be quickly compared with the abnormal data segment and at least one historical upgrade data through hardware acceleration to obtain the historical data segment corresponding to the abnormal data segment, thereby improving the processing efficiency of the abnormal data segment.

[0109] For example, taking the first processor including multiple cores as an example, the resource occupancy rates of the multiple cores are sorted, and the core with the lowest current occupancy rate is extracted, and the core is used for data verification, and the abnormal data segment is used as the retrieval point, and the data is compared as the error correction code in the data verification, and the historical upgrade data is used as the verification information code to perform the data verification operation, and the remainder bits obtained after the information code is divided by the check code are used as the check bits in the data verification, and the remainder bits are used as the input for core division processing. The divided cores will extract the error position information corresponding to the remainder bits after each verification, and obtain the corresponding data segments in the remainder bits as historical data segments.

[0110] Step S505: upgrading the target processor based on the first data segment.

[0111] In the embodiment of the present application, step S505 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0112] By implementing the embodiments of the present application, when an abnormal data segment does not cause a coupling function abnormality in the target processor, the target data segment corresponding to the abnormal data segment in the most recent historical upgrade data can be used to replace the abnormal data segment, and the target processor can be upgraded based on the replaced upgrade data. This can quickly resolve upgrade anomalies with a relatively small impact and improve the success rate of target processor generation.

[0113] See Figure 6 , Figure 6 This is an example diagram of a data segment rollback repair algorithm provided by an embodiment of the present application. Figure 6 As shown in the figure, if it is confirmed that the current data segment will affect the configuration of a single IO pin of the CPLD and the implementation of the target function, but will not be coupled to other functional points, a local rollback algorithm is used to automatically roll back the data segment corresponding to the target function to the previous version, and the error point is shielded and verified at the same time to ensure that the verification error will not cause abnormalities in the CPLD upgrade.

[0114] In one implementation, when an abnormal data segment affects the coupling between different functions, the abnormal data segment can be repaired. As an example, see Figure 7 , Figure 7 This is a flow chart of another method for handling upgrade exceptions provided by the embodiment of the present application. Figure 7 As shown, the method may include but is not limited to the following steps:

[0115] Step S701: determining that the upgrade data verification of the target processor fails, and obtaining an abnormal data segment in the upgrade data.

[0116] In the embodiment of the present application, step S701 can be implemented in any of the ways in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0117] Step S702: Perform detection based on the abnormal data segment to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0118] In the embodiment of the present application, step S702 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0119] Step S703: In response to the abnormal data segment causing abnormal interaction between the target processor and the external device, a second functional block having a coupling relationship with the first functional block corresponding to the abnormal data segment in the upgrade data is obtained.

[0120] In this embodiment of the present application, there is at least one second functional block.

[0121] Step S704: Acquire the data segment corresponding to the second functional block.

[0122] Step S705: Combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit.

[0123] Exemplarily, the first functional block and the second functional block are combined in a functional package manner, so as to combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit.

[0124] Step S706: Repair the first data unit multiple times to obtain multiple candidate data units.

[0125] Exemplarily, the first data unit is repaired using a check code pre-embedded in the upgrade data to obtain a plurality of candidate data units.

[0126] In one implementation, each candidate data unit is obtained by the following steps:

[0127] Step A1: Acquire a data link signal in a target processor as status data.

[0128] Step A2: Calculate the remainder of the first data unit based on the status data to obtain a first remainder unit.

[0129] Step A3: Perform an XOR operation on the first remainder unit and the first data unit to obtain a second data unit.

[0130] Step A4: Calculate the remainder of the second data unit based on the status data to obtain a second remainder unit.

[0131] Step A5: In response to the second remainder unit being zero, the second data unit is used as a candidate data unit. Alternatively, in response to the second remainder unit being non-zero, the second data unit is XORed based on the second remainder unit to obtain a third data unit, and the third data unit is used as the new second data unit and returned to step A4.

[0132] Step S707: Perform XOR on multiple candidate data units to obtain a candidate second data segment.

[0133] Exemplarily, an XOR operation is performed on data codes at the same position in multiple candidate data units to obtain candidate repair data units.

[0134] Step S708: In response to the verification being passed, the candidate second data segment is used as the second data segment; or, in response to the verification being failed, the process returns to the step of performing multiple repairs on the first data unit to obtain multiple candidate data units.

[0135] Exemplarily, the candidate repair data unit is used to replace the corresponding data in the upgrade data, and the new upgrade data obtained by replacement is verified. If the data verification passes, it is determined that the repair is successful; if the data verification fails, the process returns to step S707.

[0136] Step S709: upgrading the target processor based on the second data segment.

[0137] In the embodiment of the present application, step S709 can be implemented by any of the methods in the embodiments of the present application. The embodiments of the present application do not limit this and will not be described in detail.

[0138] By implementing the embodiments of the present application, when an abnormal data segment affects the coupling between different functions of a target processor, the abnormal data segment can be repaired, and the target processor can be upgraded based on the repaired data segment, thereby improving the success rate of the target processor upgrade.

[0139] As an example, see Figure 8 , Figure 8 This is a schematic diagram of an abnormal data repair process provided by an embodiment of the present application. Figure 8As shown, once it is confirmed that a bit error affects the function of a single IO pin and is coupled to the entire functional module, the bit error can be repeatedly repaired based on the CRC check. After each repair is completed, the repair result is tested until no abnormalities are observed during the testing process. Then, the upgrade is performed based on the upgraded data after the repair is completed. In addition, any abnormalities that occur during the testing process are recorded. After the recording is completed, the current recorded value and the repair content are unified into the repair factor of the CPLD unit. The functional module is then cycled again until no abnormalities are observed during the testing process, and the cyclic verification process is completed.

[0140] In some embodiments, the above method may further include the following steps: obtaining the data position corresponding to the first data unit; after the CPLD is upgraded again, obtaining the corresponding target data unit from the newly upgraded data summary based on the data position; performing functional simulation comparison based on the first data unit and the target data unit to obtain functional deviation information; obtaining the target data code from the upgraded data based on the functional deviation information; and replacing the corresponding data in the target processor based on the target data code.

[0141] Exemplarily, after the repair is complete, the starting and ending positions of the errored unit are recorded. Based on these starting and ending positions, the errored units before and after the modification are compared to obtain repair point information for the current errored unit, and this repair point information is saved. After the next successful upgrade of the target processor, the corresponding target data code is retrieved from the upgrade data used for the successful upgrade based on the aforementioned repair point information. Functional simulation operations are performed on this data code and the errored unit within the target processor to obtain target registers with different register values ​​and corresponding target data code positions. Based on this target data code position, the corresponding target data code is retrieved from the upgrade data. A data patch is generated based on this target data code, and this data patch is imported into the target processor.

[0142] In some embodiments, the above method further includes: acquiring coupling function change information; and decoupling the first functional block and the second functional block based on the coupling function change information.

[0143] Exemplarily, in order to repair changes involving coupling functions, the repaired functional blocks are decoupled, and the functional blocks involving changes in the repaired overall data code are combined, and the functional blocks that are not involved in changes during the repair process are combined, and the repaired error unit and the functional blocks involving changes are placed at the forefront of the storage address in the storage unit.

[0144] In one implementation, a data patch can be generated based on the target data code through the following steps: first, the data code corresponding to the abnormal position and coupling function in the target data code is split to obtain an abnormal unit module and a coupling function module, each module contains a position code for indicating the position of the data code that needs to be replaced, and a modified data code, the two modules are integrated to generate a data patch and imported into the upgrade module of the target processor to repair the target processor.

[0145] By implementing the embodiment of the present application, after the target processor is upgraded again, the data code changes during the repair process of the abnormal data segment can be repaired to ensure stable operation of the processor.

[0146] As an example, see Figure 9 , Figure 9 This is an example diagram of another abnormal data repair process provided by the embodiment of the present application. Figure 9 As shown, the CPLD program obtained from the cyclic verification will have functional implementation differences compared to the previous one. The abnormal position recording and analysis algorithm is used to record the repair points during the cyclic verification and fallback verification process. After the next successful CPLD upgrade, the repaired CPLD is modified and improved in the form of a patch. The final modified CPLD is consistent with the normal CPLD function and implementation method, ensuring the normal operation of the storage device.

[0147] As an example, see Figure 10 , Figure 10 This is a schematic diagram of a solution for handling upgrade exceptions provided by an embodiment of the present application. Figure 10 As shown, for processor upgrade failure caused by verification failure, the error analysis of the verification failure process is prioritized to determine whether the error affects other logical functions of the processor except the failure location. If only a single function of the failure location is affected, the data of the error location is rolled back to the previous version through the rollback algorithm for functional repair. If it is determined that other logical functions are affected, the function corresponding to the error is repaired together with the in-phase coupled function through the cyclic verification algorithm. After the repair is completed, the upgrade can proceed normally; and the abnormal position recording and analysis algorithm is used to record the verification and repair points. After the next CPLD upgrade is successful, the repaired CPLD is modified in the form of a patch for repair, thereby ensuring that the final CPLD version has no difference in function and reliability from the normal version.

[0148] See Figure 11 , Figure 11 This is a schematic diagram of the structure of an upgrade exception processing device provided by an embodiment of the present application. Figure 11As shown, the device 1100 includes: a first processing module 1101, which is used to determine whether the upgrade data verification of the target processor has failed, and obtain an abnormal data segment in the upgrade data; a second processing module 1102, which is used to perform detection based on the abnormal data segment, and determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device; a third processing module 1103, which is used to roll back the abnormal data segment in response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, and obtain a corresponding first data segment; or, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, repair the abnormal data segment to obtain a second data segment; and a fourth processing module 1104, which is used to upgrade the target processor based on the first data segment or the second data segment.

[0149] In one implementation, the first processing module 1101 is used to: obtain a data segment in the upgrade data that fails verification as a data segment to be identified; perform level analysis and frequency analysis on the data segment to be identified to obtain a signal level and signal frequency of a signal to be identified corresponding to the data segment to be identified; determine whether the signal level meets a first preset condition, and determine whether the signal frequency meets a second preset condition; determine that the signal level does not meet the first preset condition and / or the signal frequency does not meet the second preset condition, perform level calibration and / or frequency calibration on the signal to be identified to obtain a calibration signal; perform signal verification on the calibration signal; determine that the calibration signal fails the verification, and use the data segment to be identified as the abnormal data segment.

[0150] In one implementation, the second processing module 1102 is used to: generate set information based on the abnormal data segment; send the set information to the target processor; in response to obtaining feedback information from the target processor, determine based on the feedback information whether the abnormal data segment will cause abnormal interaction between the target processor and the external device; or, in response to not obtaining feedback information from the target processor, determine that the abnormal data segment will cause abnormal interaction between the target processor and the external device.

[0151] In one implementation, the third processing module 1103 is configured to: obtain at least one historical upgrade data; and compare the historical upgrade data with the abnormal data segment and the at least one historical upgrade data to obtain a first data segment corresponding to the abnormal data segment.

[0152] In one implementation, the third processing module 1103 is used to: obtain a second functional block that is coupled to the first functional block corresponding to the abnormal data segment in the upgraded data; obtain a data segment corresponding to the second functional block; combine the abnormal data segment and the data segment corresponding to the second functional block into a first data unit; obtain a data link signal in the target processor as status data; repair the first data unit multiple times based on the status data to obtain multiple candidate data units; perform XOR on the multiple candidate data units to obtain candidate data segments, and verify the candidate data segments; in response to the verification passing, use the candidate second data segment as the second data segment; or, in response to the verification failing, return to the step of repairing the first data unit multiple times to obtain multiple candidate data units.

[0153] In an optional implementation, the third processing module 1103 is used to perform the following steps: Step 1: Acquire a data link signal in the target processor as status data; Step 2: Calculate the remainder of the first data unit based on the status data to obtain a first remainder unit; Step 3: XOR the first remainder unit with the first data unit to obtain a second data unit; Step 4: Calculate the remainder of the second data unit based on the status data to obtain a second remainder unit; Step 5: In response to the second remainder unit being zero, use the second data unit as a candidate data unit; or, in response to the second remainder unit being not zero, XOR the second data unit based on the second remainder unit to obtain a third data unit, and return the third data unit as a new second data unit to execute step 4.

[0154] In an optional implementation, the third processing module 1103 is also used to: obtain the data position corresponding to the first data unit; after the target processor is upgraded again, obtain the corresponding target data unit from the newly upgraded data based on the data position; perform functional simulation comparison based on the first data unit and the target data unit to obtain functional deviation information; obtain the target data code from the upgraded data based on the functional deviation information; and use the target data code to replace the corresponding data in the target processor.

[0155] By using the device of the embodiment of the present application, when an abnormality occurs during the upgrade of the target processor, a logical function analysis can be performed based on the abnormal data segment to determine whether the abnormal data segment will cause abnormal interaction between the target processor and the external device. If the abnormal data segment does not cause abnormal interaction between the target processor and the external device, the abnormal data segment is rolled back to obtain the first data segment. If the abnormal data segment causes abnormal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain the second data segment, and the target processor is upgraded based on the first data segment or the second data segment. This can improve the success rate of the processor upgrade and ensure the normal operation of the processor.

[0156] It should be noted that the above explanation of the embodiment of the method for handling upgrade anomalies is also applicable to the apparatus for handling upgrade anomalies in this embodiment, and will not be repeated here.

[0157] In order to implement the above embodiment, the present application also proposes an electronic device. Figure 12 , Figure 12 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application. Figure 12 As shown, the electronic device 1200 includes: a target processor 1201, and a memory 1202 communicatively connected to the target processor 1201; the memory 1202 stores computer-executable instructions; the target processor 1201 executes the computer-executable instructions stored in the memory to implement the method provided by the aforementioned embodiment.

[0158] In order to implement the above embodiments, the present application also proposes a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a target processor, they are used to implement the methods provided in the above embodiments.

[0159] In order to implement the above embodiments, the present application also proposes a computer program product, including a computer program, which implements the method provided by the above embodiments when executed by a target processor.

[0160] In the description of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a way to describe the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0161] In the descriptions of the foregoing embodiments, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are mutually inconsistent.

[0162] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0163] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0164] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a target processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" is any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0165] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having logic gate circuits for implementing logical functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0166] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0167] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0168] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A method for handling upgrade exceptions, characterized in that: include: Determining that upgrade data verification of the target processor fails, and obtaining an abnormal data segment in the upgrade data; detecting the target processor based on the abnormal data segment, and determining whether the abnormal data segment causes abnormal interaction between the target processor and an external device; In response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, rolling back the abnormal data segment to obtain a corresponding first data segment; Alternatively, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain a second data segment; performing a target processor upgrade based on the first data segment or the second data segment; The obtaining of abnormal data segments in the upgrade data includes: Acquire a data segment in the upgrade data that fails verification as a data segment to be identified; Performing level analysis and frequency analysis on the data segment to be identified to obtain a signal level and a signal frequency of a signal to be identified corresponding to the data segment to be identified; Determining whether the signal level satisfies a first preset condition, and determining whether the signal frequency satisfies a second preset condition; determining that the signal level does not satisfy the first preset condition and / or the signal frequency does not satisfy the second preset condition, performing level calibration and / or frequency calibration on the signal to be identified to obtain a calibration signal; performing signal verification on the calibration signal; determining that the calibration signal fails verification, and treating the data segment to be identified as the abnormal data segment; The detecting the target processor based on the abnormal data segment and determining whether the abnormal data segment causes abnormal interaction between the target processor and the external device includes: generating setting information based on the abnormal data segment; sending the setting information to the target processor; In response to obtaining feedback information from the target processor, determining whether the abnormal data segment will cause abnormal interaction between the target processor and the external device based on the feedback information; or, in response to not obtaining feedback information from the target processor, determining whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

2. The method according to claim 1, characterized in that The step of rolling back the abnormal data segment to obtain a corresponding first data segment includes: Obtain at least one historical upgrade data; The historical upgrade data, the abnormal data segment, and the at least one historical upgrade data are compared to obtain the first data segment corresponding to the abnormal data segment.

3. The method according to claim 1, characterized in that The repairing the abnormal data segment to obtain a second data segment includes: Acquire a second functional block that is coupled to the first functional block corresponding to the abnormal data segment; Obtaining a data segment corresponding to the second functional block; combining the abnormal data segment and the data segment corresponding to the second functional block into a first data unit; Performing multiple repairs on the first data unit to obtain multiple candidate data units; Performing an XOR operation on the multiple candidate data units to obtain a candidate data segment, and verifying the candidate data segment; In response to the verification passing, the candidate data segment is used as the second data segment; or, in response to the verification failing, returning to the step of performing multiple repairs on the first data unit to obtain multiple candidate data units.

4. The method according to claim 3, characterized in that Each candidate data unit is obtained by the following steps: Step 1: Acquire a data link signal in the target processor as status data; Step 2: Calculate the remainder of the first data unit based on the state data to obtain a first remainder unit; Step 3: Perform an XOR operation on the first remainder unit and the first data unit to obtain a second data unit; Step 4: Calculate the remainder of the second data unit based on the state data to obtain a second remainder unit; Step 5: In response to the second remainder unit being zero, use the second data unit as the candidate data unit; or, in response to the second remainder unit being not zero, perform XOR on the second data unit based on the second remainder unit to obtain a third data unit, and return the third data unit as a new second data unit to execute step 4.

5. The method according to claim 3, characterized in that The method further comprises: Obtaining a data position corresponding to the first data unit; After the target processor is upgraded again, obtaining a corresponding target data unit from the newly upgraded data based on the data position; Performing a functional simulation comparison between the first data unit and the target data unit to obtain functional deviation information; acquiring a target data code from the upgrade data based on the functional deviation information; The target data code is used to replace corresponding data in the target processor.

6. A device for handling upgrade anomalies, characterized in that: include: A first processing module is configured to determine that the upgrade data verification of the target processor fails, and obtain an abnormal data segment in the upgrade data; a second processing module, configured to detect the target processor based on the abnormal data segment, and determine whether the abnormal data segment will cause abnormal interaction between the target processor and an external device; a third processing module, configured to, in response to the abnormal data segment not causing abnormal interaction between the target processor and the external device, roll back the abnormal data segment to obtain a corresponding first data segment; Alternatively, in response to the abnormal data segment causing abnormal interaction between the target processor and the external device, the abnormal data segment is repaired to obtain a second data segment; a fourth processing module, configured to upgrade a target processor based on the first data segment or the second data segment; The first processing module is specifically configured to: Acquire a data segment in the upgrade data that fails verification as a data segment to be identified; Performing level analysis and frequency analysis on the data segment to be identified to obtain a signal level and a signal frequency of a signal to be identified corresponding to the data segment to be identified; Determining whether the signal level satisfies a first preset condition, and determining whether the signal frequency satisfies a second preset condition; determining that the signal level does not satisfy the first preset condition and / or the signal frequency does not satisfy the second preset condition, performing level calibration and / or frequency calibration on the signal to be identified to obtain a calibration signal; performing signal verification on the calibration signal; determining that the calibration signal fails verification, and treating the data segment to be identified as the abnormal data segment; The second processing module is specifically configured to: generating setting information based on the abnormal data segment; sending the setting information to the target processor; In response to obtaining feedback information from the target processor, determining whether the abnormal data segment will cause abnormal interaction between the target processor and the external device based on the feedback information; or, in response to not obtaining feedback information from the target processor, determining whether the abnormal data segment will cause abnormal interaction between the target processor and the external device.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 5 when executed by a target processor.

8. A computer program product, characterized in that The method comprises a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 5.

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