JTAG-DMI interface design method based on CPU debugging system

Abstract

The invention discloses a JTAG-DMI interface design method based on a CPU debugging system, and the method comprises the following steps: S1, transmitting a clock signal tck, a selection signal tms and input data tdi to the CPU debugging system through a JTAG Master, and receiving the clock signal tck, the selection signal tms and the input data tdi through a JTAG Slaver; s2, serially inputting the input data tdi into a shift register, and then storing the input data tdi into an asynchronous FIFO (First In First Out); and S3, reading input data information in the asynchronous FIFO through an APB transmission protocol, decoding the input data information, transmitting the decoded input data information to a DM module, and transmitting the decoded input data information to a CPU processor by the DM module for Debug debugging. The perfect JTAG-DMI interface protocol design method is provided for a CPU debugging system, the system debugging function can be perfected, the CPU debugging compatibility is improved, the debugging data transmission rate is increased, and the delay is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU processor Debug debugging systems, and specifically relates to a design method for the JTAG-DMI interface of a CPU debugging system. Background Art

[0002] Currently, in the design of processors, with the update and iteration of technology, and the increasing requirements of application scenarios for the stability and reliability of processor cores, and the rapid development of the general-purpose chip field, frequent updates and replacements, and a greatly shortened R & D cycle, the Debug debugging system technology has thus become an important part of the chip design process. As the communication interface of the debugging system, JTAG-DMI is even more important in the design.

[0003] There is a debugging system for a general-purpose processor. This debugging system includes a DTM module and a DM module. The DTM module includes internal registers, a TAP control module, and a cdc clock handover module. The DTM module is used for the host computer to read and write data registers from the DTM module through the JTAG interface, and interact with the DM module through the data bus according to the DMI interface protocol. Among them, for the clock handover between the JTAG interface and the DM module, the cdc clock handover module provides a one-beat-slower processing for the clock handover between the JTAG interface and the DM module, so as to ensure the clock synchronization between the JTAG interface and the DM module.

[0004] However, currently, this debugging system for general-purpose processors has at least the following three problems: 1) Low debugging efficiency; when this debugging system performs clock handover between the JTAG interface and the DM module, it is processed by the cdc clock handover module with a one-beat-slower, but the cdc clock handover module is mainly for the cross-clock-domain transmission of single-bit signals, seriously affecting the debugging efficiency; 2) Poor system stability; this debugging system provides a one-beat-slower processing for the clock handover between the JTAG interface and the DM module through the cdc clock handover module, and is prone to metastability problems, thus affecting the stability of the debugging system; 3) Incomplete debugging functions; when this debugging system performs cross-clock-domain transmission of signals, it is mainly for the cross-clock-domain transmission of single-bit signals, and there are limitations for the cross-clock-domain transmission of multi-bit signals, so the debugging functions need to be improved. Summary of the Invention

[0005] In view of the above three problems, the object of the present invention is to propose a design method for the JTAG-DMI interface of the CPU debugging system. By further designing the JTAG-DMI interface, the debugging function of the Debug debugging system of the CPU processor is improved, and the compatibility, debugging data transmission rate, and chip design and R & D efficiency of the CPU processor debugging system are enhanced. At the same time, by using an asynchronous FIFO in the method of the present invention, the problem of asynchronous clock data storage existing in the existing debugging system is overcome, the stability of the debugging system can be further improved, and data loss during transmission can be avoided.

[0006] It is achieved through the following technical solutions: A design method for the JTAG-DMI interface of the CPU debugging system, the method comprising the following steps: S1. The debugger sends a clock signal tck, a select signal tms, and input data tdi to the Debug debugging system of the CPU processor through the JTAG Master, and receives the data and signals through the JTAG Slaver in the Debug debugging system of the CPU processor. Among them, the clock signal tck is used to drive the operation state of the TAP state machine to change; S2. Control the state of the TAP state machine through the select signal tms, complete the update of the IR register, and serially input the input data tdi into the corresponding shift register through the value of the IR register, and then store the input data tdi into the asynchronous FIFO through the DMI interface; S3. Read the input data tdi information in the asynchronous FIFO through the APB transfer protocol connected to the asynchronous FIFO and perform decoding, and then transmit the decoded data to the DM module. The DM module decodes the data and transmits it to the CPU processor for CPU processor Debug debugging.

[0007] The method of the present invention proposes a perfect design method for the interface of the Debug debugging system of the CPU processor, improves the compatibility, debugging data transmission rate, and chip design and R & D efficiency of the CPU processor debugging system, and at the same time solves the problem of data reading and writing in different clock cycles, thereby ensuring the accuracy of data transmission.

[0008] Preferably, in step S1, the select signal tms is sampled and takes effect at the rising edge of the clock signal tck. By sampling and updating the select signal tms at the rising edge of each clock cycle of the clock signal tck, the state of the TAP state machine can be accurately controlled during the test.

[0009] Preferably, in step S2, the TAP state machine has 16 states, and the transition from the current state to the next state is controlled by the selection signal tms. By changing the state of the TAP state machine through the selection signal tms, different test modes can be selected for operation, further improving the debugging function of the CPU processor Debug debugging system.

[0010] Preferably, in step S2, the shift register serially receives the input data tdi, stores the input data tdi in the highest bit of the shift register, and at the same time, the remaining data in the shift register is shifted one bit to the right until the input data tdi is completely received. By using the shift register to complete the input of new data, the accurate input of the input data tdi can be ensured.

[0011] Preferably, when the input data tdi is transmitted to the shift register, the shift register will output the previously input data through the tdo signal interface of the TAP state machine at this time. By simultaneously inputting and outputting data through the shift register, the data transmission rate can be increased, and the integrity and accuracy of data input and output can be ensured.

[0012] Preferably, in step S2, the asynchronous FIFO is used to synchronize the clock signals of the JTAG transmission protocol and the APB transmission protocol. By using the asynchronous FIFO, the stability of the debugging system can be improved, and data loss during transmission can be avoided.

[0013] Preferably, the asynchronous FIFO uses two flip-flops as the clock signal synchronization circuit to synchronize the read and write pointers to the clock domains of each other respectively, as the basis for the empty and full states of the asynchronous FIFO. By synchronizing the read and write pointers to the clock domains of each other, metastability can be avoided when reading and writing data, and at the same time, the accuracy of the empty and full state judgment of the asynchronous FIFO can be ensured.

[0014] Preferably, in step S3, the APB transmission protocol has two independent data buses, one for reading data and one for writing data. By using the APB transmission protocol, the complexity and power consumption of the interface are reduced, and at the same time, the accuracy and efficiency of data transmission are improved.

[0015] The beneficial effects of the present invention compared with the prior art are: The technical solution of the present invention further designs the JTAG-DMI interface, improves the debugging function of the CPU processor Debug debugging system, improves the compatibility of the CPU processor debugging system and the chip design and R & D efficiency, reduces the delay and waiting time during debugging, thereby improving the debugging efficiency; at the same time, the method of the present invention overcomes the problem of asynchronous clock data storage existing in the existing debugging system by using the asynchronous FIFO, can further improve the stability of the debugging system, and ensure the integrity and accuracy of data transmission. Brief Description of the Drawings

[0016] Figure 1 It is a schematic structural diagram of a design method based on the JTAG-DMI interface of a CPU debugging system; Figure 2 It is a schematic diagram of the TAP state transition of a design method based on the JTAG-DMI interface of a CPU debugging system.

[0017] Figure 3 It is a schematic structural diagram of an asynchronous FIFO in a design method based on the JTAG-DMI interface of a CPU debugging system. Specific implementation manners

[0018] Next, the technical solutions in the embodiments of the present invention will be described in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0019] As Figure 1 shown, it is a schematic structural diagram of a design method based on the JTAG-DMI interface of a CPU debugging system, including a JTAG host of a debugger, a DTM module, and a DM module. Among them, the DTM module, that is, the Debug Translator Module, is a debug converter module, including a TAP state machine, a register module, and an asynchronous FIFO; the TAP state machine inputs and outputs data and signals through four signal interfaces of tck, tms, tdi, and tdo; the register module includes an IR register and multiple DR registers, and the multiple DR registers include an MDI register, a BYPASS register, a DTMCS register, an IDCODE register, etc.; the DM module, that is, the Debug Module, is a debug module that stores, decodes, and transmits the input data information to the CPU processor through the Buffer sram register. When performing system debugging, first send the clock signal tck, the selection signal tms, and the input data tdi to the CPU processor debugging system through the JTAG Master and receive them through the JTAG Slaver; then serially input the input data tdi into the shift register and store it in the asynchronous FIFO; finally, read the input data information in the asynchronous FIFO through the APB transmission protocol, decode it, and then transmit it to the DM module, and the DM module transmits it to the CPU processor for Debug debugging.

[0020] The method specifically includes the following steps: S1. The debugger sends the clock signal tck, the select signal tms, and the input data tdi to the Debug debugging system of the CPU processor through the JTAG Master, and receives data and signals through the JTAG Slaver in the CPU processor's Debug debugging system. Among them, the JTAG interface, that is, the Joint Test Action Group, is an international standard test protocol, which is applied to internal chip testing and system simulation and debugging; the clock signal tck provides an independent and basic clock signal for the operating state of the TAP state machine, and the select signal tms is sampled and takes effect when it changes from low level to high level at each clock cycle of the clock signal tck, thereby changing the test mode of the TAP state machine. By sampling and updating the select signal tms at the rising edge of each clock cycle of the clock signal tck, the state of the TAP state machine can be accurately controlled during the test, improving the debugging efficiency of the debugging system.

[0021] S2. After receiving the clock signal tck, the select signal tms, and the input data tdi through the JTAG Slaver, under the drive of the clock signal tck, the 16 state transitions of the TAP state machine are controlled by the select signal tms to complete the update of the IR register, and a corresponding DR register, that is, the shift register, is selected according to the value of the IR register, and the input data tdi is serially input into the corresponding shift register to complete the update of the DR register, and the asynchronous FIFO write enable terminal is enabled according to the update signal, and then the input data tdi is stored in the asynchronous FIFO through the DMI interface. Among them, the TAP state machine, that is, the Test AccessPort, is a general-purpose port that can access all IR registers and DR registers for data transmission and update; the IR register, that is, the Instruction Register, is the instruction register for controlling the data register; the DR register, that is, the Data Register, is the data register for observing and controlling the system input and output; the DMI interface, that is, the Debug Module Interface, is the interface for connecting the debugger and the DM module, allowing the debugger to directly access and control the internal state of the CPU processor, including registers and memory, etc., further improving the debugging function of the CPU processor debugging system.

[0022] Such as Figure 2As shown, it is a schematic diagram of the TAP state transition based on the design method of the JTAG-DMI interface of the CPU debugging system. The TAP state machine first enters the Test-Logic-Reset test logic reset state. Driven by the clock signal tck, it sequentially enters the Run-Test / Idle run test idle state, Select-DR-Scan select data register scan state, Capture-IR capture instruction register state, Shift-IR shift instruction register state, Exit1-IR exit instruction register state 1, and Update-IR update instruction register state according to the selection signal tms. Finally, it returns to the Run-Test / Idle run test idle state to complete the update of the IR register; through the IR register, a corresponding data register is selected. At this time, the TAP state machine sequentially enters the Select-DR-Scan select data register scan state, Capture-DR capture data register state, Shift-DR shift data register state, Exit1-DR exit data register state 1, and Update-DR update data register state from the Run-Test / Idle run test idle state. During this process, the data register simultaneously performs the shift_in input operation and shift_out output operation of the data. Among them, Pause-IR is the pause instruction register state, Exit2-IR is the exit instruction register state 2, Pause-DR is the pause data register state, and Exit2-DR is the exit data register state 2.

[0023] In this embodiment, in step S1, the shift register serially receives the input data tdi through the tdi signal interface and stores the input data tdi in the highest bit of the shift register. At the same time, the remaining data in the shift register is shifted one bit to the right until all the input data tdi is received. At this time, the shift register outputs the previously input data through the tdo signal interface of the TAP state machine, that is, the data is transmitted to the shift register through the tdi signal interface and then the previously input data is output from the shift register through the tdo signal interface, thereby updating the DR register. By simultaneously performing the serial input and output of data through the shift register, the data transmission rate can be improved, and the integrity and accuracy of data input and output can be ensured.

[0024] S3. Through an asynchronous FIFO, synchronize the clock signals of the JTAG transmission protocol and the APB transmission protocol, read the input data tdi information in the asynchronous FIFO through the APB transmission protocol and perform decoding, and then transmit the decoded data to the DM module. The DM module decodes the data and transmits it to the CPU processor for CPU processor Debug debugging. Among them, the APB transmission protocol, that is, Advance Peripheral Bus, is a low-power and low-complexity interface with two independent data buses, one for reading data and one for writing data. Using the APB transmission protocol for data transmission can reduce the complexity and power consumption of the interface, and at the same time improve the accuracy and efficiency of data transmission.

[0025] In this embodiment, in step S3, the asynchronous FIFO, that is, First In First Out, is a first-in-first-out data buffer that can quickly and conveniently transfer data between two different clock systems; in the present invention, the asynchronous FIFO is used to solve the cross-clock domain transmission problem caused by data information interaction between the DMI interface and the APB transmission protocol, and completes the synchronization of the read pointer and the write pointer through the conversion between binary read / write pointer encoding and Gray code; at the same time, the asynchronous FIFO uses two flip-flops as the clock signal synchronization circuit to synchronize the read pointer and the write pointer to the clock domain of the other party respectively, as the basis for the empty / full state of the asynchronous FIFO; among them, the basis for the empty / full state of the asynchronous FIFO is: the asynchronous FIFO is empty when the read pointer and the write pointer are exactly the same, and the FIFO is full when the highest two bits of the read pointer and the write pointer are different and the remaining bits are the same. Through the asynchronous FIFO, the stability of the debugging system can be improved, data loss during transmission can be avoided, and at the same time, synchronizing the read / write pointers to the clock domain of the other party can avoid metastability when reading and writing data, ensuring the accuracy of the empty / full state judgment of the asynchronous FIFO.

[0026] Such as Figure 3As shown in the figure, it is a schematic diagram of the structure of an asynchronous FIFO in a CPU debugging system JTAG-DMI interface design method. In the figure, r_ptr and w_ptr are the read pointer and write pointer of the asynchronous FIFO respectively, and g_write_pointer_sync and g_read_pointer_sync are the Gray code write pointer synchronization and Gray code read pointer synchronization respectively. Among them, the corresponding connection relationship between the relevant signals input by the asynchronous FIFO and the JTAG interface signals is as follows: the data signal data_in is connected to the shift register signal tdi_shifter_reg, the write enable signal write_enable is connected to the data update signal Update DR, the write clock signal write_clock is connected to the JTAG interface clock signal tck, and the write reset signal write_reset_n is connected to the reset signal in the JTAG interface; by receiving the asynchronous FIFO write enable signal and determining that the asynchronous FIFO does not generate a full signal, the received shift register data is stored in the asynchronous FIFO, and at this time the binary write pointer b_write_pointer is incremented by 1. At the same time, the corresponding relationship between the relevant signals output by the asynchronous FIFO and the ABP transfer protocol signals is as follows: the data signal data_out corresponds to the ABP transfer protocol data signal, the read enable signal read_enable corresponds to the asynchronous FIFO non-empty signal, the read clock read_clock corresponds to the ABP transfer protocol clock signal, and the read reset signal read_reset_n is connected to the reset signal of the ABP transfer protocol; by receiving the asynchronous FIFO read enable signal and determining that the asynchronous FIFO is not in the empty state, the data in the asynchronous FIFO is read, and at this time the binary read pointer b_read_pointer is incremented by 1.

[0027] Among them, write pointer handler and read pointer handler are the read and write pointer processing units respectively. When converting the binary read and write pointer encoding to Gray code, the highest bit of the Gray code is the same as the highest bit of the binary code, and the remaining bits of the Gray code are the exclusive OR results of the adjacent bits of the binary code. The formula is as follows: a[width] = b_pointer[width]; If (i < width) a[i] = b_pointer[i] ^ a[i+1]; g_pointer = a; Among them, a is an intermediate variable with the same bit width as the pointer bit width; i decreases from large to small, and when it decreases to 0, it indicates that the conversion is completed; b_pointer is a binary pointer, including a write pointer b_write_pointer and a read pointer b_read_pointer, and g_pointer is a Gray code pointer, including a Gray code write pointer g_write_pointer and a Gray code read pointer g_read_pointer.

[0028] In summary, through further design of the JTAG-DMI interface, the present invention improves the debugging function of the CPU processor Debug debugging system, enhances the compatibility of the CPU processor debugging system and the chip design and R & D efficiency, reduces the delay and waiting time during the debugging process, thereby improving the debugging efficiency; at the same time, the method of the present invention overcomes the problem of asynchronous clock data storage existing in the existing debugging system by using an asynchronous FIFO, can further improve the stability of the debugging system, ensure the integrity and accuracy of data transmission, and has significant progressiveness.

[0029] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A design method for the JTAG-DMI interface of a CPU debugging system, characterized in that The method includes the following steps: S1. The debugger sends a clock signal tck, a select signal tms, and input data tdi to the Debug debugging system of the CPU processor through the JTAG Master, and receives data and signals through the JTAG Slaver in the CPU processor Debug debugging system. Among them, the clock signal tck is used to drive the operation state of the TAP state machine to change; S2. Control the state of the TAP state machine through the select signal tms, complete the update of the IR register, and serially input the input data tdi to the corresponding shift register through the value of the IR register, and then store the input data tdi in the asynchronous FIFO through the DMI interface; S3. Read the input data tdi information in the asynchronous FIFO through the APB transfer protocol connected to the asynchronous FIFO and perform decoding, and then transmit the decoded data to the DM module. The DM module decodes the data and transmits it to the CPU processor for CPU processor Debug debugging.

2. The design method of a JTAG-DMI interface for a CPU debugging system according to claim 1, wherein, In step S1, the select signal tms is sampled and takes effect at the rising edge of the clock signal tck.

3. A design method for the JTAG-DMI interface of a CPU-based debugging system according to claim 1, characterized in that, In step S2, the TAP state machine has 16 states, and the transition from the current state to the next state is controlled by the select signal tms.

4. A design method for the JTAG-DMI interface of a CPU-based debugging system according to claim 1, characterized in that In step S2, the shift register serially receives the input data tdi and stores the input data tdi in the highest bit of the shift register. At the same time, the remaining data in the shift register is shifted one bit to the right until the input data tdi is received completely.

5. A design method for the JTAG-DMI interface of a CPU-based debugging system according to claim 4, characterized in that, When the input data tdi is transmitted to the shift register, the shift register will output the previously input data through the tdo signal interface of the TAP state machine at this time.

6. A design method for the JTAG-DMI interface of a CPU-based debugging system according to claim 1, characterized in that, In step S2, the asynchronous FIFO is used to synchronize the clock signals of the JTAG transfer protocol and the APB transfer protocol.

7. A design method for the JTAG-DMI interface of a CPU debugging system according to claim 6, characterized in that The asynchronous FIFO synchronizes the read and write pointers to the clock domains of each other respectively by using two flip-flops as the clock signal synchronization circuit, as the basis for the empty / full state of the asynchronous FIFO.

8. A design method for the JTAG-DMI interface of a CPU-based debugging system according to claim 1, characterized in that, In step S3, the APB transfer protocol has two independent data buses, one for reading data and one for writing data.

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