Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, the display panel comprises a display area and a non-display area, the non-display area comprises a first fan-out area located on one side of the display area, and the first fan-out area comprises a plurality of fan-out wires; the display area comprises a plurality of data lines and a plurality of first scanning lines, the data lines are electrically connected with the fan-out wires, and at least part of the data lines are electrically connected with the fan-out wires through the connecting wires, so that compressed space can be provided for the frame of the display panel, and the narrow frame design of the display panel is realized. The connecting line comprises a first connecting line segment and a second connecting line segment, the shielding part is arranged between the second connecting line segment and the first scanning line, the fixed potential signal is transmitted to the shielding part, and direct coupling between the first scanning line and the second connecting line segment is cut off by arranging the shielding part; and the influence on the data voltage signal transmitted by the second connecting line segment is reduced, so that the problem of non-uniform display of a display product is improved, and the display effect is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, various industries have higher and higher requirements for display products. Some display products are developing towards narrow borders. In order to reduce the border of the display panel, a technology of laying out part of the fan-out line in the display area (Fanout in AA, FIAA) has emerged. However, the layout of the FIAA fan-out line may cause uneven display in the display area.

[0003] Therefore, how to improve the above problems has become one of the technical issues that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device for improving the display unevenness problem of display products and improving the display effect.

[0005] In one aspect, the present disclosure provides a display panel, comprising:

[0006] a display area and a non-display area at least partially surrounding the display area, the non-display area including a first fan-out area located at one side of the display area along a first direction, the first fan-out area including a plurality of fan-out lines, and the first direction is parallel to a plane where the display panel is located;

[0007] The display area includes a plurality of data lines extending along the first direction and arranged along a second direction, the data lines are electrically connected to the fan-out lines, wherein at least part of the data lines are electrically connected to the fan-out lines through connecting lines, the second direction is parallel to the plane where the display panel is located, and is perpendicular to the first direction; the connecting lines are located in the display area, and the connecting lines include a first connecting line segment extending along the first direction and a second connecting line segment extending along the second direction;

[0008] The display panel further includes a plurality of first scan lines extending along the second direction, at least one of the first scan lines being located on at least one side of the second connecting line segment along the first direction;

[0009] The display panel also includes multiple pixel driving circuit rows, and the pixel driving circuit rows include multiple pixel driving circuits arranged along the second direction; in the area where the same pixel driving circuit row is located, along the first direction, there is also a shielding portion between the second connecting line segment and the first scanning line, and the shielding portion receives a fixed potential signal.

[0010] On the other hand, based on the same inventive concept, the present disclosure further provides a display device including a display panel.

[0011] The technical solutions provided by the embodiments of the present disclosure have the following advantages compared with the prior art:

[0012] The present disclosure provides a display panel and a display device, including: a display area and a non-display area, the non-display area includes a first fan-out area located on one side of the display area, and the first fan-out area includes a plurality of fan-out traces; the display area includes a plurality of data lines and a plurality of first scan lines, and the data lines are electrically connected to the fan-out traces, wherein at least some of the data lines are electrically connected to the fan-out traces through connection traces. In this way, it is possible to avoid arranging the fan-out traces at the positions of the lower left border and / or the lower right border of the display panel, thereby providing a compressed space for the border of the display panel, which is beneficial to realizing the narrow border design of the display panel and improving the user experience. The connection trace includes a first connection segment and a second connection segment. The present disclosure provides a shielding portion between the second connection segment and the first scan line, and transmits a fixed potential signal to the shielding portion. By providing the shielding portion, the direct coupling between the first scan line and the second connection segment is cut off. When the signal of the first scan line jumps, the influence on the data voltage signal transmitted by the second connection segment is reduced, thereby improving the problem of uneven display of the display product, and further being beneficial to improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] Figure 1 Shown is a schematic plan view of a display panel in the related art;

[0016] Figure 2 Shown is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0017] Figure 3 Shown is a schematic wiring structure diagram of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 4 Shown is an equivalent circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0019] Figure 5 Shown is Figure 4A timing diagram of the middle pixel driving circuit;

[0020] Figure 6 The following shows a schematic diagram of a film layer of the display panel provided by an embodiment of the present disclosure;

[0021] Figure 7 The following shows another plan view of the display panel provided by an embodiment of the present disclosure;

[0022] Figure 8 The following shows yet another plan view of the display panel provided by an embodiment of the present disclosure;

[0023] Figure 9 The following shows another schematic diagram of a wiring structure provided by an embodiment of the present disclosure;

[0024] Figure 10 The following shows a schematic diagram of a wiring structure of the first metal layer provided by an embodiment of the present disclosure;

[0025] Figure 11 The following shows a schematic diagram of a wiring structure of the second metal layer provided by an embodiment of the present disclosure;

[0026] Figure 12 The following shows a schematic diagram of a wiring structure of the third metal layer provided by an embodiment of the present disclosure;

[0027] Figure 13 The following shows a schematic diagram of a wiring structure of the capacitive metal layer provided by an embodiment of the present disclosure;

[0028] Figure 14 The following shows a schematic diagram of a wiring structure of the semiconductor layer provided by an embodiment of the present disclosure;

[0029] Figure 15 The following shows a plan view of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0030] In order to more clearly understand the above objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0031] In the following description, many specific details are set forth in order to fully understand the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all of the embodiments.

[0032] In the research, the inventor found that in some display products, in order to reduce the border of the display panel, a technology of laying some fan-out lines in the active area (Fanout in AA, FIAA) has emerged. However, the way of laying the fan-out lines in the active area may cause uneven display in the active area and poor display effect. Figure 1 The following is a schematic plan view of a display panel in the related art. Please refer to Figure 1 , the display panel 000 includes a fan-out trace L0', the fan-out trace L0' includes a longitudinal trace L1' and a transverse trace L2', the display panel 100 further includes a scan signal line S1', the scan signal line S1' and the transverse trace L2' both extend in the same direction, and the distance between the transverse trace L2' and the scan signal line S1' is relatively close, and the lateral capacitance generated between the transverse trace L2' and the scan signal line S1' is too large. When the scan signal transmitted by the scan signal line S1' jumps low, it will couple the data voltage signal transmitted by the transverse trace L2'. As the scan signal line S1' scans from top to bottom, the corresponding coupled data voltage signal shifts to the right, thereby generating an oblique bright line, that is, an inverted eight mura (non-uniformity), resulting in the problem of uneven display and affecting the display effect.

[0033] In view of this, the present disclosure provides a display panel and a display device to improve the problem of uneven display of the display product and improve the display effect.

[0034] Figure 2 The following is a schematic plan view of a display panel provided by an embodiment of the present disclosure. Figure 3 The following is a schematic wiring structure view of a display panel provided by an embodiment of the present disclosure. Please refer to Figure 2 and Figure 3 , the present disclosure provides a display panel 100, including: an active area AA and at least part of a non-active area NA surrounding the active area AA, the non-active area NA includes a first fan-out area N1 located on one side of the active area AA along a first direction F1, the first fan-out area N1 includes a plurality of fan-out traces S0, the first direction F1 is parallel to the plane where the display panel 100 is located; the active area AA includes a plurality of data lines DATA extending along the first direction F1 and arranged along a second direction F2, the data lines DATA are electrically connected to the fan-out traces S0, wherein at least part of the data lines DATA are electrically connected to the fan-out traces S0 through connection traces L0, the second direction F2 is parallel to the plane where the display panel 100 is located and perpendicular to the first direction F1; the connection traces L0 are located in the active area AA, the connection traces L0 include a first connection segment L1 extending along the first direction F1 and a second connection segment L2 extending along the second direction F2; the display panel 100 further includes a plurality of first scan lines Scan1 extending along the second direction F2, and at least one first scan line Scan1 is located on at least one side of the second connection segment L2 along the first direction F1.

[0035] The display panel 100 further includes a plurality of pixel driving circuit rows 30, and each pixel driving circuit row 30 includes a plurality of pixel driving circuits 300 arranged along the second direction F2. It should be noted that, Figure 2 only the light-emitting unit D0 is shown in Figure 3 which shows the pixel driving circuit 300. The pixel driving circuit 300 is used to drive the light-emitting unit D0 to emit light. In the area where the same pixel driving circuit row 30 is located, along the first direction F1, a shielding portion 20 is further included between the second connection line segment L2 and the first scan line Scan1, and the shielding portion 20 receives a fixed potential signal.

[0036] It should be noted that, Figure 2 only the data line DATA, the first scan line Scan1, and the fan-out trace S0 included in the display panel 100 are schematically shown, and the number of the data line DATA, the first scan line Scan1, and the fan-out trace S0 actually included in the display panel 100 is not limited.

[0037] Specifically, the display panel 100 includes a plurality of traces, at least some of the traces extend along the first direction F1, and at least some of the traces extend along the second direction F2. It should be noted that the traces referred to in the present disclosure extending along the first direction F1 or the second direction F2 means that the traces generally extend along the first direction F1 or the second direction F2, and does not mean that each segment of the traces extends along the first direction F1 or the second direction F2. Among them, the first scan line Scan1 extends along the second direction F2, the data line DATA extends along the first direction F1, and the data line DATA is electrically connected to the fan-out trace S0 located in the first fan-out area N1 for transmitting a data voltage signal. In some embodiments, at least some of the data lines DATA are electrically connected to the fan-out trace S0 through the connection trace L0 located in the display area AA. Exemplarily, the data lines DATA located in the first display area AA1 and the second display area AA2 are electrically connected to the fan-out trace S0 in the first fan-out area N1 through the connection trace L0. In this way, the fan-out trace S0 can be avoided from being arranged at the lower left border and / or the lower right border of the display panel 100, thereby providing a compressed space for the border of the display panel 100, which is beneficial to realizing the narrow border design of the display panel 100 and improving the user experience.

[0038] The connecting trace L0 includes a first connecting segment L1 and a second connecting segment L2. Among them, the first connecting segment L1 extends along a first direction F1, and the second connecting segment L2 extends along a second direction F2. The display panel 100 further includes a first scan line Scan1, and the first scan line Scan1 is at least configured to provide a scan signal to the pixel driving circuit 300. The first scan line Scan1 extends along the second direction F2. In some alternative embodiments, the first scan line Scan1 and the second connecting segment L2 are arranged along the first direction F1. Since the lengths of the first scan line Scan1 and the second connecting segment L2 along the second direction F2 are relatively long, the lateral capacitance between the first scan line Scan1 and the second connecting segment L2 is relatively large, which may affect the signal transmission, and further lead to uneven display and affect the display effect. Therefore, the present disclosure provides a shielding portion 20 between the second connecting segment L2 and the first scan line Scan1, and a fixed potential signal is transmitted to the shielding portion 20. By providing the shielding portion 20, the direct coupling between the first scan line Scan1 and the second connecting segment L2 is cut off. When the signal of the first scan line Scan1 jumps, the influence on the data voltage signal transmitted by the second connecting segment L2 is reduced, so as to improve the problem of uneven display of the display product, and further facilitate the improvement of the display effect.

[0039] Please refer to Figure 2 and Figure 3 , Figure 2 The display panel 100 shown in Figure 3 shows a pixel driving circuit 300. The pixel driving circuit 300 is used to drive the corresponding light-emitting unit D0 to emit light. Figure 4 Shown is an equivalent circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Please refer to Figures 2 to 4 , the present disclosure takes Figure 4Taking the pixel driving circuit 300 shown as an example for illustration, the pixel driving circuit 300 is electrically connected to the light-emitting unit D0. The pixel driving circuit 300 includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the third transistor T3 is a driving transistor for providing a driving current to the light-emitting unit D0. The gate, the first pole, and the second pole of the third transistor T3 are respectively connected to the first node N1, the second node N2, and the third node N3. The first pole and the second pole of the first transistor T1 are respectively connected to the first power supply voltage signal line PVDD and the second node N2 for transmitting the first power supply voltage signal to the first pole of the driving transistor. The first pole and the second pole of the second transistor T2 are respectively connected to the data line DATA and the second node N2 for transmitting the data voltage signal to the second node N2. The first pole and the second pole of the fourth transistor T4 are respectively connected to the first node N1 and the third node N3 for performing threshold compensation on the third transistor T3. The first pole and the second pole of the fifth transistor T5 are respectively connected to the first reset signal line Vref1 and the first node N1 for providing a first reset signal to the first node N1. The first pole and the second pole of the sixth transistor T6 are respectively connected to the third node N3 and the first pole of the light-emitting unit D0 for transmitting the driving current to the light-emitting unit D0. The first pole and the second pole of the seventh transistor T7 are respectively connected to the second reset signal line Vref2 and the anode of the light-emitting unit D0 for resetting the anode of the light-emitting unit D0. The cathode of the light-emitting unit D0 is connected to the second power supply voltage signal line PVEE.

[0040] Figure 5 Shown as Figure 4 is a timing diagram of the pixel driving circuit in, please refer to Figure 4 and Figure 5, the specific working process of the pixel driving circuit 300 includes an initialization stage t1, a data writing stage t2, and a light emitting stage t3; in the initialization stage t1, the fifth transistor T5 and the seventh transistor T7 are turned on. The fifth transistor T5 transmits the first reset signal transmitted by the first reset signal line Vref1 to the control end of the third transistor T3 under the control of the first scan signal transmitted by the first scan line Scan1 for initialization, thereby eliminating the residual charge of the previous frame of the picture and improving the display effect of the display panel 100; the seventh transistor T7 transmits the second reset signal transmitted by the second reset signal line Vref2 to the anode of the light emitting unit D0 for reset under the control of the first scan signal transmitted by the first scan line Scan1, which can eliminate the residual charge of the previous frame of the picture, enabling the light emitting unit D0 to display the to-be-displayed brightness more accurately, thereby improving the display effect of the display panel 100. In the data writing stage t2, the fifth transistor T5 and the seventh transistor T7 are turned off, the second transistor T2 and the fourth transistor T4 are turned on, and the data voltage signal transmitted by the data line DATA is written into the third transistor T3. The fourth transistor T4 is connected between the gate and the second pole of the third transistor T3, and can capture the threshold voltage of the third transistor T3 to the gate of the third transistor T3 to achieve threshold voltage compensation. Moreover, the capacitor C is connected between the gate of the third transistor T3 and the first pole of the first transistor T1, and can maintain the potential of the first node N1. It should be noted that the reset process of the light emitting unit D0 can be performed in the initialization stage t1 or in the data writing stage t2, and the present disclosure does not limit this. In the light emitting stage t3, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are all turned off, the first transistor T1, the third transistor T3, and the sixth transistor T6 are all turned on, and the driving current is transmitted to the first pole of the light emitting unit D0, and the light emitting unit D0 emits light. It should be noted that the present disclosure only uses Figure 4 as an example to illustrate the pixel driving circuit 300, Figure 5 and the timing diagram is only for illustration and is not limited thereto. In some other embodiments of the present disclosure, the pixel driving circuit 300 may also be embodied as other feasible structures, and the present disclosure does not limit the types of transistors in the pixel driving circuit 300 either. Optionally, the fourth transistor T4 and the fifth transistor T5 can be double-gate transistors. In this way, it is beneficial to increase the control ability of carriers in the channel region, so that when the transistor is in the off state, it can more effectively suppress the flow of carriers, thereby being beneficial to improving the leakage problem.

[0041] It should also be noted that, Figure 2 the display panel 100 in Figure 2The light-emitting unit D0 is only schematically shown by a rectangular frame, which does not represent the actual quantity, size, and structure of the light-emitting unit D0. Optionally, the display panel 100 provided in this embodiment may be an organic light-emitting display panel, a display panel using organic light-emitting diode display technology, that is, an OLED (Organic Light-Emitting Diode) display panel. Figure 6 The following is a schematic diagram of a film layer of the display panel provided by an embodiment of the present disclosure. The connection manner between the light-emitting unit D0 and the pixel driving circuit 300 can be generally referred to Figure 6 , the light-emitting unit D0 includes a first electrode 201, a light-emitting material layer 202, and a second electrode layer 203. The pixel driving circuit 300 includes a driving transistor T3, and the driving transistor T3 is electrically connected to the light-emitting unit D0. When the pixel driving circuit 300 provides an appropriate voltage, the holes generated by the first electrode 201 and the electrons generated by the second electrode layer 203 will combine in the light-emitting material layer 202 to generate bright light. The display panel 100 further includes a pixel definition layer 24. The pixel definition layer 24 is located on the side of the first electrode 201 away from the substrate 10. The pixel definition layer 24 includes a plurality of pixel openings, and the light-emitting unit D0 is arranged in the pixel openings. The light-emitting unit D0 may include light-emitting units D0 of multiple different colors, and the present disclosure does not make specific limitations.

[0042] Figure 7 The following is another plan view of the display panel provided by an embodiment of the present disclosure. Please refer to Figure 7 , in an alternative embodiment of the present disclosure, the shielding portion 20 extends along the second direction F2. Specifically, since both the first scan line Scan1 and the second connection segment L2 extend along the second direction F2, and the lengths of the first scan line Scan1 and the second connection segment L2 along the second direction F2 are relatively long, in this embodiment, the shielding portion 20 is arranged to extend along the second direction F2. In this way, the overlapping length of the shielding portion 20 with the first scan line Scan1 and the second connection segment L2 along the first direction F1 is relatively large, which is more conducive to cutting off the direct coupling between the first scan line Scan1 and the second connection segment L2. When the signal of the first scan line Scan1 jumps, the influence on the data voltage signal transmitted by the second connection segment L2 is reduced, thereby improving the problem of uneven display of the display product, and further being conducive to improving the display effect.

[0043] Figure 8 The following is another plan view of the display panel provided by an embodiment of the present disclosure. Figure 9 The following is another schematic diagram of a wiring structure provided by an embodiment of the present disclosure. Please refer to Figure 8 and Figure 9, in an alternative embodiment of the present disclosure, it further includes a first reset signal line Vref1, and the first reset signal line Vref1 is configured to provide a first reset signal to the pixel driving circuit 300. The first reset signal line Vref1 includes a first sub-reset signal line Vref1-1 and a second sub-reset signal line Vref1-2 which are electrically connected. The first sub-reset signal line Vref1-1 extends along a first direction F1, and the second sub-reset signal line Vref1-2 extends along a second direction F2.

[0044] Specifically, please refer to Figure 8 、 Figure 9 and in combination with Figure 4 , the fifth transistor T5 is configured to transfer the first reset signal to the gate of the third transistor T3 (driving transistor) under the control of the first scan signal, thereby resetting the gate signal of the third transistor T3. The first reset signal line Vref1 is used to transmit the first reset signal, and the first pole of the fifth transistor T5 is connected to the first reset signal line Vref1. When the area of the display panel 100 is relatively large, if the first reset signal line Vref1 is only a single path, the voltage at the distal end of the signal line may drop due to impedance, resulting in different voltages at the proximal and distal ends of the signal line. In this embodiment, the first reset signal line Vref1 includes a first sub-reset signal line Vref1-1 extending along the first direction F1 and a second sub-reset signal line Vref1-2 extending along the second direction F2. The first sub-reset signal line Vref1-1 and the second sub-reset signal line Vref1-2 cross to form a mesh structure. The first reset signal line Vref1 with the mesh structure can reduce the resistance of the first reset signal line Vref1, improve the current-carrying capacity, and reduce the impedance in the transmission path of the first reset signal line Vref1, thereby enhancing the uniformity and stability of signal transmission.

[0045] Please continue to refer to Figure 8 and Figure 9 , further, in an alternative embodiment of the present disclosure, within the area of the same pixel driving circuit row 30, along the first direction F1, the second sub-reset signal line Vref1-2 is located between the second connection line segment L2 and the first scan line Scan1, and the second sub-reset signal line Vref1-2 is multiplexed as the shielding portion 20.

[0046] Specifically, the second sub-reset signal line Vref1-2 extends along the second direction F2. The second sub-reset signal line Vref1-2 is used to transmit the first reset signal, and the first reset signal is a fixed potential signal. For the same row 30 of the pixel driving circuit, the second sub-reset signal line Vref1-2 is disposed between the second connection segment L2 and the first scan line Scan1, and the second sub-reset signal line Vref1-2 is multiplexed as the shielding portion 20. With such a setting, on the one hand, the direct coupling between the second connection segment L2 and the first scan line Scan1 is cut off by the second sub-reset signal line Vref1-2. When the signal of the first scan line Scan1 jumps, the influence on the data voltage signal transmitted by the second connection line is reduced, thereby improving the problem of uneven display of the display product, and further facilitating the improvement of the display effect. On the other hand, there is no need to introduce new signal lines and signals in the display panel 100, which is conducive to reducing the manufacturing difficulty and cost of the display panel 100.

[0047] Please continue to refer to Figure 8 and Figure 9 , in an alternative embodiment of the present disclosure, the display panel further includes a second reset signal line Vref2. The second reset signal line Vref2 is configured to provide a second reset signal to the pixel driving circuit 300. The second reset signal line Vref2 includes a third sub-reset signal line Vref2-1 and a fourth sub-reset signal line Vref2-2. The third sub-reset signal line Vref2-1 extends along the first direction F1, and the fourth sub-reset signal line Vref2-2 extends along the second direction F2. In the area where the same row 30 of the pixel driving circuit is located, along the first direction F1, the second connection segment L2 is located between the second sub-reset signal line Vref1-2 and the fourth sub-reset signal line Vref2-2.

[0048] Specifically, please refer to Figure 8 , Figure 9 and in combination with Figure 4, the display panel 100 further includes a second reset signal line Vref2. The second reset signal line Vref2 is connected to the first pole of the seventh transistor T7. The seventh transistor T7 transmits the second reset signal transmitted by the second reset signal line Vref2 to the anode of the light-emitting unit D0 under the control of the first scan signal transmitted by the first scan line Scan1, for resetting the anode voltage of the light-emitting unit D0. The second reset signal line Vref2 includes a third sub-reset signal line Vref2-1 extending along the first direction F1 and a fourth sub-reset signal line Vref2-2 extending along the second direction F2. The third sub-reset signal line Vref2-1 and the fourth sub-reset signal line Vref2-2 cross to form a mesh structure. The second reset signal line Vref2 with the mesh structure can reduce the resistance of the second reset signal line Vref2, improve the current-carrying capacity, and reduce the impedance in the transmission path of the first reset signal line Vref1, thereby enhancing the uniformity and stability of signal transmission. For the area where the same pixel driving circuit row 30 is located, in this embodiment, the second connection segment L2 is disposed between the second sub-reset signal line Vref1-2 and the fourth sub-reset signal line Vref2-2. The second sub-reset signal line Vref1-2 receives the first reset signal, and the fourth sub-reset signal line Vref2-2 receives the second reset signal. Both the first reset signal and the second reset signal are fixed-potential signals, and the second connection segment L2 receives the data voltage signal. Along the first direction F1, the second connection segment L2 is disposed between the second sub-reset signal line Vref1-2 and the fourth sub-reset signal line Vref2-2 that receive the fixed-potential signals. In this way, it is beneficial to shield the influence of other signals on the second connection segment L2, thereby stabilizing the transmission of the data voltage signal in the second connection segment L2. The stable transmission of the data voltage signal is beneficial to improving the display effect of the display panel 100.

[0049] Please refer to Figure 2 and Figure 3 , in an alternative embodiment of the present disclosure, within the area where the same pixel driving circuit row 30 is located, along the first direction F1, the shielding portion 20 is located between the second sub-reset signal line Vref1-2 and the fourth sub-reset signal line Vref2-2 and is electrically connected to the first reset signal line Vref1 or the second reset signal line Vref2.

[0050] Specifically, in this embodiment, within the area where the same pixel driving circuit row 30 is located, it includes a first scan line Scan1, a second connection line segment L2, a second sub-reset signal line Vref1-2, a fourth sub-reset signal line Vref2-2, and a shielding portion 20. Among them, the second connection line segment L2 is located between the second sub-reset signal line Vref1-2 and the fourth sub-reset signal line Vref2-2. The second sub-reset signal line Vref1-2 receives a first reset signal, and the fourth sub-reset signal line Vref2-2 receives a second reset signal. Both the first reset signal and the second reset signal are fixed potential signals, which is beneficial to shielding the influence of other signals on the second connection line segment L2, thereby stabilizing the transmission of the data voltage signal in the second connection line segment L2. The stable transmission of the data voltage signal is beneficial to improving the display effect of the display panel 100. In addition, between the first scan line Scan1 and the second connection line segment L2, there is the second sub-reset signal line Vref1-2 that receives the first reset signal, and the shielding portion 20. The shielding portion 20 is connected to a fixed potential signal. The setting of the second sub-reset signal line Vref1-2 and the shielding portion 20 is beneficial to cutting off the direct coupling between the first scan line Scan1 and the second connection line segment L2. When the signal of the first scan line Scan1 jumps, it reduces the influence on the data voltage signal transmitted by the second connection line, thereby improving the problem of uneven display of the display product, and further being beneficial to improving the display effect. Optionally, the shielding portion 20 is electrically connected to the first reset signal line Vref1 or the second reset signal line Vref2. With such a setting, there is no need to introduce new signal lines and signals in the display panel 100, which is beneficial to reducing the manufacturing difficulty and cost of the display panel 100.

[0051] Please continue to refer to Figure 2 and Figure 3 , in an alternative embodiment of the present disclosure, the first sub-reset signal line Vref1-1 includes a first sub-segment Vref1-11 and a second sub-segment Vref1-12, and the first sub-segment Vref1-11 and the second sub-segment Vref1-12 are on different layers; the third sub-reset signal line Vref2-1 includes a third sub-segment Vref2-11 and a fourth sub-segment Vref2-12, and the third sub-segment Vref2-11 and the fourth sub-segment Vref2-12 are on different layers; the second connection line segment L2 overlaps with the second sub-segment Vref1-12, the second connection line segment L2 overlaps with the fourth sub-segment Vref2-12, and the second connection line segment L2 is arranged on the same layer as the first sub-segment Vref1-11 and the third sub-segment Vref2-11.

[0052] Specifically, the first reset signal line Vref1 includes a first sub-reset signal line Vref1-1 extending along the first direction F1 and a second sub-reset signal line Vref1-2 extending along the second direction F2. The first sub-reset signal line Vref1-1 and the second sub-reset signal line Vref1-2 intersect to form a mesh structure. The second reset signal line Vref2 includes a third sub-reset signal line Vref2-1 extending along the first direction F1 and a fourth sub-reset signal line Vref2-2 extending along the second direction F2. The third sub-reset signal line Vref2-1 and the fourth sub-reset signal line Vref2-2 intersect to form a mesh structure. The second connection segment L2 is arranged along the second direction F2. If the second connection segment L2 is arranged on the same layer as the first sub-reset signal line Vref1-1 and the second sub-reset signal line Vref1-2, then the second connection segment L2 will overlap with the first sub-reset signal line Vref1-1 and the second sub-reset signal line Vref1-2. To avoid the overlap, this embodiment provides a wiring method for the first sub-reset signal line Vref1-1 and the third sub-reset signal line Vref2-1. The first sub-reset signal line Vref1-1 includes a first sub-segment Vref1-11 and a second sub-segment Vref1-12 arranged on different layers, and the first sub-segment Vref1-11 and the second sub-segment Vref1-12 are connected by a via hole. The second sub-reset signal line Vref1-2 includes a third sub-segment Vref2-11 and a fourth sub-segment Vref2-12 arranged on different layers, and the third sub-segment Vref2-11 and the fourth sub-segment Vref2-12 are connected by a via hole, so that the second connection segment L2 is arranged on the same layer as the first sub-segment Vref1-11 and the third sub-segment Vref2-11, that is, by setting jumpers, the overlap between the second connection segment L2 and the first sub-reset signal line Vref1-1 and the second sub-reset signal line Vref1-2 is avoided.

[0053] Please continue to refer to Figure 2 and Figure 3 , in an alternative embodiment of the present disclosure, the shielding portion 20 is arranged on the same layer as the first sub-segment Vref1-11 and the third sub-segment Vref2-11. Such an arrangement is beneficial for the shielding portion 20 to be electrically connected to the first reset signal line Vref1 or the second reset signal line Vref2, avoiding introducing new signals in the display panel 100, thereby reducing the manufacturing difficulty of the display panel 100. At the same time, it also avoids adding a new film layer in the display panel 100, reduces the influence on the thickness of the display panel 100, and is beneficial to realizing the thinning of the display panel 100.

[0054] Please refer to Figure 2 , Figure 3 and Figure 6, in an alternative embodiment of the present disclosure, the display panel includes: a substrate 00; a first metal layer M1 located on one side of the substrate 00; a second metal layer M2 located on the side of the first metal layer M1 away from the substrate 00. Optionally, the display panel 100 further includes: a capacitive metal layer MC located between the first metal layer M1 and the second metal layer M2; a third metal layer M3 located on the side of the second metal layer M2 away from the substrate 00. The display panel 100 includes a first scan line Scan1, a second connection segment L2, and a first reset signal line Vref1. Among them, the first scan line Scan1 is located in the first metal layer M1, and the second connection segment L2 is located in the second metal layer M2; the first reset signal line Vref1 includes a first sub-reset signal line Vref1-1 and a second sub-reset signal line Vref1-2 that are electrically connected. The first sub-reset signal line Vref1-1 extends along a first direction F1, and the second sub-reset signal line Vref1-2 extends along a second direction F2; the first sub-reset signal line Vref1-1 includes a first sub-segment Vref1-11 and a second sub-segment Vref1-12. The first sub-segment Vref1-11 and the shielding portion 20 are located in the second metal layer M2, the second sub-segment Vref1-12 is located in the third metal layer M3, and the second sub-reset signal line Vref1-2 is located in the capacitive metal layer MC. In an alternative embodiment of the present disclosure, it further includes a first power supply signal line PVDD. At least a part of the first power supply signal line PVDD and the data line DATA are located in the third metal layer M3.

[0055] It should be noted that, according to Figure 4 the equivalent circuit diagram of the pixel driving circuit 300 shown, the present disclosure provides a wiring structure diagram of the first metal layer M1, the second metal layer M2, the third metal layer M3, the capacitive metal layer MC, and the semiconductor layer poly. Please refer to Figures 10 to 14 ,

[0056] Figure 10 Shown is a wiring structure diagram of the first metal layer provided by the embodiment of the present disclosure.

[0057] Figure 11 Shown is a wiring structure diagram of the second metal layer provided by the embodiment of the present disclosure.

[0058] Figure 12 Shown is a wiring structure diagram of the third metal layer provided by the embodiment of the present disclosure. Figure 13 Shown is a wiring structure diagram of the capacitive metal layer provided by the embodiment of the present disclosure. Figure 14 Shown is a wiring structure diagram of the semiconductor layer provided by the embodiment of the present disclosure. It should be noted that the present disclosure only takes Figures 10 to 14 as an example and is not limited thereto. At the same time, Figures 10 to 14 the filling of different film layers inFigures 10 to 14 represent different film layers and do not correspond to the film layer filling in other drawings of the present disclosure.

[0059] Please refer to Figure 2 and Figure 3 , in an alternative embodiment of the present disclosure, the pixel driving circuit row 30 includes a plurality of pixel driving circuit groups arranged along the second direction F2. The pixel driving circuit group includes a first pixel driving circuit 31 and a second pixel driving circuit 32 which are mirror - arranged; the shielding portion 20 corresponding to the first pixel driving circuit 31 and the shielding portion 20 corresponding to the second pixel driving circuit 32 are mirror - arranged.

[0060] Specifically, the pixel driving circuit row 30 includes a plurality of pixel driving circuit groups. In the area where the pixel driving circuit group is located, the first pixel driving circuit 31 and the second pixel driving circuit 32 are mirror - arranged. The first pixel driving circuit 31 includes a corresponding shielding portion 20, and the second pixel driving circuit 32 also includes a corresponding shielding portion 20. The shielding portion 20 is located between the corresponding first scan line Scan1 and the second connection line segment L2, and the shielding portion 20 corresponding to the first pixel driving circuit 31 and the shielding portion 20 corresponding to the second pixel driving circuit 32 are also mirror - arranged. In this way, the wiring structure is relatively symmetric. For the signals transmitted by the wiring, it is also relatively symmetric, which is beneficial to improving the display uniformity and the four - azimuth color shift, and further beneficial to improving the display effect of the display panel.

[0061] Based on the same inventive concept, the present disclosure also provides a display device, Figure 15 as shown in a schematic plan view of the display device provided by the embodiment of the present disclosure. Please refer to Figure 15 , the display device 200 includes a display panel 100, and the display panel 100 is any display panel 100 provided by the embodiment of the present disclosure.

[0062] It should be noted that for the embodiments of the display device 200 provided by the embodiments of the present application, reference can be made to the embodiments of the above - mentioned display panel 100, and repeated descriptions will not be elaborated. The display device 200 provided by the present application can be: a mobile phone, a tablet computer, a television, a touch controller, a notebook computer, a navigator, or any product and component with a display function.

[0063] Through the above - mentioned embodiments, it can be seen that the display panel and the display device provided by the present disclosure at least achieve the following beneficial effects:

[0064] The present disclosure provides a display panel and a display device, including: a display area and a non-display area. The non-display area includes a first fan-out area located on one side of the display area. The first fan-out area includes a plurality of fan-out traces. The display area includes a plurality of data lines and a plurality of first scan lines. The data lines are electrically connected to the fan-out traces. Among them, at least some of the data lines are electrically connected to the fan-out traces through connection traces. In this way, it is possible to avoid arranging the fan-out traces at the positions of the lower left border and / or the lower right border of the display panel, thereby providing a compressed space for the border of the display panel, which is conducive to realizing the narrow border design of the display panel and improving the user experience. The connection trace includes a first connection segment and a second connection segment. The present disclosure provides a shielding portion between the second connection segment and the first scan line, and a fixed potential signal is transmitted to the shielding portion. By providing the shielding portion, the direct coupling between the first scan line and the second connection segment is cut off. When the signal of the first scan line jumps, the influence on the data voltage signal transmitted by the second connection segment is reduced, thereby improving the problem of uneven display of the display product and further being conducive to improving the display effect.

[0065] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0066] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, Comprising: A display area and at least a part of a non-display area surrounding the display area, the non-display area including a first fan-out area located on one side of the display area along a first direction, the first fan-out area including a plurality of fan-out traces, the first direction being parallel to the plane of the display panel; The display area includes a plurality of data lines extending along the first direction and arranged along a second direction, the data lines being electrically connected to the fan-out traces, wherein at least a part of the data lines are electrically connected to the fan-out traces through connection traces, the second direction being parallel to the plane of the display panel and perpendicular to the first direction; the connection traces are located in the display area, and the connection traces include a first connection segment extending along the first direction and a second connection segment extending along the second direction; The display panel further includes a plurality of first scan lines extending along the second direction, and at least one of the first scan lines is located on at least one side of the second connection segment along the first direction; The display panel further includes a plurality of pixel driving circuit rows, the pixel driving circuit rows including a plurality of pixel driving circuits arranged along the second direction; within the area where the same pixel driving circuit row is located, along the first direction, a shielding portion is further included between the second connection segment and the first scan line, and the shielding portion receives a fixed potential signal.

2. The display panel according to claim 1, wherein The shielding portion extends along the second direction.

3. The display panel according to claim 1, characterized in that It further includes a first reset signal line configured to provide a first reset signal to the pixel driving circuit, the first reset signal line including a first sub-reset signal line and a second sub-reset signal line that are electrically connected, the first sub-reset signal line extending along the first direction, and the second sub-reset signal line extending along the second direction.

4. The display panel according to claim 3, wherein, Within the area where the same pixel driving circuit row is located, along the first direction, the second sub-reset signal line is located between the second connection segment and the first scan line, and the second sub-reset signal line is multiplexed as the shielding portion.

5. The display panel according to claim 3, wherein It further includes a second reset signal line configured to provide a second reset signal to the pixel driving circuit, the second reset signal line including a third sub-reset signal line and a fourth sub-reset signal line, the third sub-reset signal line extending along the first direction, and the fourth sub-reset signal line extending along the second direction; Within the area where the same pixel driving circuit row is located, along the first direction, the second connection segment is located between the second sub-reset signal line and the fourth sub-reset signal line.

6. The display panel according to claim 5, wherein Within the area where the same pixel driving circuit row is located, along the first direction, the shielding portion is located between the second sub-reset signal line and the fourth sub-reset signal line and is electrically connected to the first reset signal line or the second reset signal line.

7. The display panel according to claim 5, characterized in that, The first sub-reset signal line includes a first sub-segment and a second sub-segment, and the first sub-segment and the second sub-segment are on different layers; the third sub-reset signal line includes a third sub-segment and a fourth sub-segment, and the third sub-segment and the fourth sub-segment are on different layers; The second connection line segment overlaps with the second sub-segment, the second connection line segment overlaps with the fourth sub-segment, and the second connection line segment is disposed on the same layer as the first sub-segment and the third sub-segment.

8. The display panel according to claim 7, wherein The shielding portion is disposed on the same layer as the first sub-segment and the third sub-segment.

9. The display panel according to claim 1, wherein Further comprising: A substrate; A first metal layer, disposed on one side of the substrate; A second metal layer, disposed on a side of the first metal layer away from the substrate; The first scan line is located in the first metal layer, and the second connection line segment is located in the second metal layer.

10. The display panel according to claim 9, wherein Further comprising: A capacitive metal layer, disposed between the first metal layer and the second metal layer; A third metal layer, disposed on a side of the second metal layer away from the substrate; A first reset signal line, the first reset signal line includes a first sub-reset signal line and a second sub-reset signal line which are electrically connected, the first sub-reset signal line extends along the first direction, and the second sub-reset signal line extends along the second direction; The first sub-reset signal line includes a first sub-segment and a second sub-segment, the first sub-segment and the shielding portion are located in the second metal layer, the second sub-segment is located in the third metal layer, and the second sub-reset signal line is located in the capacitive metal layer.

11. The display panel according to claim 10, wherein Further comprising a first power supply signal line, at least a part of the first power supply signal line and the data line are located in the third metal layer.

12. The display panel according to claim 1, wherein The pixel driving circuit row includes a plurality of pixel driving circuit groups arranged along the second direction, and each pixel driving circuit group includes a first pixel driving circuit and a second pixel driving circuit which are mirror-symmetrically arranged; The shielding portion corresponding to the first pixel driving circuit and the shielding portion corresponding to the second pixel driving circuit are mirror-symmetrically arranged.

13. A display device, characterized in that, A display panel according to any one of claims 1 to 12.

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