Display device

Abstract

A display device includes a display panel. The display panel includes a plurality of pixels receiving a first scan signal and a second scan signal, and a scan driver. The scan driver includes a first stage and a second stage arranged in sequence. When the second scan signals output from the first stage and the second stage, respectively, are simultaneously activated, a first pulse width of the second scan signal output from the first stage is different from a second pulse width of the second scan signal output from the second stage.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0009323, filed with the Korean Intellectual Property Office on January 22, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure relate to a display device having improved display quality. Background art

[0004] Various display devices used in electronic devices such as, for example, televisions, mobile phones, tablet computers, navigation systems, or game consoles are being developed. Since portable electronic devices operate on batteries, various efforts are being continued to reduce the power consumption of the display devices used in portable electronic devices.

[0005] Reducing the operation frequency of a display device can reduce power consumption. For example, in a specific operating environment such as displaying a still image, reducing the operation frequency of the display device can reduce the power consumption of the display device. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device having improved display quality.

[0007] According to an embodiment, a display device includes: a display panel in which an active area and a peripheral area adjacent to the active area are defined. The display panel includes: a plurality of pixels disposed in the active area and receiving a first scan signal and a second scan signal; and a scan driver disposed in the peripheral area and connected to the plurality of pixels. The scan driver includes a plurality of stages arranged in sequence. The plurality of stages include a first stage and a second stage. When the second scan signals respectively output from the first stage and the second stage are simultaneously activated, a first pulse width of the second scan signal output from the first stage is different from a second pulse width of the second scan signal output from the second stage.

[0008] In an embodiment, when the second stage is disposed after the first stage, the second pulse width is narrower than the first pulse width.

[0009] In an embodiment, each of the first stage and the second stage includes: a first scan output circuit including a first output node that outputs a first scan signal; a second scan output circuit including a second output node that outputs a second scan signal; a controller circuit including a plurality of control transistors electrically connected to a control node; and a compensation circuit connected to the second scan output circuit.

[0010] In an embodiment, the compensation circuit includes an inverter circuit connected to a first output node and a multiplexer circuit connected to the first output node and the inverter circuit.

[0011] In an embodiment, the multiplexer circuit receives a first clock signal having a second pulse width.

[0012] In an embodiment, a second stage generates and outputs a second scan signal based on the first clock signal.

[0013] In an embodiment, the compensation circuit further includes a control circuit connected to a control node and configured to control a voltage level of the control node.

[0014] In an embodiment, when the second scan signal is output, the control node is in an active state.

[0015] In an embodiment, a first stage generates and outputs a second scan signal based on a first scan signal.

[0016] In an embodiment, when the second scan signals respectively output from the first stage and the second stage are simultaneously activated, in the first stage, the first scan signal has an active level, the signal output from the inverter circuit has an inactive level, and the signal output from the multiplexer circuit has an active level.

[0017] In an embodiment, when the second scan signals respectively output from the first stage and the second stage are simultaneously activated, in the second stage, the first scan signal has an inactive level, the signal output from the inverter circuit has an active level, and the signal output from the multiplexer circuit has an active level with the second pulse width.

[0018] In an embodiment, the display panel operates during a plurality of frames. Each of the plurality of frames operates in a first mode or a second mode different from the first mode. Each of the plurality of stages outputs an activated first scan signal and an activated second scan signal when operating only in the first mode. Each of the plurality of stages outputs an activated second scan signal when operating only in the second mode. The first stage and the second stage respectively output simultaneously activated second scan signals when operating simultaneously in the first mode and the second mode, respectively.

[0019] According to an embodiment, a display device includes: a display panel in which an active area and a peripheral area adjacent to the active area are defined. The display panel includes: a plurality of pixels disposed in the active area and receiving a first scan signal and a second scan signal; and a scan driver disposed in the peripheral area and connected to the plurality of pixels. The scan driver includes a plurality of stages arranged in sequence. Each of the plurality of stages includes: a first scan output circuit electrically connected to a control node and including a first output node that outputs the first scan signal; a second scan output circuit electrically connected to the control node and including a second output node that outputs the second scan signal; and a compensation circuit connected to the second scan output circuit. The compensation circuit receives the first scan signal, a first clock signal having a first pulse width, and a second clock signal having a second pulse width different from the first pulse width. The compensation circuit outputs a signal corresponding to the first clock signal or the second clock signal according to the first scan signal. The second scan output circuit outputs the second scan signal based on the signal.

[0020] In an embodiment, when second scan signals output from at least two of the plurality of stages are simultaneously activated, a first pulse width of the second scan signal output from one of the at least two stages is different from a second pulse width of the second scan signal output from another of the at least two stages.

[0021] In an embodiment, when the other stage is disposed after the one stage, the second pulse width is narrower than the first pulse width.

[0022] In an embodiment, the compensation circuit includes an inverter circuit connected to the first output node, a multiplexer circuit connected to the first output node and the inverter circuit, and a control circuit connected to the control node and controlling a state of the control node.

[0023] In an embodiment, the display panel operates during a plurality of frames. Each of the plurality of frames operates in at least one of a first mode and a second mode different from the first mode.

[0024] In an embodiment, when operating in the first mode, the plurality of stages sequentially output the first scan signal and the second scan signal. When operating in the second mode, the plurality of stages sequentially output the second scan signal.

[0025] In an embodiment, when the first mode and the second mode operate simultaneously, the one stage generates and outputs the second scan signal based on the first scan signal.

[0026] In an embodiment, when the first mode and the second mode operate simultaneously, the other stage generates and outputs the second scan signal based on the first clock signal. Description of the Drawings

[0027] The above and other objects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0028] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0030] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0031] Figure 4 is a block diagram showing a scan driver and a plurality of pixels according to an embodiment of the present disclosure.

[0032] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0033] Figure 6 is a conceptual diagram showing the operation of a display device according to an embodiment of the present disclosure.

[0034] Figure 7 is a waveform diagram showing first and second scan signals in a first interval and a second interval according to an embodiment of the present disclosure.

[0035] Figure 8 is a waveform diagram showing a second scan signal in a part of a third interval according to an embodiment of the present disclosure.

[0036] Figure 9 shows the operation of a pixel in a first part according to an embodiment of the present disclosure.

[0037] Figure 10 shows the operation of a pixel in a second part according to an embodiment of the present disclosure.

[0038] Figure 11 is according to an embodiment of the present disclosure Figure 4 is a block diagram of the first scan driving circuit shown in

[0039] Figure 12A is a circuit diagram of the j-th stage according to an embodiment of the present disclosure.

[0040] Figure 12B is a circuit diagram showing a compensation unit according to an embodiment of the present disclosure.

[0041] Figure 13 is a waveform diagram of a signal driven in the first stage according to an embodiment of the present disclosure.

[0042] Figure 14It is a waveform diagram of a signal driven in the second stage according to an embodiment of the present disclosure. Detailed Description

[0043] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0044] It will be understood that when a component such as a film, region, layer, etc. is referred to as being "on" another component, "connected to", "coupled to" another component or "adjacent to" another component, it can be directly on the other component, directly connected to, directly coupled to the other component or directly adjacent to the other component, or there may be intervening components. The term "connected to" may mean that the elements are electrically connected to each other. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there may also be one or more intervening components.

[0045] The term "and / or" includes one or more combinations of each of the related elements defined therein.

[0046] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a "first" element in an embodiment may be described as a "second" element in another embodiment.

[0047] It should be understood that the description of the features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments, unless the context clearly indicates otherwise.

[0048] As used herein, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0049] For ease of description, spatial relative terms such as "below", "beneath", "under", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature illustrated in the drawings to another (other) element or feature. It will be understood that the spatial relative terms are also intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as being "below", "beneath" or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the example terms "below" and "beneath" can cover both the upper and lower orientations.

[0050] It will be understood that the terms “comprising,” “including,” “having,” etc. specify the presence of the features, numbers, steps, operations, elements, or components described in the specification, and do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, or components, or combinations thereof.

[0051] Taking into account the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms “about” or “approximate” as used herein include the stated value and refer to an acceptable deviation range of that particular value determined by a person of ordinary skill in the art. For example, “about” or “approximate” can refer to within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] Embodiments of the present disclosure provide a display device having improved display quality and reduced power consumption. The display device according to an embodiment can reduce power consumption by reducing the operation frequency when displaying a still image without degrading the display quality. For example, the display panel can be divided into an active area including a plurality of pixels and a peripheral area including a scan driver. The scan driver can include a plurality of stages that output scan signals to the pixels in the active area, and the scan signals have different pulse widths when simultaneously activated. In an embodiment, when a second stage follows a first stage, the second pulse width can be narrower than the first pulse width. In an embodiment, the display device can include a compensation unit (also referred to as a compensation circuit) that adjusts the pulse width of the second scan signal using an inverter circuit and a multiplexer circuit, and can control the signal based on a clock signal having different pulse widths.

[0053] According to an embodiment of the present disclosure, the display panel can operate in a plurality of frames each capable of operating in a first mode or a second mode. The first mode can sequentially output both a first scan signal and a second scan signal, while the second mode can output only the second scan signal. During an overlapping interval where both modes are operating simultaneously, adjustments can be made to provide high display quality. Embodiments provide a display device that dynamically adjusts its operation frequency and scan signal characteristics to balance power efficiency and display performance.

[0054] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0055] Reference Figure 1 and Figure 2, the display device DD can be a device activated according to an electrical signal. The display device DD can be a small or medium-sized electronic device such as a mobile phone, a tablet PC, a notebook computer, a vehicle navigation system, or a game console, and a large electronic device such as a television or a monitor. The above examples are provided only as examples, and it will be understood that the display device DD can be implemented as another type of display device without departing from the concept of the present disclosure.

[0056] The display device DD can have a rectangular shape with a long side in the first direction DR1 and a short side in the second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited thereto. For example, the display device DD can be implemented in various shapes. The display device DD can display an image IM on a display surface IS parallel to each of the first direction DR1 and the second direction DR2 to face the third direction DR3. The display surface IS on which the image IM is displayed can correspond to the front surface of the display device DD.

[0057] In an embodiment, the front surface (or top surface) and the rear surface (or bottom surface) of each component are defined with respect to the direction in which the image IM is displayed. The front surface can be opposite to the rear surface in the third direction DR3, and the normal direction of each of the front surface and the rear surface can be parallel to the third direction DR3.

[0058] The distance between the front surface and the rear surface in the third direction DR3 can correspond to the thickness of the display device DD in the third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be conceptually relative and can be changed to different directions.

[0059] The display device DD can sense an external input applied from the outside of the display device DD. The external input can include various types of inputs provided from the outside of the display device DD (including, for example, an input provided by a user). For example, the display device DD according to an embodiment of the present disclosure can sense an external input of a user applied from the outside of the display device DD. The external input of the user can be one or a combination of various types of external inputs such as a part of his / her body, light, heat, his / her gaze, and pressure. In addition, depending on the structure of the display device DD, the display device DD can sense an external input of a user applied to the side surface or the rear surface of the display device DD. As an example of the present disclosure, the external input can include an input input through an input device such as a stylus, an active pen, a touch pen, an electronic pen, or an E-pen.

[0060] A display area DA and a non-display area NDA can be defined in the display surface IS of the display device DD. The display area DA refers to the area where the image IM is displayed. The user can perceive (or view) the image IM through the display area DA. In an embodiment, the display area DA is illustrated as a quadrilateral shape with rounded vertices. However, this is only illustrated as an example, and the embodiment is not limited thereto. For example, according to an embodiment of the present disclosure, the display area DA can have various shapes.

[0061] The non-display area NDA can be disposed adjacent to the display area DA. The non-display area NDA can have a given color. The non-display area NDA can surround the display area DA. Accordingly, the shape of the display area DA can be substantially defined by the non-display area NDA. However, this is illustrated as an example. For example, according to an embodiment, the non-display area NDA can be placed to be adjacent to only one side of the display area DA, or can be omitted.

[0062] As Figure 2 shown, the display device DD can include a display module DM and a window WM disposed on the display module DM. The display module DM can include a display panel DP and an input sensing layer ISP.

[0063] The display panel DP according to an embodiment of the present disclosure can be, for example, a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP can be an organic light-emitting display panel, a quantum dot light-emitting display panel, a micro-LED display panel, or a nano-LED display panel. The light-emitting layer of the organic light-emitting display panel can include, for example, an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel can include, for example, quantum dots or quantum rods, etc. The light-emitting layer of the micro-LED display panel can include, for example, micro-LEDs. The light-emitting layer of the nano-LED display panel can include, for example, nano-LEDs.

[0064] The display panel DP can output the image IM, and the output image IM can be displayed through the display surface IS.

[0065] The input sensing layer ISP can be disposed on the display panel DP and can sense an external input. According to an embodiment of the present disclosure, the input sensing layer ISP can be directly disposed on the display panel DP. According to an embodiment of the present disclosure, the input sensing layer ISP can be formed on the display panel DP through a continuous process. That is, according to an embodiment, when the input sensing layer ISP is directly disposed on the display panel DP, an internal adhesive film is not inserted between the input sensing layer ISP and the display panel DP.

[0066] The window WM can be formed of a transparent material capable of outputting the image IM. For example, the window WM can be formed of glass, sapphire, plastic, etc. Although the window WM is illustrated as being implemented with a single layer, the embodiments are not limited thereto. For example, according to an embodiment, the window WM can include multiple layers.

[0067] The non-display area NDA of the above-described display device DD can correspond to an area defined by printing a material including a given color on one area of the window WM. As an example of the present disclosure, the window WM can include a light-shielding pattern that defines the non-display area NDA. For example, the light-shielding pattern can be a colored organic film and can be formed, for example, by a coating method.

[0068] The window WM can be bonded to the display module DM through an adhesive film. As an example of the present disclosure, the adhesive film can include an optically clear adhesive (OCA) film. However, the adhesive film is not limited thereto. For example, the adhesive film can include a typical adhesive or tackifier. For example, the adhesive film can include an optically clear resin (OCR) or a pressure-sensitive adhesive (PSA) film.

[0069] An antireflection layer can be further provided between the window WM and the display module DM. The antireflection layer reduces the reflectance of external light incident from above the window WM. The antireflection layer according to an embodiment of the present disclosure can include a phase retarder and a polarizer. The phase retarder can have a film type or a liquid crystal coating type. The polarizer can also be a polarizer of a film type or a liquid crystal coating type. The film type can include a stretched synthetic resin film, and the liquid crystal coating type can include liquid crystals arranged in a given direction. The phase retarder and the polarizer can be implemented using a single polarizing film.

[0070] As an example of the present disclosure, the antireflection layer can also include a color filter. The arrangement of the color filter can be determined in consideration of the color of light generated from a plurality of pixels PX (see Figure 3 ) included in the display panel DP. In this case, the antireflection layer can further include a light-shielding pattern provided between the color filters.

[0071] The display module DM can display the image IM according to an electrical signal and can send / receive information about an external input. The display module DM can be defined by an active area AA and a non-active area NAA. The active area AA can be defined as an area (e.g., an area where the image IM is displayed) that outputs the image IM from the display panel DP. In addition, the active area AA can be defined as an area where the input sensing layer ISP senses an external input applied from the outside of the display device DD. According to an embodiment, the active area AA of the display module DM can correspond to at least a part of (or overlap with at least a part of) the display area DA.

[0072] The non-active area NAA is disposed adjacent to the active area AA. The non-active area NAA refers to an area that substantially does not display an image IM. For example, the non-active area NAA may surround the active area AA. However, this is illustrated by way of example. The non-active area NAA may be defined in various shapes. According to an embodiment, the non-active area NAA of the display module DM may correspond to at least a part of the non-display area NDA (or overlap with at least a part of the non-display area NDA).

[0073] The display device DD may further include a plurality of flexible films FF connected to the display panel DP. The driver chips DIC may be mounted on each of the flexible films FF. As an example of the present disclosure, the data driver 200 (see Figure 3 ) may include a plurality of driver chips DIC, and the plurality of driver chips DIC may be respectively mounted on the plurality of flexible films FF.

[0074] The display device DD may further include at least one printed circuit board PCB coupled to the plurality of flexible films FF. As an example of the present disclosure, four printed circuit boards PCBs are provided in the display device DD, but the number of the printed circuit boards PCBs is not limited thereto. Two adjacent printed circuit boards PCBs among the printed circuit boards PCBs may be electrically connected to each other through a connection film CF. In addition, at least one of the printed circuit boards PCBs may be electrically connected to the main board. The driving controller 100 (see Figure 3 ) and the voltage generator 400 (see Figure 3 ) may be disposed on at least one of the printed circuit boards PCBs.

[0075] Figure 2 The structure in which the driver chips DIC are respectively mounted on the flexible films FF is illustrated, but the present disclosure is not limited thereto. For example, according to an embodiment, the driver chips DIC may be directly mounted on the display panel DP. In this case, the portion of the display panel DP on which the driver chips DIC are mounted may be bent so that the driver chips DIC are disposed on the rear surface of the display module DM.

[0076] The input sensing layer ISP may be electrically connected to the printed circuit board PCB through the flexible film FF. However, the embodiments of the present disclosure are not limited thereto. That is, the display module DM may further include a separate flexible film that electrically connects the input sensing layer ISP and the printed circuit board PCB.

[0077] The display device DD further includes a housing EDC that houses the display module DM. The housing EDC can be combined with the window WM to define the appearance of the display device DD. The housing EDC can absorb external shocks and prevent foreign objects / substances / moisture, etc. from penetrating into the display module DM, so that the components housed in the housing EDC are protected. As an example of the present disclosure, the housing EDC can be provided in the form of a combination of a plurality of housing members.

[0078] The display device DD according to an embodiment can further include an electronic module including various functional modules for operating the display module DM, a power supply module (e.g., a battery) for supplying power for the overall operation of the display device DD, a bracket that is combined with the display module DM and / or the housing EDC to partition the internal space of the display device DD, etc.

[0079] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0080] Reference Figure 3 , the display device DD can include a driving controller 100, a data driver 200, a display panel DP, and a voltage generator 400.

[0081] The display panel DP can include a scan driver 300 (also referred to as a scan driver circuit), a plurality of first scan lines SCL1 to SCLn, a plurality of second scan lines SSL1 to SSLn, a plurality of data lines DL1 to DLm, a plurality of sense lines RL1 to RLm, and a plurality of pixels PX, where each of n and m is a positive integer. The plurality of first scan lines SCL1 to SCLn can be referred to as "driving scan lines". The plurality of second scan lines SSL1 to SSLn can be referred to as "sense scan lines".

[0082] An active area AR and a peripheral area NA can be defined in the display panel DP. The plurality of pixels PX can be arranged in the active area AR. The scan driver 300 can be provided in the peripheral area NA. The peripheral area NA can be adjacent to the active area AR. The active area AR can correspond to the display area DA (see Figure 1 ). The peripheral area NA can correspond to the non-display area NDA (see Figure 1 ).

[0083] Each of the plurality of first scan lines SCL1 to SCLn can extend in the second direction DR2. The plurality of first scan lines SCL1 to SCLn can be arranged spaced apart from each other in the first direction DR1.

[0084] Each of the plurality of second scan lines SSL1 to SSLn can extend in the second direction DR2. The plurality of second scan lines SSL1 to SSLn can be arranged spaced apart from each other in the first direction DR1.

[0085] Each of the plurality of data lines DL1 to DLm may extend from the data driver 200 in a first direction DR1. The plurality of data lines DL1 to DLm may be arranged spaced apart from each other in a second direction DR2.

[0086] Each of the plurality of sense lines RL1 to RLm may extend from the data driver 200 in a first direction DR1. The plurality of sense lines RL1 to RLm may be arranged spaced apart from each other in a second direction DR2.

[0087] The plurality of pixels PX may be electrically connected to the plurality of first scan lines SCL1 to SCLn, the plurality of second scan lines SSL1 to SSLn, the plurality of data lines DL1 to DLm, and the plurality of sense lines RL1 to RLm. Each of the plurality of pixels PX may be electrically connected to two scan lines. However, this is an example, and the number of scan lines connected to each of the plurality of pixels PX according to an embodiment of the present disclosure is not limited thereto.

[0088] The driving controller 100 may receive an input image signal RGB and a control signal CTRL from a main controller (e.g., a microcontroller or a graphics processing unit (GPU)). The driving controller 100 may generate image data DATA by converting the input image signal RGB.

[0089] The driving controller 100 may generate a scan control signal GCS and a data control signal DCS based on the control signal CTRL. The data driver 200 may receive the data control signal DCS and the image data DATA from the driving controller 100. The data driver 200 may convert the image data DATA into a data signal in response to the data control signal DCS. The data driver 200 may output the data signal to the plurality of data lines DL1 to DLm. The data signal may be an analog voltage corresponding to the gray value of the image data DATA.

[0090] The data driver 200 may be connected to the plurality of sense lines RL1 to RLm. The data driver 200 may further receive a sense control signal from the driving controller 100, and may sense the characteristics of the elements included in each of the pixels PX of the display panel DP in response to the sense control signal.

[0091] As an example of the present disclosure, the data driver 200 may be formed in the form of at least one chip. For example, the data driver 200 may be provided in Figure 2 the driver chip DIC shown in.

[0092] The scan driver 300 may receive a scan control signal GCS from the driving controller 100. The scan driver 300 may output a scan signal in response to the scan control signal GCS. The scan driver 300 may include a plurality of transistors, which will be described in more detail below.

[0093] The scan driver 300 may generate a first scan signal and a second scan signal in response to the scan control signal GCS. The first scan signal may be referred to as a driving scan signal. The second scan signal may be referred to as a sensing scan signal. The first scan signal may be applied to a plurality of first scan lines SCL1 to SCLn. The second scan signal may be applied to a plurality of second scan lines SSL1 to SSLn.

[0094] As an example of the present disclosure, the scan driver 300 may include a first scan driver 310 and a second scan driver 320. The first scan driver 310 may be disposed on the left side of the active region AR. The second scan driver 320 may be disposed on the right side of the active region AR. The first scan driver 310 may receive a first scan control signal GCS1 from the driving controller 100, and the second scan driver 320 may receive a second scan control signal GCS2 from the driving controller 100. The first scan driver 310 may generate a plurality of first scan signals and a plurality of second scan signals in response to the first scan control signal GCS1. The second scan driver 320 may generate a plurality of first scan signals and a plurality of second scan signals in response to the second scan control signal GCS2.

[0095] Figure 3 A structure is shown in which the first scan driver 310 and the second scan driver 320 are respectively located on the left and right sides of the active region AR. However, the present disclosure is not limited thereto. For example, according to an embodiment, the scan driver 300 may include only one of the first scan driver 310 and the second scan driver 320.

[0096] Each of the plurality of pixels PX may receive a first driving voltage ELVDD and a second driving voltage ELVSS.

[0097] The voltage generator 400 may generate voltages for the operation of the display panel DP. In an embodiment of the present disclosure, the voltage generator 400 may generate a first driving voltage ELVDD and a second driving voltage ELVSS for the operation of the display panel DP. The first driving voltage ELVDD and the second driving voltage ELVSS may be provided to the display panel DP through a first driving voltage line VL1 and a second driving voltage line VL2, respectively.

[0098] In addition to generating the first driving voltage ELVDD and the second driving voltage ELVSS, the voltage generator 400 may further generate various voltages for the operations of the data driver 200 and the scan driver 300 (e.g., gamma reference voltage, data driving voltage, high voltage VGH (see Figure 12B ), and low voltage VGL (see Figure 12B ).

[0099] Figure 4 is a block diagram showing a scan driver and a plurality of pixels according to an embodiment of the present disclosure.

[0100] Referring to Figure 4 , among the plurality of pixels PX11 to PXnm (where each of n and m is a positive integer), the pixels arranged in the same row (e.g., PX11 to PX1m) may be connected to two scan lines (e.g., SCL1 and SSL1). Among the plurality of pixels PX11 to PXnm, the pixels arranged in the same column (e.g., PX11 to PXn1) may be connected to a data line (e.g., DL1) and a sensing line (e.g., RL1).

[0101] The first scan driver 310 may be connected to one side of the scan lines SCL1 to SCLn and SSL1 to SSLn, and the second scan driver 320 may be connected to the other side (e.g., the opposite side) of the scan lines SCL1 to SCLn and SSL1 to SSLn.

[0102] Each of the first scan driver 310 and the second scan driver 320 may include a plurality of stages ST1 to STn arranged in sequence. As an example of the present disclosure, each of the plurality of stages ST1 to STn may output a first scan signal SC and a second scan signal SS.

[0103] For example, the first stage ST1 may be connected to the first scan line SCL1 and the second scan line SSL1. The first stage ST1 may output the first scan signal SC to the first scan line SCL1, and may output the second scan signal SS to the second scan line SSL1.

[0104] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0105] Figure 5 shows Figure 4 an equivalent circuit diagram of one pixel PX11 among the plurality of pixels PX11 to PXnm shown in Figure 4 ), where each of n and m is a positive integer. Since the plurality of pixels PX11 to PXnm (see Figure 4) each has the same circuit structure with pixel PX11, so for ease of explanation, the detailed description of pixels other than pixel PX11 is omitted.

[0106] Reference Figure 5 , pixel PX11 can be electrically connected to corresponding lines including a first data line DL1, a first scan line SCL1, a second scan line SSL1, and a sense line RL1.

[0107] Pixel PX11 can include a light-emitting element ED and a pixel circuit unit PXC that controls the light emission of the light-emitting element ED.

[0108] The light-emitting element ED can be a light-emitting diode. As an example of the present disclosure, the light-emitting element ED can be an organic light-emitting diode including an organic light-emitting layer. The light-emitting element ED can be, for example, one of a red light-emitting diode that emits red light, a green light-emitting diode that emits green light, and a blue light-emitting diode that emits blue light.

[0109] The pixel circuit unit PXC can include multiple transistors and at least one capacitor. For example, the pixel circuit unit PXC can include first to third transistors PT1, PT2, and PT3 and a capacitor Cst. Each of the first to third transistors PT1, PT2, and PT3 can be an N-type transistor. However, the present disclosure is not limited thereto. For example, in an embodiment, each of the first to third transistors PT1, PT2, and PT3 can be a P-type transistor. Alternatively, in an embodiment, some of the first to third transistors PT1, PT2, and PT3 can be N-type transistors, and others of the first to third transistors PT1, PT2, and PT3 can be P-type transistors. In addition, in an embodiment, at least one of the first to third transistors PT1, PT2, and PT3 can be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer.

[0110] The pixel circuit unit PXC can be formed by the same process as the scan driver 300.

[0111] The first transistor PT1 can be connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and a light-emitting element ED. The first transistor PT1 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the anode of the light-emitting element ED, and a third electrode connected to one end of a capacitor Cst. Here, the contact point where the anode of the light-emitting element ED is connected to the second electrode of the first transistor PT1 may be referred to as a first node N1. In this specification, "a transistor is connected to a signal line" means that one of the first electrode, the second electrode, and the third electrode of the transistor is integrated with the signal line or connected to the signal line through a connecting electrode. In addition, "a transistor is electrically connected to another transistor" means that one of the first electrode, the second electrode, and the third electrode of this transistor is integrated with one of the first electrode, the second electrode, and the third electrode of the other transistor or connected to one of the first electrode, the second electrode, and the third electrode of the other transistor through a connecting electrode.

[0112] The first transistor PT1 can receive a data voltage V_data transmitted through a first data line DL1 according to the switching operation of a second transistor PT2, and then can supply a driving current Id to the light-emitting element ED.

[0113] The second transistor PT2 is connected between the first data line DL1 and the third electrode of the first transistor PT1. The second transistor PT2 includes a first electrode connected to the first data line DL1, a second electrode connected to the third electrode of the first transistor PT1, and a third electrode connected to a first scan line SCL1. Here, the contact point where the second electrode of the second transistor PT2 is connected to the third electrode of the first transistor PT1 may be referred to as a second node N2. The second transistor PT2 is turned on in response to a first scan signal SC received through the first scan line SCL1, and can transmit the data voltage V_data transmitted from the first data line DL1 to the third electrode of the first transistor PT1.

[0114] The third transistor PT3 is connected between the second electrode of the first transistor PT1 and a sense line RL1. The third transistor PT3 includes a first electrode connected to the first node N1, a second electrode connected to the sense line RL1, and a third electrode connected to a second scan line SSL1. The third transistor PT3 is turned on in response to a second scan signal SS received through the second scan line SSL1 so as to electrically connect the sense line RL1 and the first node N1.

[0115] One end of the capacitor Cst is connected to the second node N2, and the other end thereof is connected to the first node N1. The cathode of the light-emitting element ED may be connected to the second driving voltage line VL2 to which the second driving voltage ELVSS is supplied. The voltage level of the second driving voltage ELVSS may be lower than the voltage level of the first driving voltage ELVDD.

[0116] The light-emitting element ED may include an anode connected to the second electrode (or the first node N1) of the first transistor PT1 and a cathode receiving the second driving voltage ELVSS. The light-emitting element ED may generate light corresponding to the amount of current supplied from the first transistor PT1. A light-emitting capacitor CEL may be defined between the anode and the cathode of the light-emitting element ED.

[0117] Figure 6 is a conceptual diagram showing the operation of a display device according to an embodiment of the present disclosure.

[0118] Reference Figure 3 and Figure 6 , the display panel DP may operate during a plurality of frames FR. The display panel DP may display an image IM in units of a driving frame DF1 or DF2 generated based on the plurality of frames FR (see Figure 1 ).

[0119] Each of the plurality of frames FR may operate in a first mode MD1 or a second mode MD2. The display device DD may change the operation frequency by using the frames FR operating in the second mode MD2. Each of the plurality of frames FR may further include a blank interval VB. The blank interval VB may be provided after each of the plurality of frames FR operates in the first mode MD1 or the second mode MD2.

[0120] Figure 6 Shows a first scan signal SC and / or a second scan signal SS sequentially driven in the arrow direction.

[0121] When operating only in the first mode MD1, each of the plurality of stages ST1 and ST2 to STn (see Figure 4 ) (where n is a positive integer) may output the first scan signal SC and the second scan signal SS. A first interval “A” may be defined as an interval of the first scan signal SC and the second scan signal SS operating in the first mode MD1.

[0122] When operating only in the second mode MD2, each of the plurality of stages ST1 and ST2 to STn (see Figure 4 ) may output the second scan signal SS. A second interval “B” may be defined as an interval of the second scan signal SS operating in the second mode MD2.

[0123] According to an embodiment of the present disclosure, the display device DD may synchronize the frame generation timing of the graphics processing device included in the display device DD with the frame output timing of the display panel DP. In other words, the display panel DP may operate at a variable operating frequency. For example, in a specific operating environment such as displaying a still image, the operating frequency of the display panel DP may be reduced. Accordingly, a display device DD with reduced power consumption may be provided.

[0124] Each of the plurality of frames FR may have a time of approximately 2.1 milliseconds (ms). In this case, each of the plurality of frames FR may have a frequency of approximately 480 Hertz (Hz). However, this is an example, and the time of each of the plurality of frames FR according to an embodiment of the present disclosure is not limited thereto. For example, according to an embodiment, each of the plurality of frames FR may have a time of approximately 4.2 ms.

[0125] For example, when the graphics processing device generates a driving frame DF1 having an operating frequency of approximately 240 Hz, the scan driver 300 may control the frame FR to drive the frame FR operating in the first mode MD1 once and drive the frame FR operating in the second mode MD2 once during the driving frame DF1, so that the display panel DP operates at an operating frequency of approximately 240 Hz.

[0126] When the graphics processing device generates a driving frame having an operating frequency of approximately 160 Hz, the scan driver 300 may control the frame FR to drive the frame FR operating in the first mode MD1 once and drive the frame FR operating in the second mode MD2 twice during the driving frame, so that the display panel DP operates at an operating frequency of approximately 160 Hz.

[0127] Therefore, when controlling the operating frequency by using the entire frame FR operating in the second mode MD2, during the first driving frame DF1 at this time, the display panel DP may be defined as operating at an integer multiple variable frequency.

[0128] For example, when the graphics processing device generates a driving frame DF2 having an operating frequency of approximately 360 Hz, the scan driver 300 may control the frame FR to drive the frame FR operating in the first mode MD1 once during the driving frame DF2, and may use a part of the frame FR operating in the second mode MD2 to make the display panel DP operate at an operating frequency of approximately 360 Hz.

[0129] Therefore, when controlling the operating frequency by using a part of the frame FR operating in the second mode MD2, during the second driving frame DF2 at this time, the display panel DP may be defined as operating at a non-integer multiple variable frequency.

[0130] The frame FR after the second driving frame DF2 operating at a non-integer multiple variable frequency may overlap with the remaining portion of the frame FR that was previously included in the second driving frame DF2 and operating in the second mode MD2. The interval at this time can be defined as the overlapping interval PD.

[0131] In the overlapping interval PD, the first mode MD1 and the second mode MD2 can operate simultaneously.

[0132] Pixels X1 and X2 arranged in the same column can be defined as pixels operating in the first mode MD1 and the second mode MD2 respectively in the overlapping interval PD.

[0133] Figure 6 Shows multiple levels ST1 and ST2 to STn (see Figure 4 ) among which the first level STa and the second level STb respectively operate pixels X1 and X2.

[0134] The first pixel X1 can operate in the first mode MD1. The first level STa can provide the first scan signal SC and the second scan signal SS to the first pixel X1. The second pixel X2 can operate in the second mode MD2. The second level STb can provide the second scan signal SS to the second pixel X2.

[0135] In the overlapping interval PD, the first level STa and the second level STb can output the second scan signal SS simultaneously. In the overlapping interval PD, the first level STa operating in the first mode MD1 can output the first scan signal SC and the second scan signal SS, and the second level STb operating in the second mode MD2 can output the second scan signal SS.

[0136] The third interval "C" can be defined as the interval of the first scan signal SC and the second scan signal SS operating in the first mode MD1 and the second mode MD2 respectively.

[0137] Figure 7 Is a waveform diagram showing the first scan signal and the second scan signal in the first interval and the second interval according to an embodiment of the present disclosure.

[0138] Figure 7 Shows in the first interval "A" (see Figure 6 ) and the second interval "B" (see Figure 6 ) the waveforms of the first scan signal SC (see Figure 6 ) and the second scan signal SS (see Figure 6 ).

[0139] Refer to Figure 5 、 Figure 6 and Figure 7, during the first mode MD1, the first interval "A" can be repeated. The first interval "A" can be referred to as a programming interval. The first interval "A" can include a 1-1 sub-interval A1 and a 1-2 sub-interval A2. The 1-1 sub-interval A1 and the 1-2 sub-interval A2 can be consecutive to each other. The 1-2 sub-interval A2 can be the remaining interval in the first interval "A" after the operation of the 1-1 sub-interval A1 is completed.

[0140] During the 1-1 sub-interval A1, each of the first scan signal SC and the second scan signal SS can be activated.

[0141] The activation interval of the first scan signal SC can overlap with the activation interval of the second scan signal SS. As an example of the present disclosure, the activation interval can be defined as a high-level interval. The activation interval of each of the first scan signal SC and the second scan signal SS can have a first pulse width PWD1. For example, the first pulse width PWD1 can be 2 horizontal time periods.

[0142] The second transistor PT2 can be turned on in response to the first scan signal SC, and the third transistor PT3 can be turned on in response to the second scan signal SS.

[0143] The data voltage V_data can be applied to the second node N2 through the first data line DL1 and the turned-on second transistor PT2. That is to say, the data voltage V_data can be applied to the third electrode of the first transistor PT1.

[0144] The initialization voltage VINT can be applied to the first node N1 through the sense line RL1 and the turned-on third transistor PT3. That is to say, the initialization voltage VINT can be applied to the second electrode of the first transistor PT1 and the anode of the light-emitting element ED. In this case, the light-emitting capacitor CEL of the light-emitting element ED can be discharged.

[0145] The voltage between the first node N1 and the second node N2 can be set to the difference between the data voltage V_data and the initialization voltage VINT. The charge corresponding to the difference between the data voltage V_data and the initialization voltage VINT can be stored in the capacitor Cst. The voltage between the first node N1 and the second node N2 can be defined as the gate-source voltage of the first transistor PT1.

[0146] During the 1-2 sub-interval A2, the first scan signal SC and the second scan signal SS can be deactivated. The second transistor PT2 and the third transistor PT3 can be turned off.

[0147] Depending on the voltage between the gate and the source of the first transistor PT1, current can flow to the light-emitting element ED. In response to the current, the light-emitting element ED can emit light. At this time, the light-emitting capacitor CEL can be charged by the flowing current.

[0148] During the second mode MD2, the second period "B" can be repeated. The second period "B" can be referred to as the initial period. The second period "B" can include a 2-1 sub-period B1 and a 2-2 sub-period B2. The 2-1 sub-period B1 and the 2-2 sub-period B2 can be continuous with each other. The 2-2 sub-period B2 can be the remaining period in the second period "B" after the operation of the 2-1 sub-period B1 is completed.

[0149] During the 2-1 sub-period B1, the first scan signal SC can be deactivated, and the second scan signal SS can be activated. The activation period of the second scan signal SS can have a second pulse width PWD2. However, this is an example, and the pulse width of the activation period of the second scan signal SS during the 2-1 sub-period B1 is not limited to this. For example, in an embodiment, the activation period of the second scan signal SS during the 2-1 sub-period B1 can have a first pulse width PWD1. The second pulse width PWD2 can be different from the first pulse width PWD1. The second pulse width PWD2 can be narrower than the first pulse width PWD1.

[0150] The second transistor PT2 can be turned off in response to the first scan signal SC, and the third transistor PT3 can be turned on in response to the second scan signal SS.

[0151] Even if the second transistor PT2 is turned off, the voltage between the first node N1 and the second node N2 can be held by the capacitor Cst. That is, the voltage between the gate and the source of the first transistor PT1 can be held.

[0152] For example, during the first period "A", the voltage level of the first node N1 can be the anode voltage (Vanode) of the light-emitting element ED, and the voltage level of the second node N2 can be a value obtained by adding the anode voltage (Vanode) and the voltage between the gate and the source of the first transistor PT1 (Vgs). During the second period "B", the voltage level of the first node N1 can be a value obtained by subtracting the initialization voltage VINT from the anode voltage (Vanode), and the voltage level of the second node N2 can be a value obtained by adding the voltage between the gate and the source of the first transistor PT1 (Vgs) to the anode voltage (Vanode) and then subtracting the initialization voltage VINT from the added result. That is, the gate-source voltage (Vgs) between the second node N2 and the first node N1 can be held constant.

[0153] The initialization voltage VINT can be applied to the first node N1 through the sensing line RL1 and the turned-on third transistor PT3. That is, the initialization voltage VINT can be applied to the second electrode of the first transistor PT1 and the anode of the light-emitting element ED. In this case, the light-emitting capacitor CEL of the light-emitting element ED can be discharged.

[0154] Referring to the comparative example, when the 2-1 sub-interval B1 does not exist, the charging time of the light-emitting capacitor CEL may increase due to the light-emitting intervals in the 1-2 sub-interval A2 and the 2-2 sub-interval B2. Charging the light-emitting capacitor CEL may increase the voltage of the first node N1. By increasing the current flowing through the light-emitting element ED, the brightness may be increased. However, according to an embodiment of the present disclosure, the second interval "B" may include the 2-1 sub-interval B1. During the 2-1 sub-interval B1, the light-emitting capacitor CEL of the light-emitting element ED can be discharged. The brightness of the light emitted from the light-emitting element ED can be kept constant. Accordingly, a display device DD with improved display quality can be provided (see Figure 1 ).

[0155] Figure 8 is a waveform diagram of a second scan signal in a part of a third interval according to an embodiment of the present disclosure. Figure 9 illustrates the operation of a pixel in a first part according to an embodiment of the present disclosure. Figure 10 illustrates the operation of a pixel in a second part according to an embodiment of the present disclosure. When referring to Figure 9 and Figure 10 , for ease of explanation and to avoid redundancy, the same reference numerals are assigned to the same components described with reference to Figure 5 .

[0156] Referring to Figure 6 , Figure 8 , Figure 9 and Figure 10 , the overlapping interval PD may be an interval in which the first mode MD1 and the second mode MD2 are driven simultaneously. For example, in non-integer multiple variable frequency operation, when a subsequent frame FR starts while a current frame FR is not completed, the subsequent frame FR can operate while the current frame FR is operating.

[0157] The third interval "C" can be repeated during the overlapping interval PD. The third interval "C" of the first stage STa can be a programming interval, and the third interval "C" of the second stage STb can be an initial interval.

[0158] In the overlapping interval PD, the first pixel X1 can operate in the first mode MD1, and the second pixel X2 can operate in the second mode MD2.

[0159] The first-stage STa can provide the second scan signal SS to the first pixel X1. The second scan signal SS output to the first pixel X1 can be defined as the 2-1 scan signal SSa.

[0160] The second-stage STb can provide the second scan signal SS to the second pixel X2. The second-stage STb can be arranged after the first-stage STa. The second scan signal SS output to the second pixel X2 can be defined as the 2-2 scan signal SSb.

[0161] When the second scan signals SS respectively output from the first-stage STa and the second-stage STb are simultaneously activated, the first pulse width PWD1 of the 2-1 scan signal SSa can be different from the second pulse width PWD2 of the 2-2 scan signal SSb. The second pulse width PWD2 can be narrower than the first pulse width PWD1. For example, the second pulse width PWD2 can be half of the first pulse width PWD1. In this case, the second pulse width PWD2 can be 1 horizontal period.

[0162] Figure 9 Illustrates the operations of the first pixel X1 and the second pixel X2 in the first part P1.

[0163] Each of the 2-1 scan signal SSa and the 2-2 scan signal SSb can be activated in the first part P1.

[0164] The first pixel X1 can operate in the first mode MD1. The first scan signal SC and the 2-1 scan signal SSa can be activated. The second transistor PT2 and the third transistor PT3 of the first pixel X1 can be turned on. In this case, the initialization voltage VINT can be applied to the first node N1 of the first pixel X1 through the first path L1. During the first part P1, the first node N1 of the first pixel X1 can be initialized by the initialization voltage VINT.

[0165] The second pixel X2 can operate in the second mode MD2. The first scan signal SC can be deactivated, and the 2-2 scan signal SSb can be activated. The third transistor PT3 of the second pixel X2 can be turned on. At this time, the initialization voltage VINT can be applied to the first node N1 of the second pixel X2 through the second path L2. During the first part P1, the light-emitting capacitor CEL of the second pixel X2 (see Figure 5 ) can be discharged.

[0166] In the first part P1, the initialization voltage VINT can be applied to the first pixel X1 and the second pixel X2 through the first path L1 and the second path L2 respectively.

[0167] Figure 10Shows the operations of the first pixel X1 and the second pixel X2 in the second part P2 according to an embodiment of the present disclosure.

[0168] In the second part P2, the 2-1 scan signal SSa may be activated, and the 2-2 scan signal SSb may be deactivated.

[0169] The first pixel X1 may operate in the first mode MD1. The first scan signal SC and the 2-1 scan signal SSa may be activated. The second transistor PT2 and the third transistor PT3 of the first pixel X1 may be turned on. In this case, the initialization voltage VINT may be applied to the first node N1 of the first pixel X1 through the first path L1. During the second part P2, the first node N1 of the first pixel X1 may be initialized by the initialization voltage VINT. During the second part P2, the initialization voltage VINT may be applied only to the pixels operating in the first mode MD1.

[0170] The second pixel X2 may operate in the second mode MD2. However, through the operations in the overlapping period PD, the first scan signal SC and the 2-2 scan signal SSb may be deactivated.

[0171] That is to say, in the overlapping period PD, the second pulse width PWD2 of the second scan signal SS output from the levels ST1 to STn (see Figure 4 ) among which operate in the second mode MD2 can be controlled. The first pulse width PWD1 of the second scan signal SS output from the levels ST1 to STn (see Figure 4 ) among which operate in the first mode MD1 in the overlapping period PD may be wider than the second pulse width PWD2.

[0172] Referring to the comparative example, when the pulse widths of the 2-1st scan signal SSa and the 2-2nd scan signal SSb are the same, the initialization voltage VINT in the overlapping period PD can always be applied to the first pixel X1 and the second pixel X2 through the first path L1 and the second path L2, respectively. In this case, the initialization voltage VINT needs to be supplied to the first pixel X1 and the second pixel X2, resulting in poor charging. Poor charging of the initialization voltage VINT may occur at the first node N1 of the first pixel X1, causing the voltage level of the gate-source voltage of the first transistor PT1 to be reduced. For this reason, the brightness of the light emitted by the first pixel X1 may be reduced. However, according to an embodiment of the present disclosure, even if the operations of the first mode MD1 and the second mode MD2 overlap in the overlapping period PD, the 2-2nd scan signal SSb can be controlled to be deactivated during the second part P2. In the first pixel X1 operating in the first mode MD1, during the second part P2, the first node N1 can be easily charged with the initialization voltage VINT. Accordingly, a display device DD with improved display quality can be provided (see Figure 1 ).

[0173] Figure 11 is a block diagram of the first scan driving circuit shown in Figure 4 according to an embodiment of the present disclosure.

[0174] Although Figure 11 only five stages ST1 to ST5 are shown therein, the remaining stages may also have a similar structure thereto.

[0175] Referring to Figure 4 and Figure 11 , each of the multiple stages ST1 to ST5 may include an input terminal IN, a control terminal CT, a carry terminal CR, a first output terminal OT1, and a second output terminal OT2. In addition, each of the multiple stages ST1 to ST5 may further include a first clock terminal CK1 to a third clock terminal CK3 and a first voltage terminal VT1 to a third voltage terminal VT3.

[0176] The input terminal IN may receive a previous carry signal or a start signal FLM output from the carry terminal CR of one of the previous stages. The start signal FLM may be a dummy carry signal output from a dummy stage before the first stage ST1 or a signal provided by the driving controller 100 (see Figure 3 ). The control terminal CT may receive a subsequent carry signal output from the carry terminal CR of one of the subsequent stages. The wiring connecting the carry terminal CR of each stage to the input terminal IN of one of the subsequent stages and the control terminal CT of one of the previous stages may be defined as a carry wiring CR_CL.

[0177] Each of the multiple stages ST1 to ST5 may receive three clock signals through first to third clock terminals CK1, CK2, and CK3. Among the multiple stages ST1 to ST5, the first clock terminal CK1 of the odd-numbered stages ST1, ST3, and ST5 may receive a first driving clock signal SC_CKO, the second clock terminal CK2 may receive a first sensing clock signal SS_CKO, and the third clock terminal CK3 may receive a first carry clock signal CR_CKO. The first clock terminal CK1 of the even-numbered stages ST2 and ST4 may receive a second driving clock signal SC_CKE, its second clock terminal CK2 may receive a second sensing clock signal SS_CKE, and its third clock terminal CK3 may receive a second carry clock signal CR_CKE.

[0178] The first driving clock signal SC_CKO and the second driving clock signal SC_CKE have the same period as each other and may have different phases from each other. For example, the first driving clock signal SC_CKO and the second driving clock signal SC_CKE may have opposite phases. The first sensing clock signal SS_CKO and the second sensing clock signal SS_CKE have the same period as each other and may have different phases from each other. For example, the first sensing clock signal SS_CKO and the second sensing clock signal SS_CKE may have opposite phases. The first carry clock signal CR_CKO and the second carry clock signal CR_CKE have the same period as each other and may have different phases from each other. For example, the first carry clock signal CR_CKO and the second carry clock signal CR_CKE may have opposite phases.

[0179] The first voltage terminal VT1, the second voltage terminal VT2, and the third voltage terminal VT3 may receive first to third low voltages VSS1, VSS2, and VSS3, respectively. Each of the first to third low voltages VSS1, VSS2, and VSS3 may have a direct current (DC) voltage level. The first to third low voltages VSS1, VSS2, and VSS3 may have different voltage levels from each other.

[0180] Multiple stages ST1 to ST5 can output first scan signals SC1 to SC5 and second scan signals SS1 to SS5 on first scan lines SCL1 to SCL5 and second scan lines SSL1 to SSL5. The first output terminal OT1 and the second output terminal OT2 of the first stage ST1 can be respectively connected to the first scan line SCL1 and the second scan line SSL1, and can respectively output the first scan signal SC1 and the second scan signal SS1 to the first scan line SCL1 and the second scan line SSL1. The first output terminal OT1 and the second output terminal OT2 of the second stage ST2 can be respectively connected to the first scan line SCL2 and the second scan line SSL2, and can respectively output the first scan signal SC2 and the second scan signal SS2 to the first scan line SCL2 and the second scan line SSL2.

[0181] Figure 12A is a circuit diagram of the j-th stage according to an embodiment of the present disclosure.

[0182] Reference Figure 11 and Figure 12A , the circuit configuration of the j-th stage STj (hereinafter referred to as "stage") among multiple stages ST1 to STn (see Figure 4 ) is described. Since each of the multiple stages ST1 to STn (see Figure 4 ) has the same circuit configuration, for the sake of convenience of explanation and to avoid redundancy, the description of the circuit configurations of the remaining stages among the multiple stages ST1 to STn (see Figure 4 ) is omitted. Here, "j" is a positive integer greater than 1 and less than "n".

[0183] The stage STj can include a first scan output unit SC_OCj (also referred to as a first scan output circuit), a second scan output unit SS_OCj (also referred to as a second scan output circuit), a carry output unit CR_OCj (also referred to as a carry output circuit), a controller CCj (also referred to as a controller circuit), and a compensation unit CPCj (also referred to as a compensation circuit).

[0184] The first scan output unit SC_OCj may include first to third buffer transistors T6, T7, and T8, a first capacitor C1, and a first output node ON1. The first scan output unit SC_OCj may be connected to a first output terminal OT1, a first clock terminal CK1, and a third voltage terminal VT3. The first output terminal OT1 may be connected to the first output node ON1. The first scan output unit SC_OCj may output the j-th first scan signal SCj (hereinafter referred to as the "first scan signal") to the first output node ON1 through the first clock terminal CK1 based on the voltage of the first control node QN and the first driving clock signal SC_CKO. The first scan signal SCj may be output to the first output terminal OT1.

[0185] The first buffer transistor T6 may output the first driving clock signal SC_CKO as the first scan signal SCj based on the voltage of the first control node QN and the first driving clock signal SC_CKO.

[0186] The first capacitor C1 may be connected between the gate and the source of the first buffer transistor T6 to perform a bootstrap operation.

[0187] The second buffer transistor T7 may output the third low voltage VSS3 as the first scan signal SCj in response to the voltage of the second control node of the subsequent stage.

[0188] The third buffer transistor T8 may output the third low voltage VSS3 as the first scan signal SCj in response to the voltage of the second control node QBN.

[0189] The second scan output unit SS_OCj may include fourth to sixth buffer transistors T9, T10, and T11, a second capacitor C2, and a second output node ON2. The second scan output unit SS_OCj may be connected to a second output terminal OT2, a compensation unit CPCj, and a third voltage terminal VT3. The second output terminal OT2 may be connected to the second output node ON2. The second scan output unit SS_OCj may output the j-th second scan signal SSj (hereinafter referred to as the "second scan signal") to the second output node ON2 through the second clock terminal CK2. The second scan signal SSj may be output to the second output terminal OT2.

[0190] The fourth buffer transistor T9 may output the first sense clock signal SS_CKO as the second scan signal SSj based on the voltage of the first control node QN and the first sense clock signal SS_CKO.

[0191] The second capacitor C2 may be connected between the gate and the source of the fourth buffer transistor T9 to perform a bootstrap operation.

[0192] The fifth buffer transistor T10 can output a third low voltage VSS3 as a second scan signal SSj in response to the voltage of the second control node of a subsequent stage.

[0193] The sixth buffer transistor T11 can output a third low voltage VSS3 as a second scan signal SSj in response to the voltage of the second control node QBN.

[0194] The carry output unit CR_OCj can include seventh to ninth buffer transistors T12, T13, and T14. The carry output unit CR_OCj can be connected to a carry terminal CR and a third clock terminal CK3. Accordingly, the carry output unit CR_OCj can receive a first carry clock signal CR_CKO through the voltage of the first control node QN and the third clock terminal CK3, and can output a carry signal CRj to the carry terminal CR.

[0195] The seventh buffer transistor T12 can output the first carry clock signal CR_CKO as a carry signal CRj based on the voltage of the first control node QN and the first carry clock signal CR_CKO.

[0196] The eighth buffer transistor T13 can output a first low voltage VSS1 as a carry signal CRj in response to the voltage of the second control node of a subsequent stage.

[0197] The ninth buffer transistor T14 can output a first low voltage VSS1 as a carry signal CRj in response to the voltage of the second control node QBN.

[0198] The controller CCj can be connected to an input terminal IN, a control terminal CT, and first and second voltage terminals VT1 and VT2. The controller CCj can be further connected to a plurality of signal terminals S1, S2, S3, S5, and S6.

[0199] The controller CCj can include a plurality of control transistors T1-1, T1-2, T2-1, T2-2, T3-1, T3-2, T4-1, T4-2, T5-1, T5-2, T15-1, T15-2, T16 to T24, T25-1, T25-2, T26, T27, T28-1, and T28-2, and a third capacitor C3.

[0200] Some of the plurality of control transistors T1-1, T1-2, T2-1, T2-2, T3-1, T3-2, T4-1, T4-2, T5-1, T5-2, T15-1, T15-2, T16 to T24, T25-1, T25-2, T26, T27, T28-1, and T28-2 can be implemented with dual transistors.

[0201] The controller CCj may include a first control node QN and a second control node QBN. The first control node QN may be electrically connected to a first scan output unit SC_OCj, a second scan output unit SS_OCj, and a carry output unit CR_OCj.

[0202] A plurality of control transistors T1-1, T1-2, T2-1, T2-2, T3-1, T3-2, T4-1, T4-2, T5-1, T5-2, T16, T19, T25-1, T25-2, T28-1, and T28-2 may be further connected to the first control node QN. The wiring for connecting the plurality of control transistors T1-1, T1-2, T2-1, T2-2, T3-1, T3-2, T4-1, T4-2, T5-1, T5-2, T16, T19, T25-1, T25-2, T28-1, and T28-2 to the gates of a first buffer transistor T6, a fourth buffer transistor T9, and a seventh buffer transistor T12 at the first control node QN may be referred to as "first control wiring".

[0203] The second control node QBN may be connected to the gates of a third buffer transistor T8, a sixth buffer transistor T11, and a ninth buffer transistor T14. A plurality of control transistors T18, T19, T20, and T26 may be further connected to the second control node QBN. The wiring for connecting the plurality of control transistors T18, T19, T20, and T26 to the gates of the third buffer transistor T8, the sixth buffer transistor T11, and the ninth buffer transistor T14 at the second control node QBN may be referred to as "second control wiring".

[0204] Fourth control transistors T4-1 and T4-2 may provide a previous carry signal CRj-3 to the first control node QN in response to the previous carry signal CRj-3.

[0205] Second control transistors T2-1 and T2-2 may provide a first low voltage VSS1 to the first control node QN in response to a subsequent carry signal CRj+4.

[0206] First control transistors T1-1 and T1-2 may provide a first low voltage VSS1 to the first control node QN in response to a control signal received through a fifth signal terminal S5.

[0207] Each of the first, second, and fourth control transistors T1-1, T1-2, T2-1, T2-2, T4-1, and T4-2 may be implemented as a dual transistor including two sub-transistors.

[0208] The 28th control transistors T28-1 and T28-2 can supply the high voltage VGH received through the sixth signal terminal S6 to the node between the sub-transistors of the dual transistor in response to the voltage of the first control node QN. In an embodiment, the 28th control transistors T28-1 and T28-2 can also be implemented as a dual transistor including two sub-transistors.

[0209] The third, fifth, and fifteenth to twentieth control transistors T3-1, T3-2, T5-1, T5-2, T15-1, T15-2, T16, T17, T18, T19, and T20 can perform an inverting operation such that the first control node QN and the second control node QBN have voltages opposite to each other. In other words, when the first control node QN has a high voltage, the second control node QBN can have a low voltage. When the first control node QN has a low voltage, the second control node QBN can have a high voltage.

[0210] The fifth control transistors T5-1 and T5-2 can supply the first low voltage VSS1 to the first control node QN in response to the voltage of the second control node QBN. The fifth control transistors T5-1 and T5-2 can be implemented as a dual transistor including two sub-transistors.

[0211] The nineteenth control transistor T19 can supply the first low voltage VSS1 to the second control node QBN in response to the voltage of the first control node QN.

[0212] The third control transistors T3-1 and T3-2 can supply the first low voltage VSS1 to the first control node QN in response to the voltage of the second control node of the subsequent stage. The third control transistors T3-1 and T3-2 can be implemented as a dual transistor including two sub-transistors.

[0213] The twentieth control transistor T20 can supply the first low voltage VSS1 to the second control node QBN in response to the previous carry signal CRj-3.

[0214] The fifteenth control transistors T15-1 and T15-2 can be turned on in response to the high voltage VGH supplied through the third signal terminal S3. The fifteenth control transistors T15-1 and T15-2 can be implemented as a dual transistor including two sub-transistors.

[0215] The sixteenth control transistor T16 can be turned on in response to the voltage of the first control node QN.

[0216] The seventeenth control transistor T17 can be turned on in response to the voltage of the second control node of the subsequent stage.

[0217] When the sixteenth control transistor T16 or the seventeenth control transistor T17 is turned on, the eighteenth control transistor T18 can be turned off based on the second low voltage VSS2 applied to the gate of the eighteenth control transistor T18. When both the sixteenth control transistor T16 and the seventeenth control transistor T17 are turned off, the eighteenth control transistor T18 can supply the high voltage VGH provided through the third signal terminal S3 to the second control node QBN.

[0218] The twenty-fourth control transistor T24 can be turned on in response to selectively sensing the voltage of the input node SSN.

[0219] The third capacitor C3 can be connected between the line of the high voltage VGH provided through the sixth signal terminal S6 and the selectively sensed input node SSN.

[0220] The twenty-fifth control transistors T25-1 and T25-2 can be turned on in response to the sensing start signal provided through the second signal terminal S2. The twenty-fifth control transistors T25-1 and T25-2 can be implemented as a dual transistor including two sub-transistors.

[0221] When the selectively sensed input node SSN has a high voltage and the sensing start signal has a high voltage, the twenty-fourth and twenty-fifth control transistors T24, T25-1, and T25-2 can supply the high voltage VGH to the first control node QN.

[0222] The twenty-sixth control transistor T26 can be turned on in response to the voltage of the sensing start signal.

[0223] The twenty-seventh control transistor T27 can be turned on in response to the voltage of the selectively sensed input node SSN.

[0224] When the selectively sensed input node SSN has a high voltage and the sensing start signal has a high voltage, the twenty-sixth control transistor T26 and the twenty-seventh control transistor T27 can transfer the first low voltage VSS1 to the second control node QBN.

[0225] The twenty-first control transistor T21 and the twenty-third control transistor T23 can be turned on in response to the control signal provided through the first signal terminal S1. The twenty-first control transistor T21 and the twenty-third control transistor T23 can supply the previous carry signal CRj-3 to the selectively sensed input node SSN.

[0226] The twenty-second control transistor T22 can apply the high voltage VGH to the node between the twenty-first control transistor T21 and the twenty-third control transistor T23 in response to the voltage of the selectively sensed input node SSN.

[0227] Figure 12AIt is shown that “j” is an odd number. Some transistors of the j-th stage STj can be connected to the (j + 1)-th stage (e.g., an even stage).

[0228] Each of the plurality of buffer transistors T6 to T14 and the plurality of control transistors T1-1, T1-2, T2-1, T2-2, T3-1, T3-2, T4-1, T4-2, T5-1, T5-2, T15-1, T15-2, T16 to T24, T25-1, T25-2, T26, T27, T28-1 and T28-2 can include an oxide semiconductor. In other words, the plurality of buffer transistors T6 to T14 and the plurality of control transistors T1-1, T1-2, T2-1, T2-2, T3-1, T3-2, T4-1, T4-2, T5-1, T5-2, T15-1, T15-2, T16 to T24, T25-1, T25-2, T26, T27, T28-1 and T28-2 can be transistors of the same type as the transistors PT1 to PT3 of the pixel circuit unit PXC.

[0229] The compensation unit CPCj can be connected to the second scan output unit SS_OCj. For example, the compensation unit CPCj can be electrically connected to the fourth buffer transistor T9 and the first control node QN. The compensation unit CPCj can be connected to the second clock terminal CK2. The first sense clock signal SS_CKO can be defined as the clock signal CLK. The clock signal CLK can refer to a square wave in which the logical states H (high, logic 1) and L (low, logic 0) appear periodically. The signal compensation unit CPCj can receive the clock signal CLK through the second clock terminal CK2. The compensation unit CPCj can receive the first scan signal SCj. The clock signal CLK can include a first clock signal CLK1 (see Figure 12B ) and a second clock signal CLK2 (see Figure 12B ) having pulse widths different from each other.

[0230] Figure 12B is a circuit diagram showing a compensation unit according to an embodiment of the present disclosure.

[0231] Refer to Figure 12A and Figure 12B , the compensation unit CPCj can control the pulse width of the second scan signal SSj. The compensation unit CPCj can allow the second scan output unit SS_OCj to output the 2-1 scan signal SSa (see Figure 8 ) or the 2-2 scan signal SSb (see Figure 8 ).

[0232] The compensation unit CPCj can be implemented by a plurality of compensation transistors CT1, CT2, CT3, CT4, CT5, CT6, and CT7. The compensation unit CPCj can include an inverter circuit IVC, a multiplexer circuit MXC, a fifth compensation transistor CT5, and a control circuit CTC.

[0233] The inverter circuit IVC can receive the first scan signal SCj. The inverter circuit IVC can perform an inversion operation such that the input node and the first output node IG have voltages opposite to each other. In other words, when the first scan signal SCj has a high voltage, the first output node IG can have a low voltage. When the first scan signal SCj has a low voltage, the first output node IG can have a high voltage.

[0234] The inverter circuit IVC can include a first compensation transistor CT1 and a second compensation transistor CT2. The first compensation transistor CT1 and the second compensation transistor CT2 can be connected to each other. The first compensation transistor CT1 can be a P-type transistor. The second compensation transistor CT2 can be an N-type transistor.

[0235] The high voltage VGH can be applied to the first electrode of the first compensation transistor CT1. The second electrode of the first compensation transistor CT1 and the first electrode of the second compensation transistor CT2 can be connected to each other and can be commonly connected to the first output node IG. The low voltage VGL can be applied to the second electrode of the second compensation transistor CT2. The low voltage VGL can have a voltage level lower than the voltage level of the high voltage VGH.

[0236] The multiplexer circuit MXC can be electrically connected to the inverter circuit IVC and the fifth compensation transistor CT5. The multiplexer circuit MXC can receive the first scan signal SCj, the first clock signal CLK1, and the high voltage VGH. The multiplexer circuit MXC can selectively output the first clock signal CLK1 or the high voltage VGH to the second output node CG.

[0237] The multiplexer circuit MXC can include a third compensation transistor CT3 and a fourth compensation transistor CT4.

[0238] The gate of the third compensation transistor CT3 can be electrically connected to the first output node IG. For example, the gate of the third compensation transistor CT3 can receive the inverted first scan signal SCj. The first electrode of the third compensation transistor CT3 can receive the first clock signal CLK1. The second electrode of the third compensation transistor CT3 can be electrically connected to the second output node CG.

[0239] The gate of the fourth compensation transistor CT4 can be electrically connected to the input node of the inverter circuit IVC. The gate of the fourth compensation transistor CT4 can receive the first scan signal SCj. The first electrode of the fourth compensation transistor CT4 can receive the high voltage VGH. The second electrode of the fourth compensation transistor CT4 can be electrically connected to the second output node CG.

[0240] The fifth compensation transistor CT5 can be connected to the multiplexer circuit MXC and the fourth buffer transistor T9. The gate of the fifth compensation transistor CT5 can be connected to the second output node CG. The first electrode of the fifth compensation transistor CT5 can receive the second clock signal CLK2. The second clock signal CLK2 can be one of the first sense clock signal SS_CKO and the second sense clock signal SS_CKE.

[0241] The second electrode of the fifth compensation transistor CT5 can be connected to the fourth buffer transistor T9 and the clock output terminal CLKO. For example, the fifth compensation transistor CT5 and the fourth buffer transistor T9 can be commonly connected to the clock output terminal CLKO.

[0242] The control circuit CTC can be electrically connected to the first control node QN. The control circuit CTC can control the voltage level of the first control node QN. The control circuit CTC can include a sixth compensation transistor CT6 and a seventh compensation transistor CT7. The sixth compensation transistor CT6 and the seventh compensation transistor CT7 can be connected in series with each other.

[0243] The gate of the sixth compensation transistor CT6 can receive the control signal STVP. The first electrode of the sixth compensation transistor CT6 can be connected to the gate to receive the control signal STVP. The second electrode of the sixth compensation transistor CT6 can be connected to the seventh compensation transistor CT7.

[0244] The gate of the seventh compensation transistor CT7 can receive the control signal STVP. The control signal STVP can include the carry look-ahead signal CRj-3. The gates of the seventh compensation transistor CT7 and the sixth compensation transistor CT6 can be commonly connected to each other. The first electrode of the seventh compensation transistor CT7 can be connected to the second electrode of the sixth compensation transistor CT6. The second electrode of the seventh compensation transistor CT7 can be electrically connected to the first control node QN.

[0245] Figure 13 is a waveform diagram of a signal driven in the first stage according to an embodiment of the present disclosure.

[0246] Reference Figure 6 、 Figure 12A 、 Figure 12B and Figure 13, during the third interval "C", the first-stage STa can output a first scan signal SCj in an active state and a second scan signal SSj in an active state. The first-stage STa can output the second scan signal SSj based on the first scan signal SCj. At this time, the second scan signal SSj can be the 2-1 scan signal SSa.

[0247] Since the previous carry signal CRj-3 is activated, the first control node QN can be precharged by the fourth control transistors T4-1 and T4-2.

[0248] The control signal STVP can be activated. In response to the control signal STVP, the sixth compensation transistor CT6 and the seventh compensation transistor CT7 can be turned on. The control circuit CTC can supply the control signal STVP to the first control node QN. The first control node QN can be bootstrapped by the second capacitor C2, and thus, the voltage level of the first control node QN can increase. The first control node QN can be activated.

[0249] Since the second clock signal CLK2 becomes low, the voltage level of the first control node QN can decrease.

[0250] Since the subsequent carry signal CRj+4 is activated, the first control node QN can be pulled down. The voltage level of the first control node QN can correspond to the first low voltage VSS1.

[0251] The high voltage VGH can have a high voltage of the gate signal.

[0252] The low voltage VGL can have a low voltage of the gate signal.

[0253] The first scan signal SCj can be activated. The first pixel X1 can be a pixel operating in the first mode MD1, and thus, can receive the activated first scan signal SCj.

[0254] The inverter circuit IVC can perform an inversion operation by receiving the first scan signal SCj. The voltage level of the first output node IG can have an inverted signal of the first scan signal SCj. For example, when the voltage level of the first scan signal SCj is an active level, the voltage level of the first output node IG can be an inactive level.

[0255] The first clock signal CLK1 can be a signal that is periodically activated with a second pulse width PWD2. The multiplexer circuit MXC can receive the first clock signal CLK1.

[0256] The third compensation transistor CT3 of the multiplexer circuit MXC can be turned off in response to the signal of the first output node IG. The fourth compensation transistor CT4 of the multiplexer circuit MXC can be turned on in response to the first scan signal SCj.

[0257] A high voltage VGH having the same pulse width as that of the first scan signal SCj can be output to the second output node CG.

[0258] The second clock signal CLK2 can be a signal that is periodically activated with a first pulse width PWD1.

[0259] The fifth compensation transistor CT5 can be turned on in response to the signal of the second output node CG.

[0260] The second clock signal CLK2 can be provided to the clock output terminal CLKO as much as the pulse width PWD1 of the signal of the second output node CG.

[0261] The fourth buffer transistor T9 can output the 2-1 scan signal SSa to the second output node ON2 in response to the signal of the first control node QN activated by the control circuit CTC. When the fourth buffer transistor T9 is activated, at least a part of the second clock signal CLK2 can be provided to the second output node ON2 through the fifth compensation transistor CT5. In other words, the first stage STa can output the 2-1 scan signal SSa based on the second clock signal CLK2.

[0262] The 2-1 scan signal SSa can have a first pulse width PWD1. When the 2-1 scan signal SSa is output, the first control node QN can be in an active state.

[0263] In the first stage STa, the first scan signal SCj can have an active level, the signal output from the inverter circuit IVC can have an inactive level, and the signal output from the multiplexer circuit MXC can have an active level with a first pulse width PWD1. The first stage STa can output an activated 2-1 scan signal SSa having a first pulse width PWD1.

[0264] Figure 14 is a waveform diagram of a signal driven in the second stage according to an embodiment of the present disclosure. In Figure 14 the description, for the sake of convenience of explanation and to avoid redundancy, the same reference numerals are assigned to the same components described in Figure 13 the reference.

[0265] Reference Figure 6 、 Figure 12B and Figure 14, during the third interval "C", the second-stage STb can output the first scan signal SCj in a deactivated state and the second scan signal SSj in an activated state. The second-stage STb can output the second scan signal SSj based on the second scan signal SCj. At this time, the second scan signal SSj can be the 2-2 scan signal SSb.

[0266] The control signal STVP can be activated. In response to the control signal STVP, the sixth compensation transistor CT6 and the seventh compensation transistor CT7 can be turned on. The control circuit CTC can provide the control signal STVP to the first control node QN. The first control node QN can be activated.

[0267] The first scan signal SCj can be deactivated. The second pixel X2 can be a pixel operating in the second mode MD2, and thus, can receive the deactivated first scan signal SCj.

[0268] The inverter circuit IVC can receive the first scan signal SCj and can perform an inversion operation on the first output node IG. The first output node IG can be activated.

[0269] The third compensation transistor CT3 of the multiplexer circuit MXC can be turned on in response to the signal of the first output node IG. The fourth compensation transistor CT4 of the multiplexer circuit MXC can be turned off in response to the first scan signal SCj.

[0270] The first clock signal CLK1 can be output to the second output node CG.

[0271] The fifth compensation transistor CT5 can be turned on in response to the signal of the second output node CG.

[0272] The second clock signal CLK2 can be provided to the clock output terminal CLKO as much as the pulse width of the signal of the second output node CG.

[0273] The fourth buffer transistor T9 can output the 2-2 scan signal SSb to the second output node ON2 in response to the signal of the first control node QN activated by the control circuit CTC. When the fourth buffer transistor T9 is activated, at least a part of the second clock signal CLK2 can be provided to the second output node ON2 through the fifth compensation transistor CT5. In other words, the second-stage STb can output the 2-2 scan signal SSb based on the second clock signal CLK2.

[0274] The 2-2 scan signal SSb can have a second pulse width PWD2. When the 2-2 scan signal SSb is output, the first control node QN can be in an active state.

[0275] In the second-stage STb, the first scan signal SCj may have an inactive level, the signal output from the inverter circuit IVC may have an active level, and the signal output from the multiplexer circuit MXC may have an active level with a second pulse width PWD2. The second-stage STb may output an activated 2-2 scan signal SSb having the second pulse width PWD2.

[0276] As described above, when the second scan signals respectively output from the first stage and the second stage are simultaneously activated, the pulse width of the 2-1 scan signal output from the first stage may be different from the pulse width of the 2-2 scan signal output from the second stage. The 2-2 scan signal may be controlled to be deactivated within a specific time period. The first pixel driven by the first stage operating in the first mode may be easily charged with an initialization voltage within a specific portion. Accordingly, a display device having improved display quality may be provided.

[0277] As is conventional in the art of the present disclosure, embodiments have been described and illustrated in the drawings from the perspective of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based manufacturing technologies or other manufacturing technologies. In cases where the blocks, units, and / or modules are implemented by a microprocessor or the like, they may be programmed using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware or may be implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions.

[0278] Although the present disclosure has been specifically shown and described with reference to embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A display device, comprising: A display panel, in which an active area and a peripheral area adjacent to the active area are defined; Wherein, the display panel includes: a plurality of pixels, disposed in the active area and configured to receive a first scan signal and a second scan signal; and a scan driver, disposed in the peripheral area and connected to the plurality of pixels, Wherein, the scan driver includes a plurality of stages arranged in sequence, Wherein, the plurality of stages include a first stage and a second stage, and Wherein, when the second scan signals respectively output from the first stage and the second stage are simultaneously activated, a first pulse width of the second scan signal output from the first stage is different from a second pulse width of the second scan signal output from the second stage.

2. The display device according to claim 1, wherein, When the second stage is disposed after the first stage, the second pulse width is narrower than the first pulse width.

3. The display device according to claim 1, wherein, Each of the first stage and the second stage includes: A first scan output circuit, including a first output node configured to output the first scan signal; A second scan output circuit, including a second output node configured to output the second scan signal; A controller circuit, including a plurality of control transistors electrically connected to a control node; and A compensation circuit, connected to the second scan output circuit.

4. The display device according to claim 3, wherein, The compensation circuit includes: An inverter circuit, connected to the first output node; and A multiplexer circuit, connected to the first output node and the inverter circuit.

5. The display device according to claim 4, wherein, The multiplexer circuit receives a first clock signal having the second pulse width.

6. The display device according to claim 5, wherein, The second stage generates and outputs the second scan signal based on the first clock signal.

7. The display device according to claim 4, wherein, The compensation circuit further includes a control circuit connected to the control node and configured to control a voltage level of the control node.

8. The display device according to claim 7, wherein, When the second scan signal is output, the control node is in an active state.

9. The display device according to claim 4, wherein, The first stage generates and outputs the second scan signal based on the first scan signal.

10. The display device according to claim 4, wherein, When the second scan signals respectively output from the first stage and the second stage are simultaneously activated, in the first stage, the first scan signal has an active level, the signal output from the inverter circuit has an inactive level, and the signal output from the multiplexer circuit has an active level.

11. The display device according to claim 4, wherein, When the second scan signals respectively output from the first stage and the second stage are simultaneously activated, in the second stage, the first scan signal has an inactive level, the signal output from the inverter circuit has an active level, and the signal output from the multiplexer circuit has an active level with the second pulse width.

12. The display device according to claim 1, wherein, The display panel operates during a plurality of frames, Wherein, each of the plurality of frames operates in a first mode or a second mode different from the first mode, Wherein, each of the plurality of stages outputs the activated first scan signal and the activated second scan signal when operating only in the first mode, Wherein, each of the plurality of stages outputs the activated second scan signal when operating only in the second mode, and Wherein, when the first stage and the second stage operate simultaneously in the first mode and the second mode, respectively, the second scan signals that are simultaneously activated are output respectively.

13. A display device, comprising: A display panel, in which an active area and a peripheral area adjacent to the active area are defined in the display panel, Wherein, the display panel includes: a plurality of pixels disposed in the active area and configured to receive a first scan signal and a second scan signal; and a scan driver disposed in the peripheral area and connected to the plurality of pixels, Wherein, the scan driver includes a plurality of stages arranged in sequence, Wherein, each of the plurality of stages includes: A first scan output circuit electrically connected to a control node and including a first output node configured to output the first scan signal; A second scan output circuit electrically connected to the control node and including a second output node configured to output the second scan signal; and A compensation circuit connected to the second scan output circuit, Wherein, the compensation circuit receives the first scan signal, a first clock signal having a first pulse width, and a second clock signal having a second pulse width different from the first pulse width, Wherein, the compensation circuit outputs a signal corresponding to the first clock signal or the second clock signal according to the first scan signal, and Wherein, the second scan output circuit outputs the second scan signal based on the signal.

14. The display device according to claim 13, wherein, When the second scan signals output from at least two of the plurality of stages are simultaneously activated, the first pulse width of the second scan signal output from one of the at least two stages is different from the second pulse width of the second scan signal output from another of the at least two stages.

15. The display device according to claim 14, wherein, When the other stage is disposed after the one stage, the second pulse width of the second scan signal is narrower than the first pulse width of the second scan signal.

16. The display device according to claim 13, wherein, The compensation circuit includes: An inverter circuit connected to the first output node; A multiplexer circuit connected to the first output node and the inverter circuit; and A control circuit connected to the control node and configured to control the state of the control node.

17. The display device according to claim 16, wherein, The display panel operates during a plurality of frames, and Wherein, each of the plurality of frames operates in at least one of a first mode and a second mode different from the first mode.

18. The display device according to claim 17, wherein, When the plurality of stages operate in the first mode, the first scan signal and the second scan signal are output sequentially, and Wherein, when the plurality of stages operate in the second mode, the second scan signal is output sequentially.

19. The display device according to claim 17, wherein, When the first mode and the second mode operate simultaneously, the one stage generates and outputs the second scan signal based on the first scan signal.

20. The display device according to claim 17, wherein, When the first mode and the second mode operate simultaneously, the other stage generates and outputs the second scan signal based on the first clock signal.

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