Anti-interference circuit, welding equipment and communication equipment

Abstract

The embodiment of the invention provides an anti-interference circuit, welding equipment and communication equipment, and belongs to the technical field of electronic circuits. The anti-interference circuit comprises a signal receiving circuit which comprises N groups of signal receiving channels and signal output ends corresponding to the signal receiving channels, and N is an integer greater than or equal to 1; the signal driving circuits are connected with the signal output end of the signal receiving circuit, each signal driving circuit comprises M groups of signal output channels, and the i * M-i * N groups of signal output channels of the ith signal driving circuit are combined with the (i + 1) * N-i * M groups of signal output channels of the (i + 1) th signal driving circuit to form a target signal driving channel, the target signal driving channel is used for driving the (i + 1) th device connected with the signal driving circuit, and M is larger than or equal to N. According to the embodiment of the invention, one-to-one transmission of the differential signals can be realized, and the transmission quality of the differential signals is improved.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to an anti-interference circuit, a welding device, and a communication device. Background Art

[0002] In industrial control systems, differential signal transmission is usually adopted for communication between devices. For example, sensing devices, control devices, coding devices, etc., to achieve high-speed and anti-interference data transmission. However, in the scenario of differential signal transmission below 5V, when multiple groups of differential signals are transmitted simultaneously, due to factors such as complex signal transmission paths, impedance mismatches, and electromagnetic interference, the differential signals received by the main communication device are prone to attenuation and interference, resulting in a decrease in signal integrity and communication quality. Summary of the Invention

[0003] The main purpose of the embodiments of this application is to propose an anti-interference circuit that can achieve one-to-one transmission of differential signals and improve the transmission quality of differential signals.

[0004] To achieve the above object, the first aspect of the embodiments of this application proposes an anti-interference circuit, including: A signal receiving circuit, including N groups of signal receiving channels and signal output terminals corresponding to the signal receiving channels, where N is an integer greater than or equal to 1; Multiple signal driving circuits, connected to the signal output terminals of the signal receiving circuit. Each signal driving circuit includes M groups of signal output channels. The i*M - i*N groups of signal output channels of the i-th signal driving circuit are combined with the (i + 1)*N - i*M groups of signal output channels of the (i + 1)-th signal driving circuit to form a target signal driving channel, and the target signal driving channel is used to drive the (i + 1)-th device connected to the signal driving circuit, where M is greater than or equal to N.

[0005] In some embodiments, it further includes a first impedance module and a second impedance module. The first impedance module includes first matching resistors corresponding to the signal output channels one by one. One end of the first matching resistor is connected to the positive pole of the signal output channel, and the other end is connected to the negative pole of the signal output channel; the second impedance module includes second matching resistors corresponding to the signal receiving channels one by one. One end of the second matching resistor is connected to the positive pole of the signal receiving channel, and the other end is connected to the negative pole of the signal receiving channel.

[0006] In some embodiments, the N groups of signal output channels of the first signal driving circuit form a first signal driving channel, and the first signal driving channel is used to drive the first device connected to the signal driving circuit.

[0007] In some embodiments, the q*M - q*N groups of signal output channels of the q-th signal driving circuit form a second signal driving channel, and the second signal driving channel is used to drive a device connected to the signal driving circuit, where q is the maximum value of the number of the signal driving circuits.

[0008] In some embodiments, the signal driving circuit further includes a signal input terminal, and the signal input terminal is used to receive the differential signal sent by the signal output terminal, and the number of the signal input terminals is greater than or equal to the number of the signal output terminals.

[0009] In some embodiments, the signal driving circuit further includes a differential signal driver, and the differential signal driver includes M groups of signal pins and a signal receiving pin. The signal pins are connected to the signal output channels in one-to-one correspondence, and the signal receiving pin is connected to the signal input terminal to receive the differential signal sent by the signal output terminal.

[0010] In some embodiments, the signal receiving circuit includes a differential signal receiver, and the differential signal receiver includes S groups of signal receiving pins and a plurality of signal output pins. The signal receiving pins are connected to the signal receiving channels in one-to-one correspondence, and the signal output pins are connected to the signal output terminal to output the differential signal, where S is greater than or equal to N.

[0011] In some embodiments, a voltage stabilizing and protecting circuit is further included, and the voltage stabilizing and protecting circuit includes a first capacitor, a second capacitor, a first diode, and a second diode. The positive electrode of the first diode is connected to an external power supply, the negative electrode of the first diode is connected to the first capacitor, one end of the first capacitor is connected to the negative electrode of the first diode and the other end is connected to the positive electrode of the second diode, the positive electrode of the second diode is connected to the first capacitor, the negative electrode of the second diode is connected to the negative electrode of the first diode, and one end of the second capacitor is connected to the negative electrode of the first diode and the other end is connected to a reference ground.

[0012] In some embodiments, a low dropout voltage regulator circuit is further included, and the low dropout voltage regulator circuit includes a voltage regulator chip, a third capacitor, and a fourth capacitor. The output voltage pins of the low dropout voltage regulator circuit are respectively connected to the third capacitor and the fourth capacitor. One end of the third capacitor is connected to the output voltage pin and the other end is connected to the adjustment pin of the low dropout voltage regulator circuit. One end of the fourth capacitor is connected to the output voltage pin and the other end is connected to the adjustment pin of the low dropout voltage regulator circuit.

[0013] In a second aspect, an embodiment of the present application provides a welding device, including a welding control board, and the welding control board includes the anti-interference circuit as described in the first aspect.

[0014] In a third aspect, an embodiment of the present application provides a communication device, including the anti-interference circuit as described in the first aspect.

[0015] The anti-interference circuit, welding device, and communication device proposed in the embodiments of the present application have the following beneficial effects: The anti-interference circuit includes a signal receiving circuit and multiple signal driving circuits. Among them, the signal receiving circuit includes N groups of signal receiving channels and signal output terminals corresponding to the signal receiving channels, so as to be able to output differential signals corresponding to the signal receiving channels through the signal output terminals. The signal driving circuits are connected to the signal output terminals of the signal receiving circuit. Each signal driving circuit includes M groups of signal output channels, and M is greater than or equal to N, so as to simultaneously connect multiple devices through multiple groups of signal output channels. Among them, the i*M - i*N groups of signal output channels of the i-th signal driving circuit and the (i + 1)*N - i*M groups of signal output channels of the (i + 1)-th signal driving circuit are combined to form a target signal driving channel, and the target signal driving channel is used to drive the (i + 1)-th device connected to the signal driving circuit, thereby realizing communication transmission with the (i + 1)-th device. By setting the signal receiving channels and signal output channels in the embodiments of the present application, each path of signals is isolated and transmitted from each other, without affecting each other, isolating the crosstalk between signals, realizing one-to-one transmission of differential signals, and avoiding signal attenuation and interference caused by simultaneous transmission of multiple groups of differential signals.

[0016] Other features and advantages of the present application will be described in the subsequent specification, and, in part, will be obvious from the specification, or will be understood by implementing the present application. The objectives and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the specification and the drawings. Description of the Drawings

[0017] Figure 1 is the frame schematic diagram of the anti-interference circuit provided by the embodiment of the present application; Figure 2 is the circuit diagram of the anti-interference circuit provided by the embodiment of the present application; Figure 3 is the circuit diagram of the voltage stabilization protection circuit provided by the embodiment of the present application; Figure 4 is the circuit diagram of the low dropout voltage regulator circuit provided by the embodiment of the present application; Figure 5 is the schematic diagram of the welding device provided by the embodiment of the present application; Figure 6 is the schematic diagram of the communication device provided by the embodiment of the present application. Detailed Embodiments

[0018] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] It should be noted that although functional modules are divided in the device schematic diagram and the logical sequence is shown in the flowchart, in some cases, the steps shown or described may be executed in a different module division in the device or a different sequence in the flowchart. Terms such as "first" and "second" in the specification, claims and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific sequence or order.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0021] In an industrial control system, communication between devices usually adopts differential signal transmission. For example, sensing devices, control devices, coding devices, etc., are used to achieve high-speed and anti-interference data transmission. However, in the scenario of differential signal transmission below 5V, when multiple groups of differential signals are transmitted simultaneously, due to factors such as complex signal transmission paths, impedance mismatches, and electromagnetic interference, the differential signals received by the main communication device are prone to attenuation and interference, resulting in a decrease in signal integrity and a reduction in communication quality.

[0022] To solve the above problems, this embodiment provides an anti-interference circuit, a welding device, and a communication device. The anti-interference circuit includes a signal receiving circuit and multiple signal driving circuits. Among them, the signal receiving circuit includes N groups of signal receiving channels and signal output terminals corresponding to the signal receiving channels, so as to be able to output differential signals corresponding to the signal receiving channels through the signal output terminals. The signal driving circuit is connected to the signal output terminal of the signal receiving circuit. Each signal driving circuit includes M groups of signal output channels, and M is greater than or equal to N, so as to simultaneously connect multiple devices through multiple groups of signal output channels. Among them, the i*M - i*N groups of signal output channels of the i-th signal driving circuit are combined with the (i + 1)*N - i*M groups of signal output channels of the (i + 1)-th signal driving circuit to form a target signal driving channel. The target signal driving channel is used to drive the (i + 1)-th device connected to the signal driving circuit, thereby realizing communication transmission with the (i + 1)-th device. By setting the signal receiving channels and signal output channels in the embodiments of the present application, each path of signals is isolated and transmitted from each other, without affecting each other, isolating the crosstalk between signals, realizing one-to-one transmission of differential signals, and avoiding signal attenuation and interference caused by the simultaneous transmission of multiple groups of differential signals.

[0023] Please refer to Figure 1 , Figure 1 which is the frame schematic diagram of the anti-interference circuit provided by the embodiments of the present application.

[0024] In some embodiments, the anti-interference circuit includes a signal receiving circuit 100 and a plurality of signal driving circuits 200.

[0025] The signal receiving circuit 100 includes N groups of signal receiving channels and signal output terminals corresponding to the signal receiving channels. N is an integer greater than or equal to 1, and the differential signals received by the signal receiving channels are transmitted through the signal output terminals.

[0026] It should be noted that each group of signal receiving channels in the embodiments of the present application includes a positive electrode and a negative electrode.

[0027] It can be understood that the number of signal output terminals in the embodiments of the present application can be set according to the number of signal receiving channels. For example, when the signal receiving circuit 100 includes three groups of signal receiving channels, the number of signal output terminals can be set to three at this time; when the signal receiving circuit 100 includes two groups of signal receiving channels, the number of signal output terminals can be set to two, etc. The embodiments of the present application do not make specific limitations.

[0028] All signal driving circuits 200 are connected to the signal output terminals of the signal receiving circuit 100. Each signal driving circuit 200 includes M groups of signal output channels, and M is greater than or equal to N. The i*M - i*N groups of signal output channels of the i-th signal driving circuit 200 and the (i + 1)*N - i*M groups of signal output channels of the (i + 1)-th signal driving circuit 200 are combined to form a target signal driving channel. At this time, the formed target signal driving channel can be used as the signal output source of the device 400 connected thereto. The target signal driving channel is used to drive the (i + 1)-th device 400 connected to the signal driving circuit 200 to achieve communication with the (i + 1)-th device 400.

[0029] It can be understood that the anti-interference circuit in the embodiments of the present application can be applied but is not limited to scenarios of differential signal communication below 5V, such as applications in communication between an encoder and a welding card, etc. The embodiments of the present application do not make specific limitations.

[0030] It should be noted that the anti-interference circuit of the embodiment of the present application will be described by taking the number of signal driving circuits 200 as three, N equal to 3, and M equal to 4 as an example. At this time, the signal receiving circuit 100 includes three groups of signal receiving channels, the signal driving circuit 200 includes four groups of signal output channels, and two groups of signal output channels of the second signal driving circuit 200 are combined with one group of signal output channels of the third signal driving circuit 200 to form a target signal driving channel. At this time, the target signal driving channel includes a total of three groups of signal output channels, and communication is carried out with the third device 400 through the target signal driving channel.

[0031] In some embodiments, since the number of signal output channels is greater than or equal to the number of signal receiving channels, the N groups of signal output channels of the first signal driving circuit 200 can directly form the first signal driving channel without combining with the signal output channels of other signal driving circuits 200. At this time, the first signal driving channel can be used as the signal output source of the device 400 connected thereto, and the first signal driving channel is used to drive the first device 400 connected to the signal driving circuit 200 to realize communication with the first device 400.

[0032] In some embodiments, the q*M - q*N groups of signal output channels of the q-th signal driving circuit 200 form the second signal driving channel, and the second signal driving channel is used to drive the q-th device 400 connected to the signal driving circuit 200, where q is the maximum value of the number of signal driving circuits 200, that is, the q-th signal driving circuit 200 is the last signal driving circuit 200. The q*M - q*N groups of signal output channels of the last signal driving circuit 200 can directly form the second signal driving channel. At this time, the second signal driving channel can be used as the signal output source of the device 400 connected thereto, and the second signal driving channel is used to drive the device 400 connected to the signal driving circuit 200, that is, the last device 400, to realize communication with the last device 400.

[0033] It should be noted that the anti-interference circuit of the embodiment of the present application will be described by taking q equal to 3, N equal to 3, and M equal to 4 as an example. At this time, the three groups of signal output channels of the first signal driving circuit 200 form the first signal driving channel to communicate with the first device 400; the three groups of signal output channels of the third signal driving circuit 200 can directly form the second signal driving channel to communicate with the last device 400.

[0034] In some embodiments, a first impedance module 310 and a second impedance module 320 are further included. The first impedance module 310 includes first matching resistors that correspond one-to-one to the signal output channels. One end of each first matching resistor is connected to the positive electrode of the corresponding signal output channel, and the other end is connected to the negative electrode of the corresponding signal output channel. The second impedance module 320 includes second matching resistors that correspond one-to-one to the signal receiving channels. One end of each second matching resistor is connected to the positive electrode of the corresponding signal receiving channel, and the other end is connected to the negative electrode of the corresponding signal receiving channel. By providing the first impedance module 310 on the signal output channels and the second impedance module 320 on the signal receiving channels, impedance matching of the circuit is achieved, ensuring the integrity of the input and output differential signals, improving the transmission quality of the differential signals, and solving the problems of signal attenuation and interference when the differential signals of a feedback device 400 communicate with the main device 400.

[0035] It can be understood that the resistance values of the first matching resistors and the second matching resistors in the embodiments of the present application can be set by the user according to their needs, and the embodiments of the present application do not make specific limitations.

[0036] Please refer to Figure 2 , Figure 2 which is the circuit diagram of the anti-interference circuit provided by the embodiments of the present application.

[0037] In some embodiments, the signal driving circuit 200 further includes a signal input end for receiving the differential signals sent by the signal output end. The number of signal input ends is greater than or equal to the number of signal output ends, so as to receive the differential signals input to the signal receiving circuit 100.

[0038] In some embodiments, the signal driving circuit 200 further includes a differential signal driver. The differential signal driver includes M groups of signal pins and signal receiving pins. The signal pins are connected to the signal output channels one-to-one, and the signal receiving pins are connected to the signal input ends to receive the differential signals sent by the signal output end. Moreover, each signal driving circuit 200 is isolated from each other during transmission and does not interfere with each other, thereby avoiding signal crosstalk.

[0039] It should be noted that the number of signal pins in the embodiments of the present application corresponds to the number of signal output channels, and the number of signal receiving pins can be set by the user according to their needs or the number of connected devices 400, and the embodiments of the present application do not make specific limitations.

[0040] It can be understood that the differential signal driver in the embodiments of the present application can be AM26LS31CDR, AM26LS31CN, AM26LS31CNSR, etc. In the embodiments of the present application, the differential signal driver is taken as an example of AM26LS31CDR for illustration. AM26LS31CDR is a four-channel differential signal driver, and its main function is to convert the input logic signal into a differential signal to drive balanced lines such as twisted pairs or parallel twin lines, so as to achieve long-distance and high anti-interference signal transmission.

[0041] In some embodiments, the signal receiving circuit 100 includes a differential signal receiver U1. The differential signal receiver U1 includes S groups of signal receiving pins and a signal output pin. The signal receiving pins are connected to the signal receiving channels in one-to-one correspondence, and the signal output pin is connected to the signal output end to output a differential signal, where S is greater than or equal to N.

[0042] It can be understood that the differential signal receiver U1 in the embodiments of the present application can be AM26LS33A, L26LS32, AM26LS32AIDR, etc. In the embodiments of the present application, the differential signal receiver U1 is taken as an example of AM26LS32AIDR for illustration. AM26LS32AIDR is a four-channel differential signal receiver U1 for balanced and unbalanced digital data transmission. Its main function is to convert the received differential signal into a single-ended logic signal for subsequent circuit processing.

[0043] In some embodiments, taking the number of signal driving circuits 200 as three, N equal to 3, M equal to 4, S equal to 4, and the first impedance module 310 including 12 first matching resistors and the second impedance module 320 including 3 second matching resistors as an example for illustration, at this time, the differential signal receiver U1 includes four groups of signal receiving pins and four signal output pins. Each group of signal receiving pins respectively includes a positive pin and a negative pin, denoted as 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B. Among them, pins 3A and 3B are not connected. The four signal output pins are respectively denoted as 1Y, 2Y, 3Y, and 4Y. Among them, pin 3Y is not connected. For each differential signal driver, it includes four groups of signal pins and four signal receiving pins. Each group of signal pins respectively includes a positive pin and a negative pin, denoted as 1Y, 1Z, 2Y, 2Z, 3Y, 3Z, 4Y, 4Z. The four signal receiving pins are respectively denoted as 1A, 2A, 3A, and 4A. The first matching resistors include a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12. The second matching resistors include a thirteenth resistor R13, a fourteenth resistor R14, and a fifteenth resistor R15. Among them, one end of the first resistor R1 is connected to 1Y among the signal pins and the other end is connected to 1Z among the signal pins. One end of the second resistor R2 is connected to 2Y among the signal pins and the other end is connected to 2Z among the signal pins. One end of the third resistor R3 is connected to 3Y among the signal pins and the other end is connected to 3Z among the signal pins. One end of the fourth resistor R4 is connected to 4Y among the signal pins and the other end is connected to 4Z among the signal pins. And so on. The connection manners of the fifth resistor R5 to the twelfth resistor R12 are the same as those of the first resistor R1 to the fourth resistor R4, and are not described herein again in the embodiments of the present application. Similarly, one end of the thirteenth resistor R13 is connected to 1A among the signal receiving pins and the other end is connected to 1B among the signal receiving pins. One end of the fourteenth resistor R14 is connected to 2A among the signal receiving pins and the other end is connected to 2B among the signal receiving pins. One end of the fifteenth resistor R15 is connected to 4A among the signal receiving pins and the other end is connected to 4B among the signal receiving pins. Through the above connection manners, each path of signals is transmitted in isolation from each other, impedance matching is achieved, and they do not affect each other, isolating the crosstalk between signals, realizing one-to-one transmission of differential signals, impedance matching, ensuring the integrity of the signals, improving the transmission quality of the differential signals, and solving the problems of signal attenuation and interference when the differential signals of a feedback device communicate with the main device.

[0044] Specifically, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, and the fifteenth resistor R15 in the embodiments of the present application are all 120 ohms, so as to prevent signal oscillation, achieve the effect of impedance matching, and improve signal quality.

[0045] It can be understood that through the above connection method, the embodiments of the present application include a set of external signal input sources {CH0A_N, CH0A_P, CH0B_N, CH0B_P, CH0C_N, CH0C_P}, and four sets of signal output sources, which are respectively represented as {(CH1A_N, CH1A_P, CH1B_N, CH1B_P, CH1C_N, CH1C_P), (CH2A_N, CH2A_P, CH2B_N, CH2B_P, CH2C_N, CH2C_P), (CH3A_N, CH3A_P, CH3B_N, CH3B_P, CH3C_N, CH3C_P), (CH4A_N, CH4A_P, CH4B_N, CH4B_P, CH4C_N, CH4C_P)}. Among them, CH0A_N is connected to the port corresponding to the 1B pin of the differential signal receiver U1, CH0A_P is connected to the port corresponding to the 1A pin of the differential signal receiver U1, CH0B_N is connected to the port corresponding to the 2B pin of the differential signal receiver U1, CH0B_P is connected to the port corresponding to the 2A pin of the differential signal receiver U1, CH0C_N is connected to the port corresponding to the 4B pin of the differential signal receiver U1, and CH0C_P is connected to the port corresponding to the 4A pin of the differential signal receiver U1.

[0046] CH1A_N is connected to the port corresponding to the 4Z pin of the first signal driving circuit U2, CH1A_P is connected to the port corresponding to the 4Y pin of the first signal driving circuit 200, CH1B_N is connected to the port corresponding to the 1Z pin of the first signal driving circuit U2, CH1B_P is connected to the port corresponding to the 1Y pin of the first signal driving circuit U2, CH1C_N is connected to the port corresponding to the 2Z pin of the first signal driving circuit U2, CH1C_P is connected to the port corresponding to the 2Y pin of the first signal driving circuit U2, CH2A_N is connected to the port corresponding to the 3Z pin of the first signal driving circuit U2, and CH2A_P is connected to the port corresponding to the 3Y pin of the first signal driving circuit U2.

[0047] CH2B_N is connected to the port corresponding to the 1Z pin of the second signal driving circuit U3, CH2B_P is connected to the port corresponding to the 1Y pin of the second signal driving circuit U3, CH2C_N is connected to the port corresponding to the 2Z pin of the second signal driving circuit U3, CH2C_P is connected to the port corresponding to the 2Y pin of the second signal driving circuit U3, CH3A_N is connected to the port corresponding to the 3Z pin of the second signal driving circuit U3, CH3A_P is connected to the port corresponding to the 3Y pin of the second signal driving circuit U3, CH3B_N is connected to the port corresponding to the 4Z pin of the second signal driving circuit U3, and CH3B_P is connected to the port corresponding to the 4Y pin of the second signal driving circuit U3.

[0048] CH3C_N is connected to the port corresponding to the 2Z pin of the third signal driving circuit U4, CH3C_P is connected to the port corresponding to the 2Y pin of the third signal driving circuit U4, CH4A_N is connected to the port corresponding to the 4Z pin of the third signal driving circuit U4, CH4A_P is connected to the port corresponding to the 4Y pin of the third signal driving circuit U4, CH4B_N is connected to the port corresponding to the 3Z pin of the third signal driving circuit U4, CH4B_P is connected to the port corresponding to the 3Y pin of the third signal driving circuit U4, CH4C_N is connected to the port corresponding to the 1Z pin of the third signal driving circuit U4, and CH4C_P is connected to the port corresponding to the 1Y pin of the third signal driving circuit U4.

[0049] Please refer to Figure 3 , Figure 3 which is the circuit diagram of the voltage stabilizing and protecting circuit provided by the embodiment of the present application.

[0050] In some embodiments, it further includes a voltage stabilizing and protecting circuit. The voltage stabilizing and protecting circuit includes a first capacitor C1, a second capacitor C2, a first diode D1, and a second diode D2. The positive electrode of the first diode D1 is connected to an external power supply, the negative electrode of the first diode D1 is connected to the first capacitor C1, one end of the first capacitor C1 is connected to the negative electrode of the first diode D1 and the other end is connected to the positive electrode of the second diode D2. The positive electrode of the second diode D2 is connected to the first capacitor C1, the negative electrode of the second diode D2 is connected to the negative electrode of the first diode D1, and one end of the second capacitor C2 is connected to the negative electrode of the first diode D1 and the other end is connected to the reference ground, thereby forming an anti-reverse overvoltage voltage stabilizing and protecting circuit.

[0051] It can be understood that the external power supply inputs a voltage of 12V (P12V). The power supply P12V passes through the first diode D1 that prevents reverse connection, then through the second diode D2 for voltage regulation, and then through the filter circuits of C1 and C2 to output a voltage of 12V. The voltage regulation and protection circuit can prevent the reverse flow of current, thereby protecting the subsequent circuits from damage, and can provide a stable voltage output through the voltage regulation diode and capacitor, reducing the impact of voltage fluctuations on the circuit.

[0052] Please refer to Figure 4 , Figure 4 which is the circuit diagram of the low dropout voltage regulator circuit provided by the embodiment of the present application.

[0053] In some embodiments, it further includes a low dropout voltage regulator circuit. The low dropout voltage regulator circuit includes a voltage regulator chip U5, a third capacitor C3, and a fourth capacitor C4. The output voltage pins of the low dropout voltage regulator circuit are respectively connected to the third capacitor C3 and the fourth capacitor C4. One end of the third capacitor C3 is connected to the output voltage pin and the other end is connected to the adjustment pin of the low dropout voltage regulator circuit. One end of the fourth capacitor C4 is connected to the output voltage pin and the other end is connected to the adjustment pin of the low dropout voltage regulator circuit, so that it can work under the condition of a very small input-output voltage difference and provide a very stable voltage output.

[0054] It can be understood that the +12V power supply is input to the 3rd pin VIN of the voltage regulator chip U5, and the +5V power supply is output through the 2nd pin VOUT. The +5V power supply passes through the third capacitor C3 and the fourth capacitor C4 to filter out the clutter, and finally outputs the +5V power supply; the 4th pin Fin of the voltage regulator chip U5 is connected to the GND terminal, and the 1st pin ADJ / GND is connected to the GND terminal.

[0055] Please refer to Figure 5 , Figure 5 which is the schematic diagram of the welding equipment provided by the embodiment of the present application.

[0056] In some embodiments, the embodiment of the present application further provides a welding equipment. The welding equipment includes a welding control board, and the welding control board includes the anti-interference circuit as described above, so as to improve the signal quality and enhance the anti-interference ability.

[0057] The specific implementation manner of this welding equipment is basically the same as that of the specific embodiment of the above anti-interference circuit, and will not be elaborated here.

[0058] Please refer to Figure 6 , Figure 6 which is the schematic diagram of the communication equipment provided by the embodiment of the present application.

[0059] In some embodiments, the embodiments of the present application further provide a communication device, which includes the anti-interference circuit as described above. The specific implementation of this communication device is substantially the same as the specific embodiments of the above anti-interference circuit and will not be elaborated here.

[0060] The embodiments described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art will know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0061] Those skilled in the art can understand that Figures 1 to 5 the technical solutions shown in do not constitute a limitation on the embodiments of the present application.

[0062] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0063] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the system and device 400 can be implemented as software, firmware, hardware, and their appropriate combinations.

[0064] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present application described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device 400 that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices 400.

[0065] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can represent: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item) of the following" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0066] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings. However, this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the rights of the embodiments of the present application.

Claims

1. An anti-interference circuit, characterized in that, Comprising: A signal receiving circuit, including N groups of signal receiving channels and signal output terminals corresponding to the signal receiving channels, where N is an integer greater than or equal to 1; Multiple signal driving circuits, connected to the signal output terminals of the signal receiving circuit. Each signal driving circuit includes M groups of signal output channels. The i*M - i*N groups of signal output channels of the i-th signal driving circuit are combined with the (i + 1)*N - i*M groups of signal output channels of the (i + 1)-th signal driving circuit to form a target signal driving channel, and the target signal driving channel is used to drive the (i + 1)-th device connected to the signal driving circuit, where M is greater than or equal to N.

2. The anti-interference circuit according to claim 1, wherein, It further includes a first impedance module and a second impedance module. The first impedance module includes first matching resistors corresponding one-to-one to the signal output channels. One end of the first matching resistor is connected to the positive pole of the signal output channel, and the other end is connected to the negative pole of the signal output channel. The second impedance module includes second matching resistors corresponding one-to-one to the signal receiving channels. One end of the second matching resistor is connected to the positive pole of the signal receiving channel, and the other end is connected to the negative pole of the signal receiving channel.

3. The anti-interference circuit according to claim 1, wherein The N groups of signal output channels of the first signal driving circuit form a first signal driving channel, and the first signal driving channel is used to drive the first device connected to the signal driving circuit.

4. The anti-interference circuit according to claim 1, wherein The q*M - q*N groups of signal output channels of the q-th signal driving circuit form a second signal driving channel, and the second signal driving channel is used to drive the device connected to the signal driving circuit, where q is the maximum value of the number of signal driving circuits.

5. The anti-interference circuit according to claim 1, wherein The signal driving circuit further includes a signal input terminal, and the signal input terminal is used to receive the differential signal sent by the signal output terminal, and the number of signal input terminals is greater than or equal to the number of signal output terminals.

6. The anti-interference circuit according to claim 5, wherein The signal driving circuit further includes a differential signal driver. The differential signal driver includes M groups of signal pins and signal receiving pins. The signal pins are connected to the signal output channels one-to-one, and the signal receiving pins are connected to the signal input terminal to receive the differential signal sent by the signal output terminal.

7. The anti-interference circuit according to claim 1, wherein The signal receiving circuit includes a differential signal receiver. The differential signal receiver includes S groups of signal receiving pins and multiple signal output pins. The signal receiving pins are connected to the signal receiving channels one-to-one, and the signal output pins are connected to the signal output terminal to output the differential signal, where S is greater than or equal to N.

8. The anti-interference circuit according to claim 1, wherein It further includes a voltage stabilizing and protecting circuit. The voltage stabilizing and protecting circuit includes a first capacitor, a second capacitor, a first diode, and a second diode. The positive pole of the first diode is connected to an external power supply, the negative pole of the first diode is connected to the first capacitor, one end of the first capacitor is connected to the negative pole of the first diode, and the other end is connected to the positive pole of the second diode. The positive pole of the second diode is connected to the first capacitor, the negative pole of the second diode is connected to the negative pole of the first diode, and one end of the second capacitor is connected to the negative pole of the first diode and the other end is connected to the reference ground.

9. The anti-interference circuit according to claim 1, wherein It further includes a low dropout regulator circuit, the low dropout regulator circuit includes a voltage regulator chip, a third capacitor and a fourth capacitor. The output voltage pins of the low dropout regulator circuit are respectively connected to the third capacitor and the fourth capacitor. One end of the third capacitor is connected to the output voltage pin and the other end is connected to the adjustment pin of the low dropout regulator circuit. One end of the fourth capacitor is connected to the output voltage pin and the other end is connected to the adjustment pin of the low dropout regulator circuit.

10. A welding device, characterized in that, It includes a welding control board, and the welding control board includes the anti-interference circuit according to any one of claims 1 to 9.

11. A communication device, characterized in that, It includes the anti-interference circuit according to any one of claims 1 to 9.

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