A method and apparatus for shortest route and deadlock avoidance in a two-layer polygon topology

Abstract

This disclosure relates to the field of computer network technology, specifically to a method and apparatus for shortest routing and deadlock avoidance in a two-layer polygonal topology. The method includes: determining the routing type of the topology; XORing the low-order bits of the labels of the source node and the target node to determine candidate nodes corresponding to the shortest path of the source node; determining the availability status of the deadlock prevention nodes; if the availability status is idle, determining routing bypass information and sending it to the source node; determining the availability status of ordinary nodes, generating routing vectors for the candidate nodes, so that the source node determines the next-hop node based on the routing vectors, sends the data packet to the next-hop node, and uses the next-hop node as the new source node. The method provided in this disclosure increases the number of shortest paths between nodes in the computer network topology by expanding the number of shortest paths to all theoretical shortest paths, thereby improving system transmission efficiency and data throughput while avoiding deadlock.

Description

Technical Field

[0001] This disclosure relates to the field of computer network technology, specifically to a method and apparatus for shortest route and deadlock avoidance in a two-layer polygonal topology. Background Technology

[0002] The topology of a computer network refers to the abstract connection method exhibited by various network devices, including computers, to achieve network interconnection.

[0003] In related technologies, only the shortest path selection of a two-layer polygonal topology under specific routing scenarios is disclosed. This leads to a significant reduction in the number of shortest paths between nodes, requiring selection from only a limited number of filtered paths, resulting in a severe decrease in system transmission efficiency. Furthermore, these technologies still pose a risk of deadlock in specific routing scenarios, potentially paralyzing the computer network. Therefore, how to increase the number of shortest paths between nodes in the computer network topology, improve system transmission efficiency, and simultaneously avoid deadlock in the topology becomes a problem that needs to be solved. Summary of the Invention

[0004] In view of this, this disclosure provides a method and apparatus for shortest routing and deadlock avoidance in a two-layer polygonal topology, in order to solve the problem of avoiding loop deadlock in the topology while increasing the number of shortest paths between nodes in the computer network topology and improving system transmission efficiency.

[0005] This disclosure provides a method for shortest route and deadlock avoidance in a two-layer polygonal topology. The method includes: determining the route type of a route request in the two-layer polygonal topology based on the highest bit of the label sequences of the source and target nodes. The route types include: outer-to-outer-layer route request, outer-to-inner-layer route request, inner-to-inner-layer route request, and inner-to-outer-layer route request; performing a preset number of XOR operations on the other bits in the label sequences of the source and target nodes to determine the number of 1s in the XOR result, and combining this with the route type to determine at least one candidate node corresponding to the shortest path of the source node; wherein, the candidate nodes include... The system uses ordinary nodes and deadlock prevention nodes with cache queues. It determines the availability of the deadlock prevention nodes; if the deadlock prevention node is idle, it determines the routing bypass information for the deadlock prevention node and sends this information to the source node. It also determines the availability of ordinary nodes and, in conjunction with the availability of the deadlock prevention nodes, generates routing vectors for at least one candidate node. This allows the source node to determine the next-hop node based on the routing vectors and send the data packet to the next-hop node, which is then used as the new source node. If the next-hop node is a deadlock prevention node, the data packet and the routing bypass information are sent to it.

[0006] This disclosure also provides a shortest route and deadlock avoidance device for a two-layer polygonal topology. The device includes: a route type determination module, used to determine the route type of a route request for the two-layer polygonal topology based on the highest bit of the label sequences of the source and target nodes, where the route type includes: outer-to-outer-layer route request, outer-to-inner-layer route request, inner-to-inner-layer route request, and inner-to-outer-layer route request; and a candidate node calculation module, used to XOR a preset number of other bits in the label sequences of the source and target nodes, determine the number of 1s in the XOR result, and combine this with the route type to determine at least one candidate node corresponding to the shortest path of the source node; wherein, the candidate node... The nodes include ordinary nodes and deadlock prevention nodes with cache queues; the deadlock prevention node status determination module is used to determine the availability status of the deadlock prevention node. If the availability status of the deadlock prevention node is idle, it determines the routing bypass information of the deadlock prevention node and sends the routing bypass information to the source node; the next-hop node determination module is used to determine the availability status of ordinary nodes and generate a routing vector for at least one candidate node in combination with the availability status of the deadlock prevention node, so that the source node can determine the next-hop node according to the routing vector and send the data packet to the next-hop node, and use the next-hop node as the new source node; wherein, if the next-hop node is a deadlock prevention node, the data packet and the routing bypass information are sent to the deadlock prevention node.

[0007] This disclosure also provides an electronic device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the above-described shortest route and deadlock avoidance method for a two-layer polygonal topology.

[0008] This disclosure also provides a computer-readable storage medium storing computer instructions for enabling a computer to implement the aforementioned shortest route and deadlock avoidance method for a two-layer polygonal topology.

[0009] This disclosure also provides a computer program product, including computer instructions for causing the computer to execute the above-described method for shortest route and deadlock avoidance in a two-layer polygonal topology.

[0010] The shortest route and deadlock avoidance method and apparatus for dual-layer polygon topology in the above embodiments of this disclosure determine the four route types of the route request for the dual-layer polygon topology by using the highest bit of the label sequence of the source node and the target node in the dual-layer polygon topology. This expands the number of shortest paths from a small number of filtered paths to all theoretical shortest paths, thereby increasing the number of shortest paths between nodes in the computer network topology and improving system transmission efficiency and data throughput.

[0011] In addition, deadlock prevention nodes are preset in the ring structure of the topology, and cache queues are used to temporarily store data to avoid deadlock loop waiting situations, thereby preventing system crashes and improving system reliability. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment;

[0014] Figure 2 This is a schematic diagram of a two-layer hexagonal topology for a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in an embodiment of this disclosure;

[0015] Figure 3 This is a schematic diagram illustrating the deadlock problem in a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment;

[0016] Figure 4 This is a schematic diagram of the anti-deadlock node settings for a two-layer hexagonal topology, which is part of a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this embodiment of the disclosure.

[0017] Figure 5 This is a schematic diagram of the routing algorithm for inner-to-inner-layer routing requests in a two-layer hexagonal topology, which is part of a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0018] Figure 6 This is a schematic diagram of the routing algorithm for outer-to-outer-layer routing requests in a two-layer hexagonal topology, which is part of a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this embodiment of the disclosure.

[0019] Figure 7 This is a specific example diagram of the outer-to-outer-layer routing request of a two-layer hexagonal topology, which is a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment.

[0020] Figure 8 This is a schematic diagram of the routing algorithm for the outer-to-inner layer routing request of a two-layer hexagonal topology, which is a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment.

[0021] Figure 9This is a first specific example diagram of the outer-to-inner layer routing request of a two-layer hexagonal topology, which is a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment.

[0022] Figure 10 This is a second specific example diagram of the outer-to-inner layer routing request of a two-layer hexagonal topology, which is a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment.

[0023] Figure 11 This is a schematic diagram of the routing algorithm for inner-to-inner-layer routing requests in a two-layer hexagonal topology, which is part of a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0024] Figure 12 This is a first specific example diagram of the inner-to-inner-layer routing request of a two-layer hexagonal topology, which is a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment.

[0025] Figure 13 This is a second specific example diagram of the inner-to-inner-layer routing request in a two-layer hexagonal topology, which is part of a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment.

[0026] Figure 14 This is a routing example diagram illustrating a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment;

[0027] Figure 15 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment;

[0028] Figure 16 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygon topology provided in this disclosure embodiment;

[0029] Figure 17 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygon topology provided in this disclosure embodiment;

[0030] Figure 18 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygon topology provided in this disclosure embodiment;

[0031] Figure 19 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygon topology provided in this disclosure embodiment;

[0032] Figure 20This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygon topology provided in this disclosure embodiment;

[0033] Figure 21 This is a schematic diagram illustrating the routing scenario judgment of another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this embodiment of the disclosure;

[0034] Figure 22 This is a schematic diagram illustrating the determination of the next-hop routing node in a routing example diagram of another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment;

[0035] Figure 23 This is a schematic diagram of the data packet transmission direction of a routing example diagram of another shortest route and deadlock avoidance method for a two-layer polygon topology provided in this embodiment of the disclosure;

[0036] Figure 24 This is a schematic diagram of the structure of a shortest route and deadlock avoidance device for a two-layer polygonal topology provided in an embodiment of this disclosure;

[0037] Figure 25 This is a schematic diagram of another shortest route and deadlock avoidance device for a two-layer polygon topology provided in this disclosure embodiment;

[0038] Figure 26 This is a schematic diagram of the structure of another shortest route and deadlock avoidance device for a two-layer polygon topology provided in this disclosure. Detailed Implementation

[0039] As research into computer network topology deepens, engineers have gradually discovered that the node degree distribution in computer network topologies follows a power-law property, meaning that a minority of nodes have high connectivity, while the majority have low connectivity. This characteristic has driven innovation in network topology modeling: based on evolutionary rules of priority connection (highly connected nodes are more likely to obtain new connections) and optimized growth (new nodes tend to connect to critical hubs), the topology is dynamically generated through self-organization, enhancing reliability while increasing network complexity.

[0040] In this context, the mechanism for constructing network topology focuses on the abstract connection relationships between nodes and links. Its core is to describe the interconnection logic between devices through graph models, rather than specific hardware details. A topology diagram clearly illustrates the wiring connections between nodes in the entire network and the overall network structure.

[0041] In related technologies, constraints are imposed on the shortest path selection for two-layer polygon topologies in the following three routing scenarios:

[0042] 1. In the outer-to-outer-layer routing scenario, data packets are transmitted only in the outer polygonal topology and will not be transmitted through the shortest path into the inner polygonal topology;

[0043] 2. In the outer-to-inner-layer routing scenario, the data packet first selects the inner-layer node connected to the source node for the first hop data transmission, and then completes the remaining routing steps in the inner polygon topology.

[0044] 3. In the inner-to-outer-layer routing scenario, the data packet first completes the routing in the inner polygon topology. When it is routed to an inner node connected to the target node, the routing process of the inner polygon topology is completed. Finally, the inner node routes the data packet to the target outer node.

[0045] Although the relevant technologies impose the above three routing scenarios on two-layer polygon topologies to ensure that data packets do not experience loop deadlocks that could lead to system paralysis during transmission, the risk of loop deadlocks still exists in these technologies and cannot be resolved.

[0046] Furthermore, the relevant technologies only disclose the shortest path selection in the three routing scenarios mentioned above, which greatly reduces the number of shortest paths between nodes. They can only select from a small number of filtered paths, resulting in a serious decrease in system transmission efficiency and exacerbating the congestion of lines and nodes.

[0047] To address the aforementioned problems, various embodiments of this disclosure provide a method for shortest route and deadlock avoidance in a two-layer polygonal topology. The method includes: determining the route type of a route request in the two-layer polygonal topology based on the highest bit of the label sequences of the source and target nodes. The route types include: outer-to-outer-layer route request, outer-to-inner-layer route request, inner-to-inner-layer route request, and inner-to-outer-layer route request; performing a preset number of XOR operations on the other bits in the label sequences of the source and target nodes to determine the number of 1s in the XOR result, and combining this with the route type to determine at least one candidate node corresponding to the shortest path of the source node. The candidate nodes include ordinary nodes and deadlock prevention nodes with cache queues. The availability status of the deadlock prevention nodes is determined. If the deadlock prevention node is idle, its routing bypass information is determined and sent to the source node. The availability status of ordinary nodes is determined, and a routing vector for at least one candidate node is generated based on the availability status of the deadlock prevention nodes. This allows the source node to determine the next-hop node based on the routing vector and send the data packet to the next-hop node, which is then used as the new source node. If the next-hop node is a deadlock prevention node, the data packet and routing bypass information are sent to it.

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0049] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure. The method may include the following steps:

[0050] Step S101: Determine the routing type of the routing request for the double-layer polygon topology based on the highest bit of the label sequence of the source node and the target node in the double-layer polygon topology.

[0051] In this embodiment, the double-layer polygonal topology of this disclosure is illustrated using a double-layer hexagonal topology as an example. It is understood that the double-layer polygonal topology in this disclosure is not only applicable to double-layer hexagonal topologies, but also to any other double-layer polygonal topology that satisfies the topological conditions and has at least 3 sides. Here, the topological conditions can be: inner-layer nodes and outer-layer nodes are connected through cross-layer links, and nodes within the inner or outer layer can form a ring connection.

[0052] For example, nodes in a two-layer polygon topology may include, but are not limited to, mobile terminals, edge computing devices, gateway devices, etc.

[0053] Furthermore, in a possible implementation prior to step S101, the method further includes:

[0054] Assign a label sequence to each node in the outer and inner polygon topologies of a two-layer polygon topology. The label sequence includes the most significant bit and other bits, which are used to indicate the specific location of the node in the outer or inner polygon topology. If the most significant bit of a node's label sequence is the first value, the node is located in the outer polygon topology; if the most significant bit of a node's label sequence is the second value, the node is located in the inner polygon topology.

[0055] Obtain the routing request for the two-layer polygon topology, and determine the source node, target node, and data packet on the two-layer polygon topology based on the routing request.

[0056] For example, please refer to Figure 2 , Figure 2 This is a schematic diagram of a two-layer hexagonal topology for a shortest route and deadlock avoidance method in a two-layer polygonal topology provided in this disclosure, as shown in the embodiment. Figure 2 As shown, the double-layer hexagonal topology includes an inner hexagonal topology and an outer hexagonal topology. There are 6 nodes in the inner layer and 6 nodes in the outer layer. The nodes in the outer layer and the inner layer are connected by cross-layer links.

[0057] Here, each node in the outer and inner layers is assigned a unique corresponding label sequence. The label sequence can be used to represent whether the current node is in the outer or inner layer, and the specific location in the outer or inner layer.

[0058] For example, Figure 2 In the label sequence "0_100", the highest bit is the first value "0", indicating that the current node is located in the outer layer. The lower 3 bits of the label sequence are "100", indicating that the current node is located in the position corresponding to the index "100" in the outer layer. In the label sequence "1_000", the highest bit is the second value "1", indicating that the current node is located in the inner layer. The lower 3 bits of the label sequence are "000", indicating that the current node is located in the position corresponding to the index "000" in the inner layer. Note that the highest bit of the label sequence can use 1 to represent the outer layer and 0 to represent the inner layer; the first and second values ​​of the highest bit can also be represented by other different number pairs, which are not specifically limited here.

[0059] Furthermore, a routing request can be a control message initiated by a source node in a two-layer polygonal topology to request the establishment of a communication path from the source node to the destination node. Here, the source node is the sender of data, and the destination node is the receiver of data. For example, Figure 2 Node 1_111 can initiate a routing request as the source node, with node 0_100 as the destination node, and establish a communication path between the two nodes to send data packets from node 1_111 to node 0_100.

[0060] Furthermore, the route types include: outer-to-outer route request, outer-to-inner route request, inner-to-inner route request, and inner-to-outer route request.

[0061] For example, continue to refer to Figure 2 An outer-to-outer routing request can be sent from 0_110 to 0_100, and an outer-to-inner routing request can be sent from 0_110 to 1_110; an inner-to-inner routing request can be sent from 1_110 to 1_111, and an inner-to-outer routing request can be sent from 1_111 to 0_111.

[0062] Step S102: Perform a preset number of other bits in the label sequence of the source node and the target node XOR operation to determine the number of 1s in the XOR operation result, and combine the routing type to determine at least one candidate node corresponding to the shortest path of the source node.

[0063] In this embodiment, candidate nodes include ordinary nodes and deadlock prevention nodes equipped with cache queues.

[0064] Here, a normal node can refer to a basic node that performs regular forwarding tasks in a two-layer polygon topology and does not have a cache queue; a deadlock-preventing node refers to a node that has a cache queue and can be used to solve deadlock problems in a two-layer polygon topology.

[0065] Please refer to this. Figure 3 , Figure 3 This is a schematic diagram illustrating the deadlock problem in a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment, as shown below. Figure 3 As shown, a ring structure consisting of no less than 4 routing nodes will form a deadlock loop if data transmissions in the same direction (clockwise or counterclockwise) are connected end to end in a certain ring structure; once a deadlock is formed, the system will be paralyzed.

[0066] For example, such as Figure 3 As shown, if node 0_000 initiates a 2-hop data transmission via 1_000 to 1_001, and the first hop is via node 1_000 ( Figure 3 (Shown by solid lines) Data transmission is in progress. Node 1_000 initiates a two-hop data transmission from 1_001 to 0_001, and the first-hop data transmission via node 1_001 is in progress. Node 1_001 initiates a two-hop data transmission from 0_001 to 0_000, and the first-hop data transmission via node 0_001 is in progress. Node 0_001 initiates a two-hop data transmission from 0_000 to 1_000, and the first-hop data transmission via node 0_000 is in progress. The first hops of these four data transmissions form a loop, which will prevent the second hop of these four data transmissions from occurring, resulting in an unsolvable deadlock.

[0067] Furthermore, the preset quantity n in other positions of the preset quantity in the label sequence can be preset to correspond to the number of sides of the double-layer polygon topology. For example, n can be 3 for a double-layer hexagonal topology and 4 for a double-layer octagonal topology. The preset correspondence can be set according to actual needs and is not limited.

[0068] For example, if Figure 2 In this context, 1_111 is the source node and 0_100 is the destination node. Based on the highest bit 1 of the source node's label sequence and the highest bit 0 of the destination node, the routing request type is determined to be an inner-to-outer-layer routing request. The lower 3 bits 111 of the source node and the lower 3 bits 100 of the destination node are XORed, and the result is 011. The number of 1s in the XOR result is determined to be 2. Combined with the inner-to-outer-layer routing request, at least one candidate node corresponding to the source node 1_111 is determined.

[0069] Here, a candidate node can refer to a node within the next hop range of the source node that is used to form the shortest path.

[0070] Step S103: Determine the availability status of the deadlock prevention node. If the availability status of the deadlock prevention node is idle, determine the routing bypass information of the deadlock prevention node and send the routing bypass information to the source node.

[0071] In this embodiment, the available state of a node is idle, which indicates that the node currently meets the conditions for receiving data. Alternatively, the available state of a node can also include congestion (or occupation, crowding), indicating that the node currently does not meet the conditions for receiving data and cannot forward data.

[0072] The source node determines the availability status of the deadlock prevention node. If the availability status of the deadlock prevention node is determined to be idle, the source node determines the routing bypass information for the deadlock prevention node.

[0073] Here, if the cache queue in the deadlock prevention node is full, the deadlock prevention node sends a full status as a backpressure signal to the upstream source node, so that the source node stops sending data to the deadlock prevention node, thereby breaking the deadlock circular waiting condition, avoiding the nodes in the loop from waiting for resources from each other, thus eliminating the deadlock risk, ensuring the stable operation of the network, and improving the reliability and fault tolerance of the system.

[0074] Furthermore, the number of cache queues in the deadlock prevention node can correspond one-to-one with the multiple output directions corresponding to the input direction constructed by the source node and the deadlock prevention node. For example, assuming the source node is 1_111 and 1_110 is the deadlock prevention node, the input direction formed by the source node and the deadlock prevention node is from 1_111 to 1_110. Assuming the output directions of this input direction at the deadlock prevention node 1_110 include the directions from 1_110 to 1_100 and from 1_110 to 0_110, then the deadlock prevention node 1_110 has two cache queues, which store the cache queues of node 1_100 and node 0_110 in the two output directions, respectively.

[0075] Furthermore, the routing bypass information of the deadlock prevention node can be used to indicate the output direction of the deadlock prevention node, and the information form of the routing bypass information can be a node number sequence.

[0076] For example, continuing to assume that the source node is 1_111 and 1_110 is the deadlock prevention node, and the source node 1_111 determines that the output direction of the deadlock prevention node 1_110 is from 1_110 to 0_110, then the route bypass information can be the label sequence of 0_110, which is used to indicate that the output direction of the deadlock prevention node 1_110 is from 1_110 to 0_110.

[0077] Step S104: Determine the availability status of ordinary nodes and generate a routing vector for at least one candidate node in combination with the availability status of deadlock prevention nodes, so that the source node can determine the next-hop node according to the routing vector and send the data packet to the next-hop node, and use the next-hop node as the new source node.

[0078] In this embodiment, if the next-hop node is a deadlock prevention node, the data packet and routing bypass information are sent to the next-hop node.

[0079] Here, if the next-hop node is a deadlock prevention node, the source node sends the data packet and routing bypass information to the next-hop node, making the next-hop node the new source node, and the new source node determines the subsequent output direction based on the routing bypass information.

[0080] Furthermore, if the next-hop node is a regular node, the source node only sends the data packet to the next-hop node.

[0081] Furthermore, after the new source node is determined, the steps shown in S101-S104 above are repeated until the data packet is forwarded to the target node.

[0082] The shortest route and deadlock avoidance method and apparatus for a two-layer polygonal topology disclosed in the above embodiments determine four routing types for routing requests in the two-layer polygonal topology by using the highest bit of the label sequence of the source and target nodes. This expands the number of shortest paths from a small number of filtered paths to all theoretical shortest paths, thereby increasing the number of shortest paths between nodes in the computer network topology and improving system transmission efficiency and data throughput. Anti-deadlock nodes are preset in the ring structure of the topology, and a cache queue is used to temporarily store data to avoid circular waiting situations that lead to deadlock, thus preventing system crashes and improving system reliability. By determining the availability status of ordinary nodes and anti-deadlock nodes in real time, a routing vector is generated to achieve dynamic path selection. The source node determines the next-hop node based on the vector. If a path node is congested, other available paths are selected, avoiding data concentration on a few nodes and lines, effectively balancing network load. Simultaneously, the routing bypass information of the anti-deadlock nodes can guide data packet diversion, further improving the flexibility of path selection, reducing the degree of node and line congestion, and optimizing network resource utilization.

[0083] In one possible implementation of the above embodiments, the method further includes:

[0084] Nodes located at multiple preset positions on the outer and inner polygon topologies are designated as anti-deadlock nodes. A buffer queue is set up within each anti-deadlock node so that at least one anti-deadlock node is provided in any ring structure of the double-layer polygon topology. The buffer queue is used to buffer data packets to be sent to the output direction.

[0085] In this embodiment, the basis for setting the anti-deadlock node in the double-layer polygon topology can be that at least one anti-deadlock node is provided in any ring structure in the double-layer polygon topology.

[0086] For example, please refer to Figure 4 , Figure 4 This is a schematic diagram of the anti-deadlock node settings for a two-layer hexagonal topology, as provided in an embodiment of the shortest route and deadlock avoidance method for a two-layer polygonal topology. Figure 4 As shown, the node next to the position indicated by the black arrow is the deadlock prevention node with a cache queue set up. For example, the position to the left of node 1_000 is indicated by the black arrow, which means that node 1_000 is a deadlock prevention node, used to represent at least one cache queue corresponding to each output direction in the input direction formed by nodes 1_001 to 1_000.

[0087] Here, setting up a buffer queue in the deadlock prevention node allows for packet buffering when the amount of data received by the node exceeds its processing capacity, preventing downstream nodes from becoming blocked while waiting for resources. Simultaneously, the full status of the buffer queue serves as a backpressure signal returned to the upstream node, promptly notifying it to pause data transmission, breaking the deadlock condition of circular waiting, and fundamentally eliminating the deadlock risk in the ring structure.

[0088] Furthermore, given that a cache queue is set up in any ring structure in the double-layer polygon topology, the number of nodes with cache queues should be minimized as much as possible, so as to save system hardware resources while solving the deadlock problem.

[0089] The shortest route and deadlock avoidance method and apparatus for a two-layer polygonal topology disclosed in the above embodiments ensure that each ring structure has deadlock prevention capability while minimizing the number of nodes with cache queues. This on-demand configuration method can effectively solve the deadlock problem while reducing system hardware costs and power consumption, and improving resource utilization efficiency, making it particularly suitable for large-scale network deployment scenarios. The reasonable layout of deadlock-prevention nodes allows the network to maintain uninterrupted data transmission even in the face of local congestion or node failures, improving the robustness and fault tolerance of the computer network.

[0090] In one possible implementation of step S101 above, the route type of the route request for the two-layer polygon topology is determined based on the highest bit of the label sequence of the source node and the target node in the two-layer polygon topology, including:

[0091] If the highest bit of the label sequence of the source node is the first value and the highest bit of the label sequence of the destination node is the first value, the routing type of the routing request is determined to be an outer-to-outer routing request.

[0092] If the highest bit of the source node's label sequence is the first value and the highest bit of the target node's label sequence is the second value, then the routing type of the routing request is determined to be an outer-to-inner routing request.

[0093] If the highest bit of the source node's label sequence is the second value and the highest bit of the target node's label sequence is the first value, then the routing type of the routing request is determined to be an inner-to-outer routing request.

[0094] If the highest bit of the source node's label sequence is the second value and the highest bit of the target node's label sequence is the second value, then the routing type of the routing request is determined to be an inner-to-inner routing request.

[0095] In this embodiment, if the highest bit of the label sequence of the source node is 0 and the highest bit of the label sequence of the target node is 0, the routing type of the routing request is determined to be an outer-to-outer routing request.

[0096] For example, the routing type of the routing request corresponding to the source node 0_110 and the destination node 0_100 is an outer-to-outer routing request.

[0097] If the highest bit of the source node's label sequence is 0 and the highest bit of the target node's label sequence is 1, the routing type of the routing request is determined to be an outer-to-inner routing request.

[0098] For example, the routing request corresponding to the source node 0_110 and the destination node 1_110 is an outer-to-inner routing request.

[0099] If the highest bit of the source node's label sequence is 1 and the highest bit of the target node's label sequence is 0, the routing type of the routing request is determined to be an inner-to-outer routing request.

[0100] For example, the routing request corresponding to source node 1_110 and destination node 0_110 is an inner-to-outer routing request.

[0101] If the highest bit of the label sequence of the source node is 1 and the highest bit of the label sequence of the destination node is 1, the routing type of the routing request is determined to be an inner-to-inner routing request.

[0102] For example, the routing type of the routing request corresponding to source node 1_110 and destination node 1_111 is an inner-to-inner routing request.

[0103] The shortest route and deadlock avoidance method and apparatus for two-layer polygon topologies disclosed in the above embodiments can clarify the routing scenario using only four combinations of the highest-order bits, simplifying the complex routing problem of two-layer topologies and avoiding complex topology traversal or global path calculation in related technologies. The route type depends only on the layer attribute of the highest-order bit and is independent of the number of polygon edges or the number of nodes within the layer, improving the generalization and adaptability of the topology structure and reducing adaptation costs.

[0104] In one possible implementation of step S101 above, a preset number of other bits in the label sequences of the source node and the target node are XORed to determine the number of 1s in the XOR result, and at least one candidate node corresponding to the shortest path of the source node is determined in combination with the routing type, including:

[0105] If the route type is an inner-to-inner route request, the other bits in the label sequence of the source node and the target node are XORed with a preset number of bits.

[0106] If the number of 1s in the XOR result is 1 or 3, then the next hop node of the source node is determined to be the target node.

[0107] If the number of 1s in the XOR result is 2, then the neighboring nodes of the source node are determined as at least one candidate node corresponding to the shortest path.

[0108] In this embodiment, if the highest bit of the source node's label sequence is 1 and the highest bit of the target node's label sequence is 1, the routing type is determined to be an inner-to-inner routing request. The lower 3 bits of the source and target node's label sequences are then XORed, including:

[0109] If the number of 1s in the XOR result is 1 or 3, then the next hop node of the source node is determined to be the target node.

[0110] If the number of 1s in the XOR result is 2, then the neighboring nodes of the source node are determined as at least one candidate node corresponding to the shortest path.

[0111] Here, if the XOR result contains 1 or 3 1s, the next-hop node of the source node is determined to be directly routed to the target node; if the XOR result contains 2 1s, at least one neighboring node of the source node is determined as the next-hop node. The selection of at least one neighboring node of the source node has no priority order; any available node can be selected.

[0112] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a routing algorithm for inner-to-inner-layer routing requests in a two-layer hexagonal topology, as provided in an embodiment of the present disclosure, which is a method for shortest routing and deadlock avoidance in a two-layer polygonal topology. Figure 5As shown, if the XOR result contains one 1 or three 1s, the next hop node is the target node; if the XOR result contains two 1s, the next hop node is the adjacent node.

[0113] For example, when a data packet is sent from node 1_000 to 1_001, the lower 3 bits of the label sequences of the two nodes are XORed, and the result is 001, where the number of 1s is 1, indicating that it only takes 1 step to reach the target node 1_001.

[0114] The data packet is sent from node 1_000 to 1_111. The lower 3 bits of the label sequences of the two nodes are XORed, and the result is 111, where the number of 1s is 3. At this time, the source node 1_000 can be routed to the target node 1_111 in one step through the inner topology diagonal.

[0115] The data packet is sent from node 1_000 to 1_011. The lower 3 bits of the label sequences of the two nodes are XORed, and the result is 011, where the number of 1s is 2. At this time, the next hop node of the source node 1_000 can choose the adjacent node 1_100, 1_001 or 1_111. Among them, there is no priority order for the selection of the three adjacent nodes, and any of them can be selected when they are available.

[0116] The shortest path and deadlock avoidance method and apparatus for a two-layer polygonal topology, as disclosed in the above embodiments, achieves efficient determination of the shortest path for inner-to-inner-layer routing requests and intelligent selection of candidate nodes through XOR operation of the lower 3 bits and bit pattern recognition of the highest bit, thereby improving the data transmission efficiency of computer networks. By combining the shortest path algorithm for inner-to-inner-layer routing requests with the setting of anti-deadlock nodes, deadlock situations that may occur in inner-to-inner-layer routing scenarios in related technologies are avoided, thus improving network security.

[0117] In one possible implementation of step S101 above, a predetermined number of other bits in the label sequences of the source node and the target node are XORed to determine the number of 1s in the XOR result, and at least one candidate node corresponding to the shortest path of the source node is determined in combination with the routing type. The implementation further includes:

[0118] If the routing type is an outer-to-outer-route request, a preset number of other bits in the label sequence of the source node and the target node are XORed to determine the first XOR result.

[0119] If the number of 1s in the first XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node.

[0120] If the number of 1s in the first XOR result is not 3, the subvector corresponding to each 1 in the first XOR result is split into at least one subvector. At least one subvector is then XORed with a preset number of other bits in the label sequence of the source node to determine the second XOR result.

[0121] Remove the preset illegal results from the second XOR processing result, and randomly select the node corresponding to the remaining legal result in the second XOR processing result as at least one candidate node corresponding to the shortest path of the source node.

[0122] In this embodiment, if the highest bit of the label sequence of the source node is 0 and the highest bit of the label sequence of the target node is 0, the routing type is determined to be an outer-to-outer-layer routing request. The lower 3 bits of the label sequences of the source node and the target node are XORed to determine the first XOR result.

[0123] If the number of 1s in the first XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node.

[0124] If the number of 1s in the first XOR result is not 3, the subvector corresponding to each 1 in the first XOR result is split into at least one subvector. At least one subvector is then XORed with a preset number of other bits in the label sequence of the source node to determine the second XOR result.

[0125] Remove the preset illegal results from the second XOR processing result, and randomly select the node corresponding to the remaining legal result in the second XOR processing result as at least one candidate node corresponding to the shortest path of the source node.

[0126] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the routing algorithm for outer-to-outer-layer route requests in a two-layer hexagonal topology, as provided in an embodiment of the present disclosure, regarding a shortest route and deadlock avoidance method for a two-layer polygonal topology. Figure 6 As shown, if the first XOR result contains three 1s, the next hop node can be an inner node connected to the source node; if the first XOR result does not contain three 1s, the first XOR result is split into sub-vectors to determine three sub-vectors. Each of the three sub-vectors is XORed with the source node label, and the three illegal sub-vectors in the second XOR result are extracted. The node corresponding to the remaining legal result in the second XOR result is randomly selected as the next hop node of the source node.

[0127] For example, please refer to Figure 7 , Figure 7This is a specific example diagram of an outer-to-outer-layer routing request in a two-layer hexagonal topology, provided in an embodiment of the shortest route and deadlock avoidance method for a two-layer polygonal topology. Assume node 0_100 sends a data packet to 0_011; the lower 3 bits of both are XORed to 111, resulting in three 1s. In related algorithms, the selection of the next-hop node for the source node is limited to the outer layer, and the next-hop node for node 0_100 can only be 0_000 or 0_110. However, in the routing algorithm for the outer-to-outer-layer routing request in this embodiment, based on the selectability of next-hop nodes 0_000 and 0_110, since the lower 3 bits of the source node label and the lower 3 bits of the target node label are XORed, the result contains three 1s. Therefore, the inner-layer node 1_100 connected to the source node 0_100 can be additionally selected, and this path is still the shortest path.

[0128] Furthermore, a preset illegal result can be a different value inserted between two identical values ​​in the lower 3 bits of the index number sequence. For example, 101 and 010 are both preset illegal results, i.e., discontinuous results; while 100, 001, 011 or 110 are all illegal results, i.e., continuous results.

[0129] For example, when source node 0_110 sends a data packet to 0_011, it performs an XOR operation on the lower 3 bits of the source node label and the lower 3 bits of the target node label. The result of the first XOR operation is 101. 101 is split into sub-vectors 100 and 001, and the sub-vectors 100 and 001 are XORed with the source node label 110 respectively. The result of the second XOR operation is 010 and 111. The default illegal result 010 is removed, and node 0_111 is taken as the next hop node of source node 0_110.

[0130] In the shortest route and deadlock avoidance method and apparatus for dual-layer polygon topology in the above embodiments of this disclosure, when the number of 1s in the XOR result is 3, the related technology forces data packets to be transmitted only in the outer layer, while the above embodiments of this disclosure allow the selection of inner connected nodes as next-hop nodes, increasing the number of shortest path options, improving system transmission efficiency, and making the network load distribution more uniform.

[0131] In one possible implementation of step S101 above, a predetermined number of other bits in the label sequences of the source node and the target node are XORed to determine the number of 1s in the XOR result, and at least one candidate node corresponding to the shortest path of the source node is determined in combination with the routing type. The implementation further includes:

[0132] If the routing type is an outer-to-inner routing request, a preset number of other bits in the label sequence of the source node and the target node are XORed to determine the XOR result.

[0133] If the number of 1s in the XOR result is 0, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node, and the node is the target node.

[0134] If the number of 1s in the XOR result is 1, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node, or a node on the outer polygon topology connected to the target node.

[0135] If the number of 1s in the XOR result is 2, the next hop node of the source node is determined to be the first adjacent node, the second adjacent node, or a node on the inner polygon topology connected to the source node.

[0136] If the number of 1s in the XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node.

[0137] In this embodiment, if the highest bit of the label sequence of the source node is 0 and the highest bit of the label sequence of the target node is 1, the routing type is determined to be an outer-to-inner routing request. The lower 3 bits of the label sequences of the source node and the target node are XORed to determine the XOR result.

[0138] Please refer to Figure 8 , Figure 8 This is a schematic diagram of a routing algorithm for the outer-to-inner layer route request in a two-layer hexagonal topology, as provided in an embodiment of this disclosure, regarding a shortest route and deadlock avoidance method for a two-layer polygonal topology. Figure 8 As shown, if the XOR result contains 0 1s, the next hop node can be an inner node connected to the source node, and this inner node is the target node; if the XOR result contains 1 1, the next hop node can be an inner node connected to the source node, or an outer node connected to the target node; if the XOR result contains 2 1s, the next hop node can be the first adjacent node, the second adjacent node, or an inner node connected to the source node; if the XOR result contains 3 1s, the next hop node can be an inner node connected to the source node.

[0139] Compared with related technologies, when there is one 1 in the XOR result, the next hop node of the related technologies has only one choice, that is, only one shortest path, while this embodiment has two choices, that is, two shortest paths; when there are two 1s in the XOR result, the next hop node of the related technologies has only one choice, that is, only one shortest path, while this embodiment has three choices, that is, three shortest paths.

[0140] For example, please refer to Figure 9 , Figure 9This is a first specific example diagram of the outer-to-inner routing request in a two-layer hexagonal topology, which is part of a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure. It is assumed that node 0_100 sends a data packet to 1_000, and the lower 3 bits of both are XORed to 100, resulting in one 1. In related technologies, the next-hop node can only be node 1_100; however, in this embodiment... Figure 9 As shown, with the next hop node 1_100 selectable, since the lower 3 bits of the source node label and the lower 3 bits of the target node label are XORed, there is a 1 in the result. At this time, the outer node 0_000 connected to the target node 1_000 can be selected as the next hop node, and this path is still the shortest path.

[0141] For example, please refer to Figure 10 , Figure 10 This is a second specific example diagram of the outer-to-inner layer routing request in a two-layer hexagonal topology, which is part of a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure. It is assumed that node 0_100 sends a data packet to 1_001, and the lower 3 bits of both are XORed to 101, resulting in two 1s. In related technologies, there is only one next-hop node to choose from, namely node 1_100; however, in this embodiment... Figure 10 As shown, with the next hop node 1_100 being selectable, since the lower 3 bits of the source node label and the lower 3 bits of the target node label are XORed, there are two 1s in the result. At this time, two outer nodes 0_000 and 0_110 adjacent to the source node 0_100 can be selected as the next hop nodes. These two paths are still the shortest paths.

[0142] The shortest route and deadlock avoidance method and apparatus for the two-layer polygon topology in the above embodiments of this disclosure expands the number of shortest paths from the outer layer to the inner layer from 1 to a maximum of 3, breaks the constraint of "first hop must be to the inner layer", increases the selectable dimension of the shortest path from the outer layer to the inner layer, and improves the transmission efficiency and load balancing capability of the computer network.

[0143] In one possible implementation of step S101 above, a predetermined number of other bits in the label sequences of the source node and the target node are XORed to determine the number of 1s in the XOR result, and at least one candidate node corresponding to the shortest path of the source node is determined in combination with the routing type. The implementation further includes:

[0144] If the routing type is an inner-to-outer-layer routing request, a preset number of other bits in the label sequence of the source node and the target node are XORed to determine the XOR result.

[0145] If the number of 1s in the XOR result is 0, the next hop node of the source node is determined to be a node on the outer polygon topology connected to the source node, and the node is the target node.

[0146] If the number of 1s in the XOR result is 1, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the target node, or a node on the outer polygon topology connected to the source node.

[0147] If the number of 1s in the XOR result is 2, the next hop node of the source node is determined to be the first adjacent node, the second adjacent node, the third adjacent node of the source node, or a node on the outer polygon topology connected to the source node.

[0148] If the number of 1s in the XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the target node.

[0149] In this embodiment, if the highest bit of the label sequence of the source node is 1 and the highest bit of the label sequence of the target node is 1, the routing type is determined to be an inner-to-inner routing request. The lower 3 bits of the label sequences of the source node and the target node are XORed to determine the XOR result.

[0150] Please refer to Figure 11 , Figure 11 This is a schematic diagram of a routing algorithm for inner-to-inner-layer routing requests in a two-layer hexagonal topology, as provided in an embodiment of the present disclosure, which is a method for shortest routing and deadlock avoidance in a two-layer polygonal topology. Figure 11 As shown, if the XOR result contains 0 1s, the next-hop node of the source node is determined to be a node on the outer polygon topology connected to the source node, and the node is the target node; if the XOR result contains 1 1, the next-hop node is a node on the inner polygon topology connected to the target node, or a node on the outer polygon topology connected to the source node; if the XOR result contains 2 1s, the next-hop node is the first adjacent node, the second adjacent node, the third adjacent node of the source node, or a node on the outer polygon topology connected to the source node; if the XOR result contains 3 1s, the next-hop node can be a node on the inner polygon topology connected to the target node.

[0151] Compared with related technologies, when there is one 1 in the XOR result, the next-hop node of related technologies has only one choice (the inner node connected to the target node), that is, there is only one shortest path, while this embodiment has two choices, that is, there are two shortest paths; when there are two 1s in the XOR result, the next-hop node of related technologies has only three choices (the first adjacent node, the second adjacent node, and the third adjacent node of the source node), that is, there are only three shortest paths, while this embodiment has four choices, that is, there are four shortest paths.

[0152] For example, please refer to Figure 12 , Figure 12 This is a first specific example diagram of an inner-to-inner-layer route request in a two-layer hexagonal topology, provided by an embodiment of the shortest route and deadlock avoidance method for a two-layer polygonal topology. It is assumed that node 1_011 sends a data packet to 0_001, and the lower 3 bits of both are XORed to 010, resulting in one 1. In related technologies, the next-hop node selection is only one, which is 1_001; however, in this embodiment... Figure 12 As shown, with the next hop node 1_001 being selectable, an additional outer node 0_011 connected to the source node 1_011 can be selected as the next hop node, and this path is still the shortest path.

[0153] For example, please refer to Figure 13 , Figure 13 This is a second specific example diagram of an inner-to-inner-layer routing request in a two-layer hexagonal topology, provided by an embodiment of the shortest route and deadlock avoidance method for a two-layer polygonal topology. It is assumed that node 1_011 sends a data packet to 0_000, and the lower 3 bits of both are XORed to 011, resulting in two 1s. In related technologies, there are three next-hop nodes: the source node's adjacent inner-layer nodes 1_001, 1_100, and 1_111. However, this embodiment... Figure 13 As shown, with the next-hop nodes 1_001, 1_100, and 1_111 selectable, since the lower 3 bits of the source node label are XORed with the lower 3 bits of the target node label, there are two 1s in the result. At this time, an additional outer node 0_011 adjacent to the source node 1_011 can be selected as the next-hop node, and this path is still the shortest path.

[0154] The shortest route and deadlock avoidance method and apparatus for the two-layer polygon topology in the above embodiments of this disclosure improves the transmission efficiency and load balancing capability of computer networks by expanding the number of selectable shortest paths from inner layer to inner layer scene.

[0155] In one possible implementation of step S103 above, the available status of the deadlock prevention node is determined. If the available status of the deadlock prevention node is idle, the routing bypass information of the deadlock prevention node is determined, and the routing bypass information is sent to the source node, including:

[0156] Determine at least one exit node in the exit direction of the shortest path from the source node to prevent deadlock, and generate a node availability state vector based on at least one exit node.

[0157] The route type is determined by the highest bit of the label sequence of the deadlock prevention node and the target node, and at least one candidate node corresponding to the shortest path of the deadlock prevention node is determined by combining the route type.

[0158] Based on at least one candidate node of the deadlock prevention node, at least one exit node is filtered, and exit nodes that belong to the non-shortest path are removed. The bits corresponding to the exit nodes of the non-shortest path in the node's available state vector are set to 0.

[0159] Determine the available status of other exit nodes in the filtered node available status vector. If the available status of an exit node is idle, set the corresponding bit in the filtered node available status vector to 1; if the available status of an exit node is congested, set the corresponding bit in the filtered node available status vector to 0.

[0160] Perform a bitwise OR operation on the filtered node available state vector. If the result of the bitwise OR operation is 1, determine that the available state of the deadlock prevention node is idle. Take the least significant bit of the filtered node available state vector with a median of 1 as the exit node of the deadlock prevention node, and use the label sequence of the subsequent node as the routing bypass information.

[0161] If the bitwise OR operation results in 0, the available state of the anti-deadlock node is determined to be congested.

[0162] In this embodiment, each exit node in the exit direction (i.e., output direction) of the deadlock prevention node among multiple candidate nodes from the source node to the source node is determined.

[0163] For example, please refer to Figure 14 , Figure 14 This is a routing example diagram illustrating a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0164] In this scenario, assuming node 1_111 is the current node (i.e., the source node) and transmits data packets to the target node 0_100, the routing scenario is determined to be an inner-to-outer-layer routing scenario. The candidate nodes for the source node 1_111 are 0_111, 1_110, 1_011 and 1_000, meaning there are 4 candidate shortest paths starting from the source node.

[0165] Further, please refer to Figure 15 , Figure 15 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0166] Among them, the candidate nodes for querying source node 1_111 are the idle states corresponding to 0_111, 1_110, 1_011 and 1_000 respectively. The idle state of nodes 0_111, 1_011 and 1_000 is 0 (indicating congestion or occupancy). The node availability state of anti-deadlock node 1_110 is 111.

[0167] Here, the node available state direction 111 of the deadlock prevention node 1_110 is used to characterize the exit nodes in the output direction from the source node 1_111 to the deadlock prevention node 1_110, including 0_110, 1_100 and 1_001.

[0168] The route type is determined by the highest bit of the label sequence of the deadlock prevention node and the target node, and at least one candidate node corresponding to the shortest path of the deadlock prevention node is determined by combining the route type.

[0169] Here, the routing type is determined to be an inner-to-outer-layer routing type based on the highest bit of the deadlock prevention node 1_110 being 1 and the highest bit of the target node 0_100 being 0. The lower 3 bits of the deadlock prevention node 1_110 and the lower 3 bits of the target node 0_100 are XORed, and the result is 010, with 1 being the number of 1s. Combined with the inner-to-outer-layer routing type, the candidate nodes for the deadlock prevention node 1_110 are determined to be 0_110 or 1_100. Node 1_001 in the exit nodes of the deadlock prevention node is not a candidate node, that is, the direction from node 1_110 to node 1_001 is not the shortest path. Node 1_001 in the node's available state vector 111 is set to 0, and the node's available state vector is updated to 110.

[0170] Furthermore, the deadlock prevention node 1_110 continues to determine the availability status of the remaining two exit nodes 0_110 and 1_100. Here, the availability status can be determined by whether the source node receives a full-state backpressure signal from the cache queue corresponding to the exit node in the deadlock prevention node 1_110. If a full-state backpressure signal is received, the availability status of the exit node is determined to be congested, and the corresponding bit in the node availability status vector of the exit node is set to 0. If no full-state backpressure signal is received, the availability status of the exit node is determined to be idle, and the corresponding bit in the node availability status vector of the exit node is set to 1.

[0171] Furthermore, if the bitwise OR result of each bit in the available state vector of a node is 1, the exit node corresponding to the least significant bit 1 in the available state vector of the node is taken as the subsequent node of the deadlock prevention node, and the label sequence of the subsequent node is taken as the routing bypass information.

[0172] For example, please refer to Figure 16 , Figure 16 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0173] Specifically, the lower 3 bits of the label sequence 0_100 of the target node are XORed with the anti-deadlock node 1_110 to determine that node 1_001 is not the shortest path among the three exit nodes of the anti-deadlock node 1_110, and the node's available status is updated to 110. The source node determines that the cache in the direction of exit node 1_100 and the direction of node 0_110 are not full based on the backpressure signal of the cache queue of the remaining two exit nodes in the anti-deadlock node 1_110, and therefore, the node's available status is finally determined to be 110. The bitwise OR result of the bits in the node's available status of 110 is 1, and the exit node 0_110 corresponding to the least significant bit 1 in the node's available status vector is taken as the subsequent node of the anti-deadlock node, and the label sequence of 0_110 is used as routing bypass information.

[0174] The shortest route and deadlock avoidance method and apparatus for a two-layer polygonal topology disclosed in the above embodiments of this invention eliminates exit nodes that are not along the shortest path through XOR processing and route type matching, ensuring that data is transmitted only along the shortest path. The node availability state vector is dynamically updated through the full-state backpressure signal of the buffer queue. When an exit node is congested, the path is automatically blocked to avoid deadlock caused by data injection into congested nodes. The exit node with the least significant bit set to 1 is selected after bitwise OR processing, ensuring determinism and fairness in path selection and avoiding conflicts when multiple nodes compete. When multiple exit nodes are idle, the node with the lowest bit of its hardware address is preferentially selected to reduce routing decision latency.

[0175] In one possible implementation of step S104 above, the availability status of ordinary nodes is determined, and a routing vector for at least one candidate node is generated in combination with the availability status of deadlock prevention nodes. This allows the source node to determine the next-hop node based on the routing vector and send the data packet to the next-hop node, using the next-hop node as the new source node. This includes:

[0176] Obtain the availability status of ordinary nodes. If the availability status of an ordinary node is idle, set the corresponding bit in the routing vector of the ordinary node to 1.

[0177] Obtain the availability status of the deadlock prevention node. If the availability status of the deadlock prevention node is idle, set the corresponding bit in the routing vector to 1.

[0178] Determine the candidate node corresponding to the least significant bit of the routing vector where the median is 1, use the candidate node as the next-hop node, cause the source node to send the data packet to the next-hop node, and use the next-hop node as the new source node.

[0179] In this embodiment, the availability status of ordinary nodes is obtained. If the availability status of an ordinary node is idle, the corresponding bit in the routing vector of the ordinary node is set to 1; if the availability status of an ordinary node is occupied (i.e. congested), the corresponding bit in the routing vector of the ordinary node is set to 0.

[0180] Obtain the availability status of the deadlock prevention node. If the availability status of the deadlock prevention node is idle, set the corresponding bit in the routing vector to 1; if the availability status of the deadlock prevention node is occupied, set the corresponding bit in the routing vector to 0.

[0181] For example, please refer to Figure 17 , Figure 17 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0182] If node 0_111 is in an occupied state, then the corresponding bit in the routing vector is set to 0. Similarly, the corresponding bits in the routing vectors of nodes 1_011 and 1_000 are both set to 0.

[0183] The available state of the deadlock prevention node 1_110 is idle, so set the corresponding bit in the routing vector of the deadlock prevention node to 1.

[0184] Here, the final routing vector is 0100. The candidate node corresponding to the least significant bit of the routing vector with a median of 1 is taken as the next-hop node, that is, the deadlock prevention node 1_110 is taken as the next-hop node.

[0185] Furthermore, for example, please refer to Figure 18 , Figure 18 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0186] In this process, after the source node determines that the next-hop node is the deadlock prevention node 1_110, the data packet is sent to the next-hop node, and the data packet jump direction is as follows: Figure 18 As indicated by the black arrow.

[0187] The shortest route and deadlock avoidance method and apparatus for the two-layer polygon topology in the above embodiments of this disclosure improve the load balancing capability of computer networks by obtaining the idle or congested status of ordinary nodes and anti-deadlock nodes, dynamically shielding unavailable nodes by routing vectors, and guiding data flow to idle paths.

[0188] In one possible implementation of the above embodiments, the method further includes:

[0189] If the next-hop node is a deadlock prevention node, the data packet and the routing bypass information corresponding to the deadlock prevention node are sent from the source node to the deadlock prevention node, so that the deadlock prevention node can de-flow and buffer the data packet into the buffer queue corresponding to the output direction of the subsequent node according to the routing bypass information;

[0190] If the amount of data stored in the cache queue exceeds the preset storage threshold, the anti-deadlock node will return the full status signal as a backpressure signal to the source node, so that the source node will suspend sending data packets in that output direction after receiving the backpressure signal until it receives a non-full status signal.

[0191] In this embodiment, when the next-hop node of the source node 1_111 is the deadlock prevention node 1_110, the source node 1_111 sends the data packet and the routing bypass information 0_110 to the next-hop node 1_110 at the same time.

[0192] The next-hop node 1_110, based on the route bypass information 0_110, de-channels and caches the data packets into the internal cache queue corresponding to the route bypass information 0_110.

[0193] Furthermore, the next-hop node 1_110's packet de-buffering and buffering steps can be as follows: Figure 19 As shown, Figure 19 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0194] The steps for packet de-buffering at the next-hop node 1_110 can be as follows: Figure 19 As shown by the black arrows, the steps include: 1. Source node 1_111 inputs data packets and routing bypass information, with the routing bypass information indicating the output direction as node 0_110. 2. Next-hop node 1_110, based on the routing bypass information, distributes and buffers the data packets into the buffer queue (i.e., data buffer 1) corresponding to node 0_110. Data buffer 1 determines whether node 0_110 is full based on the backpressure signal input by node 0_110. If node 0_110 is not full and has obtained the arbitration information from node 0_110, it inputs the buffered data packets to node 0_110. If it has not obtained the arbitration information from node 0_110, it continues to store the data packets in data buffer 1. If the amount of data stored in data buffer 1 is greater than a preset storage threshold, it returns the full status as a backpressure signal to source node 1_111 to instruct source node 1_111 to pause sending data packets.

[0195] Please refer to Figure 20 , Figure 20 This is a routing example diagram illustrating another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure.

[0196] In this process, after the next-hop node 1_100 completes the transmission of data packets to node 0_110, node 0_110 becomes the new source node. The direction of data packet transmission is as follows: Figure 20 As shown by the black arrow, node 1_110 points to the new source node 0_110.

[0197] Please refer to Figure 21 , Figure 22 and Figure 23 ,in, Figure 21 This is a schematic diagram illustrating the routing scenario judgment of another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this embodiment of the disclosure; Figure 22 This is a schematic diagram illustrating the determination of the next-hop routing node in a routing example diagram of another shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this disclosure embodiment; Figure 23 This is a schematic diagram of the data packet transmission direction of a routing example of a shortest route and deadlock avoidance method for a two-layer polygonal topology provided in this embodiment of the present disclosure.

[0198] Among them, such as Figure 21 As shown, based on the highest bit 0 of source node 0_110 and the highest bit 0 of destination node 0_100, the outer-to-outer-layer routing scenario is determined; for example... Figure 22 As shown, the lower 3 bits of the source node 0_110 and the target node 0_100 are XORed to determine the first XOR result as 010. Then, the routing algorithm corresponding to the outer-to-outer-layer routing scenario is applied to determine the sub-vector derived from 010 as 010. This sub-vector is then XORed with the lower 3 bits of the source node to determine the second XOR result as 100, which is a preset valid result. Therefore, the next hop node is determined to be 0_100, which is the target node. The data packet transmission direction is as follows... Figure 23 As shown by the black arrow, node 0_110 points to target node 0_100, thus completing the process of inner node 1_111 initiating a routing request to outer node 0_100.

[0199] By employing the shortest route and deadlock avoidance method and apparatus for a two-layer polygonal topology as described above in this disclosure, when a data packet carrying route bypass information (such as 0_110) arrives at the anti-deadlock node, the node directly caches the data in the queue of the corresponding output direction, eliminating the need to recalculate the route and improving data transmission efficiency. When the amount of data in the cache queue exceeds a threshold, the anti-deadlock node sends a backpressure signal to the source node, causing the source node to immediately suspend data injection, thereby avoiding circular deadlock caused by data accumulation. The anti-deadlock node configures an independent cache queue for each output direction, enabling multi-path parallel processing and further improving data concurrency.

[0200] In one possible implementation of the above embodiments, the method further includes: enabling the anti-deadlock node to monitor the non-empty state of the buffer queues in each output direction in real time, and if it receives arbitration information sent by a subsequent node, sending the data packet to the subsequent node through a handshake protocol.

[0201] In this embodiment, the anti-deadlock node monitors subsequent nodes in real time, determines the idle status of subsequent nodes based on backpressure information, and if it receives arbitration information from a subsequent node, it sends a data packet to the subsequent node via a handshake protocol; and,

[0202] The deadlock prevention node monitors the idle status of at least one of its own cache queues in real time. If the amount of data stored in the cache queue is greater than the preset storage threshold, the full status is returned to the source node as a backpressure signal.

[0203] The shortest route and deadlock avoidance method and apparatus for the two-layer polygon topology disclosed in the above embodiments of this disclosure ensure that the anti-deadlock node sends data packets only after receiving arbitration information from subsequent nodes, avoiding link conflicts caused by unauthorized forwarding and further optimizing the dynamic allocation of resources. Real-time monitoring of the non-empty state of the cache queue and immediate forwarding when data is available and arbitration information is received reduces data latency and further improves data transmission efficiency.

[0204] In one embodiment, Figure 24 This is a schematic diagram of a shortest route and deadlock avoidance device for a two-layer polygonal topology provided in an embodiment of this disclosure. Figure 24 As shown, a shortest path and deadlock avoidance device 2400 for a two-layer polygonal topology is provided. The device 2400 includes: a route type determination module 2401, a route vector XOR operation module 2402, a shortest path idle state query and processing module 2403, a route selection vector generation and update module 2404, a vector first 1 lookup module 2405, and a route direction management module 2406, wherein:

[0205] The route type determination module 2401 is used to determine the route type of the route request based on the highest bit of the label sequence of the source node and the label sequence of the target node.

[0206] The routing vector XOR operation module 2402 is used to perform an XOR operation between the lower 3 bits of the label sequence of the source node and the lower 3 bits of the label sequence of the target node, and output the XOR result; at the same time, it is also used to count the number of 1s in the XOR result and determine the next hop node in combination with different routing algorithm scenarios.

[0207] The shortest path idle status query and processing module 2403 is used to filter all shortest paths based on the input route type, the XOR result of the route vector, and the routing algorithm scenario, and to query the idle status of the shortest paths. At the same time, it judges and processes the status of nodes containing cache queues, and generates the idle status and route bypass information of the node. The idle status of all shortest paths is obtained to prepare for the generation of route selection vectors.

[0208] The routing vector generation and update module 2404 is used to generate or update the routing vector based on the idle status of all input shortest paths.

[0209] The vector first 1 lookup module 2405 is used to find the node corresponding to the least significant bit of the routing vector or the node available state vector where the median is 1.

[0210] The routing direction management module 2406 is used to route data packets to the next-hop node.

[0211] In one embodiment, another shortest route and deadlock avoidance device 2500 for a two-layer polygonal topology is provided, which corresponds one-to-one with the shortest route and deadlock avoidance method for the two-layer polygonal topology in the above embodiments. For example... Figure 25 As shown, the shortest route and deadlock avoidance device 2500 for the double-layer polygon topology includes a route type determination module 2501, a candidate node calculation module 2502, a deadlock prevention node status determination module 2503, and a next-hop node determination module 2504. The detailed descriptions of each functional module are as follows:

[0212] The route type determination module 2501 is used to determine the route type of the route request for the double-layer polygon topology based on the highest bit of the label sequence of the source node and the target node in the double-layer polygon topology. The route types include: outer layer to outer layer route request, outer layer to inner layer route request, inner layer to inner layer route request, and inner layer to outer layer route request.

[0213] The candidate node calculation module 2502 is used to perform XOR processing on a preset number of other bits in the label sequence of the source node and the target node, determine the number of 1s in the XOR processing result, and determine at least one candidate node corresponding to the shortest path of the source node in combination with the routing type; wherein, the candidate nodes include ordinary nodes and deadlock prevention nodes with cache queues.

[0214] The deadlock prevention node status determination module 2503 is used to determine the availability status of the deadlock prevention node. If the availability status of the deadlock prevention node is idle, the module determines the routing bypass information of the deadlock prevention node and sends the routing bypass information to the source node.

[0215] The next-hop node determination module 2504 is used to determine the availability status of ordinary nodes and generate a routing vector for at least one candidate node in combination with the availability status of the deadlock prevention node, so that the source node can determine the next-hop node according to the routing vector and send the data packet to the next-hop node, and use the next-hop node as the new source node; wherein, if the next-hop node is a deadlock prevention node, the data packet and the routing bypass information are sent to the deadlock prevention node.

[0216] In one embodiment, the apparatus further includes a node initialization module 2505, wherein:

[0217] The node initialization module 2505 is used to assign label sequences to each node in the outer and inner polygon topologies of the two-layer polygon topology. The label sequence includes the most significant bit and other bits, which are used to indicate the specific location of the node in the outer or inner polygon topology. If the most significant bit of the node's label sequence is the first value, the node is located in the outer polygon topology; if the most significant bit of the node's label sequence is the second value, the node is located in the inner polygon topology.

[0218] Obtain the routing request for the two-layer polygon topology, and determine the source node, target node, and data packet on the two-layer polygon topology based on the routing request.

[0219] In one embodiment, the node initialization module 2505 is further configured to use nodes located at multiple preset positions on the outer and inner polygon topologies as anti-deadlock nodes, and to set up a buffer queue in each anti-deadlock node so that at least one anti-deadlock node is provided in any ring structure in the double-layer polygon topology; wherein, the buffer queue is used to buffer data packets to be sent to the output direction.

[0220] In one embodiment, the route type determination module 2501 is used to determine the route type of the route request as an outer-to-outer route request if the highest bit of the label sequence of the source node is a first value and the highest bit of the label sequence of the target node is a first value.

[0221] If the highest bit of the source node's label sequence is the first value and the highest bit of the target node's label sequence is the second value, then the routing type of the routing request is determined to be an outer-to-inner routing request.

[0222] If the highest bit of the source node's label sequence is the second value and the highest bit of the target node's label sequence is the first value, then the routing type of the routing request is determined to be an inner-to-outer routing request.

[0223] If the highest bit of the source node's label sequence is the second value and the highest bit of the target node's label sequence is the second value, then the routing type of the routing request is determined to be an inner-to-inner routing request.

[0224] In one embodiment, the candidate node calculation module 2502 is used to perform XOR processing on a preset number of other bits in the label sequence of the source node and the target node when the routing type is an inner-to-inner routing request.

[0225] If the number of 1s in the XOR result is 1 or 3, then the next hop node of the source node is determined to be the target node.

[0226] If the number of 1s in the XOR result is 2, then the neighboring nodes of the source node are determined as at least one candidate node corresponding to the shortest path.

[0227] In one embodiment, the candidate node calculation module 2502 is further configured to perform XOR processing on a preset number of other bits in the label sequence of the source node and the target node when the routing type is an outer-to-outer-layer routing request, and determine the first XOR processing result.

[0228] If the number of 1s in the first XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node.

[0229] If the number of 1s in the first XOR result is not 3, the subvector corresponding to each 1 in the first XOR result is split into at least one subvector. At least one subvector is then XORed with a preset number of other bits in the label sequence of the source node to determine the second XOR result.

[0230] Remove the preset illegal results from the second XOR processing result, and randomly select the node corresponding to the remaining legal result in the second XOR processing result as at least one candidate node corresponding to the shortest path of the source node.

[0231] In one embodiment, the candidate node calculation module 2502 is further configured to perform an XOR operation on a preset number of other bits in the label sequence of the source node and the target node when the routing type is an outer-to-inner routing request, and determine the XOR operation result.

[0232] If the number of 1s in the XOR result is 0, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node, and the node is the target node.

[0233] If the number of 1s in the XOR result is 1, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node, or a node on the outer polygon topology connected to the target node.

[0234] If the number of 1s in the XOR result is 2, the next hop node of the source node is determined to be the first adjacent node, the second adjacent node, or a node on the inner polygon topology connected to the source node.

[0235] If the number of 1s in the XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node.

[0236] In one embodiment, the candidate node calculation module 2502 is further configured to perform an XOR operation on a preset number of other bits in the label sequence of the source node and the target node when the routing type is an inner-to-outer-layer routing request, and determine the XOR operation result.

[0237] If the number of 1s in the XOR result is 0, the next hop node of the source node is determined to be a node on the outer polygon topology connected to the source node, and the node is the target node.

[0238] If the number of 1s in the XOR result is 1, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the target node, or a node on the outer polygon topology connected to the source node.

[0239] If the number of 1s in the XOR result is 2, the next hop node of the source node is determined to be the first adjacent node, the second adjacent node, the third adjacent node of the source node, or a node on the outer polygon topology connected to the source node.

[0240] If the number of 1s in the XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the target node.

[0241] In one embodiment, the deadlock prevention node state determination module 2503 is used to determine at least one exit node of the deadlock prevention node in the exit direction of the shortest path of the source node, and generate a node available state vector based on the at least one exit node.

[0242] The route type is determined by the highest bit of the label sequence of the deadlock prevention node and the target node, and at least one candidate node corresponding to the shortest path of the deadlock prevention node is determined by combining the route type.

[0243] Based on at least one candidate node of the deadlock prevention node, at least one exit node is filtered, and exit nodes that belong to the non-shortest path are removed. The bits corresponding to the exit nodes of the non-shortest path in the node's available state vector are set to 0.

[0244] Determine the available status of other exit nodes in the filtered node available status vector. If the available status of an exit node is idle, set the corresponding bit in the filtered node available status vector to 1; if the available status of an exit node is congested, set the corresponding bit in the filtered node available status vector to 0.

[0245] The filtered node available state vector is bitwise ORed. If the bitwise OR result is 1, the available state of the deadlock prevention node is determined to be idle. The exit node corresponding to the least significant bit of the filtered node available state vector with a median of 1 is taken as the subsequent node of the deadlock prevention node, and the label sequence of the subsequent node is taken as the routing bypass information.

[0246] If the bitwise OR operation results in 0, the available state of the anti-deadlock node is determined to be congested.

[0247] In one embodiment, the next-hop node determination module 2504 is used to obtain the availability status of ordinary nodes. If the availability status of an ordinary node is idle, the corresponding bit of the ordinary node in the routing vector is set to 1.

[0248] Obtain the availability status of the deadlock prevention node. If the availability status of the deadlock prevention node is idle, set the corresponding bit in the routing vector to 1.

[0249] Determine the candidate node corresponding to the least significant bit of the routing vector where the median is 1, use the candidate node as the next-hop node, cause the source node to send the data packet to the next-hop node, and use the next-hop node as the new source node.

[0250] In one embodiment, the next-hop node determination module 2504 is further configured to, if the next-hop node is a deadlock prevention node, send the routing bypass information corresponding to the data packet and the deadlock prevention node from the source node to the deadlock prevention node, so that the deadlock prevention node can de-flow and cache the data packet into the cache queue corresponding to the output direction of the subsequent node according to the routing bypass information;

[0251] If the amount of data stored in the cache queue exceeds the preset storage threshold, the anti-deadlock node will return the full status signal as a backpressure signal to the source node, so that the source node will suspend sending data packets in that output direction after receiving the backpressure signal until it receives a non-full status signal.

[0252] In one embodiment, the next-hop node determination module 2504 is also used to enable the anti-deadlock node to monitor the non-empty state of the buffer queues in each output direction in real time. If it receives arbitration information sent by a subsequent node, it sends the data packet to the subsequent node through a handshake protocol.

[0253] It should be noted that the shortest route and deadlock avoidance device for the two-layer polygon topology provided in the above embodiments is only illustrated by the division of the above program modules when implementing the corresponding shortest route and deadlock avoidance method for the two-layer polygon topology. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the above system can be divided into different program modules to complete all or part of the processing described above. In addition, the system provided in the above embodiments and the corresponding Figure 1The embodiments of the methods shown belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0254] This disclosure also provides an electronic device having the above-described features. Figure 24 or Figure 25 The diagram shows the shortest route and deadlock avoidance mechanism for a two-layer polygon topology.

[0255] Please see Figure 26 , Figure 26 This is a schematic diagram of the structure of another shortest route and deadlock avoidance device for a two-layer polygonal topology provided in this disclosure, as shown in the embodiment. Figure 26 As shown, the electronic device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 26 Take a processor 10 as an example.

[0256] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0257] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0258] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0259] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0260] The electronic device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 26 Taking the example of a connection between China and Israel via a bus.

[0261] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the electronic device, such as a touch screen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touch screen.

[0262] The electronic device also includes a communication interface for communicating with other devices or communication networks.

[0263] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded over a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium may be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0264] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Accordingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer reading and executing the instructions; or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0265] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A shortest route and deadlock avoidance method for a two-layer polygon topology, characterized in that, The method includes: The routing type of the routing request for the two-layer polygon topology is determined based on the highest bit of the label sequence of the source node and the target node in the two-layer polygon topology. The routing type includes: outer-to-outer-layer routing request, outer-to-inner-layer routing request, inner-to-inner-layer routing request, and inner-to-outer-layer routing request. The source node and the target node are XORed with a preset number of other bits in their label sequences to determine the number of 1s in the XOR result. This result is then combined with the routing type to determine at least one candidate node corresponding to the shortest path of the source node. The candidate nodes include ordinary nodes and deadlock prevention nodes with cache queues. Determine the availability status of the anti-deadlock node. If the availability status of the anti-deadlock node is idle, determine the routing bypass information of the anti-deadlock node and send the routing bypass information to the source node. The availability status of the ordinary node is determined, and the availability status of the anti-deadlock node is combined to generate a routing vector for at least one candidate node, so that the source node determines the next-hop node according to the routing vector and sends the data packet to the next-hop node, and uses the next-hop node as the new source node; wherein, if the next-hop node is an anti-deadlock node, the data packet and the routing bypass information are sent to the anti-deadlock node.

2. The method according to claim 1, characterized in that, Before determining the route type of the route request for the two-layer polygon topology based on the most significant bit of the label sequence of the source and target nodes in the two-layer polygon topology, the method further includes: Assigning label sequences to each node in the outer and inner polygon topologies of a two-layer polygon topology; wherein the label sequence includes the most significant bit and other bits, the other bits being used to characterize the specific location of the node corresponding to the label sequence in the outer or inner polygon topology; if the most significant bit of a node's label sequence is a first value, the node is located in the outer polygon topology; if the most significant bit of a node's label sequence is a second value, the node is located in the inner polygon topology; Obtain the routing request of the two-layer polygon topology, and determine the source node, target node and data packet on the two-layer polygon topology based on the routing request.

3. The method according to claim 2, characterized in that, The method further includes: Nodes located at multiple preset positions on the outer and inner polygon topologies are designated as anti-deadlock nodes. A buffer queue is set up within each anti-deadlock node so that at least one anti-deadlock node is provided in any ring structure of the double-layer polygon topology. The buffer queue is used to buffer data packets to be sent to the output direction.

4. The method according to claim 3, characterized in that, The step of determining the routing type of the routing request for the two-layer polygon topology based on the highest bit of the label sequence of the source node and the target node on the two-layer polygon topology includes: If the highest bit of the label sequence of the source node is the first value and the highest bit of the label sequence of the destination node is the first value, the routing type of the routing request is determined to be an outer-to-outer routing request. If the highest bit of the source node's label sequence is the first value and the highest bit of the target node's label sequence is the second value, then the routing type of the routing request is determined to be an outer-to-inner routing request. If the highest bit of the source node's label sequence is the second value and the highest bit of the target node's label sequence is the first value, then the routing type of the routing request is determined to be an inner-to-outer routing request. If the highest bit of the source node's label sequence is the second value and the highest bit of the target node's label sequence is the second value, then the routing type of the routing request is determined to be an inner-to-inner routing request.

5. The method according to claim 4, characterized in that, The step of XORing a preset number of other bits in the label sequences of the source node and the target node to determine the number of 1s in the XOR result, and combining this with the routing type to determine at least one candidate node corresponding to the shortest path of the source node, includes: If the route type is an inner-to-inner route request, the other bits in the label sequence of the source node and the target node are XORed with a preset number of bits. If the number of 1s in the XOR result is 1 or 3, then the next hop node of the source node is determined to be the target node. If the number of 1s in the XOR result is 2, then the neighboring nodes of the source node are determined as at least one candidate node corresponding to the shortest path.

6. The method according to claim 4, characterized in that, The step of XORing a preset number of other bits in the label sequences of the source node and the target node to determine the number of 1s in the XOR result, and combining this with the routing type to determine at least one candidate node corresponding to the shortest path of the source node, further includes: If the routing type is an outer-to-outer-route request, a preset number of other bits in the label sequence of the source node and the target node are XORed to determine the first XOR result. If the number of 1s in the first XOR processing result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node. If the number of 1s in the first XOR result is not 3, the subvector corresponding to each 1 in the first XOR result is split into at least one subvector. The at least one subvector is then XORed with a preset number of other bits in the label sequence of the source node to determine the second XOR result. Remove the preset illegal results from the second XOR processing result, and randomly select the node corresponding to the remaining legal result in the second XOR processing result as at least one candidate node corresponding to the shortest path of the source node.

7. The method according to claim 4, characterized in that, The step of XORing a preset number of other bits in the label sequences of the source node and the target node to determine the number of 1s in the XOR result, and combining this with the routing type to determine at least one candidate node corresponding to the shortest path of the source node, further includes: If the routing type is an outer-to-inner routing request, a preset number of other bits in the label sequence of the source node and the target node are XORed to determine the XOR result. If the number of 1s in the XOR result is 0, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node, and the node is the target node. If the number of 1s in the XOR result is 1, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node, or a node on the outer polygon topology connected to the target node. If the number of 1s in the XOR result is 2, the next hop node of the source node is determined to be the first adjacent node, the second adjacent node, or a node on the inner polygon topology connected to the source node. If the number of 1s in the XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the source node.

8. The method according to claim 4, characterized in that, The step of XORing a preset number of other bits in the label sequences of the source node and the target node to determine the number of 1s in the XOR result, and combining this with the routing type to determine at least one candidate node corresponding to the shortest path of the source node, further includes: If the routing type is an inner-to-outer-layer routing request, a preset number of other bits in the label sequence of the source node and the target node are XORed to determine the XOR result. If the number of 1s in the XOR result is 0, the next hop node of the source node is determined to be a node on the outer polygon topology connected to the source node, and the node is the target node. If the number of 1s in the XOR result is 1, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the target node, or a node on the outer polygon topology connected to the source node. If the number of 1s in the XOR result is 2, the next hop node of the source node is determined to be the first adjacent node, the second adjacent node, the third adjacent node of the source node, or a node on the outer polygon topology connected to the source node. If the number of 1s in the XOR result is 3, the next hop node of the source node is determined to be a node on the inner polygon topology connected to the target node.

9. The method according to any one of claims 1-8, characterized in that, The step of determining the availability status of the deadlock prevention node, and if the availability status of the deadlock prevention node is idle, determining the routing bypass information of the deadlock prevention node, and sending the routing bypass information to the source node, includes: Determine at least one exit node in the exit direction of the shortest path from the source node to prevent deadlock, and generate a node availability state vector based on the at least one exit node; The routing type is determined based on the highest bit of the label sequence of the deadlock prevention node and the target node, and at least one candidate node corresponding to the shortest path of the deadlock prevention node is determined in combination with the routing type. Based on at least one candidate node of the deadlock prevention node, filter the at least one exit node, remove the exit nodes that are not the shortest path, and set the bits corresponding to the exit nodes that are not the shortest path in the available state vector of the node to 0. Determine the availability status of other exit nodes in the filtered node availability status vector. If the availability status of an exit node is idle, set the corresponding bit in the filtered node availability status vector to 1; if the availability status of an exit node is congested, set the corresponding bit in the filtered node availability status vector to 0. The filtered node available state vector is bitwise ORed. If the bitwise OR result is 1, the available state of the anti-deadlock node is determined to be idle. The exit node corresponding to the least significant bit of the filtered node available state vector with a median of 1 is taken as the subsequent node of the anti-deadlock node, and the label sequence of the subsequent node is taken as the routing bypass information. If the bitwise OR operation result is 0, the available state of the anti-deadlock node is determined to be congested.

10. The method according to claim 9, characterized in that, The step of determining the availability status of the ordinary node and generating a routing vector for at least one candidate node in conjunction with the availability status of the deadlock prevention node, so that the source node determines the next-hop node according to the routing vector and sends the data packet to the next-hop node, and uses the next-hop node as the new source node, includes: Obtain the availability status of ordinary nodes. If the availability status of an ordinary node is idle, set the corresponding bit of the ordinary node in the routing vector to 1. Obtain the availability status of the anti-deadlock node. If the availability status of the anti-deadlock node is idle, set the corresponding bit of the anti-deadlock node in the routing vector to 1. The candidate node corresponding to the least significant bit of the routing vector with a median of 1 is determined. The candidate node is then used as the next-hop node, and the source node sends the data packet to the next-hop node, which is then used as the new source node.

11. The method according to claim 10, characterized in that, The method further includes: If the next-hop node is a deadlock prevention node, the data packet and the routing bypass information corresponding to the deadlock prevention node are sent from the source node to the deadlock prevention node, so that the deadlock prevention node can de-flow and buffer the data packet into the buffer queue corresponding to the output direction of the subsequent node according to the routing bypass information; If the amount of data stored in the cache queue is greater than a preset storage threshold, the anti-deadlock node will return a full status signal as a backpressure signal to the source node, so that the source node will suspend sending data packets in that output direction after receiving the backpressure signal until it receives a non-full status signal.

12. The method according to claim 11, characterized in that, The method further includes: enabling the anti-deadlock node to monitor the non-empty state of the buffer queues in each output direction in real time; and if it receives arbitration information sent by a subsequent node, sending the data packet to the subsequent node through a handshake protocol.

13. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the shortest route and deadlock avoidance method for a two-layer polygon topology as described in any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the shortest route and deadlock avoidance method for a two-layer polygon topology as described in any one of claims 1 to 12.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the shortest route and deadlock avoidance method for a two-layer polygon topology as described in any one of claims 1 to 12.

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