Address allocation method

Abstract

The invention provides an address allocation method, and an address allocation circuit transmits address allocation trigger signals output by a first control unit one by one through at least two trigger signal processing units, so that each trigger signal processing unit obtains the address allocation trigger signals; sending an address receiving trigger signal to a second control unit connected with the first control unit, controlling the response of the second control unit to the address receiving trigger signal to obtain an address to be allocated from the first control unit so as to carry out corresponding address allocation, and after the second control unit completes address allocation, sending the address to be allocated to the second control unit. And controlling the second control unit to send a feedback signal to the trigger signal processing unit corresponding to the second control unit so as to control the transmission of the address allocation trigger signal among the trigger signal processing units, thereby simplifying the calculation process of resource allocation and transmission logic of the address data in the first control unit. Therefore, the address allocation complexity of the battery management system is reduced, and the address allocation efficiency is improved.

Description

Technical Field

[0001] This application relates to, but is not limited to, an address allocation method. Background Art

[0002] A lithium battery energy storage system is a large-scale energy storage system formed by connecting multiple single cells with low voltage in series to form battery clusters and then connecting multiple battery clusters in parallel. To ensure the stable operation of each battery cluster, a battery management system is required to monitor the states of each single cell, for example, monitor the voltage and temperature of the single cell. Before monitoring, corresponding addresses need to be set for each single cell to determine the position of the single cell based on the allocated address when a fault occurs in the single cell. In the energy storage system, the voltage of the single cell is much lower than that of the battery cluster. Therefore, the number of single cells connected in series in each battery cluster is large, and the workload of address allocation is large.

[0003] In the related art, before the controller of the applied battery management system leaves the factory, the addresses of each single cell in the energy storage system can be encoded and programmed one by one, but there are problems of low efficiency and easy errors. It is also possible to use the bus between multiple-level control units in the battery management system during the installation and debugging of the battery module to define the data transmission relationship between each slave control unit and the superior controller based on the communication protocol and allocate the corresponding addresses for each single cell. The above process relies on the resource allocation of address data, the operation of transmission logic, and the multiplexing of the bus in the battery management system, which will occupy the data storage resources of each device and lengthen the overall operation time.

[0004] Therefore, how to reduce the complexity of address allocation by the battery management system and improve the efficiency of address allocation has become the focus of research. Summary of the Invention

[0005] This application provides an address allocation method to solve the above technical problems.

[0006] An embodiment of this application provides an address allocation method, which is applied to an address allocation circuit. The address allocation circuit includes: a first control unit, at least two trigger signal processing units, and at least two second control units. The first control unit is connected to the first trigger signal processing unit among the at least two trigger signal processing units and is also connected to each of the second control units. The at least two trigger signal processing units are connected in series, and each trigger signal processing unit is connected to a corresponding second control unit;

[0007] Output an address allocation trigger signal and an address to be allocated through the first control unit;

[0008] For each of the trigger signal processing units, after obtaining the address allocation trigger signal, control it to generate and send an address reception trigger signal to a second control unit connected thereto based on the address allocation trigger signal, so that when the second control unit obtains the address reception trigger signal, it obtains the address to be allocated from the first control unit;

[0009] After the second control unit completes the address allocation of the device address it supervises with the address to be allocated, control the second control unit to output a feedback signal to the trigger signal processing unit connected thereto;

[0010] Control the trigger signal processing unit to output the address allocation trigger signal according to the feedback signal until the second control unit connected to the trigger signal processing unit at the end of the at least two trigger signal processing units completes the address allocation.

[0011] In the above technical solution, the address allocation circuit sequentially transmits the address allocation trigger signal output by the first control unit through at least two trigger signal processing units, so that after each trigger signal processing unit obtains the address allocation trigger signal, it sends an address reception trigger signal generated based on the address allocation trigger signal to the second control unit connected thereto. By controlling the response of the second control unit to the address reception trigger signal, the address to be allocated is obtained from the first control unit for corresponding address allocation. After the second control unit completes the address allocation, control the second control unit to send a feedback signal to its corresponding trigger signal processing unit to control the transmission of the address allocation trigger signal between the trigger signal processing units. The above address allocation method simplifies the calculation process of resource allocation and transmission logic of address data inside the first control unit, thereby reducing the address allocation complexity of the battery management system and improving the address allocation efficiency.

[0012] In a feasible embodiment, the trigger signal processing unit includes a trigger signal transmission unit and a trigger signal reception unit, and the trigger signal transmission unit includes a first signal conversion module;

[0013] For each of the trigger signal processing units, controlling it to generate an address reception trigger signal based on the address allocation trigger signal after obtaining the address allocation trigger signal includes:

[0014] For each of the trigger signal processing units, obtain the address allocation trigger signal through the trigger signal transmission unit, and control the first signal conversion module to generate and send a first trigger signal to the trigger signal reception unit based on the address allocation trigger signal;

[0015] Control the trigger signal reception unit to generate the address reception trigger signal based on the first trigger signal.

[0016] In a feasible embodiment, the first signal conversion module includes a first switching device;

[0017] Controlling the first signal conversion module to generate and send a first trigger signal to the trigger signal receiving unit based on the address assignment trigger signal includes:

[0018] Controlling the first switching device to obtain the address assignment trigger signal from its control terminal, obtain a first preset signal from its first terminal, control its first terminal and second terminal to conduct by the address assignment trigger signal, and when it conducts, output the first preset signal from its second terminal as the first trigger signal.

[0019] In a feasible embodiment, the trigger signal receiving unit includes a second switching device, and the control terminal of the second switching device is connected to the second terminal of the first switching device;

[0020] Controlling the trigger signal receiving unit to generate the address receiving trigger signal based on the first trigger signal includes:

[0021] Controlling the second switching device to obtain the first trigger signal from its control terminal, obtain a second preset signal from its first terminal, control its first terminal and second terminal to conduct by the first trigger signal, and when it conducts, output the second preset signal from its second terminal as the address receiving trigger signal.

[0022] In a feasible embodiment, the trigger signal transmission unit further includes a signal output control module;

[0023] Controlling the trigger signal processing unit to output the address assignment trigger signal according to the feedback signal includes:

[0024] When the trigger signal processing unit obtains the address assignment trigger signal, controlling the signal output control module to obtain the address assignment trigger signal from its first terminal;

[0025] When the signal output control module obtains the feedback signal, it conducts based on the feedback signal to output the address assignment trigger signal.

[0026] In a feasible embodiment, the address assignment circuit further includes a signal interruption control device, and the trigger signal processing unit at the end among the at least two trigger signal processing units is connected to the signal interruption control device;

[0027] The address assignment method further includes:

[0028] After controlling the trigger signal processing unit at the end to obtain the feedback signal sent by the corresponding connected second control unit, obtain an interrupt signal from the interrupt control device, and transmit the interrupt signal to the first control unit through each of the trigger signal processing units;

[0029] Control the first control unit to stop outputting the to-be-allocated address when obtaining the interrupt signal.

[0030] In a feasible embodiment, in the address allocation circuit, the first control unit and the second control unit are control units for the battery cell module, and the control level of the first control unit is higher than that of the second control unit; the battery cell module includes a plurality of battery cells;

[0031] Outputting the to-be-allocated address through the first control unit includes:

[0032] Control the first control unit to sequentially output a preset number of groups of to-be-allocated addresses after outputting the address allocation trigger signal, where the number of addresses in each group of to-be-allocated addresses is the total number of battery cells controlled by the second control unit;

[0033] The number of groups of the to-be-allocated addresses is the same as the number of the trigger signal processing units.

[0034] In a feasible embodiment, controlling the first control unit to sequentially output a preset number of groups of to-be-allocated addresses includes:

[0035] Control the first control unit to output a group of to-be-allocated addresses to the bus, and transmit the next group of to-be-allocated addresses after obtaining the feedback signal output by any second control unit.

[0036] In a feasible embodiment, the first control unit includes a first controller and a signal transmission monitoring circuit;

[0037] Outputting the address allocation trigger signal through the first control unit includes:

[0038] Control the signal transmission monitoring circuit to output the address allocation trigger signal to the trigger signal processing unit at the first position through the first controller until the signal transmission monitoring circuit obtains the interrupt signal, and then control the signal transmission monitoring circuit to stop outputting the address allocation trigger signal through the first controller.

[0039] In a feasible embodiment, the second control unit includes at least one second controller and a feedback circuit, the second controller is connected to the feedback circuit, and the second controller is connected to the first control unit through a bus;

[0040] After the second control unit finishes allocating the to-be-allocated address to the device addresses it supervises, it outputs a feedback signal to the trigger signal processing unit connected to it, including:

[0041] In the second control unit, the at least one second controller is used to obtain the address reception trigger signal, and based on the address reception trigger signal, a set of to-be-allocated addresses sent by the first control unit is obtained from the bus, and the mapping relationship between the to-be-allocated address and each battery cell in the battery cell module it manages is constructed;

[0042] After all the second controllers in the second control unit have constructed the mapping relationship, the feedback circuit is controlled to output a feedback signal.

[0043] This application provides an address allocation method. The address allocation circuit sequentially transmits the address allocation trigger signal output by the first control unit through at least two trigger signal processing units, so that after each trigger signal processing unit obtains the address allocation trigger signal, it sends an address reception trigger signal generated based on the address allocation trigger signal to the second control unit connected to it. By controlling the response of the second control unit to the address reception trigger signal, the to-be-allocated address is obtained from the first control unit for corresponding address allocation. After the second control unit finishes the address allocation, the second control unit is controlled to send a feedback signal to its corresponding trigger signal processing unit to control the transmission of the address allocation trigger signal between the trigger signal processing units. The above address allocation method simplifies the calculation process of resource allocation and transmission logic of address data inside the first control unit, thereby reducing the address allocation complexity of the battery management system and improving the address allocation efficiency. Description of the Drawings

[0044] The drawings here are incorporated into the specification and constitute a part of this specification, showing the embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0045] Figure 1A and Figure 1B is a schematic structural diagram of an energy storage system provided by some exemplary embodiments of this application;

[0046] Figure 2 is a schematic structural diagram of an address allocation circuit provided by some embodiments of this application;

[0047] Figure 3 is a schematic flowchart of an address allocation method provided by some embodiments of this application;

[0048] Figure 4A and Figure 4B is a schematic structural diagram of a trigger signal processing unit provided by some embodiments of this application;

[0049] Figure 5 Schematic flowchart of the address allocation method provided in some other embodiments of the present application;

[0050] Figures 6A to 6F Schematic structural diagram of the trigger signal transmission unit provided in some embodiments of the present application;

[0051] Figures 7A to 7D Schematic structural diagram of the trigger signal receiving unit provided in some embodiments of the present application;

[0052] Figure 8 Schematic structural diagram of the address allocation circuit provided in some other embodiments of the present application;

[0053] Figure 9 Schematic flowchart of the address allocation method provided in some other embodiments of the present application;

[0054] Figure 10 Schematic diagram of the circuit connection relationship of the address allocation circuit provided in some embodiments of the present application;

[0055] Figure 11 Schematic diagram of the circuit connection relationship of the battery module provided in some embodiments of the present application;

[0056] Figure 12 Schematic diagram of the circuit connection relationship of the address allocation circuit provided in some other embodiments of the present application.

[0057] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0059] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a" and "the" used in the embodiments of the present application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0060] It should also be noted that the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a commodity or system including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such commodity or system. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the commodity or system including the above elements.

[0061] A lithium battery energy storage system is a large-scale energy storage system formed by connecting multiple single cells in series to form battery clusters at a low voltage and then connecting multiple battery clusters in parallel. In an exemplary embodiment, the schematic structural diagram of the energy storage system is as Figure 1A and Figure 1B shown.

[0062] Figure 1A shows the schematic structural diagram of a battery module. In the battery module 101, it includes multiple single cells, and the positive and negative electrodes of each single cell are connected in series in turn. The voltage value of the battery module 101 is the sum of the voltages of the multiple single resistors connected in series.

[0063] The connection structure of the battery stack composed of multiple battery modules and the corresponding battery management system is as Figure 1B shown. Among them, the positive and negative electrodes of multiple battery modules 101 are connected in series successively to form a battery cluster 201 with a larger voltage value. Each battery cluster 201 is connected to the copper busbar through a corresponding control switch QF. When the control switch QF is turned on, each battery cluster 201 is connected in parallel to form a battery stack. Among them, the control switch QF includes a circuit breaker and a contactor.

[0064] Based on the above battery stack architecture, the battery management system also performs hierarchical management and control accordingly.

[0065] For each battery module 101, a corresponding Battery Management Unit (BMU) 102 is set to collect the status information of each cell in the battery module 101. The status information includes: voltage, temperature, etc.

[0066] For each battery cluster 201, a corresponding Battery Cluster management Unit (BCU) 202 is set to collect the status information of the battery cluster 201 and the status information of each battery module 101 it contains, and control the conduction state of the circuit breaker and contactor connected to the battery cluster 201 and the operation state of the associated air conditioning system based on the collected information. Among them, the status of the battery cluster 201 includes battery cluster voltage, current, battery cluster insulation information, etc.

[0067] For the battery stack, a Battery Array Management System (BMS) 302 is provided to collect information of all battery cells transmitted by the BCU 202, transmit the information to the Energy Management System (EMS) in the background for monitoring, and perform corresponding protection actions when there is a battery status alarm.

[0068] When the battery management system controls the battery cells, corresponding addresses need to be set for each battery cell to determine the position of the battery cell based on the allocated address when a fault occurs in the battery cell. As can be seen from the above-mentioned energy storage system architecture, the number of battery cells in the battery stack is large, and the corresponding address allocation workload is large.

[0069] In the related art, before the controller of the battery management system leaves the factory, the addresses of each battery cell in the energy storage system can be encoded and programmed one by one, but there are problems of low efficiency and easy errors. It is also possible to use the bus between multiple control units in the battery management system during the installation and debugging of the battery module to define the data transmission relationship between each slave control unit and the upper-level controller based on the communication protocol, and allocate the corresponding addresses for each battery cell. The above process relies on the resource allocation of address data, the operation of transmission logic, and the multiplexing of the bus in the battery management system, which will occupy the data storage resources of each device and lengthen the overall operation time.

[0070] Therefore, how to reduce the complexity of address allocation in the battery management system and improve the efficiency of address allocation has become the focus of research.

[0071] To solve the above problems, the present application provides an address allocation method. The technical concept of the present application is: using multiple trigger signal processing units in the energy storage system to control the address allocation process of a first control unit with a higher level to multiple second control units with a lower level, so as to reduce the address allocation calculation process of the first control unit for the second control unit, thereby reducing the complexity of address allocation in the battery management system and improving the efficiency of address allocation.

[0072] The technical solution of the present application will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0073] Figure 2 The structural schematic diagram of the address allocation circuit provided for some embodiments of the present application is as Figure 2As shown in the figure, it includes: a first control unit 401, at least two trigger signal processing units 402, and at least two second control units 403. Among them, the first control unit 401 is connected to at least two trigger signal processing units 402, and the trigger signal processing units 402 and the second control units 403 are connected in one-to-one correspondence. Among them, both the first control unit 401 and the second control unit 403 are control units for devices whose addresses are to be allocated, and the control level of the first control unit 401 is higher than that of the second control unit 403.

[0074] At least two trigger signal processing units 402 are connected in series. The first end of the trigger signal processing unit 402 at the first position is connected to the first control unit 401, and the first ends of the multiple trigger signal processing units 402 at non-first positions are connected to the second end of the previous trigger signal processing unit 402. Each trigger signal processing unit 402 is connected according to its corresponding relationship with the second control unit 403, and each second control unit 403 is connected to the first control unit 401. The above connection relationships include but are not limited to: electrical connection, communication connection, where the communication connection includes a connection based on a wireless communication signal or a connection based on an optical / acoustic signal.

[0075] Figure 3 This application is based on Figure 2 The structural schematic diagram shown provides a flowchart of an address allocation method. As Figure 3 shown, it includes:

[0076] S101: Output an address allocation trigger signal and an address to be allocated through the first control unit.

[0077] S102: For each trigger signal processing unit, control it to generate and send an address reception trigger signal to the second control unit connected to it based on the address allocation trigger signal after obtaining the address allocation trigger signal, so that when the second control unit obtains the address reception trigger signal, it obtains the address to be allocated from the first control unit.

[0078] S103: After the second control unit completes the address allocation for the device it supervises with the address to be allocated, control the second control unit to output a feedback signal to the trigger signal processing unit connected to it.

[0079] The second control unit performs address allocation by constructing a mapping relationship between the address it obtains and the device it manages. When the second control unit is a control unit in a battery management system, it constructs a mapping relationship between the address and the battery cells it manages.

[0080] When the first control unit and the second control unit are control units in a battery management system, when the first control unit is an EMS, the second control unit can be a BMU, a BCU, or a BMS; when the first control unit is a BMS, the second control unit can be a BMU or a BCU; when the first control unit is a BCU, the second control unit is a BMU. When the second control unit is not a BMU, it is also necessary to allocate the obtained address to multiple BMUs it manages.

[0081] S104. The control trigger signal processing unit outputs an address allocation trigger signal according to the feedback signal until the second control unit connected to the last trigger signal processing unit among at least two trigger signal processing units completes the address allocation.

[0082] More specifically, since at least two trigger signal processing units are connected in series, the trigger signal processing unit, under the control of the feedback signal, transmits the address allocation trigger signal generated by the first control unit one by one from the first to the last along the connection order of each unit. The trigger signal processing unit that obtains the address allocation trigger signal sends an address reception trigger signal to the corresponding second control unit, so that the second control unit obtains the address to be allocated from the first control unit, and allocates the obtained address to multiple devices it manages. After the allocation is completed, a feedback signal is generated and transmitted to its corresponding trigger signal processing unit, so that the trigger signal processing unit transmits the address allocation trigger signal to other trigger signal processing units connected to its second end to switch other second control units to allocate the address until all addresses are allocated.

[0083] It should be noted that the addresses to be allocated obtained by different second control units are different.

[0084] The above address allocation method simplifies the calculation process of resource allocation and transmission logic of address data inside the first control unit, thereby reducing the address allocation complexity of the battery management system and improving the address allocation efficiency.

[0085] Next, the internal structure of the trigger signal processing unit 402 will be explained.

[0086] Figure 4A The structural schematic diagram of the trigger signal processing unit provided by some embodiments of the present application is as Figure 4A shown. The trigger signal processing unit 402 includes a trigger signal transmission unit 4021 and a trigger signal reception unit 4022; the trigger signal transmission unit 4021 includes a first signal conversion module 4023 and a signal output control module 4024.

[0087] The first end of the trigger signal transmission unit 4021 serves as the first end of the trigger signal processing unit 402, and this first end is used to obtain the address allocation trigger signal.

[0088] The first end of the first signal conversion module 4023 is connected to the first end of the trigger signal transmission unit 4021, and the second end is connected to the first end of the trigger signal receiving unit 4022. This second end is used to transmit the first trigger signal generated by the first signal conversion module 4023 to the trigger signal receiving unit 4022.

[0089] The second end of the trigger signal receiving unit 4022 is connected to the second control unit corresponding to the trigger signal processing unit 402, and is used to generate an address receiving trigger signal based on the first trigger signal when the first trigger signal is obtained.

[0090] The first end of the signal output control module 4024 is connected to the first end of the trigger signal transmission unit 4021, and its second end serves as the second end of the trigger signal transmission unit 4021, that is, the second end of the trigger signal processing unit 402. This second end is connected to the first connection of the next trigger signal processing unit 402.

[0091] The control end of the signal output control module 4024 is connected to the second control unit corresponding to the trigger signal processing unit 402 where it is located, and is used to connect its first end and its second end when obtaining a feedback signal from its control end, and output the address assignment trigger signal obtained at its first end from its second end.

[0092] During the process of transmitting the address assignment trigger signal between the trigger signal processing units 402, in order to prevent signal attenuation from causing information transmission errors, a signal gain module 4025 is also provided on the signal transmission channel.

[0093] In one embodiment, the signal gain module 4025 is provided on the connection line between two adjacent trigger signal processing units 402.

[0094] In another embodiment, the signal gain module 4025 is integrated within the trigger signal processing unit 402.

[0095] Figure 4B For the trigger signal processing unit 402 integrated with the signal gain module 4025, as shown in the figure, the input end of the signal gain module 4025 is connected to the input end of the trigger signal processing unit 402, and the output end of the signal gain module 4025 is connected to the first ends of the first signal conversion module 4023 and the signal output control module 4024.

[0096] In some scenarios, the Figure 4A shown circuit structure can be used as the circuit structure of the trigger signal processing unit 402 at the first position or the first few positions, and the Figure 4B shown circuit structure can be used as the circuit structure of other trigger signal processing units 402.

[0097] Based on the circuit structure of the above address allocation circuit, the present application also provides another address allocation method, as Figure 5 shown, including:

[0098] S201. Output an address allocation trigger signal and an address to be allocated through the first control unit.

[0099] The first control unit is connected to the bus BUS and the trigger signal processing unit. After outputting the address allocation trigger signal to the trigger signal processing unit through the first control unit, a preset number of groups of addresses to be allocated are sequentially output to the bus BUS. After each group of addresses to be allocated is completed by the second control unit, the transmission of the next group of addresses to be allocated is carried out. Different groups of addresses to be allocated are different.

[0100] Wherein, when the first control unit and the second control unit are control units in a battery management system, the number of addresses in each group of addresses to be allocated is the total number of battery cells controlled by the second control unit.

[0101] The number of groups of the multiple groups of addresses to be allocated is the same as the number of trigger signal processing units.

[0102] S202. For each trigger signal processing unit, obtain the address allocation trigger signal through the trigger signal transmission unit, control the first signal conversion module to generate and send a first trigger signal to the trigger signal receiving unit based on the address allocation trigger signal, and control the signal output control module to obtain the address allocation trigger signal from its first end.

[0103] S203. Control the trigger signal receiving unit to generate an address receiving trigger signal based on the first trigger signal, so that when the second control unit obtains the address receiving trigger signal, it obtains the address to be allocated from the first control unit.

[0104] S204. After the second control unit completes the address allocation of the device it supervises with the address to be allocated, control the second control unit to output a feedback signal to the trigger signal processing unit connected to it.

[0105] S205. When the signal output control module obtains the feedback signal, conduct based on the feedback signal to output the address allocation trigger signal until the second control unit connected to the last trigger signal processing unit among at least two trigger signal processing units completes the address allocation.

[0106] In Figure 4A and Figure 4B the circuit structure shown, in the trigger signal transmission unit 4021, the first signal conversion module 4023 includes a first switching device.

[0107] The first switching device is provided with a first terminal, a second terminal and a control terminal. The control terminal serves as the first terminal of the trigger signal transmission unit. The first switching device is configured to conduct its first terminal and its second terminal when obtaining an address assignment trigger signal from its control terminal, and output the first preset signal obtained at its first terminal from its second terminal as the first trigger signal.

[0108] Among them, the first trigger signal and the feedback signal obtained by the signal output control module can be a current signal, a voltage signal, a preset waveform signal, an optical signal or a sound signal.

[0109] The trigger signal receiving unit 4022 includes a second switching device.

[0110] The second switching device is provided with a first terminal, a second terminal and a control terminal. The second switching device is configured to conduct its first terminal and its second terminal when obtaining the first trigger signal from its control terminal, and output the second preset signal obtained at its first terminal from its second terminal as the address receiving trigger signal.

[0111] The circuit schematic diagram of the trigger signal transmission unit 4021 is as Figures 6A to 6F shown.

[0112] As Figure 6A , 6C , and as shown in 6E, the first switching device in the first signal conversion module 4023 is an NPN-type triode. Its control terminal obtains the address assignment trigger signal, its emitter is grounded, and its collector serves as the terminal for outputting the first trigger signal. When the NPN triode obtains the address assignment trigger signal, its emitter and collector are conducted, and a low-level signal is output from its collector as the first trigger signal.

[0113] As Figure 6B , 6D , and as shown in 6F, the first switching device in the first signal conversion module 4023 is a PNP-type triode. Its control terminal obtains the address assignment trigger signal, its emitter is connected to a voltage source to obtain a preset voltage, and its collector serves as the terminal for outputting the first trigger signal. When the PNP triode obtains the address assignment trigger signal, its emitter and collector are conducted, and a preset level is output from its collector as the first trigger signal.

[0114] In some other embodiments, the first switching tube can also be other controllable transistors or relays. The controllable transistors include but are not limited to light-emitting diodes, thyristors, field-effect transistors, etc.

[0115] As Figure 6A and Figure 6B shown, the signal output control module 4024 includes a controllable switch, whose default state is the off state, and the controllable switch closes when it obtains the feedback signal.

[0116] The controllable switch can be a controllable transistor or a relay.

[0117] More specifically, Figure 6C and Figure 6D the controllable switch shown is an optocoupler device constructed based on a light-emitting diode and a triode, Figure 6E and Figure 6F the controllable switch shown is an optocoupler device constructed based on a light-emitting diode and a field-effect transistor.

[0118] When the optocoupler device obtains a feedback signal, the feedback signal is greater than the turn-on voltage of the light-emitting diode, the light-emitting diode emits light, and the triode or the field-effect transistor conducts, outputting an address allocation trigger signal.

[0119] The circuit structure diagram of the trigger signal receiving unit 4022 is as shown in Figures 7A to 7D shown.

[0120] The second switching device in the trigger signal receiving unit 4022 can be a commonly used controllable switching device (e.g., a triode, a field-effect transistor, etc.), or a device for electrical isolation (e.g., an optocoupler).

[0121] When the first trigger signal is a voltage signal less than the first preset level, the circuit structure of the second switching device is as shown in Figure 7A and Figure 7B shown. In Figure 7A , the first trigger signal is used as the input signal of the optocoupler device. When it is at a low level, the light-emitting diode emits light, and the triode in the optocoupler conducts. The potential value of the address receiving the trigger signal output from the collector is the same as the potential value of the ground connected to the emitter; in Figure 7B , when the triode in the optocoupler conducts, the potential value of the address receiving the trigger signal output from the emitter is the same as the potential value of the second preset voltage electrically connected to the collector.

[0122] Similarly, in Figure 7C and Figure 7D , the light-emitting diode in the optocoupler emits light when it obtains a first trigger signal greater than its turn-on voltage, controlling the triode to output an address receiving the trigger signal.

[0123] An interrupt control device is also provided in the address allocation circuit. Below, the connection relationship between the trigger signal processing unit and the interrupt control device and the internal structures of the first control unit and the second control unit will be explained through an embodiment.

[0124] Figure 8 This is the structure diagram of the address allocation circuit provided by some other embodiments of the present application. As shown in Figure 8As shown in the figure, the first control unit 401 includes a first controller 4011 and a signal transmission monitoring circuit 4012. The first controller 4011 is connected to the bus BUS and the signal transmission monitoring circuit 4012, and the signal transmission monitoring circuit 4012 is connected to the trigger signal transmission unit 4021 at the first position.

[0125] A plurality of trigger signal transmission units 4021 are connected in series. The interruption control device 404 is connected to the trigger signal processing unit 402 at the last position. More specifically, the interruption control device 404 is connected to the second end of the signal output control module 4024 in the trigger signal processing unit 402 at the last position.

[0126] The second control unit 403 is connected to the bus BUS and its corresponding trigger signal processing unit 402.

[0127] The second control unit 401 includes at least one second controller 4031 and a feedback circuit 4032. Each second controller 4031 is connected to the trigger signal processing unit 402, the bus BUS, and the feedback circuit 4032. At least one second controller 4031 simultaneously obtains the address reception trigger signal sent by the trigger signal processing unit 402, and obtains the address from the bus BUS based on this trigger signal.

[0128] Based on the above circuit structure, the present application also provides another address allocation method. The schematic flow diagram of this method is as Figure 9 shown, including:

[0129] S301. Control the signal transmission monitoring circuit by the first controller to output an address allocation trigger signal to the trigger signal processing unit at the first position, and output a set of addresses to be allocated to the bus.

[0130] S302. For each trigger signal processing unit, after obtaining the address allocation trigger signal, control it to generate and send an address reception trigger signal to the second control unit connected thereto based on the address allocation trigger signal.

[0131] The trigger signal transmission unit obtains the address allocation trigger signal from the upstream unit (the first control unit 401 or other trigger signal transmission units 4021), generates an address reception trigger signal based on the address allocation trigger signal, and controls the second control unit communicating with it to allocate addresses based on the address reception trigger signal to manage the transmission process of the address allocation trigger signal.

[0132] S303. In the second control unit, use at least one second controller to obtain the address reception trigger signal, obtain a set of addresses to be allocated sent by the first control unit from the bus based on the address reception trigger signal, and construct the mapping relationship between the addresses to be allocated and each battery cell in the battery module it manages.

[0133] When the second control unit obtains the address reception trigger signal, it acquires the to-be-allocated addresses broadcast by the first control unit from the bus BUS. Among them, the to-be-allocated addresses broadcast by the first control unit are a group of addresses, and the number of addresses in this group is the same as the number of battery cells managed by the second control unit.

[0134] The second control unit constructs a mapping relationship between addresses and battery cells based on this group of addresses to achieve address allocation.

[0135] The second control unit includes at least one second controller and a feedback circuit. Each second controller is connected to the trigger signal processing unit, the bus BUS, and the feedback circuit. At least one second controller simultaneously obtains the address reception trigger signal sent by the trigger signal processing unit and acquires addresses from the bus BUS based on this trigger signal.

[0136] When the number of second controllers in the second control unit is 1, the second controller directly acquires addresses from the bus BUS and performs address allocation.

[0137] When the number of second controllers in the second control unit is at least 2, each second controller acquires a part of the broadcast addresses from the bus BUS based on a preset contention mechanism for address allocation.

[0138] S304. After all the second controllers in the second control unit have constructed the mapping relationship, control the feedback circuit to output a feedback signal.

[0139] When there is one second controller in the second control unit, the feedback circuit obtains the control signal generated after the second controller completes address allocation and generates a feedback signal based on this control signal.

[0140] When there are at least two second controllers in the second control unit, for each second controller, when it completes the address allocation of the battery cells it manages, it transmits a control signal to the feedback circuit, and the feedback circuit determines the address allocation situation of all the battery cells managed by the second control unit based on the reception situation of the control signal.

[0141] In an embodiment, the control signals transmitted by each second controller are high-level signals. Then the feedback circuit performs an AND operation on the obtained signals. When the result is high level, it is determined that all the second controllers have completed address allocation, and then a feedback signal is output.

[0142] S305. Control the trigger signal processing unit to output an address allocation trigger signal according to the feedback signal.

[0143] On the one hand, the feedback signal is transmitted to the bus BUS so that the first controller can obtain it and adjust the address it broadcasts on the bus BUS based on the feedback signal. On the other hand, it is fed back to the output end of the signal output control module in the trigger signal processing unit 402 connected thereto.

[0144] S306. Determine whether the trigger signal processing unit at the end has obtained the interruption signal sent by the interruption control device.

[0145] Since the trigger signal processing units are connected in series, after obtaining the address assignment trigger signal, they keep the state of transmitting the address assignment trigger signal until the signal is transmitted to the interruption control device.

[0146] When the signal is not transmitted to the interruption control device and the second control unit corresponding to the trigger signal processing unit at the end has not completed the address assignment, the first end and the second end of the signal output control module therein are disconnected, and the interruption control device cannot transmit the interruption signal to the first control unit.

[0147] In one embodiment, the interruption control device is a grounding device, and the interruption signal generated by it is a grounding signal.

[0148] When the signal is transmitted to the interruption control device, the interruption control device generates an interruption signal based on this and feeds back the interruption signal to the signal transmission monitoring unit in the first control unit along the opposite direction of the address assignment trigger signal transmitted by each trigger signal processing unit. The signal transmission monitoring unit will generate an interruption trigger signal based on the interruption signal so that the first controller stops generating the address assignment trigger signal and stops broadcasting the address to be assigned.

[0149] If yes, go to step S308; otherwise, go to step S307.

[0150] S307. Determine the next group of addresses to be output by the first controller.

[0151] The first controller stores multiple groups of addresses. The pointers, addresses, or labels corresponding to different addresses are different. After the first controller receives the feedback information during the process of broadcasting a group of addresses, it adjusts the pointers, addresses, or labels, and obtains the next available address based on the adjusted pointers, addresses, or labels for broadcasting.

[0152] S308. Control the first control unit to stop outputting the address to be assigned and the address assignment trigger signal when obtaining the interruption signal from each trigger signal processing unit.

[0153] Next, the circuit structure and operation process of the address assignment circuit will be explained through an embodiment.

[0154] The circuit structure is as Figure 10As shown in the figure, the first control unit is arranged in the busbar cabinet. The first control unit includes K0 and a controller. The IO port of the controller is connected to the DGND terminal of K0. K1 to Kn are the aforementioned trigger signal transmission units. When performing address allocation, the first control unit broadcasts address signals to multiple battery modules outside the busbar cabinet. At the same time, a power supply providing 24V is connected to K0(1). The 24V voltage signal passes through K0(2) and flows to K1(1), triggering battery module 1 to perform address allocation. After battery module 1 completes address allocation, K1 closes, and the 24V voltage signal continues to be transmitted downward, flowing through K1(2) to K2(1), triggering battery module 2 to perform address allocation, and so on in a cycle until the last battery module, that is, after battery module n completes address allocation, the 24V voltage is connected and conducted to the 24V ground signal (24G), causing the current of the light-emitting diode in K0 to conduct, the diode emits light, the opto-coupler switch opens, the 3.3V terminal is connected to the digital ground DGND, and the level of the IO port DI (digital input port) of the controller changes from low level to 3.3V high level, completing the feedback to the main control unit that the address allocation of all battery modules is completed.

[0155] The circuit structure diagrams of each battery module are as Figure 11 shown, including an opto-coupler D1, a triode D2, a controllable switch K1, and a control device D3. The control terminal of the triode D2 is connected to K1(1). The collector of the triode D2 is connected to the negative electrode of the light-emitting diode in the opto-coupler D1. The emitter of the triode D2 is grounded. The positive electrode of the light-emitting diode in the opto-coupler D1 is connected to the 24V positive voltage. The emitter of the triode in the opto-coupler D1 is connected to the 3.3V positive voltage, and the collector is connected to the input terminal of the controller in the second control unit. The control terminal of the controllable switch K1 is connected to the control device D3. In one embodiment, the control device D3 is a light-emitting diode.

[0156] When K1(1) obtains a 24V voltage signal, the triode D2 conducts, and a ground signal is output from its collector as the first trigger signal. The light-emitting diode in the opto-coupler D1 emits light, the triode conducts, and a 3.3V electrical signal is output from its collector. The input terminal of the controller in the second control unit detects that the received electrical signal changes from low level to high level, performs address allocation, and after completion, transmits a feedback signal to drive and control the light-emitting diode in D3 to emit light, so that K1 conducts, K1(2) obtains a 24V voltage signal, and drives the next battery module to work.

[0157] Based on Figure 11 the circuit structure of the battery module shown in the figure, Figure 10 the circuit structure of the address allocation circuit shown in the figure can be as Figure 12 shown. Its operation process has been explained above and will not be elaborated here.

[0158] Other embodiments of the present application will be readily contemplated by those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0159] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. An address allocation method, characterized in that, The method is applied to an address allocation circuit, which includes: a first control unit, at least two trigger signal processing units, and at least two second control units. The first control unit is connected to the first trigger signal processing unit among the at least two trigger signal processing units and is also connected to each of the second control units. The at least two trigger signal processing units are connected in series, and each trigger signal processing unit is connected to a corresponding second control unit; Output an address allocation trigger signal and an address to be allocated through the first control unit; For each of the trigger signal processing units, after obtaining the address allocation trigger signal, control it to generate and send an address reception trigger signal to the second control unit connected thereto based on the address allocation trigger signal, so that when the second control unit obtains the address reception trigger signal, it obtains the address to be allocated from the first control unit; After the second control unit completes the address allocation for the device addresses it supervises, control the second control unit to output a feedback signal to the trigger signal processing unit connected thereto; Control the trigger signal processing unit to output the address allocation trigger signal according to the feedback signal until the second control unit connected to the last trigger signal processing unit among the at least two trigger signal processing units completes the address allocation.

2. The address allocation method according to claim 1, wherein The trigger signal processing unit includes a trigger signal transmission unit and a trigger signal reception unit, and the trigger signal transmission unit includes a first signal conversion module; For each of the trigger signal processing units, controlling it to generate an address reception trigger signal based on the address allocation trigger signal after obtaining the address allocation trigger signal includes: For each of the trigger signal processing units, obtain the address allocation trigger signal through the trigger signal transmission unit, and control the first signal conversion module to generate and send a first trigger signal to the trigger signal reception unit based on the address allocation trigger signal; Control the trigger signal reception unit to generate the address reception trigger signal based on the first trigger signal.

3. The address allocation method according to claim 2, characterized in that, The first signal conversion module includes a first switching device; Controlling the first signal conversion module to generate and send a first trigger signal to the trigger signal reception unit based on the address allocation trigger signal includes: Control the first switching device to obtain the address allocation trigger signal from its control terminal and obtain a first preset signal from its first terminal. The address allocation trigger signal controls the conduction of its first terminal and second terminal. When it is conducting, output the first preset signal from its second terminal as the first trigger signal.

4. The address allocation method according to claim 3, wherein The trigger signal reception unit includes a second switching device, and the control terminal of the second switching device is connected to the second terminal of the first switching device; Controlling the trigger signal reception unit to generate the address reception trigger signal based on the first trigger signal includes: Control the second switching device to obtain the first trigger signal from its control terminal, obtain a second preset signal from its first terminal, control its first terminal and second terminal to conduct by the first trigger signal, and when it conducts, output the second preset signal from its second terminal as the address reception trigger signal.

5. The address allocation method according to claim 2, wherein The trigger signal transmission unit further includes a signal output control module; Controlling the trigger signal processing unit to output the address assignment trigger signal according to the feedback signal includes: When the trigger signal processing unit obtains the address assignment trigger signal, controlling the signal output control module to obtain the address assignment trigger signal from its first terminal; When the signal output control module obtains the feedback signal, conduct based on the feedback signal to output the address assignment trigger signal.

6. The address allocation method according to any one of claims 1 to 5, characterized in that The address assignment circuit further includes a signal interruption control device, and the trigger signal processing unit at the end among the at least two trigger signal processing units is connected to the signal interruption control device; The address assignment method further includes: After controlling the trigger signal processing unit at the end to obtain the feedback signal sent by the corresponding connected second control unit, obtain an interruption signal from the interruption control device, and transmit the interruption signal to the first control unit through each trigger signal processing unit; Control the first control unit to stop outputting the address to be assigned when obtaining the interruption signal.

7. The address allocation method according to claim 6, wherein In the address assignment circuit, the first control unit and the second control unit are control units for the battery cell module, and the control level of the first control unit is higher than that of the second control unit; The battery cell module includes a plurality of battery cells; Outputting the address to be assigned through the first control unit includes: Controlling the first control unit to sequentially output a preset number of groups of addresses to be assigned after outputting the address assignment trigger signal, where the number of addresses in each group of addresses to be assigned is the total number of battery cells controlled by the second control unit; The number of groups of the plurality of groups of addresses to be assigned is the same as the number of trigger signal processing units.

8. The address allocation method according to claim 7, wherein Controlling the first control unit to sequentially output a preset number of groups of addresses to be assigned includes: Controlling the first control unit to output a group of addresses to be assigned to the bus, and transmit the next group of addresses to be assigned after obtaining the feedback signal output by any second control unit.

9. The address allocation method according to claim 7, wherein The first control unit includes a first controller and a signal transmission monitoring circuit; Outputting the address assignment trigger signal through the first control unit includes: Controlling the signal transmission monitoring circuit to output the address assignment trigger signal to the trigger signal processing unit at the first place through the first controller, and until the signal transmission monitoring circuit obtains the interruption signal, controlling the signal transmission monitoring circuit to stop outputting the address assignment trigger signal through the first controller.

10. The address allocation method according to claim 1, wherein The second control unit includes at least one second controller and a feedback circuit, the second controller is connected to the feedback circuit, and the second controller is connected to the first control unit through a bus; After the second control unit has completed the allocation of the to-be-allocated address to the device addresses it supervises, it outputs a feedback signal to the trigger signal processing unit connected to it, including: In the second control unit, the at least one second controller is used to obtain the address reception trigger signal, and based on the address reception trigger signal, a set of to-be-allocated addresses sent by the first control unit is acquired from the bus, and a mapping relationship between the to-be-allocated address and each battery cell in the battery cell module it manages is constructed; After all the second controllers in the second control unit have completed the construction of the mapping relationship, the feedback circuit is controlled to output a feedback signal.

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