Semiconductor device and preparation method thereof
Through the self-aligned semiconductor device structure, the problem of high power consumption and process node gap between BiCMOS circuit is solved, and high frequency compatible and low-cost semiconductor devices are realized, suitable for 6G, vehicle-mounted radar and optical communications.
Patent Information
- Application Number
- CN202510392176.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-22
AI Technical Summary
The existing BiCMOS circuit has the problem of high power consumption and inability to further improve the operating frequency, and there is a gap in manufacturing process nodes between the BJT/HBT process and the CMOS process, and the cost of improving lithography technology is high.
The semiconductor device structure adopts a self-aligned design, including growing epitaxial stacks on the substrate, and forming a self-aligned semiconductor structure through multiple side wall transfers and etching, using conductive metal materials to fill the connection through holes, reducing manufacturing difficulty and cost, and improving process node compatibility.
It reduces device power consumption, reduces device size, achieves high frequency compatibility with FinFET/GAA devices, supports THz high-frequency circuit applications, and is suitable for 6G, vehicle-mounted radar and optical communication fields.
Smart Images
Figure CN120358759A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art
[0002] With the development of technologies such as 6G technology, vehicle-mounted lidar, and optical interconnection chips, higher requirements are put forward for higher-frequency processing circuits. For example, it is required that the BiCMOS circuit can increase the operating frequency to THz, reduce power consumption, and control costs.
[0003] In the prior art, the BiCMOS circuit manufactured by the planar process has problems such as high power consumption and inability to further increase the operating frequency. Moreover, there is a large gap in the manufacturing process nodes between the BJT / HBT process and the CMOS process. If the BJT manufacturing node is improved through lithography technology, it will inevitably bring a huge increase in cost. Summary of the Invention
[0004] In view of the above problems, the present disclosure provides a semiconductor device and a method for manufacturing the same.
[0005] One aspect of the present disclosure provides a semiconductor device, including: 4Q×M semiconductor structures, where, taking the first direction as rows and the second direction as columns, each row of the semiconductor device includes 4Q semiconductor structures, each column of the semiconductor device includes M semiconductor structures, M is determined according to the lithography selection condition, M is an integer greater than or equal to 1, and Q is an integer greater than or equal to 1; the semiconductor structure includes: a substrate; a first N-type epitaxial layer formed on the substrate; a P-type epitaxial layer formed on the first N-type epitaxial layer; a second N-type epitaxial layer formed on the P-type epitaxial layer; wherein, the first side edges of the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are aligned vertically, the second side edges of the substrate, the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are gradually shortened layer by layer from bottom to top in the vertical direction, and the first side edge and the second side edge of the same layer are opposite side edges; connection vias are sequentially arranged on the upper surfaces of the substrate, the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer, and the connection vias are filled with a conductive metal material.
[0006] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: growing an epitaxial stack on a substrate, where the epitaxial stack includes a first N-type epitaxial layer, a P-type epitaxial layer, and a second N-type epitaxial layer arranged in sequence; performing N-type doping implantation on the second N-type epitaxial layer, and sequentially depositing an amorphous carbon layer and a silicon nitride layer on the second N-type epitaxial layer; performing Q sidewall transfers on the silicon nitride layer according to a preset pattern to form Q annular oxide layers on the surface of the amorphous carbon layer; based on the Q annular oxide layers, sequentially performing sidewall deposition and etching on the amorphous carbon layer, the second N-type epitaxial layer, the P-type epitaxial layer, and the first N-type epitaxial layer to form vertical silicon nitride layers on the surfaces of the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate and vertical oxide layers vertically connected to the vertical silicon nitride layers in the vertical direction; polishing the vertical silicon nitride layers and the vertical oxide layers to expose the surface of the amorphous carbon layer, and based on the amorphous carbon layer, etching the amorphous carbon layer, the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate to form a target window exposing the substrate, and filling the target window with a filling material; performing photolithography on the vertical silicon nitride layers, the vertical oxide layers, and the filling material according to a preset pattern for lithography selection conditions to expose the substrate, and filling the trenches formed by the photolithography with a filling material; etching away the vertical silicon nitride layers to respectively form connection through holes exposing the surfaces of the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate; filling the connection through holes with a conductive metal material to form a semiconductor device.
[0007] According to the semiconductor device and its manufacturing method provided by the present disclosure, according to the lithography selection conditions, the number of rows of semiconductor structures to be prepared in the semiconductor device to be prepared is ensured, and the first side edges of the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are aligned vertically, so that the manufactured semiconductor device, through the self-aligned design of the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the semiconductor structure, greatly reduces the manufacturing difficulty, reduces the manufacturing cost, reduces the device size, reduces the device power consumption, and the manufactured semiconductor device can be highly compatible with the FinFET / GAA device manufacturing process, facilitating the integration of high-frequency BiCMOS circuits with FinFET / GAA devices, contributing to the realization of THz (terahertz) high-frequency circuits, and providing solutions for application fields such as 6G / vehicle-mounted radar / optical communication. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above content and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:
[0009] Figure 1 Schematically shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
[0010] Figures 2A to 33A Schematically shows a cross-sectional view along a first direction during the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;
[0011] Figures 2B to 33B Schematically shows a top view during the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;
[0012] Figure 8C Schematically shows a cross-sectional view along a first direction of an annular oxide formed in the case of Q = 2 according to an embodiment of the present disclosure;
[0013] Figure 8D Schematically shows a top view of forming an annular oxide layer in the case of Q = 2 according to an embodiment of the present disclosure;
[0014] Figure 29C Schematically shows a top view after lithography according to lithography selection conditions in an embodiment of the present disclosure;
[0015] Figure 29D Schematically shows a top view after filling after lithography according to lithography selection conditions in an embodiment of the present disclosure. Detailed implementation manners
[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.
[0017] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0018] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0019] In the case of using expressions such as "at least one of A, B, and C", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).
[0020] Embodiments of the present disclosure provide a semiconductor device, which may include 4Q×M semiconductor structures.
[0021] Among them, taking the first direction as rows and the second direction as columns, each row of the semiconductor device may include 4Q semiconductor structures, and each column of the semiconductor device may include M semiconductor structures, that is, the semiconductor device may be composed of M rows and 4Q columns of semiconductor structures. Among them, M is determined according to the lithography selection conditions, M is an integer greater than or equal to 1, and Q is an integer greater than or equal to 1.
[0022] For each semiconductor structure in the semiconductor device, the semiconductor structure may include a substrate; a first N-type epitaxial layer formed on the substrate; a P-type epitaxial layer formed on the first N-type epitaxial layer; a second N-type epitaxial layer formed on the P-type epitaxial layer; and connection vias sequentially arranged on the upper surfaces of the substrate, the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer, and the connection vias are filled with a conductive metal material.
[0023] Among them, in each semiconductor structure, the first side edges of the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are aligned vertically, and the second side edges of the substrate, the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are shortened layer by layer from bottom to top in the vertical direction, and the first side edge and the second side edge of the same layer are opposite side edges.
[0024] According to the embodiments of the present disclosure, based on the lithography selection conditions, the number of rows of semiconductor structures to be prepared in the semiconductor device to be prepared is ensured, and the first side edges of the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are aligned vertically, so that the prepared semiconductor device has a self-aligned design of the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the semiconductor structure, greatly reducing the manufacturing difficulty, reducing the manufacturing cost, reducing the device size, reducing the device power consumption, and the prepared semiconductor device can be highly compatible with the FinFET / GAA device manufacturing process, facilitating the integration of high-frequency BiCMOS circuits with FinFET / GAA devices, contributing to the realization of THz (terahertz) high-frequency circuits, and providing solutions for application fields such as 6G / vehicle-mounted radar / optical communication, etc.
[0025] Figure 1 A flowchart schematically showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.
[0026] As Figure 1 shown, the method includes operations S101 to S108.
[0027] In operation S101, an epitaxial stack is grown on a substrate, wherein the epitaxial stack may include a first N-type epitaxial layer, a P-type epitaxial layer, and a second N-type epitaxial layer sequentially arranged.
[0028] Figure 2A is a cross-sectional view of the substrate and the epitaxial stack along a first direction during the process of manufacturing a semiconductor device. Figure 2B is a top view of forming the epitaxial stack during the process of manufacturing a semiconductor device.
[0029] As Figure 2A shown, an epitaxial stack may be grown on the substrate 210, and the epitaxial stack may include a first N-type epitaxial layer 220, a P-type epitaxial layer 230, and a second N-type epitaxial layer 240 sequentially arranged on the substrate 210.
[0030] Wherein, the materials of the substrate and the epitaxial stack may be determined according to the type of the semiconductor device to be manufactured.
[0031] For example, in the case where the semiconductor device to be manufactured is a silicon-germanium heterojunction bipolar transistor, the first N-type epitaxial layer may include N-type silicon, the second N-type epitaxial layer may also include N-type silicon, and the P-type epitaxial layer may include a P-type silicon-germanium alloy.
[0032] As Figure 2B shown, the direction of the horizontal line is the first direction, and the direction perpendicular to the first direction is the second direction. Figure 2A may be Figure 2B the cross-sectional view from the horizontal line in.
[0033] In operation S102, N-type doping implantation is performed on the second N-type epitaxial layer, and an amorphous carbon layer and a silicon nitride layer are sequentially deposited on the second N-type epitaxial layer.
[0034] Figure 3A and Figure 4A are cross-sectional views of the amorphous carbon layer and the silicon nitride layer along the first direction during the process of manufacturing a semiconductor device. Figure 3B and Figure 4B are top views of forming the amorphous carbon layer and the silicon nitride layer during the process of manufacturing a semiconductor device.
[0035] According to an embodiment of the present disclosure, N-type doping implantation is performed on the second N-type epitaxial layer, that is, an N-type doping material is implanted into the second N-type epitaxial layer to reduce the contact resistance. Wherein, the N-type doping material may be a pentavalent element, such as phosphorus.
[0036] As Figure 3A shown, phosphorus can be implanted into the second N-type epitaxial layer 240, but the layer thickness of the second N-type epitaxial layer 240 does not change.
[0037] According to an embodiment of the present disclosure, after N-type doping implantation of the second N-type epitaxial layer, an amorphous carbon layer and a silicon nitride layer are sequentially deposited on the second N-type epitaxial layer.
[0038] Among them, the amorphous carbon layer has high hardness and corrosion resistance, and can effectively protect the epitaxial stack below the amorphous carbon layer from possible damage during subsequent process steps.
[0039] As Figure 4A shown, an amorphous carbon layer 410 and a silicon nitride layer 420 can be sequentially deposited on the second N-type epitaxial layer 240.
[0040] In operation S103, according to a preset pattern, the silicon nitride layer is subjected to Q sidewall transfers to form Q annular oxide layers on the surface of the amorphous carbon layer. Wherein, Q is an integer greater than or equal to 1.
[0041] Taking Q = 1 as an example, a layer of photoresist (PR, PhotoResist) is coated on the silicon nitride layer, and according to a preset pattern, the photoresist is irradiated. After exposure, the photoresist is developed by a developer to remove the photoresist in the unexposed area, leaving a photoresist pattern in the exposed area, and using the photoresist with the preset pattern as a mask, the silicon nitride layer is etched. After the etching is completed, the remaining photoresist is removed.
[0042] Among them, the photoresist outside the preset pattern is irradiated to leave the photoresist with the preset pattern.
[0043] Figures 5A to 8A is a cross-sectional view along the first direction of forming an annular oxide during the process of manufacturing a semiconductor device. Figures 5B to 8B is a top view of forming an annular oxide during the process of manufacturing a semiconductor device.
[0044] As Figure 5A shown, the photoresist in the unexposed area is removed, leaving the photoresist 520 in the exposed area. The silicon nitride layer can be etched using the photoresist 520 as a mask. After the etching is completed, the silicon nitride layer 510 can be obtained.
[0045] According to an embodiment of the present disclosure, after removing the remaining photoresist 520, an oxide can be deposited on the etched silicon nitride layer 510 to cover the surfaces of the amorphous carbon layer and the etched silicon nitride layer. Among them, the oxide can be a silicon dioxide material.
[0046] As Figure 6AAs shown in [reference], after removing the remaining photoresist, an oxide layer 610 can be deposited on the etched silicon nitride layer 510.
[0047] According to an embodiment of the present disclosure, the oxide layer is etched to expose the surfaces of the etched silicon nitride layer and the amorphous carbon layer, leaving only the oxide around the etched silicon nitride layer.
[0048] As Figure 7A shown in [reference], the oxide is etched, leaving only the oxide around the etched silicon nitride layer 510 to form an annular oxide layer 1.
[0049] According to an embodiment of the present disclosure, after leaving the oxide layer around the etched silicon nitride layer, the silicon nitride layer is etched away to expose the surface of the amorphous carbon layer and form an annular oxide layer on the surface of the amorphous carbon layer.
[0050] As Figure 8A shown in [reference], etching away the remaining silicon nitride layer 510 can form an annular oxide layer 1 on the surface of the amorphous carbon layer 410.
[0051] Based on the above, according to a preset pattern, sidewall transfer is performed on the silicon nitride layer, and an annular oxide layer can be formed on the surface of the amorphous carbon layer.
[0052] When Q is equal to 1, according to a preset pattern, sidewall transfer is performed on the silicon nitride layer once, and one annular oxide layer can be formed on the surface of the amorphous carbon layer, such as the annular oxide layer 1 obtained through the process shown in Figures 5A to 8A [reference]. As Figure 8B shown, when Q = 1, there is one annular oxide layer 1 on the amorphous carbon layer 410.
[0053] When Q is greater than or equal to 2, after performing sidewall transfer on the silicon nitride layer once, the remaining silicon nitride layer is not etched away first. Based on the remaining silicon nitride layer, subsequent sidewall transfers are performed in sequence to finally obtain Q annular oxide layers.
[0054] For example, when Q = 2, the annular oxide layer obtained by performing the second sidewall transfer is located within the annular region of the annular oxide layer obtained by performing the first sidewall transfer, so as to form two annular oxide layers on the amorphous carbon layer.
[0055] Figure 8C is a cross-sectional view along the first direction of the annular oxide formed when Q = 2 during the process of manufacturing a semiconductor device. Figure 8D is a top view of the annular oxide layer formed when Q = 2 during the process of manufacturing a semiconductor device.
[0056] As Figure 8C andFigure 8D As shown, when Q = 2, two annular oxide layers, such as the first annular oxide layer 1 and the second annular oxide layer 1', can be formed on the amorphous carbon layer.
[0057] In operation S104, based on the Q annular oxide layers, sidewall deposition and etching are sequentially performed on the amorphous carbon layer, the second N-type epitaxial layer, the P-type epitaxial layer, and the first N-type epitaxial layer to form vertical silicon nitride layers on the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate surface, and vertical oxide layers that are vertically connected to the vertical silicon nitride layers.
[0058] Figures 9A to 24A FIG. is a cross-sectional view along a first direction of the formation of the vertical silicon nitride layer and the vertical oxide layer during the manufacturing process of the semiconductor device. Figures 9B to 24B FIG. is a top view of the formation of the vertical silicon nitride layer and the vertical oxide layer during the manufacturing process of the semiconductor device.
[0059] Operation S104 may specifically include: etching the amorphous carbon layer based on the Q annular oxide layers to expose the surface of the second N-type epitaxial layer and form Q annular amorphous carbon layers.
[0060] According to an embodiment of the present disclosure, using the Q annular oxide layers as masks respectively, the amorphous carbon layer is etched to expose the surface of the second N-type epitaxial layer, and only the amorphous carbon layer corresponding to the lower surface of the annular oxide layer is retained, that is, Q annular amorphous carbon layers are formed.
[0061] Taking Q = 1 as an example, as Figure 9A shown, using the annular oxide layer 1 as a mask, etching the amorphous carbon layer 410 can form an annular amorphous carbon layer 910.
[0062] Operation S104 may further include: performing sidewall deposition and etching on the Q annular oxide layers and the Q annular amorphous carbon layers to form a first vertical silicon nitride layer on the second N-type epitaxial layer.
[0063] According to an embodiment of the present disclosure, by performing sidewall deposition and etching on each annular oxide layer and the annular amorphous carbon layer, a first vertical silicon nitride layer corresponding to each of the Q annular oxide layers and the Q annular amorphous carbon layers can be formed on the second N-type epitaxial layer.
[0064] Performing sidewall deposition and etching on each annular oxide layer and the annular amorphous carbon layer means depositing silicon nitride on the surfaces of the Q annular oxide layers and the Q annular amorphous carbon layers to form a silicon nitride layer, and etching the silicon nitride layer to expose the surfaces of the second N-type epitaxial layer and the annular oxide layer, and only retaining the silicon nitride layers around the inner and outer circumferences of the annular oxide layer and the annular amorphous carbon layer, that is, forming a first vertical silicon nitride layer on the second N-type epitaxial layer.
[0065] Wherein, a first vertical silicon nitride layer is formed on both the inner and outer sides of each annular oxide layer, that is, the number of the first vertical silicon nitride layers is 2Q.
[0066] Taking Q = 1 as an example, as Figure 10A shown, a silicon nitride layer 1010 is deposited on the surfaces of the annular oxide layer 1 and the annular amorphous carbon layer 910. The silicon nitride layer 1010 is etched to form the first vertical silicon nitride layer 2 as Figure 11A shown. As Figure 11B shown, the number of the first vertical silicon nitride layers is 2, which are respectively located on the inner and outer sides of the annular oxide layer 1.
[0067] Operation S104 may further include: etching the second N-type epitaxial layer and the P-type epitaxial layer based on the first vertical silicon nitride layer to expose the P-type epitaxial layer, forming Q first annular N-type epitaxial layers, and performing P-type doping implantation on the P-type epitaxial layer.
[0068] According to an embodiment of the present disclosure, using the first vertical silicon nitride layer, the annular oxide layer, and the annular amorphous carbon layer as masks, the second N-type epitaxial layer and the P-type epitaxial layer are etched until a certain thickness of the P-type epitaxial layer is etched away to expose the P-type epitaxial layer, thereby forming Q first annular N-type epitaxial layers. Wherein, a certain thickness of the P-type epitaxial layer can be etched away as needed.
[0069] Taking Q = 1 as an example, as Figure 12A shown, using the first vertical silicon nitride layer 2, the annular oxide layer 1, and the annular amorphous carbon layer 910 as masks, the second N-type epitaxial layer 240 is etched to form the first annular N-type epitaxial layer 1210, and a certain thickness of the P-type epitaxial layer 230 is etched.
[0070] After forming Q first annular N-type epitaxial layers, P-type doping implantation is performed on the exposed portion of the P-type epitaxial layer, that is, a P-type doping material is implanted into the P-type epitaxial layer. The P-type doping material may be a trivalent element, such as boron.
[0071] Taking Q = 1 as an example, as Figure 13A shown, boron can be implanted into the exposed portion of the P-type epitaxial layer 230.
[0072] Operation S104 may further include: performing sidewall deposition and etching on Q first annular N-type epitaxial layers to form a first vertical oxide layer on the P-type epitaxial layer, and performing sidewall deposition and etching on the first vertical oxide layer to form a second vertical silicon nitride layer on the P-type epitaxial layer.
[0073] According to an embodiment of the present disclosure, sidewall deposition and etching are performed on Q first annular N-type epitaxial layers, that is, an oxide is deposited on the surfaces of the first annular N-type epitaxial layer, the first vertical silicon nitride layer, the annular oxide layer, and the P-type epitaxial layer to form an oxide layer, and the oxide layer is etched to expose the surfaces of the P-type epitaxial layer, the first vertical silicon nitride layer, and the annular oxide layer, and only the oxide layers around the inner and outer peripheries of the first annular N-type epitaxial layer are retained, so that a first vertical oxide layer on the P-type epitaxial layer can be formed.
[0074] Among them, the number of the first vertical oxide layers is 2Q.
[0075] Taking Q = 1 as an example, as Figure 14A shown, an oxide layer 1410 is deposited on the surfaces of the first annular N-type epitaxial layer 1210, the first vertical silicon nitride layer 2, the annular oxide layer 1, and the P-type epitaxial layer 230. The oxide layer 1410 is etched to form a first vertical oxide layer 3 as Figure 15A shown. As Figure 15B shown, the number of the first vertical oxide layers 3 is 2, which are adjacent to the two first vertical silicon nitride layers 2 respectively.
[0076] According to an embodiment of the present disclosure, after the first vertical oxide layer is formed, sidewall deposition and etching are performed on the first vertical oxide layer, that is, silicon nitride is deposited on the surfaces of the first vertical oxide layer and the P-type epitaxial layer to form a silicon nitride layer, and the silicon nitride layer is etched to expose the surfaces of the P-type epitaxial layer and the first vertical oxide layer, and only the silicon nitride around the first vertical oxide layer is retained, that is, a second vertical silicon nitride layer on the P-type epitaxial layer is formed.
[0077] Among them, the number of the second vertical silicon nitride layers is 2Q.
[0078] Taking Q = 1 as an example, as Figure 16A shown, a silicon nitride layer 1610 is deposited on the surfaces of the first vertical oxide 3 and the P-type epitaxial layer 230. The silicon nitride layer 1610 is etched to form a second vertical silicon nitride layer 4 as Figure 17A shown. As Figure 17B shown, the number of the second vertical silicon nitride layers 4 is 2, which are respectively located around the two first vertical oxide layers 3.
[0079] Operation S104 may further include: etching the P-type epitaxial layer and the first N-type epitaxial layer based on the second vertical silicon nitride layer to expose the first N-type epitaxial layer, and performing N-type doping implantation on the first N-type epitaxial layer.
[0080] According to an embodiment of the present disclosure, using the second vertical silicon nitride layer, the first vertical oxide layer, the first vertical silicon nitride layer, and the annular oxide layer as masks, the P-type epitaxial layer and the first N-type epitaxial layer are etched until a certain thickness of the first N-type epitaxial layer is etched away to expose the first N-type epitaxial layer, thereby forming Q annular P-type epitaxial layers.
[0081] Taking Q = 1 as an example, as Figure 18A shown, using the second vertical silicon nitride layer 4, the first vertical oxide layer 3, the first vertical silicon nitride layer 2, and the annular oxide layer 1 as masks, the P-type epitaxial layer 230 is etched, and a certain thickness of the first N-type epitaxial layer 220 is etched, thereby forming an annular P-type epitaxial layer 1810.
[0082] After forming Q annular P-type epitaxial layers, N-type doping implantation is performed on the exposed portion of the first N-type epitaxial layer. As Figure 19A described, phosphorus can be implanted into the exposed portion of the first N-type epitaxial layer 220.
[0083] Operation S104 may further include: performing sidewall deposition and etching on the second vertical silicon nitride layer to form a second vertical oxide layer and a third vertical silicon nitride layer on the first N-type epitaxial layer.
[0084] According to an embodiment of the present disclosure, sidewall deposition and etching are performed on the second vertical silicon oxide layer, that is, an oxide is deposited on the surfaces of the second vertical silicon oxide layer and the first N-type epitaxial layer to form an oxide layer, and the oxide layer is etched to expose the surface of the first N-type epitaxial layer, and only the oxides around the inner and outer perimeters of the second vertical silicon nitride layer are retained, thereby forming a second vertical oxide layer on the first N-type epitaxial layer.
[0085] According to an embodiment of the present disclosure, sidewall deposition and etching are performed on the second vertical oxide layer, that is, silicon nitride is deposited on the surfaces of the second vertical oxide layer and the first N-type epitaxial layer to form a silicon nitride layer, and the silicon nitride layer is etched to expose the surface of the first N-type epitaxial layer, and only the silicon nitrides around the inner and outer perimeters of the second vertical oxide layer are retained, that is, a third silicon nitride layer is formed on the first N-type epitaxial layer.
[0086] Taking Q = 1 as an example, as Figure 20A shown, the number of second vertical oxide layers 5 on the first N-type epitaxial layer 220 is 2, and the number of third vertical silicon nitride layers 6 is 2.
[0087] As Figure 20B shown, the two second vertical oxide layers 5 are respectively located around the two second vertical silicon nitride layers 4; the two third vertical silicon nitride layers 6 are respectively located around the two second vertical oxide layers 5.
[0088] Operation S104 may further include: etching the first N-type epitaxial layer and the substrate based on the third vertical silicon nitride layer to expose the substrate, and performing sidewall deposition and etching on the third vertical silicon nitride layer to form a third vertical oxide layer and a fourth vertical silicon nitride layer on the substrate.
[0089] According to an embodiment of the present disclosure, using the third vertical silicon nitride layer as a mask, etching the first N-type epitaxial layer and the substrate until a certain thickness of the substrate is etched away to expose the substrate.
[0090] Taking Q = 1 as an example, as Figure 21A shown, using the third vertical silicon nitride layer 6 as a mask, etching the first N-type epitaxial layer 220 and etching a certain thickness of the substrate 210, so as to form a second annular N-type epitaxial layer 2110.
[0091] According to an embodiment of the present disclosure, performing sidewall deposition and etching on the third vertical silicon nitride layer, that is, depositing an oxide on the surfaces of the substrate and the third vertical silicon nitride layer, and etching the oxide, only retaining the oxides around the inner and outer sides of the third vertical silicon nitride layer, so as to form a third vertical oxide layer on the substrate.
[0092] Taking Q = 1 as an example, as Figure 22A shown, depositing an oxide on the surfaces of the substrate 210 and the third vertical silicon nitride layer 6, and etching the oxide to form a third vertical oxide 7 on the substrate 210.
[0093] As Figure 22B shown, the number of the third vertical oxide layers 7 is 2, and they are respectively located around the two third vertical silicon nitride layers 6.
[0094] Among them, the first annular N-type epitaxial layer 1210 is used to form an emitter (E) subsequently, the annular P-type epitaxial layer 1810 is used to form a base (B) subsequently, the second annular N-type epitaxial layer 2110 is used to form a collector (Collector) subsequently, and the substrate 210 is used to form a Well (well) subsequently.
[0095] According to an embodiment of the present disclosure, performing sidewall deposition and etching on the third vertical oxide layer, that is, forming silicon nitride on the surfaces of the substrate and the third vertical oxide layer, and etching the silicon nitride, only retaining the silicon nitride around the third vertical oxide layer, so as to form a fourth vertical silicon nitride layer on the substrate.
[0096] Taking Q = 1 as an example, as Figure 23A shown, depositing silicon nitride on the surfaces of the substrate 210 and the third vertical oxide layer 7, and etching the silicon nitride to form a fourth vertical silicon nitride layer 8 on the substrate 210.
[0097] AsFigure 23B As shown, the number of the fourth vertical silicon nitride layers 8 is 2, which are respectively located around the two third vertical oxide layers 7.
[0098] In operation S105, the vertical silicon nitride layer and the vertical oxide layer are polished to expose the surface of the amorphous carbon layer, and based on the amorphous carbon layer, the amorphous carbon layer, the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer and the substrate are etched to form a target window exposing the substrate, and the target window is filled with a filling material.
[0099] Figures 25A to 28A is a schematic cross-sectional view of forming a target window in the first direction during the process of manufacturing a semiconductor device. Figures 25B to 28B is a top view of forming a target window during the process of manufacturing a semiconductor device.
[0100] According to an embodiment of the present disclosure, after forming the third vertical oxide layer and the fourth vertical silicon nitride layer on the substrate, an oxide is first deposited on the surfaces of the substrate and the fourth vertical silicon nitride layer to form an oxide layer 2410 as Figure 24A shown.
[0101] According to an embodiment of the present disclosure, the deposited oxide, the vertical silicon nitride layer and the vertical oxide layer are polished until the surface of the annular amorphous carbon layer is exposed. As Figure 25A shown, the deposited oxide, the vertical silicon nitride layer and the vertical oxide layer can be polished until the surface of the annular amorphous carbon layer 910 is exposed.
[0102] Among them, chemical mechanical polishing (CMP) technology can be used for polishing to make the surface flat.
[0103] Among them, the vertical silicon nitride layer may include a first vertical silicon nitride layer, a second vertical silicon nitride layer, a third vertical silicon nitride layer and a fourth silicon nitride layer, and the vertical oxide layer may include a first vertical oxide layer, a second vertical oxide layer and a third vertical oxide layer.
[0104] According to an embodiment of the present disclosure, the annular amorphous carbon layer 910 is etched away to form a window as Figure 26A shown on the first annular N-type epitaxial layer 1210.
[0105] According to an embodiment of the present disclosure, after exposing the surface of the amorphous carbon layer, the amorphous carbon layer is etched away, and taking the window formed on the second N-type epitaxial layer after etching away the amorphous carbon layer as a mask, the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer and the substrate are etched until the substrate is exposed, and a target window exposing the substrate is formed.
[0106] As Figure 26AAs shown in [reference], using the window formed on the first annular N-type epitaxial layer 1210 as a mask, the first annular N-type epitaxial layer 1210, the annular P-type epitaxial layer 1810, the second annular N-type epitaxial layer 2110 and the substrate 210 are etched to expose the substrate, and a target window 9 as shown in Figure 27A is formed on the substrate.
[0107] As Figure 27A shown in [reference], etching the first annular N-type epitaxial layer 1210 can form two first annular N-type sub-epitaxial layers 2730; etching the annular P-type epitaxial layer 1810 can form two annular P-type sub-epitaxial layers 2710; etching the second annular N-type epitaxial layer 2110 can form two second annular N-type sub-epitaxial layers 2710. Thus, each functional layer (such as the collector, base, and emitter) of the semiconductor structure is formed by one-time growth.
[0108] The target window 9 is a window surrounded by two first annular N-type sub-epitaxial layers 2730, two annular P-type sub-epitaxial layers 2710, and two second annular N-type sub-epitaxial layers 2710.
[0109] Since the sizes of the first annular N-type sub-epitaxial layer 2730, the annular P-type sub-epitaxial layer 2720, and the second annular N-type sub-outer layer 2710 in the semiconductor structure are determined by the sizes of the vertical oxide layer and the vertical silicon nitride layer during the sidewall deposition process, that is, the sizes of the collector, base, emitter and their connection parts, as well as the isolation between the collector, base and emitter are formed by self-alignment through sidewall deposition and etching. And the doping of the contacts of the collector, base and emitter is also formed by self-alignment injection through the sidewall.
[0110] According to an embodiment of the present disclosure, the etched target window is filled with a filling material. After filling, as Figure 28A shown in [reference], wherein the filling material can be an oxide, such as silicon oxide; the STI method can be used for filling.
[0111] In operation S106, according to a preset pattern for lithography selection conditions, lithography is performed on the vertical silicon nitride layer, the vertical oxide layer and the filling material to expose the substrate, and the trenches formed by lithography are filled with the filling material.
[0112] Figure 29A is a cross-sectional view of lithography in the first direction during the process of manufacturing a semiconductor device. Figure 29B is a top view of lithography during the process of manufacturing a semiconductor device. Figure 29A is Figure 29B the cross-sectional view at the horizontal line in [reference].
[0113] According to an embodiment of the present disclosure, after the filling is completed, a layer of photoresist is coated on the filling material, and the photoresist is irradiated according to a preset pattern for lithography selection conditions. After exposure, the photoresist is developed through a developer to remove the photoresist in the unexposed area, leaving the photoresist in the exposed area. As shown in Figure 29B the photoresist 2910 shown in is the photoresist in the exposed area left, that is, the photoresist that is desired to be left according to the lithography selection conditions.
[0114] And using the photoresist 2910 as a mask, the filling material is etched until the substrate is exposed, and the photoresist 2910 is removed, as can be seen in Figure 29C shown. After the trenches formed by lithography are filled with the filling material, it can be as shown in Figure 29D shown in.
[0115] Among them, the lithography selection conditions can characterize the area where the photoresist needs to be irradiated, and the lithography selection conditions are set according to the number of semiconductor structures to be prepared in each column of the semiconductor device to be prepared.
[0116] Among them, according to the preset pattern for the lithography selection conditions, AA lithography can be used to perform lithography on the vertical silicon nitride layer, the vertical oxide layer, and the filling material.
[0117] In operation S107, the vertical silicon nitride layer is etched away to form connection vias exposing the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate surface respectively.
[0118] Figure 30A And Figure 31A are cross-sectional schematic views of forming connection vias in the first direction during the process of manufacturing a semiconductor device. Figure 30B And Figure 31B are top views of forming connection vias during the process of manufacturing a semiconductor device.
[0119] Before etching away the vertical silicon nitride layer, the filling material can be polished until the surface of the vertical silicon nitride layer is exposed. After polishing, it can be as shown in Figure 30A shown in.
[0120] Etching away the vertical silicon nitride layer to form connection vias exposing the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate surface respectively can specifically refer to etching away the vertical silicon nitride layer shown in Figure 30A until the surfaces of the first annular N-type sub-epitaxial layer 2730, the annular P-type sub-epitaxial layer, the second annular N-type sub-epitaxial layer 2710, and the substrate 210 are exposed respectively to form connection vias on the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate surface.
[0121] In operation S108, a conductive metal material is filled in the connection vias to form a semiconductor device.
[0122] Figure 32A And Figure 33A are cross-sectional schematic views of the semiconductor device formed in the process of preparing the semiconductor device in the first direction. Figure 32B And Figure 33B is a top view of the semiconductor device formed in the process of preparing the semiconductor device.
[0123] In Figure 31A the connection vias shown, a conductive metal material is filled. After filling the conductive metal material, it can be as shown in Figure 32A . And the conductive metal material is polished until the filling material is exposed. After polishing, it can be as shown in Figure 33A .
[0124] Wherein, the conductive metal material can be tungsten; when the materials of the second N-type epitaxial layer, P-type epitaxial layer, first N-type epitaxial layer and substrate are silicon, the conductive metal material contacts with the second N-type epitaxial layer, P-type epitaxial layer, first N-type epitaxial layer and substrate, and metal silicide will be formed at the contact part.
[0125] According to the embodiments of the present disclosure, based on the lithography selection conditions, M semiconductor structures can be generated in each column in the second direction, and 4Q×M semiconductor structures can be prepared through two lithographies, thereby reducing the manufacturing cost and improving the process node, that is, reducing the device size. And, through the sidewall transfer of one lithography and multiple non-lithography sidewall transfers, the definition of E / B / C / Well in the semiconductor structure can be realized, and at the same time, the self-aligned contact of E / B / C / Well is realized. While effectively realizing the device size scaling, the device pitch is effectively reduced, thereby reducing the power consumption of the device and improving the performance of the device.
[0126] Thus, in the process of preparing the semiconductor device, through the self-aligned design, the manufacturing difficulty is greatly reduced, the manufacturing cost is reduced, the device size is reduced, the device power consumption is reduced, and the prepared semiconductor device can be highly compatible with the FinFET / GAA device manufacturing process, which is convenient to integrate high-frequency BiCMOS circuits with FinFET / GAA devices.
[0127] Taking the first direction as the row and the second direction as the column, according to the preset pattern for the lithography selection conditions, lithography is performed on the vertical silicon nitride layer, vertical oxide layer and filling material, including: performing lithography on the vertical silicon nitride layer, vertical oxide layer and filling material according to the preset pattern for the lithography selection conditions to form M rows of semiconductor structures in the second direction of the semiconductor device, where M is an integer greater than or equal to 1; wherein, the semiconductor device forms 4Q columns of semiconductor structures in the first direction.
[0128] Taking Q = 1 as an example, when it is determined to leave 8 rows of photoresist according to the lithography selection conditions, each row in the finally formed semiconductor device can include 4 semiconductor structures, and each column can include 8 semiconductor devices.
[0129] Figure 33A It is a schematic cross-sectional view of the semiconductor device in the first direction in the case of Q = 1. Figure 33B It is a top view of the semiconductor device in the case of Q = 1 and M = 8. Figure 33A It is Figure 33B The schematic cross-sectional view at the horizontal line in
[0130] Such as Figure 33A In , each semiconductor structure may include a substrate 210; a first N-type epitaxial layer 220 formed on the substrate; a P-type epitaxial layer 230 formed on the first N-type epitaxial layer; and a second N-type epitaxial layer 240 formed on the P-type epitaxial layer.
[0131] The region of the first N-type epitaxial layer 220 not covered by the P-type epitaxial layer 230 is doped with a first N-type doping material, the region of the P-type epitaxial layer 230 not covered by the second N-type epitaxial layer 240 is doped with a P-type doping material, and the second N-type epitaxial layer 240 is doped with a second N-type doping material. Among them, the first N-type doping material and the second N-type doping material may be pentavalent element materials, such as phosphorus, and the P-type doping material may be a trivalent element, such as boron.
[0132] According to an embodiment of the present disclosure, doping implantation is performed on the first N-type epitaxial layer, the second N-type epitaxial layer, and the P-type epitaxial layer, that is, doping implantation is performed on the emitter, the base, and the collector, so that the performance of the device can be controlled. Taking 4 adjacent semiconductor structures in each row of the semiconductor device in the first direction as a group, the semiconductor structures in each group are sequentially the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure in the first direction. There is a first window exposing the substrate surface between the first semiconductor structure and the second semiconductor structure, and there is a second window exposing the substrate surface between the third semiconductor structure and the fourth semiconductor structure.
[0133] Taking Q = 1 as an example, each row of the semiconductor device has a group of semiconductor structures in the first direction, that is, each row has 4 semiconductor structures. Such as Figure 33A As shown in , each row of the semiconductor device may include a first semiconductor structure 3310, a second semiconductor structure 3320, a third semiconductor structure 3330, and a fourth semiconductor structure 3340. There is a first window 10 exposing the substrate surface between the first semiconductor structure 3310 and the second semiconductor structure 3320, and there is a second window 11 exposing the substrate surface between the third semiconductor structure 3330 and the fourth semiconductor structure 3340.
[0134] The connection vias on the substrate surface in the second semiconductor structure 3320 and the third semiconductor structure 3330 are the same connection via. When Q is greater than or equal to 2, in the semiconductor device, if the first semiconductor structure group and the second semiconductor structure group in each row are adjacent in the first direction, then the connection vias on the substrate surface in the fourth semiconductor structure in the first semiconductor structure group and the first semiconductor structure in the second semiconductor structure group are also the same connection via.
[0135] In each semiconductor structure, the first side edges of the first N-type epitaxial layer 220, the P-type epitaxial layer 230, and the second N-type epitaxial layer 240 in the first direction are vertically aligned, and the second side edges of the substrate, the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are gradually shortened layer by layer from bottom to top in the vertical direction. The first side edge and the second side edge of the same layer are opposite side edges.
[0136] The first side edges of the first semiconductor structure 3310 and the second semiconductor structure 3320 that are vertically aligned are respectively on both sides of the first window 10 in the first direction; the first side edges of the third semiconductor structure and the fourth semiconductor structure that are vertically aligned are respectively on both sides of the second window 11 in the first direction.
[0137] For the M semiconductor structures included in each column of the semiconductor device, there is a third window exposing the substrate surface between two adjacent semiconductor structures in the second direction.
[0138] When M = 8, as Figure 33B shown, there is a third window exposing the substrate surface between two adjacent semiconductor structures in the second direction. Moreover, the first window, the second window, and the third window are filled with a filling material to form a gap between the semiconductor structures adjacent in the first direction and the second direction.
[0139] As Figure 33A shown, connection vias are sequentially arranged on the upper surfaces of the substrate, the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer, and the connection vias are filled with a conductive metal material.
[0140] Those skilled in the art can understand that the features described in various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.
[0141] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.
Claims
1. A semiconductor device, comprising: 4Q×M semiconductor structures, wherein, taking the first direction as rows and the second direction as columns, each row of the semiconductor device includes 4Q of the semiconductor structures, each column of the semiconductor device includes M of the semiconductor structures, M is determined according to lithography selection conditions, M is an integer greater than or equal to 1, and Q is an integer greater than or equal to 1; The semiconductor structure, comprising: A substrate; A first N-type epitaxial layer formed on the substrate; A P-type epitaxial layer formed on the first N-type epitaxial layer; A second N-type epitaxial layer formed on the P-type epitaxial layer; wherein, a first side of the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are aligned vertically, a second side of the substrate, the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer in the first direction are gradually shortened layer by layer from bottom to top vertically, and the first side and the second side of the same layer are opposite sides; Connecting vias sequentially arranged on the upper surfaces of the substrate, the first N-type epitaxial layer, the P-type epitaxial layer, and the second N-type epitaxial layer, and the connecting vias are filled with a conductive metal material.
2. The semiconductor device according to claim 1, wherein, Regions in the first N-type epitaxial layer not covered by the P-type epitaxial layer are doped with a first N-type doping material, regions in the P-type epitaxial layer not covered by the second N-type epitaxial layer are doped with a P-type doping material, and the second N-type epitaxial layer is doped with a second N-type doping material.
3. The semiconductor device according to claim 1, wherein, Taking 4 adjacent semiconductor structures in each row of the semiconductor device in the first direction as a group, the semiconductor structures in each group are sequentially the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure in the first direction. There is a first window exposing the surface of the substrate between the first semiconductor structure and the second semiconductor structure, and there is a second window exposing the surface of the substrate between the third semiconductor structure and the fourth semiconductor structure.
4. The semiconductor structure according to claim 3, wherein, The connecting vias on the substrate surface in the second semiconductor structure and the third semiconductor structure are the same connecting via. The first semiconductor structure group and the second semiconductor structure group are adjacent in the first direction, and the connecting vias on the substrate surface in the fourth semiconductor structure in the first semiconductor structure group and the first semiconductor structure in the second semiconductor structure group are the same connecting via.
5. The semiconductor device according to claim 4, wherein, The first sides of the first semiconductor structure and the second semiconductor structure aligned vertically are respectively two sides of the first window in the first direction; the first sides of the third semiconductor structure and the fourth semiconductor structure aligned vertically are respectively two sides of the second window in the first direction.
6. The semiconductor device according to claim 3, wherein, For the M semiconductor structures included in each column of the semiconductor device, there is a third window exposing the surface of the substrate between two adjacent semiconductor structures in the second direction.
7. The semiconductor device according to claim 6, wherein, The first window, the second window, and the third window are filled with a filling material.
8. A method for manufacturing a semiconductor device, comprising: Grow an epitaxial stack on a substrate, wherein the epitaxial stack includes a first N-type epitaxial layer, a P-type epitaxial layer, and a second N-type epitaxial layer arranged in sequence; Perform N-type doping implantation on the second N-type epitaxial layer, and sequentially deposit an amorphous carbon layer and a silicon nitride layer on the second N-type epitaxial layer; According to a preset pattern, perform Q times of sidewall transfer on the silicon nitride layer to form Q annular oxide layers on the surface of the amorphous carbon layer; Based on the Q annular oxide layers, sequentially perform sidewall deposition and etching on the amorphous carbon layer, the second N-type epitaxial layer, the P-type epitaxial layer, and the first N-type epitaxial layer to form vertical silicon nitride layers on the surfaces of the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate, and vertical oxide layers that are vertically connected to the vertical silicon nitride layers; Polish the vertical silicon nitride layers and the vertical oxide layers to expose the surface of the amorphous carbon layer, and based on the amorphous carbon layer, etch the amorphous carbon layer, the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate to form a target window exposing the substrate, and fill the target window with a filling material; According to a preset pattern for lithography selection conditions, perform lithography on the vertical silicon nitride layers, the vertical oxide layers, and the filling material to expose the substrate, and fill the trenches formed by lithography with the filling material; Etch away the vertical silicon nitride layers to respectively form connection through holes exposing the surfaces of the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate; Fill the connection through holes with a conductive metal material to form a semiconductor device.
9. The method according to claim 8, wherein The step of, based on the Q annular oxide layers, sequentially performing sidewall deposition and etching on the amorphous carbon layer, the second N-type epitaxial layer, the P-type epitaxial layer, and the first N-type epitaxial layer to form vertical silicon nitride layers on the surfaces of the second N-type epitaxial layer, the P-type epitaxial layer, the first N-type epitaxial layer, and the substrate, and vertical oxide layers that are vertically connected to the vertical silicon nitride layers, includes: Based on the Q annular oxide layers, etch the amorphous carbon layer to expose the surface of the second N-type epitaxial layer and form Q annular amorphous carbon layers; Perform sidewall deposition and etching on the Q annular oxide layers and the Q annular amorphous carbon layers to form a first vertical silicon nitride layer on the second N-type epitaxial layer; Based on the first vertical silicon nitride layer, etch the second N-type epitaxial layer and the P-type epitaxial layer to expose the P-type epitaxial layer, and form Q first annular N-type epitaxial layers, and perform P-type doping implantation on the P-type epitaxial layer; Perform sidewall deposition and etching on the Q first annular N-type epitaxial layers to form a first vertical oxide layer on the P-type epitaxial layer, and perform sidewall deposition and etching on the first vertical oxide layer to form a second vertical silicon nitride layer on the P-type epitaxial layer; Based on the second vertical silicon nitride layer, etch the P-type epitaxial layer and the first N-type epitaxial layer to expose the first N-type epitaxial layer, and perform N-type doping implantation on the first N-type epitaxial layer; Perform sidewall deposition and etching on the second vertical silicon nitride layer to form a second vertical oxide layer and a third vertical silicon nitride layer on the first N-type epitaxial layer; Based on the third vertical silicon nitride layer, etch the first N-type epitaxial layer and the substrate to expose the substrate, and perform sidewall deposition and etching on the third vertical silicon nitride layer to form a third vertical oxide layer and a fourth vertical silicon nitride layer on the substrate.
10. The method according to claim 9, wherein, Taking the first direction as rows and the second direction as columns, perform photolithography on the vertical silicon nitride layer, the vertical oxide layer, and the filling material according to a preset pattern for photolithography selection conditions, including: Perform photolithography on the vertical silicon nitride layer, the vertical oxide layer, and the filling material according to a preset pattern for the photolithography selection conditions to form M rows of semiconductor structures in the second direction of the semiconductor device, where M is an integer greater than or equal to 1; Among them, the semiconductor device forms 4Q columns of semiconductor structures in the first direction.