Battery structure, battery monomer and photovoltaic system

Abstract

The invention discloses a battery structure, a battery monomer and a photovoltaic system, and belongs to the technical field of batteries. The battery structure comprises a silicon substrate having a front surface and a back surface which are oppositely arranged along a first direction; the first intrinsic amorphous silicon layer, the crystalline silicon layer and the first microcrystalline silicon layer are sequentially stacked on the front face of the silicon substrate in the direction away from the silicon substrate, the crystalline silicon layer and the first microcrystalline silicon layer have a first doping type, and the crystalline silicon layer contains hydrogen elements and oxygen elements; the second intrinsic amorphous silicon layer and the second microcrystalline silicon layer are sequentially stacked on the back face of the silicon substrate in the direction away from the silicon substrate, and the second microcrystalline silicon layer is of a second doping type; wherein the thickness of the crystalline silicon layer is smaller than that of the first microcrystalline silicon layer, and the first doping type is opposite to the second doping type. The crystalline silicon layer is deposited between the amorphous silicon layer and the microcrystalline silicon layer, so that the microcrystalline silicon layer has higher crystallization rate and light transmission, the process time is shortened, and the amorphous silicon layer cannot be etched.

Description

Technical Field

[0001] This application belongs to the technical field of batteries, and particularly relates to a battery structure, a battery cell, and a photovoltaic system. Background Art

[0002] The silicon heterojunction solar cell (Heterojunction with Back Contact, abbreviated as HJT) is a highly efficient photovoltaic device. By forming a high-quality heterojunction, excellent surface passivation effect is achieved, thus obtaining significant advantages such as high conversion efficiency. However, at present, the process time of the film layer structure of HJT is long, the preparation difficulty is high, and the final efficiency of the battery needs to be improved. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application provides a battery structure, a battery cell, and a photovoltaic system. By depositing a crystalline silicon layer between the amorphous silicon layer and the microcrystalline silicon layer, the microcrystalline silicon layer has a higher crystallization rate and light transmittance, while shortening the process duration and not causing an etching effect on the amorphous silicon layer.

[0004] In a first aspect, this application provides a battery structure, including: A silicon substrate having a front surface and a back surface oppositely disposed along a first direction; In a direction away from the silicon substrate, a first intrinsic amorphous silicon layer, a crystalline silicon layer, and a first microcrystalline silicon layer are sequentially stacked on the front surface of the silicon substrate. The crystalline silicon layer and the first microcrystalline silicon layer have a first doping type, and the crystalline silicon layer contains hydrogen and oxygen elements; In a direction away from the silicon substrate, a second intrinsic amorphous silicon layer and a second microcrystalline silicon layer are sequentially stacked on the back surface of the silicon substrate. The second microcrystalline silicon layer has a second doping type; Wherein, the thickness of the crystalline silicon layer is less than the thickness of the first microcrystalline silicon layer, and the first doping type and the second doping type are opposite.

[0005] According to the battery structure of this application, by depositing amorphous silicon and microcrystalline silicon on both sides of the silicon substrate, a high-quality heterojunction is formed. Among them, a crystalline silicon layer is also deposited on the front surface, which can promote the high-quality growth of the microcrystalline silicon layer, improve the crystallization rate and light transmittance of the microcrystalline silicon, optimize the energy band structure of the heterojunction interface, reduce recombination loss, enhance the carrier collection efficiency, and the current is significantly increased. At the same time, the deposition time of the crystalline silicon layer is short, the process duration is shortened, and no etching effect is caused on the amorphous silicon layer.

[0006] According to some embodiments of this application, the thickness of the crystalline silicon layer is 0.5 nm to 1 nm.

[0007] According to some embodiments of this application, the total thickness of the crystalline silicon layer and the first microcrystalline silicon layer is 18 nm to 20 nm.

[0008] According to some embodiments of the present application, the thickness ratio of the crystalline silicon layer to the first microcrystalline silicon layer is 1:(17 - 40).

[0009] According to some embodiments of the present application, the oxygen doping concentration of the crystalline silicon layer is 1×10 21 cm -3 -1×10 23 cm -3 , and the oxygen doping concentration of the first microcrystalline silicon layer is 1×10 17 cm -3 -1×10 18 cm -3 .

[0010] According to some embodiments of the present application, the crystalline silicon layer is a phosphorus-doped crystalline silicon layer, the first microcrystalline silicon layer is a phosphorus-doped microcrystalline silicon layer, and the second microcrystalline silicon layer is a boron-doped microcrystalline silicon layer.

[0011] According to some embodiments of the present application, the thickness of the first intrinsic amorphous silicon layer is 5 nm to 7 nm, the thickness of the phosphorus-doped crystalline silicon layer is 0.5 nm to 1 nm, the thickness of the phosphorus-doped microcrystalline silicon layer is 18 nm to 22 nm, the thickness of the second intrinsic amorphous silicon layer is 5 nm to 8 nm, and the thickness of the boron-doped microcrystalline silicon layer is 25 nm to 30 nm.

[0012] According to some embodiments of the present application, the phosphorus doping concentration of the phosphorus-doped crystalline silicon layer is 1×10 17 cm -3 -1×10 18 cm -3 , and the phosphorus doping concentration of the phosphorus-doped microcrystalline silicon layer is 1×10 18 cm -3 -1×10 20 cm -3 .

[0013] According to some embodiments of the present application, a second intrinsic amorphous silicon layer, a first intrinsic amorphous silicon layer, a crystalline silicon layer, a first microcrystalline silicon layer, and a second microcrystalline silicon layer are sequentially stacked on the surface of the silicon substrate in a second direction. The second intrinsic amorphous silicon layer is disposed close to the silicon substrate, and a first direction is perpendicular to the second direction.

[0014] In a second aspect, the present application provides a battery cell, including a first conductive structure, a second conductive structure, and the battery structure according to the foregoing. The first conductive structure is disposed on the surface of the first microcrystalline silicon layer of the battery structure away from the silicon substrate, and the second conductive structure is disposed on the surface of the second microcrystalline silicon layer of the battery structure away from the silicon substrate.

[0015] The battery cell according to the present application has good electrochemical performance and has a high short-circuit current and conversion efficiency.

[0016] In a third aspect, the present application provides a photovoltaic system including the battery cells described above.

[0017] The photovoltaic system according to the present application has higher system efficiency and total output power.

[0018] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. Description of the Drawings

[0019] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a schematic structural diagram of the battery structure provided by an embodiment of the present application; Figure 2 is a schematic structural diagram of the battery cell provided by an embodiment of the present application.

[0020] Reference Signs: Battery structure 100, battery cell 200, silicon substrate 10, first intrinsic amorphous silicon layer 21, crystalline silicon layer 30, first microcrystalline silicon layer 41, second intrinsic amorphous silicon layer 22, second microcrystalline silicon layer 42, first transparent conductive film layer 51, second transparent conductive film layer 52, first electrode 61, second electrode 62. Detailed Description of the Embodiments

[0021] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings. In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0022] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not imply that there must be a first element, component, region, layer, or part in the present disclosure.

[0023] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0024] In the related art, the silicon heterojunction (HJT) solar cell structure uses crystalline silicon (c-Si) as the substrate, and intrinsic amorphous silicon and microcrystalline silicon layers are deposited on both sides to form a heterojunction. For example, the back side of the cell structure uses P-type boron-doped microcrystalline silicon to form the emitter. The front side of the cell structure uses an N-type phosphorus-doped microcrystalline silicon layer. However, based on the front side of the heterojunction cell with a conventional structure, there is a serious parasitic absorption effect at the contact interface between the intrinsic amorphous silicon layer and the microcrystalline silicon layer. In view of this, the present application proposes a cell structure. By depositing amorphous silicon and microcrystalline silicon on both sides of the silicon substrate, a high-quality heterojunction is formed. Among them, an oxygen-containing silicon layer is further deposited between the intrinsic amorphous silicon layer and the microcrystalline silicon layer on the front side, serving as a seed layer before the formation of the dense microcrystalline silicon layer. It can promote the high-quality growth of the microcrystalline silicon layer, improve the crystallization rate and light transmittance of the microcrystalline silicon, optimize the energy band structure of the heterojunction interface, reduce recombination losses, enhance the carrier collection efficiency, and the current is significantly increased. At the same time, the deposition time of the crystalline silicon layer is short, shortening the process duration, and it will not cause an etching effect on the amorphous silicon layer. At the same time, the introduction of the oxygen-containing silicon layer can reduce the overall thickness of the front-side doped microcrystalline silicon layer.

[0025] Referring to Figure 1 , Figure 1 FIG. shows a battery structure. An embodiment of the present application proposes a battery structure. In this embodiment, the battery structure 100 includes a silicon substrate 10, a first intrinsic amorphous silicon layer 21, a second intrinsic amorphous silicon layer 22, a crystalline silicon layer 30, a first microcrystalline silicon layer 41, and a second microcrystalline silicon layer 42. The silicon substrate 10 has a front surface and a back surface oppositely disposed in a first direction; the first intrinsic amorphous silicon layer 21, the crystalline silicon layer 30, and the first microcrystalline silicon layer 41 are sequentially stacked on the front surface of the silicon substrate, and the second intrinsic amorphous silicon layer 22 and the second microcrystalline silicon layer 42 are sequentially stacked on the back surface of the silicon substrate. The crystalline silicon layer 30 and the first microcrystalline silicon layer 41 have a first doping type, the second microcrystalline silicon layer 42 has a second doping type, and the crystalline silicon layer contains hydrogen and oxygen elements; wherein, the thickness of the crystalline silicon layer 30 is less than the thickness of the first microcrystalline silicon layer 41, and the first doping type and the second doping type are opposite.

[0026] The silicon substrate may be an N-type single crystal silicon wafer, and the thickness may be 50μm - 200μm (specifically, such as 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, etc.).

[0027] The first direction is the thickness direction of the silicon substrate 10, and the two large-area surfaces of the silicon substrate 10 are respectively used as the front surface and the back surface. For example, taking the upper surface of the silicon substrate 10 as the front surface and the lower surface as the back surface, the first intrinsic amorphous silicon layer 21 is formed on the upper surface of the silicon substrate 10, the crystalline silicon layer 30 is formed on the surface of the first intrinsic amorphous silicon layer 21 away from the silicon substrate 10, the first microcrystalline silicon layer 41 is formed on the surface of the crystalline silicon layer 30 away from the silicon substrate 10, the second intrinsic amorphous silicon layer 22 is formed on the lower surface of the silicon substrate 10, and the second microcrystalline silicon layer 42 is formed on the surface of the second intrinsic amorphous silicon layer 22 away from the silicon substrate 10.

[0028] It should be noted that the first microcrystalline silicon layer 41 and the second microcrystalline silicon layer 42 in this embodiment are fully crystallized film layers, or are partially crystallized and contain amorphous silicon film layers. In terms of technology, the raw materials for preparing microcrystalline silicon and amorphous silicon are roughly the same. Therefore, in actual preparation, the film layer of microcrystalline silicon may contain some amorphous silicon.

[0029] The first doping type may be N-type, and the second doping type is P-type. Alternatively, the first doping type may be P-type, and the second doping type is N-type. Among them, N-type doping may be phosphorus doping, arsenic doping, or antimony doping, etc., and P-type doping may be boron doping, gallium doping, or indium doping, etc.

[0030] As an example, the crystalline silicon layer 30 and the first microcrystalline silicon layer 41 can be phosphorus-doped microcrystalline silicon layers, and the second microcrystalline silicon layer 42 can be boron-doped.

[0031] The crystalline silicon layer 30 is a transition film layer between amorphous silicon and microcrystalline silicon, which is mainly used to promote the uniform nucleation and high-quality growth of the subsequent first microcrystalline silicon layer 41. In this embodiment, the crystalline silicon layer 30 containing hydrogen and oxygen is used as the seed layer. The oxygen element can quickly promote crystallization, making the nucleation effect of the first microcrystalline silicon layer 41 higher, with a higher crystallization rate and light transmittance. At the same time, the thickness of the crystalline silicon layer 30 can be reduced, and the deposition time can be shortened.

[0032] In some embodiments, the thickness of the crystalline silicon layer 30 is 0.5 nm to 1 nm. For example, the thickness of the crystalline silicon layer can be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, or 1 nm. Since the presence of the crystalline silicon layer can promote crystallization more quickly, the required deposition time can be further shortened.

[0033] In some embodiments, the total thickness of the crystalline silicon layer 30 and the first microcrystalline silicon layer 41 is 18 nm to 20 nm. For example, the total thickness can be 18 nm, 18.5 nm, 19 nm, 19.5 nm, or 20 nm.

[0034] The crystallization rate of microcrystalline silicon gradually increases as the film thickness increases. However, increasing the film thickness will inevitably increase the parasitic absorption of microcrystalline silicon and the problem of electron tunneling contact. In this embodiment, since the crystalline silicon layer 30 containing hydrogen and oxygen is used as the seed layer, the first microcrystalline silicon layer 41 has a higher crystallization rate and light transmittance. Furthermore, the thickness of the first microcrystalline silicon layer 41 can be reduced while maintaining the original advantages. With a low total film thickness, lower front parasitic absorption and low electron tunneling contact resistivity can be achieved.

[0035] In some embodiments, the thickness of the first microcrystalline silicon layer 41 is 17 nm to 19.5 nm. For example, the thickness of the first microcrystalline silicon layer 41 can be 17 nm, 17.5 nm, 18 nm, 18.5 nm, 19 nm, or 19.5 nm.

[0036] In some other embodiments, the thickness ratio of the crystalline silicon layer 30 to the first microcrystalline silicon layer 41 is 1:(17 - 40). For example, 1:17, 1:20, 1:25, 1:30, 1:35, or 1:40. The crystalline silicon layer 30 is beneficial to promoting the growth quality of the first microcrystalline silicon layer 41, making the growth of the microcrystalline silicon layer denser. Controlling the thickness ratio between the two can balance or preferentially select between the crystallization rate and light transmittance of the first microcrystalline silicon layer 41 and the parasitic absorption and contact resistivity of the total film thickness, and can ensure the conversion efficiency of the battery structure 100.

[0037] In some embodiments, the oxygen doping concentration of the crystalline silicon layer 30 is 1×10 21 cm -3 -1×10 23 cm -3 , and the oxygen doping concentration of the first microcrystalline silicon layer is 1×10 17 cm -3 -1×10 18 cm -3 . For example, the oxygen doping concentration of the crystalline silicon layer 30 can be 1×10 21 cm -3 , 1×10 22 cm -3 , or 1×10 23 cm -3 . The crystalline silicon layer with a high oxygen content can broaden the bandgap, enhance the absorption of short-wavelength light, and significantly improve the current.

[0038] As an example, the crystalline silicon layer 30 is a phosphorus-doped crystalline silicon layer, the first microcrystalline silicon layer 41 is a phosphorus-doped microcrystalline silicon layer, and the second microcrystalline silicon layer 42 is a boron-doped microcrystalline silicon layer. The front surface of the silicon substrate 10 adopts a stacked structure of an intrinsic layer, an N-type microcrystalline silicon layer, and an intrinsic layer, and the back surface forms a stacked structure of an intrinsic layer and a P-type microcrystalline silicon layer, forming a high-quality heterojunction. In particular, the front surface has a high crystallization rate, better light transmittance, and low parasitic absorption with an ultra-thin thickness.

[0039] In some embodiments, the thickness of the first intrinsic amorphous silicon layer 21 is 5 nm to 7 nm, the thickness of the phosphorus-doped crystalline silicon layer is 0.5 nm to 1 nm, the thickness of the phosphorus-doped microcrystalline silicon layer is 18 nm to 22 nm, the thickness of the second intrinsic amorphous silicon layer 22 is 5 nm to 8 nm, and the thickness of the boron-doped microcrystalline silicon layer is 25 nm to 30 nm.

[0040] The thickness of the first intrinsic amorphous silicon layer 21 can be 5 nm, 5.5 nm, 6 nm, 6.5 nm, or 7 nm, which has a high transmittance and good passivation effect, is beneficial to reducing light absorption loss, and improving the conversion efficiency of the solar cell.

[0041] The thickness of the second intrinsic amorphous silicon layer 22 can be 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, or 8 nm, which has a good passivation effect, can reduce the recombination rate of the back field of the solar cell, and improve the conversion efficiency of the solar cell.

[0042] The thickness of the boron-doped microcrystalline silicon layer can be 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, or 30 nm, which can ensure the carrier transport path, provide more carrier transport channels, and thus improve the conversion efficiency of the battery. The boron doping concentration of the boron-doped microcrystalline silicon layer can be 1×10 19 cm -3-1*10 20 cm -3 In the boron-doped microcrystalline silicon layer, appropriate boron doping can establish a hole conduction network, thereby improving the short-circuit current and conversion efficiency of the battery.

[0043] The thickness of the phosphorus-doped crystalline silicon layer and the thickness of the phosphorus-doped microcrystalline silicon layer can refer to the foregoing description of the crystalline silicon layer 30 and the first microcrystalline silicon layer 41, and they also have the same technical effects, which will not be elaborated herein in this embodiment.

[0044] The phosphorus doping concentration of the phosphorus-doped crystalline silicon layer is 1*10 17 cm -3 -1*10 18 cm -3 , such as 1*10 17 cm -3 or 1*10 18 cm -3 . The doping of phosphorus elements can improve the energy band structure of the seed layer, reduce the band gap width, facilitate the transition of photo-generated electrons, improve the absorption and utilization efficiency of photons by the battery, increase the generation quantity of photo-generated carriers, and thereby improve the short-circuit current and conversion efficiency of the solar cell.

[0045] The phosphorus doping concentration of the phosphorus-doped microcrystalline silicon layer is 1*10 18 cm -3 -1*10 20 cm -3 . Such as 1*10 18 cm -3 、1*10 19 cm -3 or 1*10 20 cm -3 . It improves the absorption and utilization efficiency of photons by the battery, increases the generation quantity of photo-generated carriers, and thereby improves the short-circuit current and conversion efficiency of the solar cell.

[0046] In the related art, the phosphorus doping concentration of the hydrogen-containing seed layer is basically the same as that of the phosphorus-doped microcrystalline silicon layer. The phosphorus doping concentration of the crystalline silicon layer 30 in this embodiment is lower, which improves passivation and potentially increases the open-circuit voltage.

[0047] An embodiment of the present application also proposes a preparation process for each film layer of a battery structure 100 as follows: Silicon substrate 10: The silicon substrate 10 can be a double-sided polished and clean silicon substrate 10 obtained after completing double-sided cleaning and polishing, removing surface organic substances, metal impurities, and surface damage layers, etc.

[0048] The present application does not specifically limit the process for cleaning the silicon substrate, and it can be any cleaning process, such as Standard Clean 1 or Standard Clean 2; among them, Standard Clean 1 can include a mixture of ammonium hydroxide, hydrogen peroxide, and water, and Standard Clean 2 can include a mixture of hydrochloric acid, hydrogen peroxide, and water.

[0049] In some embodiments, texturing can be performed on a double-sided polished and clean silicon substrate. Specifically, texturing refers to forming a microscopic textured surface structure on the silicon substrate through chemical etching or physical methods. This structure can increase the residence time of light on the silicon surface and reduce light reflection, thereby improving the light absorption efficiency.

[0050] In some embodiments, texturing can be carried out by chemical etching using an alkaline solution (such as sodium hydroxide or potassium hydroxide). Utilizing the anisotropic etching characteristics of silicon in the alkaline solution, a pyramidal textured surface structure is formed.

[0051] In some embodiments, the first intrinsic amorphous silicon layer 21, the crystalline silicon layer 30, the first microcrystalline silicon layer 41, the second intrinsic amorphous silicon layer 22, and the second microcrystalline silicon layer 42 can be prepared by plasma-enhanced chemical vapor deposition, hot wire chemical vapor deposition, or low-pressure chemical vapor deposition. The thickness control of each film layer can refer to the foregoing, and other relevant process parameters are as follows: First intrinsic amorphous silicon layer 21: Under the conditions of 180°C - 210°C, 0.4 Torr - 0.7 Torr, and a coating power of 200 W - 500 W, hydrogen is introduced at a flow rate of 500 sccm - 2000 sccm and silane is introduced at a flow rate of 500 sccm - 1000 sccm; the flow rate ratio of hydrogen to silane is controlled to be (1 - 3):1.

[0052] Crystalline silicon layer 30: Under the conditions of 170°C - 190°C, 4 Torr - 5 Torr, and a coating power of 2000 W - 4000 W, hydrogen is introduced at a flow rate of 5000 sccm - 8000 sccm, silane is introduced at a flow rate of 50 sccm - 100 sccm, a phosphorus source is introduced at a flow rate of 50 sccm - 200 sccm, and an oxygen source is introduced at a flow rate of 300 sccm - 800 sccm; the flow rate ratio of the oxygen source to silane is controlled to be (5 - 10):1.

[0053] First microcrystalline silicon layer 41: Under the conditions of 170°C - 190°C, 0.4 Torr - 1 Torr, and a coating power of 3000 W - 5000 W, hydrogen is introduced at a flow rate of 10000 sccm - 20000 sccm, silane is introduced at a flow rate of 500 sccm - 1000 sccm, a phosphorus source is introduced at a flow rate of 100 sccm - 300 sccm, and an oxygen source is introduced at a flow rate of 10 sccm - 100 sccm; the flow rate ratio of hydrogen to silane is controlled to be (200 - 300):1.

[0054] Second intrinsic amorphous silicon layer 22: Under the conditions of 180°C - 220°C, 0.4 Torr - 0.7 Torr, and a coating power of 100 W - 400 W, hydrogen is introduced at a flow rate of 1000 sccm - 3000 sccm and silane is introduced at a flow rate of 500 sccm - 1000 sccm; the flow rate ratio of hydrogen to silane is controlled to be (1 - 3):1.

[0055] Second microcrystalline silicon layer 42: Under the conditions of 140°C - 170°C, 3 Torr - 5 Torr, and a coating power of 5000 W - 7000 W, hydrogen is introduced at a flow rate of 18000 sccm - 25000 sccm, silane is introduced at a flow rate of 50 sccm - 80 sccm, a boron source is introduced at a flow rate of 20 sccm - 100 sccm, and an oxygen source is introduced at a flow rate of 10 sccm - 30 sccm; the flow rate ratio of hydrogen to silane is controlled to be (250 - 350):1.

[0056] In some embodiments, the silane in the above preparation processes may include one or more of SiH4, Si2H6, and Si3H8. The oxygen source may include one or more of CO2, O2, and N2O. The phosphorus source may include one or more of PH3 and P2H4. The boron source may include one or more of BH3, B3H6, B4H 10 of one or more.

[0057] The embodiments of the battery structure 100 in the present application will be described in detail below in combination with the preparation processes.

[0058] Example 1 (1) Cleaning and texturing An N-type monocrystalline silicon wafer with a thickness of 150 μm is selected. The front and back sides of the silicon wafer are cleaned by a trough-type cleaning and texturing machine, and then the silicon wafer is textured with a sodium hydroxide solution to form a textured surface on the front and back sides of the silicon wafer to provide the silicon substrate 10.

[0059] (2) Preparation of the second intrinsic amorphous silicon layer 22 The second intrinsic amorphous silicon layer 22 is prepared by plasma-enhanced chemical (PECVD) vapor chemical deposition; the second intrinsic amorphous silicon layer 22 is prepared on the silicon substrate 10 of the silicon wafer obtained in step (1). The specific parameters are as follows: Hydrogen and silane are introduced. Under the conditions of 200°C, 0.5 Torr, and a coating power of 200 W, the thickness is controlled to be 5 nm - 7 nm, the hydrogen flow rate range is 1500 sccm, and the silane flow rate range is 750 sccm.

[0060] (3) Preparation of the first intrinsic amorphous silicon layer 21 On the basis of step (2), the second intrinsic amorphous silicon layer 22 remaining on the front side of the silicon substrate 10 is cleaned, and the first intrinsic amorphous silicon layer 21 is prepared on the front side of the silicon substrate 10 by plasma-enhanced chemical (PECVD) vapor chemical deposition method. The specific parameters are as follows: hydrogen and silane are introduced, and under the conditions of 200 °C, 0.5 Torr and a coating power of 200 W, the thickness is controlled to be 5 nm - 8 nm, the hydrogen flow rate range is 1500 sccm, and the silane flow rate range is 750 sccm.

[0061] (4)Prepare the crystalline silicon layer 30 The crystalline silicon layer 30 is continuously prepared on the front side of the silicon substrate 10 obtained in step (4) by plasma-enhanced chemical (PECVD) vapor chemical deposition method, and the crystalline silicon layer 30 is formed on the surface of the first intrinsic amorphous silicon layer 21. The specific parameters are as follows: hydrogen, silane, CO2, and phosphine are introduced, and under the conditions of 180 °C, 4.5 Torr and a coating power of 3000 W, the thickness is controlled to be 0.5 nm - 1 nm, the hydrogen flow rate range is 6000 sccm, the silane flow rate range is 75 sccm, the CO2 flow rate range is 500 sccm, and the phosphine is 100 sccm.

[0062] (5)Prepare the first microcrystalline silicon layer 41 The first microcrystalline silicon layer 41 is continuously prepared on the front side of the silicon substrate 10 obtained in step (5) by plasma-enhanced chemical (PECVD) vapor chemical deposition method, and the first microcrystalline silicon layer 41 is formed on the surface of the crystalline silicon layer 30. The specific parameters are as follows: hydrogen, silane, CO2, and phosphine are introduced, and under the conditions of 180 °C, 0.5 Torr and a coating power of 4000 W, the thickness is controlled to be 20 nm - 22 nm, the coating time is 60 s, the hydrogen flow rate range is 15000 sccm, the silane flow rate range is 700 sccm, the phosphine is 200 sccm, and the CO2 flow rate is 50 sccm.

[0063] (6)Prepare the second microcrystalline silicon layer 42 On the basis of step (5), the front film layer remaining on the back side of the silicon substrate 10 is cleaned, and the second microcrystalline silicon layer 42 is continuously prepared on the back side of the silicon substrate 10 by plasma-enhanced chemical (PECVD) vapor chemical deposition method, and the second microcrystalline silicon layer 42 is formed on the surface of the second intrinsic amorphous silicon layer 22. The specific parameters are as follows: hydrogen, silane, and CO2 are introduced, and under the conditions of 150 °C, 4 Torr, and a coating power of 6000 W, the thickness is controlled to be 25 nm - 30 nm, the hydrogen flow rate range is 20000 sccm, the silane flow rate range is 70 sccm; the CO2 flow rate range is 20 sccm, and the borane is 50 sccm.

[0064] In Embodiment 1, a stacked structure is formed on the surface of the silicon substrate 10 in the second direction. The first direction is perpendicular to the second direction, and the second direction is the lateral direction of the silicon substrate 10. This stacked structure is formed on the side surface of the silicon substrate 10 and includes, in sequence, a second intrinsic amorphous silicon layer 22, a first intrinsic amorphous silicon layer 21, a crystalline silicon layer 30, a first microcrystalline silicon layer 41, and a second microcrystalline silicon layer 42. Among them, the second intrinsic amorphous silicon layer 22 is disposed close to the silicon substrate 10 and is in contact with the side surface of the silicon substrate 10.

[0065] It should be noted that the stacked structure on this side surface will cause short circuits between the front and back surfaces of the battery structure 100. Therefore, in the subsequent process, it is necessary to perform cutting and removal or set trench isolation to expose the side surface of the silicon substrate 10 again and restore the electrical performance of the battery structure 100.

[0066] Embodiment 2 The difference between the preparation process of the battery structure 100 in this embodiment and that in Embodiment 1 lies only in that: in this embodiment, the preparation parameters of the N-type doping layer in step (5) are adjusted: the coating time is shortened to 40 s, and the thickness of the first microcrystalline silicon layer 41 is adjusted to 18 nm.

[0067] The remaining steps are carried out according to the method in Embodiment 1.

[0068] Comparative Example 1 The difference between the preparation process of the battery structure 100 in this comparative example and that in Embodiment 1 lies only in that: in this comparative example, step (4) is adjusted to prepare a high-hydrogen seed layer, and the specific parameters are as follows: hydrogen, silane, and phosphine are introduced, and under the conditions of 180 °C, 4.5 Torr, and a coating power of 3000 W, the thickness is controlled to be 4 nm, the hydrogen flow rate range is 25000 sccm, the silane flow rate range is 75 sccm, and the phosphine is 100 sccm.

[0069] The remaining steps are carried out according to the method in Embodiment 1.

[0070] The performance comparisons of the above Embodiment 1, Embodiment 2, and Comparative Example 2 are shown in Table 1.

[0071] Table 1

[0072] As can be seen from Table 1, by comparing Embodiment 1 with Comparative Example 1, it can be obtained that by introducing an ultra-thin silicon-based layer containing oxygen elements on the front surface of the solar cell, the crystallization rate of the solar cell is improved, the light transmittance is better, the high oxygen content in the crystalline silicon layer 30 broadens the bandgap, enhances the absorption of short-wavelength light, and the short-circuit current and conversion efficiency are significantly improved.

[0073] Comparing Example 1 with Example 2, it can be concluded that in Example 2, the thickness of the N-type doping layer is reduced by 2 nm based on Example 1, thereby reducing the front electron tunneling contact resistivity and improving the fill factor (FF). At the same time, due to the reduction in the thickness of the N-type doping layer, parasitic absorption is reduced, and the short-circuit current and conversion efficiency are improved.

[0074] Referring to Figure 2 , Figure 2 , which shows the structure of a battery cell, and an embodiment of the present application also provides a battery cell. In this embodiment, the battery cell 200 includes a first conductive structure, a second conductive structure, and the battery structure 100 described above. The first conductive structure is disposed on the surface of the first microcrystalline silicon layer 41 of the battery structure 100 away from the silicon substrate 10, and the second conductive structure is disposed on the surface of the second microcrystalline silicon layer 42 of the battery structure 100 away from the silicon substrate 10.

[0075] The first conductive structure includes a first transparent conductive film layer 51 and a first electrode 61. The first transparent conductive film layer 51 is disposed on the surface of the first microcrystalline silicon layer 41 away from the crystalline silicon layer 30, and the first electrode 61 is disposed on the surface of the first transparent conductive film layer 51 away from the first microcrystalline silicon layer 41.

[0076] The second conductive structure includes a second transparent conductive film layer 52 and a second electrode 62. The second transparent conductive film layer 52 is disposed on the surface of the second microcrystalline silicon layer 42 away from the second intrinsic amorphous silicon layer 22, and the second electrode 62 is disposed on the surface of the second transparent conductive film layer 52 away from the second microcrystalline silicon layer 42.

[0077] The first transparent conductive film layer 51 and the second transparent conductive film layer 52 may include one or more of indium tin oxide (ITO), lanthanide metal-doped indium oxide, fluorine-doped tin oxide (FTO), antimony-doped tin oxide, boron-doped zinc oxide (BZO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), gallium zinc oxide (GZO), indium tungsten oxide (IWO). The above oxides have good light transmittance, good electrical conductivity, and chemical stability, and can collect the current generated by the photovoltaic effect in the solar cell.

[0078] The thickness of both the first transparent conductive film layer 51 and the second transparent conductive film layer 52 may be 50 nm - 150 nm, such as 50 nm, 75 nm, 100 nm, 125 nm, or 150 nm. The thickness of the first transparent conductive film layer 51 and the second transparent conductive film layer 52 may be the same or different.

[0079] The first transparent conductive film layer 51 and the second transparent conductive film layer 52 can be prepared by atmospheric pressure chemical vapor deposition (APCVD), radio frequency magnetron sputtering (PVD), or reactive plasma deposition (RPD).

[0080] The first electrode 61 and the second electrode 62 may include one or more of Al, Ti, Ni, Co, Ag, Cu, and Sn.

[0081] The first electrode 61 and the second electrode 62 may be prepared using low-temperature copper paste or silver-coated copper paste. Or they may be prepared by electroplating one or more of Al, Ti, Ni, Co, Ag, Cu, and Sn.

[0082] The battery cell according to the present application has good electrochemical performance and has a high short-circuit current and conversion efficiency.

[0083] An embodiment of the present application provides a photovoltaic system, including the battery cell 200 described above.

[0084] The photovoltaic system according to the present application has a higher system efficiency and total output power.

[0085] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A battery structure, characterized in that, Comprising: A silicon substrate having a front surface and a back surface oppositely disposed in a first direction; In a direction away from the silicon substrate, a first intrinsic amorphous silicon layer, a crystalline silicon layer, and a first microcrystalline silicon layer are sequentially stacked on the front surface of the silicon substrate. The crystalline silicon layer and the first microcrystalline silicon layer have a first doping type, and the crystalline silicon layer contains hydrogen and oxygen elements; In a direction away from the silicon substrate, a second intrinsic amorphous silicon layer and a second microcrystalline silicon layer are sequentially stacked on the back surface of the silicon substrate. The second microcrystalline silicon layer has a second doping type; Wherein, the thickness of the crystalline silicon layer is less than the thickness of the first microcrystalline silicon layer, and the first doping type and the second doping type are opposite.

2. The battery structure according to claim 1, wherein, The thickness of the crystalline silicon layer is 0.5 nm to 1 nm.

3. The battery structure according to claim 2, characterized in that, The total thickness of the crystalline silicon layer and the first microcrystalline silicon layer is 18 nm to 20 nm.

4. The battery structure according to claim 1, wherein The thickness ratio of the crystalline silicon layer to the first microcrystalline silicon layer is 1:(17 - 40).

5. The battery structure according to any one of claims 1-4, characterized in that, The oxygen doping concentration in the crystalline silicon layer is greater than the hydrogen doping concentration, and the oxygen doping concentration of the crystalline silicon layer is 1×10 21 cm -3 -1×10 23 cm -3 , and the oxygen doping concentration of the first microcrystalline silicon layer is 1×10 17 cm -3 -1×10 18 cm -3 .

6. The battery structure according to any one of claims 1-4, characterized in that, The crystalline silicon layer is a phosphorus-doped crystalline silicon layer, the first microcrystalline silicon layer is a phosphorus-doped microcrystalline silicon layer, and the second microcrystalline silicon layer is a boron-doped microcrystalline silicon layer.

7. The battery structure according to claim 6, characterized in that, The thickness of the first intrinsic amorphous silicon layer is 5 nm to 7 nm, the thickness of the phosphorus-doped crystalline silicon layer is 0.5 nm to 1 nm, the thickness of the phosphorus-doped microcrystalline silicon layer is 18 nm to 22 nm, the thickness of the second intrinsic amorphous silicon layer is 5 nm to 8 nm, and the thickness of the boron-doped microcrystalline silicon layer is 25 nm to 30 nm.

8. The battery structure according to claim 7, wherein, The phosphorus doping concentration of the phosphorus-doped crystalline silicon layer is 1×10 17 cm -3 -1×10 18 cm -3 ; the phosphorus doping concentration of the phosphorus-doped microcrystalline silicon layer is 1×10 18 cm -3 -1×10 20 cm -3 .

9. The battery structure according to any one of claims 1-4, characterized in that, On the surface of the silicon substrate in a second direction, the second intrinsic amorphous silicon layer, the first intrinsic amorphous silicon layer, the crystalline silicon layer, the first microcrystalline silicon layer, and the second microcrystalline silicon layer are sequentially stacked. The second intrinsic amorphous silicon layer is disposed adjacent to the silicon substrate, and the first direction is perpendicular to the second direction.

10. A battery cell, characterized in that, Comprising a first conductive structure, a second conductive structure, and the battery structure according to any one of claims 1-9. The first conductive structure is disposed on the surface of the first microcrystalline silicon layer of the battery structure away from the silicon substrate, and the second conductive structure is disposed on the surface of the second microcrystalline silicon layer of the battery structure away from the silicon substrate.

11. A photovoltaic system, characterized in that, Comprising the battery cell according to claim 10.

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