Image sensor and manufacturing method thereof, camera module and electronic equipment

Abstract

The present invention relates to the field of integrated circuit technology, and in particular to an image sensor and a manufacturing method thereof, a camera module and an electronic device, comprising a substrate; a plurality of photoelectric sensing regions formed on a first surface of the substrate in a mutually spaced manner, the photoelectric sensing region having a first trench formed on the first surface of the substrate, a first semiconductor formed conformally on the surface of the first trench and having a doping function, and a second semiconductor formed conformally on the surface of the first semiconductor and having a doping function, the second semiconductor having a different doping type from the first semiconductor; and a plurality of isolation regions formed on the first surface of the substrate in an interlaced manner with the plurality of photoelectric sensing regions, the isolation region having a second trench formed on the first surface of the substrate, the first semiconductor formed conformally on the surface of the second trench, and the second semiconductor formed on the surface of the first semiconductor.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an image sensor and a manufacturing method thereof, a camera module and an electronic device. Background Art

[0002] Semiconductor image sensors are used to detect radiation, such as light. Complementary metal oxide semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are widely used in various applications, such as digital cameras and mobile phone cameras. These devices utilize an array of pixels on a substrate to absorb incident radiation and convert the detected radiation into electrical signals, enabling image capture and transmission.

[0003] The fabrication of the photoelectric sensing area is undoubtedly a core step in the semiconductor image sensor manufacturing process, directly impacting its performance and reliability. However, traditional manufacturing methods present several significant challenges. High-energy ion implantation is typically used to form the photoelectric sensing area. While effective, this method can cause a certain degree of damage to the substrate. Furthermore, single ion implantation isolation can easily lead to optical crosstalk, resulting in reduced image quality. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is: to provide an image sensor and its manufacturing method, camera module and electronic equipment that can effectively solve the problem of substrate damage during the image sensor manufacturing process, can reduce dark current, can improve image quality, and can improve the isolation performance of the isolation area.

[0005] To solve the above technical problems, the present invention adopts a technical solution: providing an image sensor, comprising:

[0006] substrate;

[0007] a plurality of photoelectric sensing regions formed on a first surface of a substrate in a spaced-apart manner, the photoelectric sensing regions comprising a first trench formed on the first surface of the substrate, a first semiconductor formed conformally on a surface of the first trench and having a doping factor, and a second semiconductor formed conformally on a surface of the first semiconductor and having a doping factor different from that of the first semiconductor; and

[0008] A plurality of isolation regions and a plurality of photoelectric sensing regions are formed on the first surface of the substrate in an alternating manner, wherein the isolation regions have a second trench formed on the first surface of the substrate, the first semiconductor formed conformally on the surface of the second trench, and the second semiconductor formed on the surface of the first semiconductor.

[0009] Further, the first semiconductor is configured as a p-type semiconductor having p-type doping, and the second semiconductor is configured as an n-type semiconductor having n-type doping; or, the first semiconductor is configured as an n-type semiconductor having n-type doping, and the second semiconductor is configured as a p-type semiconductor having p-type doping;

[0010] The second semiconductor located in the second trench fully fills the second trench.

[0011] Furthermore, the first semiconductor includes a first semiconductor material layer formed on the surface of the first trench in a conformal manner and a second semiconductor material layer formed on the surface of the first semiconductor material layer in a conformal manner, the first semiconductor material layer is configured as a heavily doped first semiconductor material layer, and the second semiconductor material layer is configured as a lightly doped second semiconductor material layer; the second semiconductor includes a third semiconductor material layer formed on the surface of the second semiconductor material layer in a conformal manner and a fourth semiconductor material layer formed on the surface of the third semiconductor material layer, the third semiconductor material layer is configured as a lightly doped third semiconductor material layer, and the fourth semiconductor material layer is configured as a heavily doped fourth semiconductor material layer.

[0012] Furthermore, the fourth semiconductor material layer located in the second trench fully fills the second trench.

[0013] Furthermore, a filling medium is formed in the first groove and fully filled therein;

[0014] The first groove is configured as a U-shaped groove; or the first groove and the second groove are both configured as U-shaped grooves.

[0015] Furthermore, the substrate has a base and an epitaxial layer formed on the surface of the base; the several photoelectric sensing regions and the several isolation regions are all formed on the surface of the epitaxial layer, and the doping type of the first semiconductor is the same as the doping type of the epitaxial layer.

[0016] To solve the above technical problems, another technical solution adopted by the present invention is to provide a method for manufacturing an image sensor, comprising the following steps:

[0017] providing a substrate;

[0018] Forming a plurality of first trenches spaced apart from each other and second trenches interlaced with the plurality of first trenches on a first surface of the substrate;

[0019] A first semiconductor and a second semiconductor with doping are continuously or sequentially grown on the first surface of the substrate, the surfaces of several first trenches, and the surfaces of several second trenches, wherein the second semiconductor has a different doping type from the first semiconductor; wherein the first trench, the first semiconductor and the second semiconductor grown therein constitute a photoelectric sensing region, and the first semiconductor and the second semiconductor in the first trench are both continuously or sequentially grown on the surface of the first trench in a conformal manner; the second trench, the first semiconductor and the second semiconductor grown therein constitute an isolation region, and the first semiconductor and the second semiconductor in the second trench are both continuously or sequentially grown on the surface of the second trench in a conformal manner, or the first semiconductor is conformally grown on the surface of the second trench, and the second semiconductor is grown on the surface of the first semiconductor and fills the second trench.

[0020] Furthermore, the method for manufacturing the image sensor further includes the following steps:

[0021] The connection between the first semiconductor belonging to the isolation region and the first semiconductor belonging to the photodiode region is blocked, and the connection between the second semiconductor belonging to the isolation region and the second semiconductor belonging to the photoelectric sensing region is blocked.

[0022] In order to solve the above technical problems, another technical solution adopted by the present invention is: providing a camera module, including the image sensor described above; or an image sensor obtained by the method for manufacturing the image sensor described above.

[0023] In order to solve the above technical problems, another technical solution adopted by the present invention is: providing an electronic device, including the camera module described above.

[0024] Based on the embodiments described above, the image sensor of the present invention has the following unexpected benefits: (1) The first trench in the photoelectric sensing region conformally forms a first semiconductor and a second semiconductor of a different doping type. The profiles of the first and second semiconductors are identical to the profile of the first trench, forming multiple light-absorbing surfaces in different orientations and directions. This creates a natural light-trapping structure that increases light absorption, eliminates the fabrication steps for the light-trapping structure, reduces production costs, and addresses the issue of high plasma damage to the substrate associated with traditional light-trapping structures. Furthermore, the natural light-trapping structure can reduce dark current. (2) The first and second semiconductors are formed on the substrate using epitaxial growth, addressing the issue of substrate damage caused by ion implantation. (3) Both the first and second trenches can be U-shaped. Compared to rectangular trenches in conventional techniques, at the same depth, this reduces the area of ​​substrate damage caused by etching. Furthermore, the U-shaped trenches provide more surfaces in different orientations and directions, increasing the light-absorbing surfaces of the natural light-trapping structure. Furthermore, the U-shaped trenches increase the cross-sectional area of ​​the first and second semiconductors, thereby increasing the full well capacity of the image sensor. (4) A first semiconductor and a second semiconductor are formed in the second trench of the isolation region in the same or similar manner as the first trench, so that the first semiconductor and the second semiconductor of the isolation region form a pnp structure or an npn structure. The pnp structure or the npn structure has the function of isolating the signals of two adjacent photoelectric sensing regions, and its isolation performance is superior to that of an isolation structure formed by filling with an isolation dielectric. (5) The second trench of the isolation region, the first semiconductor, and the second semiconductor can be formed simultaneously in the same step as the first trench, the first semiconductor, and the second semiconductor of the photoelectric sensing region, thereby reducing the number of steps in the manufacture of the image sensor, optimizing the manufacturing process of the image sensor, and making the manufacture of the image sensor more efficient. (6) The doping type of the first semiconductor in contact with the first surface of the substrate is configured to be the same as the doping type of the substrate. When the epitaxial layer of the substrate is a p-epitaxial layer, the first semiconductor of the same doping type has the effect of compounding the free electrons on the surface of the p-epitaxial layer, which can reduce the dark current; when the epitaxial layer of the substrate is an n-epitaxial layer, the first semiconductor of the same doping type has the effect of repelling the free electrons of the n-epitaxial layer, preventing the free electrons of the n-epitaxial layer from generating crosstalk, which can reduce the dark current.(7) The first semiconductor is configured as a heavily doped first semiconductor material layer and a lightly doped second semiconductor material layer, formed continuously or sequentially on the first surface of the substrate; the second semiconductor is configured as a lightly doped third semiconductor material layer and a heavily doped fourth semiconductor material layer, formed continuously or sequentially on the surface of the first semiconductor; the lightly doped second and third semiconductor material layers in the intermediate layers can increase the pn junction width of the photoelectric sensing region, increase the light-receiving area, and thus improve the performance of the photoelectric sensing region. The width of the pnp structure or npn structure of the isolation region can also be increased, further enhancing isolation performance. (8) The isolation region is isolated by the heavily doped first semiconductor material layer and the heavily doped fourth semiconductor material layer, further enhancing the isolation performance of the isolation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0026] Figure 1 It is a process flow chart of an embodiment of a method for manufacturing an image sensor of the present invention.

[0027] Figure 2 FIG. 1 is a schematic cross-sectional view of a substrate in an embodiment of a method for manufacturing an image sensor according to the present invention.

[0028] Figures 3a to 3c 1 is a schematic cross-sectional view of a structure obtained during the trench fabrication stage in one embodiment of a method for fabricating an image sensor according to the present invention.

[0029] Figure 4 1 is a schematic cross-sectional view of a structure obtained during the semiconductor formation stage in the trench in one embodiment of a method for manufacturing an image sensor according to the present invention.

[0030] Figure 5 1 is a schematic cross-sectional view of a structure obtained during the trench dielectric filling manufacturing stage in one embodiment of a method for manufacturing an image sensor of the present invention.

[0031] Figure 6 FIG. 1 is a schematic cross-sectional view of a structure obtained during the thinning process in one embodiment of a method for manufacturing an image sensor according to the present invention.

[0032] Figure 7 1 is a schematic cross-sectional view of a structure obtained during the multi-layer interconnection structure fabrication stage in an embodiment of a method for fabricating an image sensor according to the present invention.

[0033] Figure 8FIG. 1 is a schematic cross-sectional view of the structure obtained during the color filter layer and microlens layer fabrication stage in one embodiment of a method for fabricating an image sensor according to the present invention.

[0034] Figure 9 yes Figure 8 A magnified schematic diagram of part A in the figure.

[0035] The accompanying drawings in this specification are numeraled as follows:

[0036] Substrate 110; first surface 110a; second surface 110b; base 111; epitaxial layer 112; photoelectric sensing region 120; first trench 121; isolation region 130; second trench 131; first semiconductor 141; first semiconductor material layer 141a; second semiconductor material layer 141b; second semiconductor 142; third semiconductor material layer 142a; fourth semiconductor material layer 142b; filling dielectric 150; first dielectric layer 151; high-k dielectric layer 152; second dielectric layer 153; metal interconnect structure 160; interlayer dielectric layer 161; multilayer interconnect structure 162; color filter layer 170; color filter 171; microlens layer 180; microlens 181;

[0037] Protection layer 210 ; pad oxide layer 211 ; pad nitride layer 212 ; patterned photoresist layer 220 ; opening 221 . DETAILED DESCRIPTION

[0038] The following disclosure provides a variety of different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which other components may be formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the present invention may repeat reference symbols and / or characters in multiple instances. This repetition is for simplicity and clarity and does not, by itself, represent a relationship between the multiple embodiments and / or configurations.

[0039] Furthermore, spatially relative terms, such as "below," "beneath," "below," "above," and "upper," may be used herein to readily describe the relationship of one element or component to another element(s) or component(s) as illustrated in the figures. Spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] Although the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain necessary errors resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard deviation of the mean as would be considered by one of ordinary skill in the art. Except in the operating / work examples, or unless expressly indicated otherwise, all numerical ranges, totals, values, and percentages, such as for amounts of materials, durations, temperatures, operating conditions, amounts, and other aspects of the invention disclosed herein, should be understood as modified in all instances by the term "about." Therefore, unless expressly stated to the contrary, the numerical parameter settings recited herein and the appended claims are approximations that may vary as required. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to the other or between two endpoints. All ranges disclosed herein are inclusive unless otherwise indicated.

[0041] Furthermore, the technical components described in the present invention and the appended claims are primarily those improved by the present invention and do not limit the protected object of the present invention to encompassing only those technical components. Known essential components (structures and / or methods) and / or non-essential components of the protected object, other than the technical components described in the present invention and the appended claims, are not included in the present invention and the appended claims because they do not fall within the scope of improvement of the present invention. However, this does not mean that the protected object of the present invention lacks these known components.

[0042] See Figure 8 and Figure 9 This article uses a front-illuminated image sensor as an example to illustrate the solution protected by the present invention. It should be understood that the solution protected by the present invention is not limited to this exemplary embodiment of a front-illuminated image sensor. For example, the solution protected by the present invention can also be applied to a back-illuminated image sensor or other suitable image sensors.

[0043] In the illustrated embodiment, the image sensor includes a substrate 110 , a plurality of photoelectric sensing regions 120 , and a plurality of isolation regions 130 .

[0044] The substrate 110 is a silicon substrate doped with a p-type dopant, such as boron, and thus functions as a p-type substrate. Alternatively, the substrate 110 may comprise another suitable semiconductor material. For example, the substrate 110 may be a silicon substrate doped with an n-type dopant, such as phosphorus or arsenic, and thus functions as an n-type substrate. Furthermore, the substrate 110 may comprise other elemental semiconductors, such as germanium and diamond. The substrate 110 may alternatively comprise a compound semiconductor and / or an alloy semiconductor.

[0045] The substrate 110 has a first surface 110a and an opposing second surface 110b. The substrate 110 may be composed of a base 111 and an epitaxial layer 112 formed on the surface of the base 111. The surface of the base 111 facing away from the epitaxial layer 112 may be configured as the second surface 110b of the substrate 110, and the surface of the epitaxial layer 112 facing away from the base 111 (hereinafter referred to as the surface of the epitaxial layer 112) may be configured as the first surface 110a of the substrate 110. The base 111 may be configured as a p-type doped base 111, and the epitaxial layer 112 may be configured as a lightly doped p-epitaxial layer. During implementation, an in-situ doping process is performed to cover the base 111 with a certain thickness of semiconductor material, such as silicon, and p-type epitaxial growth, thereby completing the growth of the p-epitaxial layer and forming a p-type substrate. The base 111 may also be configured as an n-type doped base 111, and the epitaxial layer 112 may be configured as a lightly doped n-epitaxial layer. During implementation, an in-situ doping process is performed to cover the substrate 111 with a certain thickness of semiconductor material such as silicon and n-type epitaxial layer, thereby completing the growth of the n-epitaxial layer and obtaining an n-type substrate. The doping concentration is represented by its logarithmic value with base 10. For example, the doping concentration of the lightly doped epitaxial layer 112 is less than about 10 14 cm -3 , for example, a doping concentration of about 10 13 cm -3 .

[0046] In the embodiment shown, a plurality of photoelectric sensing regions 120 may be arranged to be formed on the first surface 110a of the substrate 110 in a spaced manner along a predetermined direction, for example, on the surface of the epitaxial layer 112. Each of the plurality of photoelectric sensing regions 120 has a first trench 121 extending inwardly from the first surface 110a of the substrate 110 (see FIG. Figure 3c ), a first semiconductor 141 conformally formed on a surface of the first trench 121 and having a doping structure, and a second semiconductor 142 conformally formed on a surface of the first semiconductor 141 and having a doping structure. The second semiconductor 142 and the first semiconductor 141 have different doping types.

[0047] The first groove 121 may be configured as Figure 3c The U-shaped groove shown in the figure can also be configured as a rectangular groove, a trapezoidal groove, or other suitable shapes. In addition to having a bottom and side surfaces, the U-shaped groove also has a curved surface that smoothly transitions between the bottom and side surfaces. Combined with the first semiconductor 141 and the second semiconductor 142 conformally distributed on its surface (bottom, side, and curved surface), a natural light-trapping structure can be formed. This eliminates the manufacturing steps of the light-trapping structure, reduces production costs, and solves the problem of high plasma damage to the substrate caused by traditional light-trapping structures. The natural light-trapping structure can also reduce dark current. Compared to rectangular grooves, the U-shaped groove can increase the cross-sectional area of ​​the conformal first semiconductor 141 and the second semiconductor 142 (pn junction), which can improve the full well capacity of the image sensor.

[0048] The first semiconductor 141 can be configured as a p-type semiconductor having p-type doping, such as boron, gallium, and / or indium. The first semiconductor 141 can also be configured as an n-type semiconductor having n-type doping, such as phosphorus, arsenic, and / or antimony. If the substrate 110 is configured as a p-type substrate, the first semiconductor 141 can be configured as a p-type semiconductor having the same doping type as the p-epitaxial layer of the p-type substrate. If the substrate 110 is configured as an n-type substrate, the first semiconductor 141 can be configured as an n-type semiconductor having the same doping type as the n-epitaxial layer of the n-type substrate.

[0049] The first semiconductor 141 is conformally grown on the surface (bottom, side, and curved surface) of the first trench 121, that is, the first semiconductor 141 is grown on the surface (bottom, side, and curved surface) of the first trench 121, and its profile follows the profile of the first trench 121 or is located on the profile of the first trench 121. The first semiconductor 141 may include a first semiconductor material layer 141a formed conformally on the surface of the first trench 121 and a second semiconductor material layer 141b formed conformally on the surface of the first semiconductor material layer 141a. The first semiconductor material layer 141a and the second semiconductor material layer 141b may be epitaxially grown continuously or sequentially on the surface of the first trench 121. The first semiconductor material layer 141a may be configured as a heavily doped first semiconductor material layer 141a, and the second semiconductor material layer 141b may be configured as a lightly doped second semiconductor material layer 141b. The doping concentration is represented by its logarithmic value with base 10. For example, the doping concentration of the heavily doped first semiconductor material layer 141a is greater than or equal to about 10. 14 cm -3 , for example, a doping concentration of about 10 17 cm -3 The doping concentration of the lightly doped second semiconductor material layer 141b is less than about 10 14 cm-3 , for example, a doping concentration of about 10 12 cm -3 .

[0050] If the first semiconductor 141 is configured as a p-type semiconductor, the first semiconductor material layer 141a corresponds to a heavily doped p+ semiconductor material layer, and the second semiconductor material layer 141b corresponds to a lightly doped p- semiconductor material layer. The p+ semiconductor material layer has the function of recombination of free electrons on the surface of the p- epitaxial layer, which can reduce dark current. If the first semiconductor 141 is configured as an n-type semiconductor, the first semiconductor material layer 141a corresponds to a heavily doped n+ semiconductor material layer, and the second semiconductor material layer 141b corresponds to a lightly doped n- semiconductor material layer. The n+ semiconductor material layer has the function of repelling free electrons in the n- epitaxial layer, preventing crosstalk between free electrons in the n- epitaxial layer and reducing dark current.

[0051] The second semiconductor 142 can be configured as an n-type semiconductor having n-type doping, such as phosphorus, arsenic, and / or antimony. The second semiconductor 142 can also be configured as a p-type semiconductor having p-type doping, such as boron, gallium, and / or indium. If the first semiconductor 141 is configured as a p-type semiconductor, the second semiconductor 142 can be configured as an n-type semiconductor having a doping type different from that of the first semiconductor 141. If the first semiconductor 141 is configured as an n-type semiconductor, the second semiconductor 142 can be configured as a p-type semiconductor having a doping type different from that of the first semiconductor 141.

[0052] The second semiconductor 142 is grown on the surface of the first semiconductor 141 in a conformal manner, that is, the second semiconductor 142 is grown on the surface (bottom, side and curved surface) of the first semiconductor 141, and its contour follows the contour of the first semiconductor 141 or is located on the contour of the first semiconductor 141. The second semiconductor 142 may include a third semiconductor material layer 142a formed on the surface of the second semiconductor material layer 141b in a conformal manner and a fourth semiconductor material layer 142b formed on the surface of the third semiconductor material layer 142a in a conformal manner. The third semiconductor material layer 142a and the fourth semiconductor material layer 142b may be grown continuously or sequentially on the surface of the second semiconductor material layer 141b. The third semiconductor material layer 142a may be configured as a lightly doped third semiconductor material layer 142a, and the fourth semiconductor material layer 142b may be configured as a heavily doped fourth semiconductor material layer 142b. The doping concentration is represented by its logarithmic value with base 10. For example, the doping concentration of the lightly doped third semiconductor material layer 142a is less than about 10 14 cm -3 , for example, a doping concentration of about 10 12 cm-3 The doping concentration of the heavily doped fourth semiconductor material layer 142b is greater than or equal to about 10 14 cm -3 , for example, a doping concentration of about 10 17 cm -3 .

[0053] If the second semiconductor 142 is configured as an n-type semiconductor, the third semiconductor material layer 142a corresponds to a lightly doped n- semiconductor material layer, and the fourth semiconductor material layer 142b corresponds to a heavily doped n+ semiconductor material layer. Together with the p-type doped first semiconductor 141, they form a p+ semiconductor material layer, a p- semiconductor material layer, an n- semiconductor material layer, and an n+ semiconductor material layer, which continuously or sequentially overlie the p-epitaxial layer. If the second semiconductor 142 is configured as a p-type semiconductor, the third semiconductor material layer 142a corresponds to a lightly doped p- semiconductor material layer, and the fourth semiconductor material layer 142b corresponds to a heavily doped p+ semiconductor material layer. Together with the n-type doped first semiconductor 141, they form an n+ semiconductor material layer, an n- semiconductor material layer, a p- semiconductor material layer, and a p+ semiconductor material layer, which continuously or sequentially overlie the n-epitaxial layer. Based on this, the p- and n- semiconductor material layers located in the middle layer can increase the pn junction width of the photoelectric sensing region 120, increasing the light-receiving area, and thereby improving the performance of the photoelectric sensing region 120. In addition, the p+ semiconductor material layer located on the surface (a layer away from the epitaxial layer 112 ) has the function of compounding the interface state brought by the subsequent process, such as the unstable surface electrons in the compound dielectric layer, which can reduce the dark current.

[0054] In the embodiment shown, a plurality of isolation regions 130 and a plurality of photoelectric sensing regions 120 are formed in an alternating manner on the first surface 110a of the substrate 110, for example, on the surface of the epitaxial layer 112. Each of the plurality of isolation regions 130 has a second trench 131 extending inwardly from the first surface 110a of the substrate 110 (see FIG. Figure 3c ), the first semiconductor 141 is formed on the surface of the second trench 131 in a conformal manner, and the second semiconductor 142 is formed on the surface of the first semiconductor 141.

[0055] The second groove 131 may be configured as Figure 3cThe U-shaped groove shown in the figure may also be configured as a rectangular groove, a trapezoidal groove, or other suitable shapes. The width of the second groove 131 may be configured to be smaller than the width of the first groove 121, and the depth of the second groove 131 may be configured to be greater than the depth of the first groove 121. The second groove 131 and the first groove 121 can be formed simultaneously in a single step, thereby reducing the number of steps in the image sensor manufacturing process, lowering manufacturing complexity, and saving manufacturing time.

[0056] For example, the material, doping type, distribution method, and doping concentration of the first semiconductor 141 within the second trench 131 can be the same or similar to those of the first semiconductor 141 within the first trench 121. For example, when the first semiconductor 141 within the first trench 121 is silicon boride, the first semiconductor 141 within the second trench 131 can be silicon boride. The material, doping type, and doping concentration of the second semiconductor 142 within the second trench 131 can be the same or similar to those of the second semiconductor 142 within the first trench 121. For example, when the second semiconductor 142 within the first trench 121 is silicon arsenide, the second semiconductor 142 within the second trench 131 can be silicon arsenide. A subtle point is that the second semiconductor 142 within the second trench 131 can be formed in a fully filled manner within the second trench 131, that is, the fourth semiconductor material layer 142b located within the second trench 131 fully fills the second trench 131. Full filling can mean that the second semiconductor 142 or the fourth semiconductor material layer 142b completely covers the second trench 131. The second semiconductor 142 or the fourth semiconductor material layer 142b can be epitaxially grown throughout the second trench 131. Therefore, the first semiconductor 141 on both sides of the second trench 131 (the sides adjacent to the two adjacent photoelectric sensing regions 120) and the second semiconductor 142 formed on the surface of the first semiconductor 141 and completely filling the second trench 131 form a pnp structure (the first semiconductor 141 is a p-type semiconductor, the second semiconductor 142 is an n-type semiconductor) or an npn structure (the first semiconductor 141 is an n-type semiconductor, the second semiconductor 142 is a p-type semiconductor). This effectively isolates the photoelectric signals of the two adjacent photoelectric sensing regions 120 from each other, preventing signal crosstalk between the two adjacent photoelectric sensing regions 120. Of course, the second semiconductor 142 within the second trench 131 can also be conformally formed on the surface of the first semiconductor 141, and this is not specifically limited in the present invention. If the second semiconductor 142 is formed conformally on the surface of the first semiconductor 141 , the isolation region 130 may be made to function as an isolation region by filling the second trench 131 with an isolation dielectric layer or a light-shielding dielectric.

[0057] Please continue to see Figure 8 and Figure 9Exemplarily, the image sensor further includes a filling dielectric 150 formed in the first trench 121 in a fully filled manner. The filling dielectric 150 may include silicon oxide, silicon nitride, and / or silicon oxynitride, etc., deposited in the first trench 121. The filling dielectric 150 may also be configured to include a first dielectric layer 151 and a high-k dielectric layer 152, which are sequentially formed in the first trench 121. Alternatively, the filling dielectric 150 may also be configured to include a first dielectric layer 151, a high-k dielectric layer 152, and a second dielectric layer 153, which are sequentially formed in the first trench 121. Both the first dielectric layer 151 and the second dielectric layer 153 may be silicon oxide, silicon nitride, or silicon oxynitride, etc., deposited in the first trench 121. The first dielectric layer 151 contacts the surface of the second semiconductor 142, that is, the first dielectric layer 151 contacts the surface of the fourth semiconductor material layer 142b. The material of the high-k dielectric layer 152 may be hafnium oxide, titanium oxide or lanthanum oxide, and may also include tantalum oxide, strontium titanium oxide, hafnium silicon oxide and / or zirconium oxide.

[0058] Please continue to see Figure 8 and Figure 9 For example, as a front-illuminated image sensor, it may further include a metal interconnection structure 160 formed at the photoelectric sensing region 120, the isolation region 130 and the first surface 110a of the substrate 110, and a color filter layer 170 and a microlens layer 180 formed on the side of the metal interconnection structure 160 facing away from the substrate 110.

[0059] The metal interconnect structure 160 may include multiple patterned dielectric layers and conductive layers that provide interconnections (e.g., wiring) between different doped components, circuits, and input / outputs of the image sensor. The metal interconnect structure 160 includes an interlayer dielectric layer 161 and a multilayer interconnect structure 162. The multilayer interconnect structure 162 may include contacts, vias, and metal lines. The multilayer interconnect structure 162 may include conductive materials such as aluminum, aluminum / silicon / copper alloy, copper, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof. The metal interconnect structure 160 may be formed by chemical vapor deposition, physical vapor deposition, or other suitable processes. It will be understood that Figure 8 The multi-layer interconnect structure 162 is shown for illustration purposes only, and the actual location and configuration of metal lines and vias / contacts may vary depending on design requirements and manufacturing considerations.

[0060] The color filter layer 170 includes a plurality of color filters 171 configured to direct incident radiation thereon and therethrough. The color filters 171 include a dye-based (or pigment-based) polymer or resin for filtering incident radiation within specific wavelength bands corresponding to a color spectrum (e.g., red, green, and blue). A microlens layer 180 having a plurality of microlenses 181 is formed above the color filter layer 170. The microlenses 181 direct and concentrate incident radiation toward specific radiation-concentrating areas within the image sensor, such as the photosensitive region 120. The microlenses 181 can be positioned in various arrangements and have various shapes depending on the refractive index of the material used for the microlenses 181 and their distance from the image sensor surface.

[0061] Based on the embodiments described above, the image sensor of the present invention has the following unexpected benefits: (1) The first trench in the photoelectric sensing region conformally forms a first semiconductor and a second semiconductor of a different doping type. The profiles of the first and second semiconductors are identical to the profile of the first trench, forming multiple light-absorbing surfaces in different orientations and directions. This creates a natural light-trapping structure that increases light absorption, eliminates the fabrication steps for the light-trapping structure, reduces production costs, and addresses the issue of high plasma damage to the substrate associated with traditional light-trapping structures. Furthermore, the natural light-trapping structure can reduce dark current. (2) The first and second semiconductors are formed on the substrate using epitaxial growth, addressing the issue of substrate damage caused by ion implantation. (3) Both the first and second trenches can be U-shaped. Compared to rectangular trenches in conventional techniques, at the same depth, this reduces the area of ​​substrate damage caused by etching. Furthermore, the U-shaped trenches provide more surfaces in different orientations and directions, increasing the light-absorbing surfaces of the natural light-trapping structure. Furthermore, the U-shaped trenches increase the cross-sectional area of ​​the first and second semiconductors, thereby increasing the full well capacity of the image sensor. (4) A first semiconductor and a second semiconductor are formed in the second trench of the isolation region in the same or similar manner as the first trench, so that the first semiconductor and the second semiconductor of the isolation region form a pnp structure or an npn structure. The pnp structure or the npn structure has the function of isolating the signals of two adjacent photoelectric sensing regions, and its isolation performance is superior to that of an isolation structure formed by filling with an isolation dielectric. (5) The second trench of the isolation region, the first semiconductor, and the second semiconductor can be formed simultaneously in the same step as the first trench, the first semiconductor, and the second semiconductor of the photoelectric sensing region, thereby reducing the number of steps in the manufacture of the image sensor, optimizing the manufacturing process of the image sensor, and making the manufacture of the image sensor more efficient. (6) The doping type of the first semiconductor in contact with the first surface of the substrate is configured to be the same as the doping type of the substrate. When the epitaxial layer of the substrate is a p-epitaxial layer, the first semiconductor of the same doping type has the effect of compounding the free electrons on the surface of the p-epitaxial layer, which can reduce the dark current; when the epitaxial layer of the substrate is an n-epitaxial layer, the first semiconductor of the same doping type has the effect of repelling the free electrons of the n-epitaxial layer, preventing the free electrons of the n-epitaxial layer from generating crosstalk, which can reduce the dark current.(7) The first semiconductor is configured as a heavily doped first semiconductor material layer and a lightly doped second semiconductor material layer, formed continuously or sequentially on the first surface of the substrate; the second semiconductor is configured as a lightly doped third semiconductor material layer and a heavily doped fourth semiconductor material layer, formed continuously or sequentially on the surface of the first semiconductor; the lightly doped second and third semiconductor material layers in the intermediate layers can increase the pn junction width of the photoelectric sensing region, increase the light-receiving area, and thus improve the performance of the photoelectric sensing region. The width of the pnp structure or npn structure of the isolation region can also be increased, further enhancing isolation performance. (8) The isolation region is isolated by the heavily doped first semiconductor material layer and the heavily doped fourth semiconductor material layer, further enhancing the isolation performance of the isolation region.

[0062] See Figures 1 to 8 , Figure 1 A process flow chart of a method for manufacturing the front-illuminated image sensor described above is shown. Figures 2 to 8 A schematic cross-sectional diagram showing the various stages of manufacturing a front-illuminated image sensor.

[0063] In the illustrated embodiment, the method for manufacturing the image sensor includes the following steps:

[0064] S100 , providing a substrate 110 .

[0065] The substrate 110 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate 110 can be any of the following materials: a silicon substrate, a silicon-germanium substrate, a silicon-germanium-carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, the substrate 110 can be a layered substrate such as silicon-on-insulator or silicon-germanium-on-insulator.

[0066] The substrate 110 is a silicon substrate doped with a p-type dopant, such as boron, and thus functions as a p-type substrate. Alternatively, the substrate 110 may comprise another suitable semiconductor material. For example, the substrate 110 may be a silicon substrate doped with an n-type dopant, such as phosphorus or arsenic, and thus functions as an n-type substrate. Furthermore, the substrate 110 may comprise other elemental semiconductors, such as germanium and diamond. The substrate 110 may alternatively comprise a compound semiconductor and / or an alloy semiconductor.

[0067] S200 , forming a plurality of first trenches 121 spaced apart from each other and second trenches 131 staggered with the plurality of first trenches 121 on the first surface 110 a of the substrate 110 .

[0068] The first trench 121 can be configured as a U-shaped trench, or as a rectangular trench, a trapezoidal trench, or other suitable shape. The U-shaped trench, in addition to having a bottom and side surfaces, also has a curved surface that smoothly transitions between the bottom and side surfaces. Combined with the first semiconductor 141 and the second semiconductor 142 conformally distributed on its surface (bottom, side, and curved surface), a natural light-trapping structure can be formed, eliminating the need for light-trapping structure fabrication steps and saving raw materials.

[0069] The second groove 131 can be configured as a U-shaped groove having the same or similar structure as the first groove 121, or can be configured as a rectangular groove, a trapezoidal groove, or other suitable shapes. The width of the second groove 131 can be configured to be smaller than the width of the first groove 121, and the depth of the second groove 131 can be configured to be greater than the depth of the first groove 121.

[0070] S300 , continuously or sequentially growing a doped first semiconductor 141 and a second semiconductor 142 on the first surface 110 a of the substrate 110 , surfaces of the first trenches 121 , and surfaces of the second trenches 131 .

[0071] The first trench 121 and the first and second semiconductors 141 and 142 grown therein constitute the photoelectric sensing region 120. The first and second semiconductors 141 and 142 in the first trench 121 are both formed continuously or sequentially on the surface of the first trench 121 in a conformal manner. The second trench 131 and the first and second semiconductors 141 and 142 grown therein constitute the isolation region 130. The first and second semiconductors 141 and 142 in the second trench 131 can both be formed continuously or sequentially on the surface of the second trench 131 in a conformal manner; alternatively, the first semiconductor 141 can be formed conformally on the surface of the second trench 131, and the second semiconductor 142 can be grown on the surface of the first semiconductor 141 and fully fill the second trench 131.

[0072] The first semiconductor 141 can be configured as a first semiconductor 141 having the same doping type as the substrate 110, such as a p-type semiconductor or an n-type semiconductor. The first semiconductor 141 includes a heavily doped first semiconductor material layer 141a and a lightly doped second semiconductor material layer 141b, which are epitaxially grown continuously or sequentially in a conformal manner on the first surface 110a of the substrate 110, the surfaces of the first trenches 121, and the surfaces of the second trenches 131.

[0073] The second semiconductor 142 is configured as a second semiconductor 142 having a different doping type from the first semiconductor 141, such as an n-type semiconductor or a p-type semiconductor. The second semiconductor 142 includes a lightly doped third semiconductor material layer 142a and a heavily doped fourth semiconductor material layer 142b, which are epitaxially grown continuously or sequentially in a conformal manner on the surface of the first semiconductor 141.

[0074] In the illustrated embodiment, the image sensor further includes the following additional manufacturing processes:

[0075] S400 , forming a filling medium 150 in the first trench 121 to fully fill the first trench 121 .

[0076] The filling dielectric 150 may be configured as silicon oxide, silicon nitride, and / or silicon oxynitride, etc., deposited in the first trench 121. The filling dielectric 150 may also be configured to include a first dielectric layer 151 and a high-k dielectric layer 152 sequentially formed in the first trench 121. Alternatively, the filling dielectric 150 may also be configured to include a first dielectric layer 151, a high-k dielectric layer 152, and a second dielectric layer 153 sequentially formed in the first trench 121.

[0077] S500 , blocking the connection between the first semiconductor 141 belonging to the isolation region 130 and the first semiconductor 141 belonging to the photodiode region, and blocking the connection between the second semiconductor 142 belonging to the isolation region 130 and the second semiconductor 142 belonging to the photoelectric sensing region 120 .

[0078] S600 , forming a metal interconnection structure 160 in the isolation region 130 , the photoelectric sensing region 120 and the first surface 110 a of the substrate 110 .

[0079] The metal interconnect structure 160 includes multiple patterned dielectric layers and conductive layers that provide interconnections (e.g., wiring) between the various doped components, circuits, and input / outputs of the image sensor. The metal interconnect structure 160 includes an interlayer dielectric layer 161 and a multilayer interconnect structure 162. The multilayer interconnect structure 162 may include contacts, vias, and metal lines. The multilayer interconnect structure 162 may include conductive materials such as aluminum, an aluminum / silicon / copper alloy, copper, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof.

[0080] S700 , forming a color filter layer 170 and a microlens layer 180 on a side of the metal interconnect structure 160 facing away from the substrate 110 .

[0081] The color filter layer 170 includes a plurality of color filters 171 configured to direct incident radiation thereon and therethrough. The color filters 171 include a dye-based (or pigment-based) polymer or resin for filtering incident radiation within specific wavelength bands corresponding to a color spectrum (e.g., red, green, and blue). A microlens layer 180 having a plurality of microlenses 181 is formed above the color filter layer 170. The microlenses 181 direct and concentrate incident radiation toward specific radiation-concentrating areas within the image sensor, such as the photosensitive region 120. The microlenses 181 can be positioned in various arrangements and have various shapes depending on the refractive index of the material used for the microlenses 181 and their distance from the image sensor surface.

[0082] The following combination Figures 2 to 8 The detailed production steps of each stage are explained exemplarily.

[0083] See Figure 2 , step S100 includes the following sub-steps:

[0084] S101 , providing a substrate 111 .

[0085] According to this embodiment, substrate 111 is configured as a p-type doped silicon substrate 111, such as a boron-doped substrate. However, this is not a limitation of the present invention. For example, substrate 111 may be configured as an n-type doped silicon substrate 111. Substrate 111 may also include other elemental semiconductors such as germanium and diamond. Substrate 111 may also optionally include a compound semiconductor and / or an alloy semiconductor. Substrate 111 may be made of any known material.

[0086] S102 , epitaxially growing an epitaxial layer 112 on the surface of the substrate 111 .

[0087] An in-situ doping process is performed to deposit a lightly doped epitaxial layer 112 having the same doping type as the substrate 111 on the surface of the substrate 111. For example, a lightly doped p-epitaxial layer having the same doping type as the p-type substrate 111 is deposited on the surface of the p-type substrate 111, or a lightly doped n-epitaxial layer having the same doping type as the n-type substrate 111 is deposited on the surface of the n-type substrate 111.

[0088] It should be understood that the epitaxial layer 112 can be formed on the surface of the substrate 111 using any known process. For example, a chemical vapor deposition process can be used to grow the lightly doped epitaxial layer 112 on the surface of the substrate 111.

[0089] See Figures 3a to 3c , exemplarily, step S200 may include the following sub-steps:

[0090] S201 , forming a protection layer 210 on the surface of the epitaxial layer 112 .

[0091] The protective layer 210 may include multiple film layers. For example, the protective layer 210 may include a pad oxide layer 211 and a pad nitride layer 212 sequentially formed on the surface of the epitaxial layer 112. The pad oxide layer 211, as a buffer layer, can improve the stress between the substrate 110 and the subsequently formed pad nitride layer 212. The pad oxide layer 211 is, for example, a dense silicon oxide material. The pad oxide layer 211 can be formed on the surface of the epitaxial layer 112 by methods such as dry oxidation, wet oxidation, or in-situ water vapor growth. The pad nitride layer 212 is, for example, a silicon nitride material. The pad nitride layer 212 can be used as a hard mask during trench etching to protect the substrate 110 from damage. The pad nitride layer 212 can be formed on the surface of the pad oxide layer 211 by methods such as low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition.

[0092] S202 , forming a patterned photoresist layer 220 on the surface of the protection layer 210 .

[0093] The patterned photoresist layer 220 is formed with a plurality of openings 221 corresponding to the isolation region 130 and the photoelectric sensing region 120 . Each opening 221 exposes the surface of the protection layer 210 to the outside.

[0094] S203 , using the patterned photoresist layer 220 as a mask, sequentially etching the pad oxide layer 211 , the pad nitride layer 212 and a portion of the substrate 110 (a portion of the epitaxial layer 112 ) to form a first trench 121 and a second trench 131 .

[0095] S204 , after the first trench 121 and the second trench 131 are formed, the patterned photoresist layer 220 and the protection layer 210 are removed.

[0096] See Figure 4 , exemplarily, step S300 can be implemented by the following sub-steps:

[0097] S301. A first semiconductor material layer 141a is grown on the surface of the epitaxial layer 112. The surface of the epitaxial layer 112 is defined as the surface of the epitaxial layer 112 in a broad sense, including the surface of the first trench 121, the surface of the second trench 131, and the surface of the region between the trenches on the epitaxial layer 112 (the surface of the epitaxial layer 112 in a narrow sense). The first semiconductor material layer 141a is formed conformally along the surface of the epitaxial layer 112. The first semiconductor material layer 141a is a heavily doped material layer of the same doping type as the substrate 110, for example, a p+ semiconductor material layer similar to a p- epitaxial layer of a p-type substrate, or an n+ semiconductor material layer similar to an n- epitaxial layer of an n-type substrate.

[0098] S302 , conformally growing a second semiconductor material layer 141 b on the surface of the first semiconductor material layer 141 a .

[0099] The second semiconductor material layer 141 b is a lightly doped material layer having the same doping type as the first semiconductor material layer 141 a , for example, a p- semiconductor material layer corresponding to a p+ semiconductor material layer, or an n- semiconductor material layer corresponding to an n+ semiconductor material layer.

[0100] S303 , conformally growing a third semiconductor material layer 142 a on the surface of the second semiconductor material layer 141 b .

[0101] The third semiconductor material layer 142a is a lightly doped material layer with a different doping pattern from that of the first semiconductor material layer 141a, for example, an n-semiconductor material layer grown on the surface of a p-semiconductor material layer (the second semiconductor material layer 141b), or a p-semiconductor material layer grown on the surface of an n-semiconductor material layer (the second semiconductor material layer 141b).

[0102] S304 , growing a fourth semiconductor material layer 142 b on the surface of the third semiconductor material layer 142 a .

[0103] The fourth semiconductor material layer 142b is a heavily doped material layer of the same doping type as the third semiconductor material layer 142a, for example, an n+ semiconductor material layer corresponding to the n- semiconductor material layer (third semiconductor material layer 142a), or a p+ semiconductor material layer corresponding to the p- semiconductor material layer (third semiconductor material layer 142a).

[0104] The fourth semiconductor material layer located in the first trench 121 is conformally grown on the surface of the third semiconductor material layer 142 a. The fourth semiconductor material layer 142 b located in the second trench 131 can be conformally grown on the surface of the third semiconductor material layer 142 a or can be fully filled in the second trench 131.

[0105] Based on steps S301 to S304, for a p-type substrate, a p+ semiconductor material layer, a p- semiconductor material layer, an n- semiconductor material layer, and an n+ semiconductor material layer are continuously or sequentially grown on the surface of the p- epitaxial layer. For an n-type substrate, an n+ semiconductor material layer, an n- semiconductor material layer, a p- semiconductor material layer, and a p+ semiconductor material layer are continuously or sequentially grown on the surface of the n- epitaxial layer.

[0106] The first semiconductor material layer 141a, the second semiconductor material layer 141b, the third semiconductor material layer 142a, and the fourth semiconductor material layer 142b can be grown continuously or sequentially on the surface of the epitaxial layer 112 by any known method. For example, in some embodiments, solid materials can be used to perform dopant diffusion to form semiconductor material layers with different doping types and doping concentrations. For another example, in some embodiments, vapor phase doping can be used to form semiconductor material layers with different doping types and doping concentrations.

[0107] See Figure 5 , illustratively, step S400 can be implemented by the following sub-steps:

[0108] S401 , growing a first dielectric layer 151 on the surface of the fourth semiconductor material layer 142 b .

[0109] The first dielectric layer 151 can be configured as a material layer such as silicon oxide, silicon nitride, or silicon oxynitride. Based on the above implementation steps, the dielectric layer corresponding to the first trench 121 is still distributed in a conformal manner on the surface of the fourth semiconductor material layer 142b in the first trench 121, that is, the first dielectric layer 151 in the first trench 121 is distributed in a U-shape.

[0110] S402 , growing a high-k dielectric layer 152 on the surface of the first dielectric layer 151 .

[0111] The high-k dielectric layer 152 may be made of hafnium oxide, titanium oxide, or lanthanum oxide, and may also include tantalum oxide, strontium titanium oxide, hafnium silicon oxide, and / or zirconium oxide. The high-k dielectric layer 152 corresponding to the first trench 121 is still conformally distributed on the surface of the first dielectric layer 151 within the first trench 121, i.e., the first high-k dielectric layer 152 is distributed in a U-shaped manner.

[0112] S403 , growing a second dielectric layer 153 on the surface of the high-k dielectric layer 152 .

[0113] The second dielectric layer 153 can be made of the same or similar material as the first dielectric layer 151, such as silicon oxide, silicon nitride, or silicon oxynitride. The second dielectric layer 153 corresponding to the first trench 121 completely fills the first trench 121, and its height is consistent with the height of the first dielectric layer 151 at the surface of the narrow epitaxial layer 112 and in the second trench 131, thereby completely covering the high-k dielectric layer 152 in all areas (the first trench 121, the second trench 131, and the surface of the narrow epitaxial layer 112).

[0114] The first dielectric layer 151, the high-k dielectric layer 152, and the second dielectric layer 153 may be grown continuously or sequentially on the surface of the epitaxial layer 112 by any known method. For example, they may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, electroplating, electroless plating, or any combination thereof.

[0115] See Figure 6 In step S500, a thinning process is performed to thin the substrate 110 from the first surface 110a. The thinning process can be a mechanical grinding process, such as a chemical mechanical polishing process. During the mechanical grinding process, a sufficient amount of substrate material can be removed from the substrate 110 to thin the substrate 110 from the first surface 110a to the second surface 110b. As a result, the first semiconductor 141 and the second semiconductor 142 in the region between the isolation region 130 and the photoelectric sensing region 120 are completely removed, exposing the surface of the epitaxial layer 112 in a narrow sense, and disconnecting the first semiconductor 141 and the second semiconductor 142 in the isolation region 130 from the first semiconductor 141 and the second semiconductor 142 in the photoelectric sensing region 120.

[0116] See Figure 7 In step S600 , a metal interconnection structure 160 is fabricated by growing a plurality of interlayer dielectric layers 161 and a multilayer interconnection structure 162 on the surfaces of the epitaxial layer 112 , the photoelectric sensing region 120 , and the isolation region 130 .

[0117] The metal interconnect structure 160 may include multiple patterned dielectric layers and conductive layers that provide interconnections (e.g., wiring) between the various doped components, circuits, and input / outputs of the image sensor. The metal interconnect structure 160 includes an interlayer dielectric layer 161 and a multilayer interconnect structure 162. The multilayer interconnect structure 162 may include contacts, vias, and metal lines. The multilayer interconnect structure 162 may include conductive materials such as aluminum, an aluminum / silicon / copper alloy, copper, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof. The metal interconnect structure 160 may be formed by chemical vapor deposition, physical vapor deposition, or other suitable processes.

[0118] Based on the embodiments described above, the method for fabricating a pattern sensor of the present invention has the following unexpected benefits: (1) The fabrication process of the photoelectric sensing region is modified, whereby the photoelectric sensing region is formed by growing a first semiconductor and a second semiconductor within the first trench, thereby preventing damage to the substrate. (2) Both the first semiconductor and the second semiconductor are conformally grown on the surface of the first trench, forming a plurality of light-absorbing surfaces located in different orientations and directions, thereby forming a natural light-trapping structure to increase light absorption. This eliminates the fabrication steps of the light-trapping structure, reduces production costs, and solves the problem of high plasma damage to the substrate caused by traditional light-trapping structures. Furthermore, the natural light-trapping structure can reduce dark current. (3) The fabrication process of the isolation region is modified, so that the first trench, first semiconductor, and second semiconductor of the isolation region are fabricated in the same process as the photoelectric sensing region. Specifically, the first and second trenches are etched simultaneously, and the first semiconductor and the second semiconductor are grown within the first and second trenches simultaneously. This eliminates the need for separate fabrication of the isolation region and the photoelectric sensing region, thereby optimizing the process flow and improving fabrication efficiency.

[0119] Based on the image sensor and its manufacturing method provided in the above embodiment, the present invention also provides a camera module and an electronic device having the camera module. The camera module includes the image sensor described above or the image sensor obtained by the manufacturing method of the image sensor described above. The electronic device can be any electronic device on the market that has a camera module. The electronic device can be a communication electronic device with a camera module, such as a handheld phone, a wearable communication device, etc. The electronic device can be a portable computer with a camera module, such as a tablet, a notebook, etc. Alternatively, the electronic device can be various camera devices, monitoring devices, etc.

[0120] In summary, the camera module and the electronic device having the camera module provided by the present invention optimize the internal structure of the photoelectric sensing area and the isolation area of ​​the image sensor, thereby optimizing the internal structure of the camera module. The unique pnp or npn structure of the isolation area effectively prevents signal crosstalk between two adjacent photoelectric sensing areas, thereby improving the image quality of the camera module and the electronic device.

[0121] The above embodiments merely represent preferred embodiments of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. An image sensor, characterized in that: include: substrate; A plurality of photoelectric sensing regions are formed on the first surface of the substrate in a spaced-apart manner, wherein the photoelectric sensing regions include a first trench formed on the first surface of the substrate, a first semiconductor formed conformally on the surface of the first trench and having a doping factor, and a second semiconductor formed conformally on the surface of the first semiconductor and having a doping factor, wherein the second semiconductor has a different doping type from the first semiconductor. as well as A plurality of isolation regions and a plurality of photoelectric sensing regions are formed on the first surface of the substrate in an alternating manner, wherein the isolation regions have a second trench formed on the first surface of the substrate, the first semiconductor formed conformally on the surface of the second trench, and the second semiconductor formed on the surface of the first semiconductor.

2. The image sensor according to claim 1, wherein: The first semiconductor is configured as a p-type semiconductor having p-type doping, and the second semiconductor is configured as an n-type semiconductor having n-type doping; or the first semiconductor is configured as an n-type semiconductor having n-type doping, and the second semiconductor is configured as a p-type semiconductor having p-type doping; The second semiconductor located in the second trench fully fills the second trench.

3. The image sensor according to claim 1, wherein: The first semiconductor includes a first semiconductor material layer formed on a surface of the first trench in a conformal manner and a second semiconductor material layer formed on a surface of the first semiconductor material layer in a conformal manner, wherein the first semiconductor material layer is configured as a heavily doped first semiconductor material layer, and the second semiconductor material layer is configured as a lightly doped second semiconductor material layer; The second semiconductor includes a third semiconductor material layer formed on the surface of the second semiconductor material layer in a conformal manner and a fourth semiconductor material layer formed on the surface of the third semiconductor material layer, the third semiconductor material layer is configured as a lightly doped third semiconductor material layer, and the fourth semiconductor material layer is configured as a heavily doped fourth semiconductor material layer.

4. The image sensor according to claim 3, wherein: The fourth semiconductor material layer located in the second trench fully fills the second trench.

5. The image sensor according to any one of claims 1 to 4, wherein: A filling medium is formed in the first groove and is fully filled therein; The first groove is configured as a U-shaped groove; or the first groove and the second groove are both configured as U-shaped grooves.

6. The image sensor according to any one of claims 1 to 4, wherein: The substrate has a base and an epitaxial layer formed on the surface of the base; the plurality of photoelectric sensing regions and the plurality of isolation regions are all formed on the surface of the epitaxial layer, and the doping type of the first semiconductor is the same as the doping type of the epitaxial layer.

7. A method for manufacturing an image sensor, characterized in that: The following steps are involved: providing a substrate; Forming a plurality of first trenches spaced apart from each other and second trenches interlaced with the plurality of first trenches on a first surface of the substrate; A first semiconductor and a second semiconductor with doping are continuously or sequentially grown on the first surface of the substrate, the surfaces of several first trenches, and the surfaces of several second trenches, wherein the second semiconductor has a different doping type from the first semiconductor; wherein the first trench, the first semiconductor and the second semiconductor grown therein constitute a photoelectric sensing region, and the first semiconductor and the second semiconductor in the first trench are both continuously or sequentially grown on the surface of the first trench in a conformal manner; the second trench, the first semiconductor and the second semiconductor grown therein constitute an isolation region, and the first semiconductor and the second semiconductor in the second trench are both continuously or sequentially grown on the surface of the second trench in a conformal manner, or the first semiconductor is conformally grown on the surface of the second trench, and the second semiconductor is grown on the surface of the first semiconductor and fills the second trench.

8. The method for manufacturing an image sensor according to claim 7, wherein: The following steps are also included: The connection between the first semiconductor belonging to the isolation region and the first semiconductor belonging to the photodiode region is blocked, and the connection between the second semiconductor belonging to the isolation region and the second semiconductor belonging to the photoelectric sensing region is blocked.

9. A camera module, characterized in that: An image sensor comprising the image sensor according to any one of claims 1 to 6; or an image sensor obtained by the method for manufacturing the image sensor according to any one of claims 7 to 8.

10. An electronic device, characterized in that: Including the camera module as described in claim 9.

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