Display panel, display device and preparation method of display panel

Abstract

The embodiment of the invention provides a display panel, a display device and a preparation method of the display panel, and the display panel comprises a substrate which is provided with a first side; the light-emitting unit is arranged on the first side, and the light-emitting unit comprises a first hole blocking layer; the photoelectric sensing unit is arranged on the first side, the photoelectric sensing unit is configured to receive optical signals and generate corresponding electric signals according to the optical signals, the photoelectric sensing unit comprises a photoelectric conversion layer, a buffer layer and a second hole blocking layer, the buffer layer is arranged on the side, away from the substrate, of the photoelectric conversion layer, and the second hole blocking layer is arranged on the substrate. The second hole blocking layer is arranged on the side, away from the photoelectric conversion layer, of the buffer layer; wherein the first hole barrier layer and the second hole barrier layer are made of the same material, the buffer layer has first conductivity, the second hole barrier layer has second conductivity, and the first conductivity is greater than the second conductivity. According to the embodiment of the invention, by adding the buffer layer, the performance of the photoelectric detector of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display panel, a display device, and a method for manufacturing a display panel. Background Art

[0002] Biometrics plays an important role in smartphones and tablets. The common existing technologies include facial recognition and fingerprint recognition, among which fingerprint recognition includes ultrasonic fingerprint, capacitive fingerprint and optical fingerprint. Among them, optical fingerprint has the advantages of high resolution, high sensitivity and can be used for life and health detection. Summary of the invention

[0003] The embodiments of the present application provide a display panel, a display device, and a method for manufacturing a display panel, aiming to improve the performance of a photodetector in a display panel.

[0004] An embodiment of the first aspect of the present application provides a display panel, which includes: a substrate having a first side; a light-emitting unit arranged on the first side, the light-emitting unit including a first hole blocking layer; a photoelectric sensing unit arranged on the first side, the photoelectric sensing unit being configured to receive a light signal and generate a corresponding electrical signal according to the light signal, the photoelectric sensing unit including a photoelectric conversion layer, a buffer layer and a second hole blocking layer, the buffer layer being arranged on a side of the photoelectric conversion layer away from the substrate, and the second hole blocking layer being arranged on a side of the buffer layer away from the photoelectric conversion layer; wherein the first hole blocking layer and the second hole blocking layer are made of the same material, the buffer layer has a first electrical conductivity, the second hole blocking layer has a second electrical conductivity, and the first electrical conductivity is greater than the second electrical conductivity.

[0005] According to an implementation of the first aspect of the present application, the material of the buffer layer includes metal elements.

[0006] According to any of the aforementioned embodiments of the first aspect of the present application, the first hole blocking layer and the second hole blocking layer are an integrated structure.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the buffer layer includes a first buffer layer, and the material of the first buffer layer includes metal.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the first buffer layer is not less than 0.1 nanometers, and the thickness of the first buffer layer is not greater than 5 nanometers.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the first buffer layer is not less than 0.5 nanometers, and the thickness of the first buffer layer is not greater than 2 nanometers.

[0010] According to any of the foregoing embodiments of the first aspect of the present application, the first buffer layer includes a first sub-layer and a second sub-layer. The second sub-layer is located on the side of the first sub-layer away from the photoelectric conversion layer, and the thickness of the first sub-layer is less than the thickness of the second sub-layer.

[0011] According to any of the foregoing embodiments of the first aspect of the present application, the work function of the metal material in the first sub-layer is greater than the work function of the metal material in the second sub-layer.

[0012] According to any of the foregoing embodiments of the first aspect of the present application, the work function of the metal material in the first sub-layer is greater than 3.5 electron volts, and the work function of the metal material in the second sub-layer is less than or equal to 3.5 electron volts.

[0013] According to any of the foregoing embodiments of the first aspect of the present application, the metal material in the first sub-layer includes aluminum, and the metal material in the second sub-layer includes ytterbium.

[0014] According to any of the foregoing embodiments of the first aspect of the present application, the buffer layer further includes a second buffer layer, and the material of the second buffer layer includes an electron transport material.

[0015] According to any of the foregoing embodiments of the first aspect of the present application, the second buffer layer is located between the first sub-layer and the second sub-layer, or the second buffer layer is located between the first sub-layer and the photoelectric conversion layer.

[0016] According to any of the foregoing embodiments of the first aspect of the present application, the light-emitting unit further includes a light-emitting layer and an electron transport layer. The first hole blocking layer is disposed on the side of the light-emitting layer away from the substrate, and the electron transport layer is disposed on the side of the first hole blocking layer away from the light-emitting layer. The material of the second buffer layer is the same as the material of the electron transport layer.

[0017] According to any of the foregoing embodiments of the first aspect of the present application, the electron transport material in the second buffer layer has a phenanthroline structure.

[0018] According to any of the foregoing embodiments of the first aspect of the present application, the electron transport material includes at least one of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline, 4,7-diphenyl-1,10-phenanthroline, and 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline.

[0019] According to any of the foregoing embodiments of the first aspect of the present application, the thickness of the second buffer layer is not less than 0.5 nanometers and not greater than 10 nanometers.

[0020] According to any of the foregoing embodiments of the first aspect of the present application, the buffer layer includes a third buffer layer, and the material of the third buffer layer includes a host material and an n-type dopant. The n-type dopant includes a metal element.

[0021] According to any of the foregoing embodiments of the first aspect of the present application, the material of the optoelectronic conversion layer includes a donor material and an acceptor material, and the host material includes at least one of an electron transport material, the material of the second hole blocking layer, and an acceptor material.

[0022] According to any of the foregoing embodiments of the first aspect of the present application, the electron transport material has a phenanthroline structure.

[0023] According to any of the foregoing embodiments of the first aspect of the present application, the electron transport material includes at least one of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline, 4,7-diphenyl-1,10-phenanthroline, and 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline.

[0024] According to any of the foregoing embodiments of the first aspect of the present application, the third buffer layer includes a plurality of sub-layers, and in the direction away from the substrate of the optoelectronic conversion layer, the absolute value of the LUMO energy level of the host material of each sub-layer gradually increases.

[0025] According to any of the foregoing embodiments of the first aspect of the present application, the n-type dopant includes at least one of a metal compound, a metal oxide, and a metal with a low work function.

[0026] According to any of the foregoing embodiments of the first aspect of the present application, the work function of the metal with a low work function is less than 3.5 electron volts, and the metal with a low work function includes at least one of ytterbium, lithium, calcium, and cesium.

[0027] According to any of the foregoing embodiments of the first aspect of the present application, the metal oxide includes at least one of lithium carbonate and cesium carbonate, and the metal compound includes at least one of lithium amide and W2(hpp)4.

[0028] According to any of the foregoing embodiments of the first aspect of the present application, the thickness of the third buffer layer is not less than 0.5 nanometers and not greater than 20 nanometers.

[0029] According to any of the foregoing embodiments of the first aspect of the present application, the thickness of the third buffer layer is not less than 1 nanometer and not greater than 10 nanometers.

[0030] According to any of the foregoing embodiments of the first aspect of the present application, the n-type dopant has a first amount of substance, the material of the third buffer layer has a second amount of substance, and the ratio of the first amount of substance to the second amount of substance is not less than 0.1% and not greater than 10%.

[0031] According to any of the foregoing embodiments of the first aspect of the present application, the ratio of the first amount of substance to the second amount of substance is not less than 0.5% and not greater than 10%.

[0032] According to any of the aforementioned embodiments of the first aspect of the present application, the buffer layer further includes a fourth buffer layer, the material of the fourth buffer layer includes at least one of a metal and a metal oxide, and the fourth buffer layer is arranged on a side of the third buffer layer facing toward or away from the photoelectric conversion layer.

[0033] According to any of the aforementioned embodiments of the first aspect of the present application, the buffer layer further includes a fourth buffer layer, the material of the fourth buffer layer includes at least one of a metal and a metal oxide, and the fourth buffer layer is arranged on a side of the third buffer layer facing toward or away from the photoelectric conversion layer.

[0034] According to any of the aforementioned embodiments of the first aspect of the present application, the fifth buffer layer is formed by at least one of lithium carbonate, cesium carbonate, lithium nitride, and lithium fluoride.

[0035] According to any of the aforementioned embodiments of the first aspect of the present application, the material of the fifth buffer layer includes an alkali metal with a low work function, and the alkali metal with a low work function includes lithium.

[0036] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the fifth buffer layer is not less than 0.5 nanometers, and the thickness of the fifth buffer layer is not greater than 5 nanometers.

[0037] According to any of the aforementioned embodiments of the first aspect of the present application, the buffer layer also includes a sixth buffer layer, which is arranged on one side of the fifth buffer layer, and the material of the sixth buffer layer includes a metal with a high work function, and the work function of the metal with a high work function is greater than 4.0 electron volts.

[0038] According to any of the aforementioned embodiments of the first aspect of the present application, the metal with a high work function includes at least one of aluminum and silver.

[0039] According to any of the aforementioned embodiments of the first aspect of the present application, the sixth buffer layer is disposed on a side of the fifth buffer layer facing the photoelectric conversion layer.

[0040] According to any of the aforementioned embodiments of the first aspect of the present application, the thickness of the sixth buffer layer is not less than 0.5 nanometers, and the thickness of the sixth buffer layer is not greater than 5 nanometers.

[0041] An embodiment of the second aspect of the present application further provides a display device, comprising a display panel provided by any of the embodiments of the first aspect above.

[0042] The third aspect of the present application also provides a method for preparing a display panel, including:

[0043] Preparing a photoelectric conversion layer of a photoelectric sensing unit on the first side of the substrate, wherein the photoelectric sensing unit is configured to receive a light signal and generate a corresponding electrical signal according to the light signal;

[0044] A buffer layer is prepared on the side of the optoelectronic conversion layer facing away from the substrate, where the buffer layer has a first conductivity.

[0045] A first hole blocking layer of the light-emitting unit is prepared on the first side, and a second hole blocking layer is prepared on the side of the buffer layer facing away from the optoelectronic conversion layer. The materials of the first hole blocking layer and the second hole blocking layer are the same. The second hole blocking layer has a second conductivity, and the first conductivity is greater than the second conductivity.

[0046] In the display panel provided by the embodiment of the present application, the display panel includes a substrate, a light-emitting unit, and an optoelectronic sensing unit. The light-emitting unit is used to realize the light-emitting display of the display panel, and the optoelectronic sensing unit is used to realize the optoelectronic sensing function of the display panel. Optionally, the light-emitting unit further includes a light-emitting layer. The first hole blocking layer is used to block the movement of holes from the light-emitting layer in the direction away from the substrate, improving the light-emitting efficiency. The second hole blocking layer is used to block the movement of holes from the optoelectronic conversion layer in the direction away from the substrate, improving the performance of optoelectronic sensing. A buffer layer is provided between the second hole blocking layer and the optoelectronic conversion layer, and the conductivity of the buffer layer is greater than that of the second hole blocking layer. The potential barrier between the buffer layer and the optoelectronic conversion layer is small, which can reduce the potential barrier between the second hole blocking layer and the optoelectronic conversion layer, improve the electron transport efficiency, and improve the performance of the optoelectronic conversion layer. Therefore, by adding a buffer layer between the optoelectronic conversion layer and the second hole blocking layer in the embodiment of the present application, the performance of the photodetector of the display panel can be improved. Description of the Drawings

[0047] By reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, other features, objects, and advantages of the present application will become more apparent, where the same or similar reference numerals represent the same or similar features.

[0048] Figure 1 is a schematic structural diagram of a display panel provided by a related embodiment;

[0049] Figure 2 is a schematic layer structure diagram of a display panel provided by a related embodiment.

[0050] Figure 3 is a schematic energy level structure diagram of a display panel provided by a related embodiment;

[0051] Figure 4 is a schematic layer structure diagram of a display panel provided by an embodiment of the present application;

[0052] Figure 5 is a schematic energy level structure diagram of a display panel provided by an embodiment of the present application;

[0053] Figure 6 is a schematic layer structure diagram of a display panel provided by another embodiment of the present application;

[0054] Figure 7 It is a schematic energy level structure diagram of a display panel provided by another embodiment of the present application;

[0055] Figure 8 It is a curve graph of the test results of a display panel provided by an embodiment of the present application;

[0056] Figure 9 It is a schematic layer structure diagram of a display panel provided by still another embodiment of the present application;

[0057] Figure 10 It is a schematic energy level structure diagram of a display panel provided by still another embodiment of the present application;

[0058] Figure 11 It is a schematic layer structure diagram of a display panel provided by yet another embodiment of the present application;

[0059] Figure 12 It is a schematic energy level structure diagram of a display panel provided by yet another embodiment of the present application;

[0060] Figure 13 It is a schematic energy level structure diagram of a display panel provided by yet another embodiment of the present application;

[0061] Figure 14 It is a curve graph of the test results of a display panel provided by another embodiment of the present application;

[0062] Figure 15 It is another curve graph of the test results of a display panel provided by another embodiment of the present application;

[0063] Figure 16 It is a schematic energy level structure diagram of a display panel provided by yet another embodiment of the present application;

[0064] Figure 17 It is a schematic energy level structure diagram of a display panel provided by yet another embodiment of the present application;

[0065] Figure 18 It is a schematic energy level structure diagram of a display panel provided by yet another embodiment of the present application;

[0066] Figure 19 It is a schematic energy level structure diagram of a display panel provided by yet another embodiment of the present application;

[0067] Figure 20 It is a schematic layer structure diagram of a display panel provided by yet another embodiment of the present application;

[0068] Figure 21 It is a schematic diagram of the preparation process of a display panel provided by an embodiment of the present application. Detailed implementation manners

[0069] The features and exemplary embodiments of each aspect of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is only provided to provide a better understanding of the present application by showing examples of the present application. In the drawings and the following description, at least some of the well-known structures and technologies are not shown in order to avoid unnecessarily obscuring the present application; and, for clarity, the dimensions of some structures may be exaggerated. In addition, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0070] In the description of the present application, it should be noted that unless otherwise specified, the meaning of "a plurality" is two or more; the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "inner", "outer", etc. is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present application. In addition, terms such as "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0071] The orientation terms appearing in the following description are all the directions shown in the figures and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be directly connected or indirectly connected. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0072] Biometric identification plays an important role in mobile terminals such as smart phones and tablets. In the prior art, the common methods include face recognition and fingerprint recognition. Among them, fingerprint recognition includes ultrasonic fingerprint, capacitive fingerprint, and optical fingerprint, etc. Optical fingerprint has become the mainstream technical means due to its advantages such as high resolution, high sensitivity, and the ability to perform life and health detection.

[0073] Figure 1 For a display panel provided by a related technology Figure 1The transmission path of light is indicated by an arrow. It should be noted that integrating an organic light-emitting diode and a photoelectric sensor together in a panel can achieve a larger integration area and a thinner overall thickness of the device. An organic photodetector (OPD) based on an organic photosensitive material is compatible with the vacuum evaporation process of an organic light-emitting diode (OLED), which is an important direction for integrating fingerprint recognition functions in panels in the future.

[0074] As Figure 2 shown, an OPD generally includes a cathode, an anode, a photoinductive structure (Active layer, or also known as the photosensitive layer), and a carrier layer. It is an optoelectronic device that converts an incident light signal into an electrical signal, while an organic light-emitting diode is a device that converts an electrical signal into a light signal.

[0075] The photoinductive structure in an OPD generally includes two organic materials with staggered energy levels. One of the materials is a donor material, typical donor materials include copper phthalocyanine oligomers (chemical symbol: CuPc), dibutyl phthalate (abbreviation: DBP), etc. The other material is an acceptor material, typical acceptor materials include fullerenes (such as C60 and C70, where C60 is a molecule composed of 60 carbon atoms, C60 is also called buckminsterfullerene, and C70 is a molecule composed of 70 carbon atoms). The working principle of an OPD can include the following steps, namely: the material absorbs light to generate excitons, the excitons diffuse to the donor-acceptor interface, the excitons diffuse to the donor-acceptor interface and undergo charge separation, and the charges are transported and collected. To improve the exciton dissociation efficiency, the donor and acceptor are usually mixed (co-evaporated) together as the photoinductive structure.

[0076] To improve the carrier collection efficiency, a reverse bias voltage, such as -3V, is usually applied to the cathode and anode of the OPD. However, this reverse voltage will also increase the injection of dark current.

[0077] The OPD is usually configured to implement optoelectronic sensing functions. For example, the OPD can be used for image recognition. Further, when the OPD is configured to implement fingerprint recognition, the OPD is required to have high recognition accuracy. Therefore, the OPD is required to have a high signal-to-noise ratio (SNR). It should be noted that in the OPD, the magnitude of the signal-to-noise ratio is related to the external quantum efficiency (EQE). Specifically, the EQE represents the ratio of the number of photo-generated electrons flowing through the device under illumination to the number of photons incident on the device, that is, the ability to convert light into electricity. The EQE is the most basic parameter of the OPD. Therefore, maximizing the EQE is the direction for optimizing the OPD device and improving product performance.

[0078] In the integrated application of the OPD and the OLED, as Figure 3 shown, considering cost and process difficulty, the OPD needs to share some carrier layers with the OLED. Although this integration method is economical, it also reduces the device performance of the OPD. For example, when a hole blocking layer and an electron transport layer of the OLED are disposed on the active layer of the OPD, since the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the hole blocking layer of the OLED is about -3.0 electron volts, while the LUMO energy level of the commonly used acceptor material of the OPD is about -4.0 electron volts, there is a potential barrier of about 1 electron volt between the two, and this potential barrier will significantly affect the extraction of photo-generated electrons and significantly reduce the device EQE.

[0079] To solve the above technical problems, in the integrated application of the OPD and the OLED in the embodiments of the present application, an interface modification film layer is introduced into the OPD device structure to reduce or eliminate the potential barrier, solve the problem that the extraction of the above photo-generated electrons is hindered, and improve the EQE of the OPD device.

[0080] To better understand the present application, the following describes the display panel and the display device according to the embodiments of the present application in conjunction with Figures 4 to 21 in detail.

[0081] Please refer to Figure 4 and Figure 5 , Figure 4 which is a schematic diagram of the layer structure of a display panel provided by an embodiment of the present application; Figure 5 which is a schematic diagram of the energy level structure of a display panel provided by an embodiment of the present application.

[0082] As Figure 4 and Figure 5As shown in the figure, an embodiment of the first aspect of the present application provides a display panel, which includes: a substrate 100, a light-emitting unit, and a photoelectric sensing unit; the light-emitting unit is disposed on the first side of the substrate 100, and the light-emitting unit includes a first hole blocking layer 221; the photoelectric sensing unit is disposed on the first side of the substrate 100, and the photoelectric sensing unit includes a photoelectric conversion layer, a buffer layer 400, and a second hole blocking layer 222. The buffer layer 400 is disposed on the side of the photoelectric conversion layer 320 away from the substrate 100, and the second hole blocking layer 222 is disposed on the side of the buffer layer 400 away from the photoelectric conversion layer 320; wherein, the materials of the first hole blocking layer 221 and the second hole blocking layer 222 are the same, the buffer layer 400 has a first conductivity, the second hole blocking layer 222 has a second conductivity, and the first conductivity is greater than the second conductivity.

[0083] In the display panel provided by the embodiment of the present application, the display panel includes a substrate 100, a light-emitting unit, and a photoelectric sensing unit. The light-emitting unit is used to realize the light-emitting display of the display panel, and the photoelectric sensing unit is used to realize the photoelectric sensing function of the display panel. Optionally, the light-emitting unit further includes a light-emitting layer 310. The first hole blocking layer 221 is used to block the movement of holes from the light-emitting layer 310 in the direction away from the substrate 100, thereby improving the light-emitting efficiency. The second hole blocking layer 222 is used to block the movement of holes from the photoelectric conversion layer 320 in the direction away from the substrate 100, thereby improving the performance of photoelectric sensing. A buffer layer 400 is disposed between the second hole blocking layer 222 and the photoelectric conversion layer 320, and the conductivity of the buffer layer 400 is greater than that of the second hole blocking layer 222. The potential barrier between the buffer layer 400 and the photoelectric conversion layer 320 is small, which can reduce the potential barrier between the second hole blocking layer 222 and the photoelectric conversion layer 320, improve the electron transport efficiency, and improve the performance of the photoelectric conversion layer 320. Therefore, by adding a buffer layer 400 between the photoelectric conversion layer 320 and the second hole blocking layer 222 in the embodiment of the present application, the performance of the photodetector of the display panel can be improved.

[0084] Optionally, the light-emitting unit is a structure for converting an electrical signal into an optical signal and then realizing the light-emitting display of the display panel. Optionally, the photoelectric sensing unit is a structure for converting an optical signal line into an electrical signal and then realizing the photoelectric detection function of the display panel. Optionally, the photoelectric sensing unit can be the above-mentioned OPD device.

[0085] Optionally, the display panel further includes a first electrode 110 and a second electrode 120. The first electrode 110 and the second electrode 120 are respectively disposed on both sides of the light-emitting unit and the photoelectric sensing unit. The light-emitting unit can be driven to emit light through the first electrode 110 and the second electrode 120, and the signal of the photoelectric sensing unit can also be transmitted through the first electrode 110 and the second electrode 120. Optionally, the substrate 100 further includes a driving circuit, and the driving circuit is used to drive the light-emitting unit to emit light.

[0086] Optionally, one of the first electrode 110 and the second electrode 120 is an anode and the other is a cathode. In the embodiments of the present application, it is exemplified that the first electrode 110 is an anode and the second electrode 120 is a cathode. The material of the first electrode 110 may include indium tin oxide, and the material of the second electrode 120 may include magnesium (chemical symbol: Mg), silver (chemical symbol: Ag), ytterbium (chemical symbol: Yb), etc.

[0087] Optionally, the first hole blocking layer 221 and the second hole blocking layer 222 may be integrally formed to form the hole blocking layer 220. So that the first hole blocking layer 221 and the second hole blocking layer 222 can be prepared and formed in the same process step and do not need to be patterned, which can simplify the manufacturing process of the display panel. Optionally, in some embodiments, there may also be a gap between the first hole blocking layer 221 and the second hole blocking layer 222.

[0088] Optionally, the light-emitting unit further includes a first hole transport layer 211, a first hole injection layer 231, and a first electron transport layer 241. Optionally, the photoelectric sensing unit further includes a second hole transport layer 212, a second hole injection layer 232, and a second electron transport layer 242. Optionally, the first hole transport layer 211 and the second hole transport layer 212 are integrally formed to form the hole transport layer 210. Optionally, the first hole injection layer 231 and the second hole injection layer 232 are integrally formed to form the hole injection layer 230. Optionally, the first electron transport layer 241 and the second electron transport layer 242 are integrally formed to form the electron transport layer 240.

[0089] Optionally, in some embodiments, there may also be a gap between the first hole transport layer 211 and the second hole transport layer 212. Optionally, in some embodiments, there may also be a gap between the first hole injection layer 231 and the second hole injection layer 232. Optionally, in some embodiments, there may also be a gap between the first electron transport layer 241 and the second electron transport layer 242.

[0090] Optionally, the hole injection layer 230 is disposed on a side of the hole transport layer 210 away from the photoelectric conversion layer 320 and the light-emitting layer 310, and the electron transport layer 240 is located on a side of the hole blocking layer 220 away from the substrate 100.

[0091] Optionally, the light-emitting layer 310 and the photoelectric conversion layer 320 are disposed in the same layer and constitute a part of the functional layer 300. The hole transport layer 210, the hole blocking layer 220, the hole injection layer 230, and the electron transport layer 240 constitute a part of the common layer 200.

[0092] In some optional embodiments, the photoelectric conversion layer 320 includes a donor material and an acceptor material, and the donor material and the acceptor material interact with each other to realize a photoelectric sensing function.

[0093] Optionally, the photoelectric conversion layer 320 includes a mixed layer 321 , and the material of the mixed layer 321 includes a donor material and an acceptor material.

[0094] Optionally, the photoelectric conversion layer 320 further includes a donor layer 322, which is located on the side of the mixed layer 321 facing the substrate 100, and the material of the donor layer 322 includes a donor material; and / or, the photoelectric conversion layer 320 further includes an acceptor layer 323, which is located on the side of the mixed layer 321 facing away from the substrate 100, and the material of the acceptor layer 323 includes an acceptor material.

[0095] There are many ways to set the material of the buffer layer 400. The material of the buffer layer 400 may include metal elements, so that the buffer layer 400 can have higher conductivity and the buffer layer 400 can transmit electrons more easily.

[0096] In some optional embodiments, please continue to refer to Figure 4 and Figure 5 The buffer layer 400 includes a first buffer layer 410, and the material of the first buffer layer 410 includes metal. Specifically, the material of the first buffer layer 410 includes metal, which can rearrange the interface energy level between the first buffer layer 410 and the film layer in contact with the first buffer layer 410, thereby reducing the interface barrier.

[0097] The first buffer layer 410 may be a single-layer film structure.

[0098] Or, if Figure 6 and Figure 7 As shown, the first buffer layer 410 may include two or more stacked sublayers. By providing multiple sublayers, the conductivity of the first buffer layer 410 at different thickness positions can be adjusted, which can reduce the potential barrier between the first buffer layer 410 and the photoelectric conversion layer 320, and also reduce the potential barrier between the first buffer layer 410 and the second hole blocking layer 222.

[0099] Optionally, the thickness of the first buffer layer 410 is not less than 0.1 nanometers, and the thickness of the first buffer layer 410 is not greater than 5 nanometers, which can ensure that the thickness of the first buffer layer 410 is not too small to affect the degree of improvement of the potential barrier between the photoelectric conversion layer 320 and the second hole blocking layer 222, and can also ensure that the thickness of the first buffer layer 410 is not too large to affect the efficiency of signal transmission due to the excessive transmission path of electrons.

[0100] Further optionally, the thickness of the first buffer layer 410 is not less than 0.5 nanometers and not greater than 2 nanometers, such that the first buffer layer 410 has a better thickness, which can not only improve the problem of excessive barrier between the optoelectronic conversion layer 320 and the second hole blocking layer 222, but also does not affect electron transport. Moreover, it can avoid the problem of electron lateral crosstalk caused by too thick a first buffer layer 410.

[0101] In some alternative embodiments, when the first buffer layer 410 includes a first sub-layer 411 and a second sub-layer 412, the second sub-layer 412 is located on the side of the first sub-layer 411 facing the second hole blocking layer 222. That is, the first sub-layer 411 is disposed closer to the optoelectronic conversion layer 320 than the second sub-layer 412. The thicknesses and materials of the first sub-layer 411 and the second sub-layer 412 may be the same.

[0102] Alternatively, in some other embodiments, the thickness of the first sub-layer 411 is less than the thickness of the second sub-layer 412.

[0103] In these alternative embodiments, the thickness of the first sub-layer 411 is less than the thickness of the second sub-layer 412, that is, the sub-layer closer to the optoelectronic conversion layer 320 has a smaller thickness, such that the sub-layer closer to the optoelectronic conversion layer 320 has a higher conductivity, which can better improve the problem of excessive barrier between the optoelectronic conversion layer 320 and the second hole blocking layer 222. At the same time, making the conductivity of the sub-layer closer to the second hole blocking layer 222 smaller can improve the problem of excessive barrier between the first buffer layer 410 and the second hole blocking layer 222.

[0104] In still some other embodiments, the work function of the metal material in the first sub-layer 411 is greater than the work function of the metal material in the second sub-layer 412.

[0105] In these alternative embodiments, the metal materials included in the first sub-layer 411 and the second sub-layer 412 are different, and the work function of the metal material in the first sub-layer 411 is larger, such that the first sub-layer 411 has a higher conductivity, that is, the sub-layer closer to the optoelectronic conversion layer 320 has a higher conductivity, which can better improve the problem of excessive barrier between the optoelectronic conversion layer 320 and the second hole blocking layer 222. At the same time, making the conductivity of the sub-layer closer to the second hole blocking layer 222 smaller can improve the problem of excessive barrier between the first buffer layer 410 and the second hole blocking layer 222.

[0106] In still some other embodiments, the thickness of the first sub-layer 411 is less than the thickness of the second sub-layer 412, and the work function of the metal material in the first sub-layer 411 is greater than the work function of the metal material in the second sub-layer 412, so as to better improve the problem of excessive barrier between the optoelectronic conversion layer 320 and the hole blocking layer 220.

[0107] Optionally, the work function of the metal material in the first sub-layer 411 is greater than 3.5 electron volts, and the work function of the metal material in the second sub-layer 412 is less than or equal to 3.5 electron volts. This makes the overall work function of the first sub-layer 411 relatively large and the work function of the second sub-layer 412 relatively small. Therefore, the potential barrier between the first sub-layer 411 and the photoelectric conversion layer 320 is small, and the potential barrier between the second sub-layer 412 and the second hole blocking layer 222 is small.

[0108] There are various ways to set the materials of the first sub-layer 411 and the second sub-layer 412. For example, the material of the first sub-layer 411 includes aluminum, and the material of the second sub-layer 412 includes ytterbium. These two materials have good electrical conductivity and satisfy the above work function relationship, and are simple to prepare and have low cost.

[0109] In the above embodiment, by introducing the first sub-layer 411 and the second sub-layer 412 between the photoelectric conversion layer 320 and the second hole blocking layer 222, the interface energy levels are rearranged, thereby reducing the interface potential barrier. For example, when the material of the first sub-layer 411 is aluminum, aluminum can be in direct contact with the acceptor layer to form an ohmic contact. Further, a second sub-layer 412 is provided on the side of the first sub-layer 411 away from the acceptor layer. The material of the second sub-layer 412 includes ytterbium, which can effectively reduce the interface potential barrier between the metal and the second hole blocking layer 222.

[0110] To further illustrate the beneficial effects of the present application, the inventor conducted a comparative experiment. The comparative implementation includes: Comparative Example 1 and Embodiment 1. Both Comparative Example 1 and Embodiment 1 provide a display panel including a light-emitting unit and a photoelectric sensing unit.

[0111] The difference between Embodiment 1 and Comparative Example 1 is that a first sub-layer 411 and a second sub-layer 412 are provided between the photoelectric conversion layer 320 and the second hole blocking layer 222. The material of the first sub-layer 411 is aluminum, and the material of the second sub-layer 412 is ytterbium. And the thicknesses of the first sub-layer 411 and the second sub-layer 412 are 1 nanometer.

[0112] By testing the above Comparative Example 1 and Embodiment 1 when the wavelength of the incident light is 590 nanometers, the following Figure 8 shown curve graph and the following table are obtained. Figure 8 where the abscissa is the reverse voltage applied to the OPD. From Figure 8 it can be clearly seen that when the buffer layer 400 is not provided, the EQE of Comparative Example 1 is very low. After introducing the first sub-layer 411 and the second sub-layer 412, the EQE of the display panel at -3V is significantly increased by 25%. At higher voltages, the EQE gradually reaches saturation, indicating that most of the photo-generated carriers are extracted, indicating that the first sub-layer 411 and the second sub-layer 412 significantly reduce the interface potential barrier between the second hole blocking layer 222 and the photoelectric conversion layer 320.

[0113] Display panel EQE Dark current Comparative Example 1 4％ <![CDATA[39nA / cm 2 > Example 1 25％ <![CDATA[19nA / cm 2 >

[0114] On the other hand, as shown in the above table, by introducing the first sub-layer 411 and the second sub-layer 412, the dark current is also reduced from 39 nA / cm 2 to 19 nA / cm 2 . It should be noted that the thicknesses of aluminum and ytterbium can be maintained near 1 nanometer. Considering the reflection and absorption characteristics of the metal, too thick aluminum and ytterbium will reduce the light absorption of the device, thereby reducing the EQE; while too thin metal cannot form an effective electrical connection, and the barrier reduction effect is not ideal.

[0115] In some other alternative embodiments, a single-layer metal layer can also be selected as the buffer layer 400. For example, the buffer layer 400 only includes the above-mentioned first sub-layer 411 and / or second sub-layer 412,

[0116] In some alternative embodiments, as Figure 9 and Figure 10 shown, the buffer layer 400 includes a second buffer layer 420. The second buffer layer 420 is disposed between the first buffer layer 410 and the photoelectric conversion layer 320, and the material of the second buffer layer 420 includes an electron transport material.

[0117] In these alternative embodiments, a second buffer layer 420 is additionally provided between the second sub-layer 412 and the photoelectric conversion layer 320. The material of the second buffer layer 420 includes an electron transport material. For example, the material of the second buffer layer 420 is the same as that of the electron transport layer 240, so that electrons can be more easily transported between the photoelectric conversion layer 320 and the second hole blocking layer 222, and better improve the problem of the relatively large barrier between the photoelectric conversion layer 320 and the second hole blocking layer 222.

[0118] Optionally, as Figures 11 to 12 shown, when the first buffer layer 410 includes the first sub-layer 411 and the second sub-layer 412, the second buffer layer 420 can be disposed between the second sub-layer 412 and the photoelectric conversion layer 320. For example, the second buffer layer 420 can be located between the first sub-layer 411 and the second sub-layer 412, or, as Figure 13 shown, the second buffer layer 420 can be located between the first sub-layer 411 and the photoelectric conversion layer 320, that is, the second buffer layer 420 is located between the first buffer layer 410 and the photoelectric conversion layer 320.

[0119] Optionally, as above, the display panel further includes an electron transport layer 240, and the material of the second buffer layer 420 is the same as that of the electron transport layer 240 to simplify the manufacturing process of the display panel.

[0120] For example, the material of the second buffer layer 420 includes a host material and an n-type dopant, so that the second buffer layer 420 has good electron transport ability.

[0121] The host material may include at least one of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: BCP), 4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: Bphen), and 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: Nbphen), so that the host material has the advantages of easy preparation and low cost.

[0122] Optionally, the thickness of the second buffer layer 420 is not less than 0.5 nanometers and not greater than 10 nanometers. This can improve the situation where the second buffer layer 420 fails to function effectively due to its too small thickness, and can also improve the situation where the electron transport distance is too large due to the too large thickness of the second buffer layer 420. An overly thin second buffer layer 420 cannot play an effective blocking role, while an overly thick second buffer layer 420 will block the extraction of photo-generated holes.

[0123] In addition, by introducing the second buffer layer 420 including an electron transport material, the transport material in the second buffer layer 420 can form a complex with the metal atoms in the first buffer layer 410, or trap energy levels can be formed by the hot metal material therein. Optionally, when the material of the second buffer layer 420 is selected as an electron transport material with a rophenylene structure, such as the host material of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: BCP), 4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: Bphen), and 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: Nbphen), the host material can form a complex with the metal atoms to improve the conductivity and achieve the effect of n doping.

[0124] The second buffer layer 420 can be selected as a single-layer or multi-layer metal layer. For example, the setting method of the second buffer layer 420 can be the same as that of the first buffer layer 410. The second buffer layer 420 can include a third sub-layer and a fourth sub-layer arranged in a stacked manner. The setting method of the third sub-layer is the same as that of the first sub-layer 411, and the setting method of the fourth sub-layer is the same as that of the second sub-layer 412.

[0125] To further illustrate the beneficial effects of the present application, the inventor conducted a comparative experiment. The comparative experiment includes: Comparative Example 2 and Example 2. Both Comparative Example 2 and Example 2 provide a display panel including a light-emitting unit and a photoelectric sensing unit.

[0126] The difference between Example 2 and Comparative Example 2 is that a first buffer layer 410 and a second buffer layer 420 are provided between the optoelectronic conversion layer 320 and the second hole blocking layer 222. The material of the first buffer layer 410 includes aluminum and ytterbium. The thickness of the second buffer layer 420 is 3 nanometers, and the material of the third buffer layer 430 is the same as that of the electron transport layer 240.

[0127] By testing Comparative Example 2 and Example 2 when the wavelength of the incident light is 590 nanometers, the following Figure 14 and Figure 15 shown curve graphs are obtained. Figure 14 and Figure 15 In which, the abscissa is the reverse voltage applied to the OPD. Figure 14 The ordinate in Figure 15 is EQE, Figure 14 and Figure 15 It can be seen from

[0128] that after introducing the second buffer layer 420, the EQE remains basically unchanged, but the forward current of the device increases significantly, indicating that the interfacial electrical contact is improved. In the circuit, a high forward current is beneficial to the rapid reset of the OPD and can improve the response speed.

[0128] In some alternative embodiments, as Figure 16 shown, the buffer layer 400 includes a third buffer layer 430. The material of the third buffer layer 430 includes a host material and an n-type dopant. The n-type dopant includes the metal element, so that the third buffer layer 430 has a high conductivity and is convenient for electron transport.

[0129] Optionally, when a first buffer layer 410 is provided between the optoelectronic conversion layer 320 and the second hole blocking layer 222, or when a first buffer layer 410 and a second buffer layer 420 are provided between the optoelectronic conversion layer 320 and the second hole blocking layer 222, the third buffer layer 430 may not be provided between the optoelectronic conversion layer 320 and the second hole blocking layer 222. Or, a first buffer layer 410, a second buffer layer 420, and a third buffer layer 430 are provided between the optoelectronic conversion layer 320 and the second hole blocking layer 222.

[0130] Optionally, the host material in the third buffer layer 430 can be arranged in the same manner as the second buffer layer 420. For example, the host material in the third buffer layer 430 can include an electron transport material having a phenanthroline structure, such as at least one of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: BCP), 4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: Bphen), and 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (chemical abbreviation: Nbphen), so that the host material in the third buffer layer 430 has the advantages of easy preparation and low cost. Optionally, the n-type dopant can be selected from the acceptor material or the material of the second hole blocking layer 222, that is, the material of the n-type dopant can be the same as the material of part of the optoelectronic conversion layer 320, or the material of the n-type dopant can be the same as the material of the second hole blocking layer 222.

[0131] Optionally, the third buffer layer 430 can be a single-layer structure.

[0132] Or, in other embodiments, the third buffer layer 430 includes a plurality of sub-layers. In the direction away from the optoelectronic conversion layer 320, the absolute value of the LUMO energy level of the host material of each sub-layer gradually increases. That is, in the direction away from the optoelectronic conversion layer 320, the absolute value of the LUMO energy level of the host material of the previous sub-layer is less than the absolute value of the LUMO energy level of the host material of the subsequent sub-layer, so as to reduce the potential barrier between the third buffer layer 430 and the second hole blocking layer 222.

[0133] Optionally, when the third buffer layer 430 includes a plurality of sub-layers, the thicknesses of the plurality of sub-layers can be the same to simplify the preparation of the display panel.

[0134] Optionally, the n-type dopant in the third buffer layer 430 includes at least one of a metal compound, a metal oxide, and a metal with a low work function. For example, the n-type dopant in the third buffer layer 430 includes a metal with a low work function, and the work function of the metal with a low work function is less than 3.5 electron volts, so that the third buffer layer 430 has a suitable conductivity. Optionally, when the n-type dopant in the third buffer layer 430 includes a metal with a low work function, the metal with a low work function can include at least one of ytterbium, lithium, calcium, and cesium. These metals have good conductivity and a suitable work function, can meet the use requirements, and have a low cost.

[0135] In the above embodiments, the introduction of the third buffer layer 430 can increase the carrier concentration, improve the conductivity, and further cause the interface energy level to bend. The photo-generated electrons can pass through the interface potential barrier through the tunneling effect, significantly improving the photo-generated carrier extraction efficiency and EQE.

[0136] In other embodiments, the material of the n-type dopant of the third buffer layer 430 may also include at least one of a metal oxide and a compound, as long as the material of the third buffer layer 430 includes a main material and an n-type dopant, so that the third buffer layer 430 has good conductivity. When the material of the n-type dopant of the third buffer layer 430 includes at least one of a metal oxide and a compound, the n-type dopant of the third buffer layer 430 may include at least one of lithium carbonate, cesium carbonate, lithium amide, and W2(hpp)4Cl2.

[0137] Optionally, the thickness of the third buffer layer 430 is not less than 0.5 nanometers, and the thickness of the third buffer layer 430 is not greater than 20 nanometers. When the thickness of the third buffer layer 430 is within the above range, it can ensure that the thickness of the third buffer layer 430 is not too small to affect the degree of improvement of the barrier between the photoelectric conversion layer 320 and the second hole blocking layer 222, and it can also ensure that the thickness of the third buffer layer 430 is not too large to affect the efficiency of signal transmission due to the long transmission path of electrons. As an optional embodiment, the thickness of the third buffer layer 430 is not less than 1 nanometer, and the thickness of the third buffer layer 430 is not greater than 10 nanometers, which better improves the problem of the third buffer layer 430 being too thick or too thin.

[0138] In some optional embodiments, the n-type dopant in the third buffer layer has an amount of the first substance, the material of the third buffer layer has an amount of the second substance, the ratio of the amount of the first substance to the amount of the second substance is not less than 0.1%, and the ratio of the amount of the first substance to the amount of the second substance is not greater than 10%. Too high a doping ratio or too thick a film thickness will lead to an increase in the absorption of electrons by the film layer, thereby reducing EQE, while too low a doping ratio or too thin a film thickness will make it difficult to form an effective energy level transition. When the above ratio is between 0.1% and 10%, the third buffer layer 430 can have a suitable conductivity. Further, the above ratio is not less than 0.5%, and the above ratio is not greater than 10%.

[0139] In some optional embodiments, when the buffer layer 400 includes a third buffer layer 430, as Figure 17 As shown, the buffer layer 400 may further include a fourth buffer layer 440 , the material of the fourth buffer layer 440 includes at least one of metal and metal oxide, and the fourth buffer layer 440 is disposed on the side of the third buffer layer 430 facing toward or away from the photoelectric conversion layer 320 .

[0140] In these optional embodiments, by adding a fourth buffer layer 440 whose material includes at least one of metal and metal oxide, the conductivity of the buffer layer 400 can be further improved, and the problem of excessive potential barrier between the photoelectric conversion layer 320 and the hole blocking layer 220 can be better improved.

[0141] In some alternative embodiments, such as Figure 18 shown, the buffer layer 400 further includes a fifth buffer layer 450, and the fifth buffer layer 450 is formed by preparing at least one of a metal, an alkali metal compound, and an alkaline earth metal compound, so that the buffer layer 400 has good conductivity.

[0142] Optionally, the fifth buffer layer is formed by preparing at least one of lithium carbonate, cesium carbonate, lithium nitride, and lithium fluoride.

[0143] Optionally, when the fifth buffer layer 450 is formed by preparing at least one of an alkali metal compound and an alkaline earth metal compound. During the preparation evaporation process, these materials will decompose to generate low work function alkali metals, alkaline earth metal oxides or simple substances, or have insulating properties, and through the interface tunneling effect, the interface barrier can be effectively reduced.

[0144] Optionally, the thickness of the fifth buffer layer 450 is not less than 0.5 nanometers and not greater than 5 nanometers. If the fifth buffer layer 450 is too thin, the barrier improvement effect is poor, and if the fifth buffer layer 450 is too thick, a large series resistance will be caused, reducing the EQE. The fifth buffer layer 450 within this thickness range can not only ensure that the thickness of the fifth buffer layer 450 is not too small to improve the problem of too large a barrier between the optoelectronic conversion layer 320 and the second hole blocking layer 222, but also ensure that the thickness of the fifth buffer layer 450 is not too large to make the electron transport path too large.

[0145] In some alternative embodiments, such as Figure 19 shown, the buffer layer 400 further includes a sixth buffer layer 460, the sixth buffer layer 460 is disposed on the side of the fifth buffer layer 450 facing the optoelectronic conversion layer 320, and the material of the sixth buffer layer 460 includes a metal with a high work function, and the work function of the metal with a high work function is greater than 4.0 electron volts. To improve the overall conductivity of the buffer layer 400.

[0146] Optionally, the metal with a high work function can be at least one of aluminum and silver. These metals have a relatively high work function and are easy to obtain, which can reduce the preparation cost of the display panel.

[0147] Optionally, the sixth buffer layer 460 can be located between the fifth buffer layer 450 and the optoelectronic conversion layer 320 to better improve the problem of too large a barrier.

[0148] Optionally, the thickness of the sixth buffer layer 460 is not less than 0.5 nanometers and not greater than 5 nanometers. This can not only ensure that the thickness of the sixth buffer layer 460 is not too small to improve the problem of excessive barrier between the optoelectronic conversion layer 320 and the hole blocking layer 220, but also ensure that the thickness of the sixth buffer layer 460 is not too large to cause an excessive electron transmission path.

[0149] In some other embodiments, the fifth buffer layer 450 may include a blended structure of a metal and an alkali metal or alkaline earth metal compound, and is prepared by co-evaporation, for example.

[0150] Optionally, the display panel may include a first buffer layer 410, or the display panel may include a first buffer layer 410 and a second buffer layer 420, or the display panel may include a third buffer layer 430, or the display panel may include a third buffer layer 430 and a fourth buffer layer 440, or the display panel may include a fifth buffer layer 450, or the display panel may include a fifth buffer layer 450 and a sixth buffer layer 460. Or the display panel may include at least one of the first buffer layer 410, the second buffer layer 420, the third buffer layer 430, the fourth buffer layer 440, the fifth buffer layer 450, and the sixth buffer layer 460.

[0151] Optionally, in any of the above embodiments, the buffer layer 400 and the optoelectronic conversion layer 320 may be provided in one-to-one correspondence. When there are multiple optoelectronic conversion layers 320 and they are spaced apart, there may also be multiple buffer layers 400, and the orthographic projection of each optoelectronic conversion layer 320 on the substrate 100 is located within the orthographic projection of each buffer layer 400 on the substrate 100. Or, as Figure 20 shown, the buffer layer 400 may be a common layer, and the orthographic projections of the optoelectronic conversion layer 320 and the light-emitting layer 310 on the substrate 100 are located within the orthographic projection of the buffer layer 400 on the substrate 100.

[0152] An embodiment of the second aspect of the present application further provides a display device, including the display panel of any of the above embodiments of the first aspect. Since the display device provided by the embodiment of the second aspect of the present application includes the display panel of any of the above embodiments of the first aspect, the display device provided by the embodiment of the second aspect of the present application has the beneficial effects of the display panel of any of the above embodiments of the first aspect, which will not be elaborated here.

[0153] The display device in the embodiments of the present application includes, but is not limited to, devices with a display function such as mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control devices, smart landline telephones, and consoles.

[0154] An embodiment of the third aspect of the present application further provides a method for manufacturing a display panel, which can be the display panel provided in any of the above first aspect embodiments. Please refer to Figures 1 to 21 simultaneously. The method for manufacturing the display panel may include:

[0155] Step S01: Prepare a photoelectric conversion layer 320 of the photoelectric sensing unit on the first side of the substrate 100.

[0156] Step S02: Prepare a buffer layer 400 on the side of the photoelectric conversion layer 320 facing away from the substrate 100, where the buffer layer 400 has a first conductivity.

[0157] Step S03: Prepare a first hole blocking layer 221 of the light emitting unit on the first side, and prepare a second hole blocking layer 222 on the side of the buffer layer 400 facing away from the photoelectric conversion layer 320. The second hole blocking layer 222 has a second conductivity, and the first conductivity is greater than the second conductivity.

[0158] In the display panel manufactured by the method provided in the embodiments of the present application, the display panel includes a substrate 100, a hole transport layer 210, a light emitting layer 310, a photoelectric conversion layer 320, a hole blocking layer 220, and a buffer layer 400. The light emitting layer 310 is used to realize the light emitting display of the display panel, and the photoelectric conversion layer 320 is used to realize the photoelectric induction function of the display panel. The hole transport layer 210 is used to transport holes to realize the conversion of optical signals to electrical signals, or the conversion of electrical signals to optical signals. The hole blocking layer 220 is used to block the movement of holes from the photoelectric conversion layer 320 or the light emitting layer 310 in the direction away from the hole transport layer 210, and improve the photoelectric induction or light emitting efficiency. A buffer layer 400 is disposed between the hole blocking layer 220 and the photoelectric conversion layer 320, and the conductivity of the buffer layer 400 is greater than that of the hole blocking layer 220. The potential barrier between the buffer layer 400 and the photoelectric conversion layer 320 is small, which can reduce the potential barrier between the hole blocking layer 220 and the photoelectric conversion layer 320 and improve the performance of the photoelectric conversion layer 320. Therefore, by adding a buffer layer 400 between the photoelectric conversion layer 320 and the hole blocking layer 220 in the embodiments of the present application, the performance of the photodetector of the display panel can be improved.

[0159] Although the present application has been described with reference to the preferred embodiments, various improvements can be made to it and components therein can be replaced with equivalents without departing from the scope of the present application. In particular, as long as there is no structural conflict, the technical features mentioned in each embodiment can be combined in any way. The present application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display panel, characterized in that, Comprising: A substrate having a first side; A light-emitting unit disposed on the first side, the light-emitting unit including a first hole-blocking layer; A photoelectric sensing unit disposed on the first side, the photoelectric sensing unit being configured to receive an optical signal and generate a corresponding electrical signal according to the optical signal, the photoelectric sensing unit including a photoelectric conversion layer, a buffer layer, and a second hole-blocking layer, the buffer layer being disposed on a side of the photoelectric conversion layer away from the substrate, and the second hole-blocking layer being disposed on a side of the buffer layer away from the photoelectric conversion layer; Wherein, the first hole-blocking layer and the second hole-blocking layer are made of the same material, the buffer layer has a first conductivity, the second hole-blocking layer has a second conductivity, and the first conductivity is greater than the second conductivity.

2. The display panel according to claim 1, wherein The material of the buffer layer includes a metal element; Preferably, the first hole-blocking layer and the second hole-blocking layer are of an integral structure.

3. The display panel according to claim 2, characterized in that, The buffer layer includes a first buffer layer, and the material of the first buffer layer includes a metal; Preferably, the thickness of the first buffer layer is not less than 0.1 nanometer and not greater than 5 nanometers; Preferably, the thickness of the first buffer layer is not less than 0.5 nanometer and not greater than 2 nanometers; Preferably, the first buffer layer includes a first sub-layer and a second sub-layer, the second sub-layer is located on a side of the first sub-layer away from the photoelectric conversion layer, and the thickness of the first sub-layer is less than the thickness of the second sub-layer; Preferably, the work function of the metal material in the first sub-layer is greater than the work function of the metal material in the second sub-layer; Preferably, the work function of the metal material in the first sub-layer is greater than 3.5 electron volts, and the work function of the metal material in the second sub-layer is less than or equal to 3.5 electron volts; Preferably, the metal material in the first sub-layer includes aluminum, and the metal material in the second sub-layer includes ytterbium.

4. The display panel according to claim 3, wherein The buffer layer further includes a second buffer layer, and the material of the second buffer layer includes an electron transport material; Preferably, the second buffer layer is located between the first sub-layer and the second sub-layer, or the second buffer layer is located between the first sub-layer and the photoelectric conversion layer.

5. The display panel according to claim 4, wherein The light-emitting unit further includes a light-emitting layer and an electron transport layer, the first hole-blocking layer is disposed on a side of the light-emitting layer away from the substrate, the electron transport layer is disposed on a side of the first hole-blocking layer away from the light-emitting layer, and the material of the second buffer layer is the same as the material of the electron transport layer; Preferably, the electron transport material in the second buffer layer has a phenanthroline structure; Preferably, the electron transport material includes at least one of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline, 4,7-diphenyl-1,10-phenanthroline, and 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline; Preferably, the thickness of the second buffer layer is not less than 0.5 nanometer and not greater than 10 nanometers.

6. The display panel according to claim 2, wherein, The buffer layer includes a third buffer layer, and the material of the third buffer layer includes a host material and an n-type dopant, and the n-type dopant includes the metal element; Preferably, the material of the optoelectronic conversion layer includes a donor material and an acceptor material, and the host material includes at least one of an electron transport material, the material of the second hole blocking layer, and the acceptor material; Preferably, the electron transport material has a phenanthroline structure; Preferably, the electron transport material includes at least one of 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline, 4,7-diphenyl-1,10-phenanthroline, and 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline; Preferably, the third buffer layer includes a plurality of sub-layers, and in the direction away from the substrate of the optoelectronic conversion layer, the absolute value of the LUMO energy level of the host material of each sub-layer gradually increases; Preferably, the n-type dopant includes at least one of a metal compound, a metal oxide, and a metal with a low work function; Preferably, the work function of the metal with a low work function is less than 3.5 electron volts, and the metal with a low work function includes at least one of ytterbium, lithium, calcium, and cesium; Preferably, the metal oxide includes at least one of lithium carbonate and cesium carbonate, and the metal compound includes at least one of lithium amide and W2(hpp)4; Preferably, the thickness of the third buffer layer is not less than 0.5 nanometers and not more than 20 nanometers; Preferably, the thickness of the third buffer layer is not less than 1 nanometer and not more than 10 nanometers; Preferably, the n-type dopant has a first amount of substance, the material of the third buffer layer has a second amount of substance, and the ratio of the first amount of substance to the second amount of substance is not less than 0.1% and not more than 10%; Preferably, the ratio of the first amount of substance to the second amount of substance is not less than 0.5% and not more than 10%.

7. The display panel according to claim 6, wherein The buffer layer further includes a fourth buffer layer, and the material of the fourth buffer layer includes at least one of a metal and a metal oxide, and the fourth buffer layer is disposed on one side of the third buffer layer facing or away from the optoelectronic conversion layer.

8. The display panel according to claim 2, characterized in that, The buffer layer further includes a fifth buffer layer, and the fifth buffer layer is prepared from at least one of a metal, an alkali metal compound, and an alkaline earth metal compound; Preferably, the fifth buffer layer is prepared from at least one of lithium carbonate, cesium carbonate, lithium nitride, and lithium fluoride; Preferably, the material of the fifth buffer layer includes an alkali metal with a low work function, and the alkali metal with a low work function includes lithium; Preferably, the thickness of the fifth buffer layer is not less than 0.5 nanometers and not more than 5 nanometers.

9. The display panel according to claim 8, wherein The buffer layer further includes a sixth buffer layer disposed on one side of the fifth buffer layer. The material of the sixth buffer layer includes a metal with a high work function, and the work function of the metal with a high work function is greater than 4.0 electron volts; Preferably, the metal with a high work function includes at least one of aluminum and silver; Preferably, the sixth buffer layer is disposed on the side of the fifth buffer layer facing the photoelectric conversion layer; Preferably, the thickness of the sixth buffer layer is not less than 0.5 nanometers and not greater than 5 nanometers.

10. A display device, characterized in that, A display panel according to any one of claims 1-9.

11. A method for manufacturing a display panel, characterized in that, Comprising: Preparing a photoelectric conversion layer of a photoelectric sensing unit on a first side of a substrate, wherein the photoelectric sensing unit is configured to receive an optical signal and generate a corresponding electrical signal according to the optical signal; Preparing a buffer layer on a side of the photoelectric conversion layer facing away from the substrate, wherein the buffer layer has a first conductivity; Preparing a first hole blocking layer of a light emitting unit on the first side and preparing a second hole blocking layer on a side of the buffer layer facing away from the photoelectric conversion layer, wherein the materials of the first hole blocking layer and the second hole blocking layer are the same, the second hole blocking layer has a second conductivity, and the first conductivity is greater than the second conductivity.

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