Isolated thermal resistor temperature signal conditioning system

Abstract

The invention belongs to the technical field of industrial automatic measurement and control, and discloses an isolated thermal resistance temperature signal conditioning system, which comprises a constant current source circuit; an amplification circuit; a VF conversion circuit; an FV conversion circuit; a low-pass filter circuit; and a linearization circuit. The instrument amplifier with a high common-mode rejection ratio is adopted to suppress common-mode noise, hardware filtering design is optimized, multi-stage low-pass filtering is adopted to eliminate power frequency harmonic waves, and a mirror image constant current source is adopted to enhance stability; a reverse protection circuit is added in a double-TVS diode clamping mode, and a wide input voltage range power supply chip is properly selected. VF / FV conversion time sequence control is adopted, a scheme of dynamically adjusting cut-off frequency is adopted, filtering parameters are automatically switched according to a signal variable rate, and noise suppression and response speed are balanced.

Description

Technical Field

[0001] The present invention relates to the field of industrial automation measurement and control technology, and particularly to an isolated thermoresistance temperature signal conditioning system. Background Art

[0002] RTD (resistance temperature detector) exhibits high precision and reliability in the field of temperature measurement due to the excellent temperature sensitivity and chemical stability of platinum (Pt) material. Its typical representatives, Pt100 (resistance value of 100 Ω at 0 °C) and Pt1000 (resistance value of 1000 Ω at 0 °C), can operate stably in a wide temperature range from -200 °C to +850 °C, meeting the requirements of extreme environments such as ultra-low temperature experiments and high-temperature industrial furnace monitoring. The resistance-temperature (R-T) relationship of platinum resistance is close to linear. After correcting the non-linear deviation by combining the Callendar-Van Dusen equation (a formula for calculating the relationship between temperature and resistance), the measurement error can be controlled within ±0.1 °C, and some high-precision models can reach ±0.03 °C, with outstanding long-term stability.

[0003] In industrial applications, RTD is widely used in process control scenarios such as temperature monitoring of chemical reaction kettles, heat management of power steam pipelines, and overheat protection of metallurgical motors. It is also the core sensing element in laboratory constant temperature baths, medical equipment, and new energy fields (such as lithium battery production and low-temperature monitoring of hydrogen energy storage tanks). To adapt to complex industrial environments, RTD adopts a multi-wire interface design: the 2-wire system has low cost but limited precision and is suitable for short-distance scenarios; the 3-wire system compensates for the wire resistance (for example, the error of a 100-meter cable can be reduced to ±0.1 °C) and has become the mainstream industrial solution; the 4-wire system isolates the excitation and measurement paths based on the Kelvin connection method to achieve ultra-high precision at the ±0.01 °C level and is mostly used for laboratory calibration. In addition, differential signal transmission and shielded twisted pair design effectively suppress common-mode noise caused by motor startup and shutdown, etc., further ensuring the anti-interference ability of the industrial site.

[0004] Defects of the existing technology:

[0005] 1. Insufficient suppression of power frequency interference:

[0006] Problem manifestation: 50 / 60 Hz power frequency noise is superimposed on the weak RTD signal, resulting in ADC output jumps (such as ±0.5 °C fluctuations).

[0007] Root causes: (1) The common-mode rejection ratio (CMRR) of the differential amplifier is insufficient (<80 dB), and it cannot effectively eliminate common-mode noise. (2) The filter circuit design is rough (such as the cut-off frequency of a single-stage RC filter is too high) and is not optimized for power frequency harmonics. (3) Grounding design defects (such as ground loops) or the use of unshielded cables introduce space electromagnetic interference.

[0008] 2. Lack of protection against incorrect power connection is likely to damage equipment:

[0009] Problem manifestation: The front - end circuit is burned out due to reverse power connection or over - voltage (e.g., misconnecting 24V as 48V), resulting in a high device failure rate.

[0010] Root cause: (1) To reduce costs, reverse - protection diodes, TVS tubes, or self - recovering fuses (PTC) are omitted. (2) Relying on the withstand voltage limit of linear voltage - regulating chips (such as LM7805), redundant protection is not designed.

[0011] 3. Signal delay caused by multi - stage filtering:

[0012] Problem manifestation: When the temperature changes step - by - step, the system response time is too long (e.g., > 200ms), which cannot meet the requirements of real - time control.

[0013] Root cause: (1) Using multi - stage analog filtering (such as RC low - pass + operational amplifier buffer) and superimposing digital filtering (moving average), the phase delay accumulates. (2) The filtering cut - off frequency is too low (e.g., 10Hz), sacrificing bandwidth, and there is a contradiction between dynamic response and noise suppression.

[0014] Generally speaking, the deficiencies of the existing technology are as follows:

[0015] (1) The problem of insufficient suppression of power - frequency interference. The specific manifestation is that 50 / 60Hz power - frequency noise is superimposed on the weak RTD signal, resulting in jumps in the ADC output (e.g., ±0.5°C fluctuations).

[0016] (2) The problem that the lack of protection against incorrect power connection easily damages the device. The specific manifestation is that the front - end circuit is burned out due to reverse power connection or over - voltage (e.g., misconnecting 24V as 48V), resulting in a high device failure rate.

[0017] (3) The problem of signal delay caused by multi - stage filtering. The specific manifestation is that when the temperature changes step - by - step, the system response time is too long (e.g., > 200ms), which cannot meet the requirements of real - time control.

[0018] Therefore, how to provide an isolated RTD temperature signal conditioning system is an urgent problem to be solved at present. Summary of the Invention

[0019] The embodiments of the present invention provide an isolated RTD temperature signal conditioning system to solve the problems of insufficient suppression of power - frequency interference, the problem that the lack of protection against incorrect power connection easily damages the device, and the problem of signal delay caused by multi - stage filtering in the existing technology.

[0020] To provide a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary part is not a general review, nor is it intended to identify key / important constituent elements or delineate the protection scope of these embodiments. Its sole purpose is to present some concepts in a simple form as a preface to the subsequent detailed description.

[0021] According to an embodiment of the present invention, an isolated thermal resistance temperature signal conditioning system is provided.

[0022] In one embodiment, an isolated thermal resistance temperature signal conditioning system includes:

[0023] A constant current source circuit for providing a constant current to a thermal resistance temperature sensor and providing a constant current source to a VF conversion circuit;

[0024] An amplifier circuit for proportionally amplifying the voltage across the thermal resistance temperature sensor and transmitting it to the VF conversion circuit;

[0025] A VF conversion circuit for mapping an analog voltage to a frequency signal through a closed-loop mechanism of integration, comparison, and reset;

[0026] An FV conversion circuit for mapping the frequency signal back to an analog voltage through a chain process of frequency, pulse width, and voltage;

[0027] A low-pass filter circuit for using a low-pass filter to improve the stability of the analog voltage output by the FV conversion circuit;

[0028] A linearization circuit for linearizing the finally output voltage by adjusting the resistance;

[0029] The constant current source circuit, the amplifier circuit, the VF conversion circuit, the FV conversion circuit, and the low-pass filter circuit are sequentially connected and maintained.

[0030] In one embodiment, the constant current source circuit includes: diode D3, triode Q17, resistor R36, resistor R67, diode D10, triode Q26, and resistor R37; wherein, one end of the resistor R37 is connected to the first end of the triode Q26, the second end of the triode Q26 is connected to the second end of the triode Q17, the third end of the triode Q17 is connected to the negative electrode of the diode D3, the first end of the triode Q17 is connected to one end of the resistor R36, the third end of the triode Q26 is connected to the negative electrode of the diode D10, and a resistor R67 is further provided on one side of the diode D10.

[0031] In one embodiment, the amplification circuit includes: resistor R38, resistor R39, resistor R40, amplifier U4A, resistor R36, resistor R68, resistor R66, and amplifier U4B; wherein, the first end of the amplifier U4A is sequentially connected to one end of the resistor R39 and one end of the resistor R40, the other end of the resistor R39 is connected to one end of the resistor R38, the other end of the resistor R38 is sequentially connected to the third end of the amplifier U4A and one end of the resistor R69, the other end of the resistor R69 is sequentially connected to the first end of the amplifier U4B and one end of the resistor R68, the other end of the resistor R68 is connected to one end of the resistor R66, and the other end of the resistor R66 is connected to the third end of the amplifier U4B.

[0032] In one embodiment, the amplification circuit further includes a dual TVS tube structure protection circuit, and the dual TVS tube structure protection circuit includes: capacitor C23 and diode Q22, and the diode C23 is connected in parallel with the first end and the second end of the diode Q22.

[0033] In one embodiment, the VF conversion circuit includes: switch tube Q13, switch tube Q14, capacitor C12, amplifier U5A, resistor R30, resistor R29, resistor R26, capacitor C10, resistor R24, resistor R25, capacitor C14, resistor R35, resistor R41, chip U1, and capacitor C11; wherein, the second end of the switch tube Q13 is sequentially connected to one end of the capacitor C12 and the second end of the amplifier U5A, the other end of the capacitor C12 is sequentially connected to the first end of the amplifier U5A, the second end of the amplifier Q14, one end of the capacitor C10, and one end of the resistor R24, the other end of the capacitor C10 is sequentially connected to the other end of the resistor R24, the resistor R25, and the first end of the chip U1, and the C1 end of the chip U1 is connected to the capacitor C11; the second end of the chip U1 is connected to one end of the resistor R26, the other end of the resistor R26 is sequentially connected to one end of the resistor R30, one end of the resistor R29, and the first end of the switch tube Q13, the other end of the resistor R30 is connected to the third end of the amplifier U5A, the third end of the switch tube Q13 is connected to the third end of the switch tube Q14, the first end of the switch tube Q14 is sequentially connected to one end of the capacitor C14, one end of the resistor R35, and one end of the resistor R41, and the other end of the resistor R35 is connected to the other end of the capacitor C14.

[0034] In one embodiment, the FV conversion circuit includes: chip U2, resistor R17, capacitor C8, capacitor C9, diode Q4, resistor R15, resistor R54, resistor R22, resistor R58, resistor R21, resistor R20, triode Q8, resistor R61, resistor R56, capacitor C21, amplifier U6A, and triode Q11; wherein, the A2 terminal of the chip U2 is connected to one end of the resistor R17, the other end of the resistor R17 is sequentially connected to one end of the capacitor C9, the A1 terminal and the B2 terminal of the chip U2, the C1 terminal of the chip U2 is connected to one end of the capacitor C8, and the other end of the capacitor C8 is connected to the other end of the capacitor C9; the first end of the triode Q8 is sequentially connected to the resistor R21, the resistor R20, and the resistor R58, the second end of the triode Q8 is sequentially connected to the second end of the amplifier U6A, one end of the capacitor C21, one end of the resistor R61, and one end of the resistor R22, the other end of the resistor R22 is connected to one end of the resistor R54, and the other end of the resistor R54 is sequentially connected to the resistor R15 and the diode Q4; the other end of the resistor R61 is connected to one end of the resistor R56, the other end of the resistor R56 is sequentially connected to the other end of the capacitor C21, the second end of the triode Q11, and the first end of the amplifier U6A, and the third end of the triode Q11 is connected to the third end of the triode Q8.

[0035] In one embodiment, mapping a frequency signal back to an analog voltage through a chain process of frequency, pulse width, and voltage includes:

[0036] Isolate the output signal of the VF conversion circuit using an optocoupler, and through a pulse shaping circuit, shape the output signal of the optocoupler into a square wave signal with the same frequency and fixed width as the -F conversion circuit; when the input voltage is at a low level, the triode Q8 is cut off, and the input signal of the proportional amplifier circuit U6A is the reference voltage; when the input voltage is at a high level, the triode Q8 is turned on, and the reference voltage and the constant current source act on the proportional amplifier circuit U6A at the same time; based on Kirchhoff's theorem, calculate the theoretical value of the output voltage, and with the help of the relationship between the frequency of the input voltage and the resistance of the thermal resistance temperature sensor, obtain the linear relationship between the output voltage of the FV circuit and the RTD resistance.

[0037] In one embodiment, the low-pass filter circuit includes: capacitor C6, resistor R5, resistor R7, resistor R55, resistor R11, capacitor C5, amplifier U1B, resistor R9, capacitor C4, and resistor R14; wherein, the third terminal of the amplifier U1B is sequentially connected to one end of the capacitor C4 and one end of the resistor R9, and the other end of the resistor R9 is connected to one end of the capacitor C6; the second terminal of the amplifier U1B is sequentially connected to one end of the capacitor C5 and the third terminal of the resistor R55, the second terminal of the resistor R55 is sequentially connected to one end of the resistor R11 and one end of the resistor R7, the other end of the resistor R7 is sequentially connected to the first terminal of the resistor R55 and one end of the resistor R5, the other end of the resistor R5 is sequentially connected to the other end of the capacitor C6 and one end of the resistor R14, and the other end of the resistor R14 is sequentially connected to the other end of the capacitor C5 and the first terminal of the amplifier U1B.

[0038] In one embodiment, the linearization circuit includes: amplifier U1A, resistor R8, resistor R6, capacitor C2, voltage reference chip Q1, triode Q18, resistor R44, resistor R1, resistor R45, triode Q19, resistor R46, triode Q2, resistor R3, resistor R48, resistor R50, triode Q3, resistor R49, triode Q20, triode Q21, triode R52 and triode R51; wherein, the first end of the triode Q21 is sequentially connected to the third end of the triode Q21, the resistor R52 and one end of the resistor R51, the other end of the resistor R51 is sequentially connected to one end of the resistor R48 and the first end of the triode Q20, the second end of the triode Q20 is connected to one end of the resistor R49, the other end of the resistor R49 is sequentially connected to one end of the resistor R50, one end of the resistor R46, one end of the resistor R45, the second end of the amplifier U1A and one end of the capacitor C1, the other end of the resistor R50 is connected to the second end of the triode Q3, the first end of the triode Q3 is sequentially connected to the other end of the resistor R48 and one end of the resistor R3, the other end of the resistor R3 is sequentially connected to the first end of the triode Q2 and one end of the resistor R1, the second end of the triode Q2 is connected to the other end of the resistor R46; the other end of the resistor R45 is connected to the second end of the triode Q19, the first end of the triode Q19 is sequentially connected to the other end of the resistor R1 and one end of the R44, the other end of the resistor R44 is connected to the first end and the third end of the triode Q18, the second end of the triode Q18 is connected to the first end of the voltage reference chip Q1; the third end of the amplifier U1A is connected to the resistor R8, the other end of the capacitor C1 is connected to the first end of the amplifier U1A, one end of the resistor R6 and one end of the capacitor C2, and the other end of the resistor R6 is connected to the other end of the capacitor C2.

[0039] In one embodiment, by adjusting the resistors, the linearly regulated final output voltage includes:

[0040] By controlling the conduction states of the triodes Q20, Q3, Q2 and Q19, the internal resistors of the linearization circuit are adjusted to achieve linear regulation of the final output voltage.

[0041] The technical solution provided by the embodiments of the present invention may include the following beneficial effects:

[0042] (1)Insufficient suppression of power frequency interference: The present invention adopts a two-stage proportional amplification architecture (inverting + non-inverting), combined with an INA128 instrumentation amplifier (CMRR ≥ 120 dB), to effectively suppress the 50 Hz power frequency common-mode interference. The measured common-mode rejection ratio ≥ 110 dB @ 50 Hz, and the residual power frequency noise ≤ 31.6 μV. The input stage integrates a symmetric RC low-pass filter (R = 10 kΩ, C = 47 nF), with a cut-off frequency of 340 Hz, to attenuate the power frequency harmonic components. A dual-triode mirror current source (250 μA ± 0.5%), combined with a 1.23 V zener diode reference, has a temperature drift ≤ 10 ppm / °C. The conductive resistance separation wiring technology eliminates the ground wire return interference and improves the signal-to-noise ratio of the RTD signal.

[0043] (2)Lack of protection against incorrect power connection, which is likely to damage the device: The present invention supports protection against incorrect connection of 240 VAC. A bidirectional TVS array is deployed at the input stage, combined with a self-recovery fuse (60 V / 0.5 A). It passes the IEC 61000-4-5 surge test (4 kV / 1.2 × 50 μs) and meets the Class IDiv 2 explosion-proof requirements.

[0044] (3)Signal delay caused by multi-stage filtering: V-F / F-V conversion timing control. An integrator + monostable flip-flop architecture (LM331), with a conversion rate of 8.8 kHz and a pulse width of 22 μs. The combination of opto-isolation (HCPL-2630) and Schmitt shaping (74HC14) has an isolation delay ≤ 1 μs. Optimized dynamic response filtering design. A second-order active low-pass filter (cut-off frequency 100 Hz), using phase compensation technology (C5 negative feedback). Compared with the traditional fourth-order filter, the group delay is reduced by 63% (5 ms → 1.85 ms), and the overshoot of the step response ≤ 2%.

[0045] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. Description of the Drawings

[0046] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0047] Figure 1 is a block diagram of an isolated RTD temperature signal conditioning system shown according to an exemplary embodiment;

[0048] Figure 2 is a system block diagram shown according to an exemplary embodiment;

[0049] Figure 3 is a constant current source circuit diagram shown according to an exemplary embodiment;

[0050] Figure 4is an enlarged circuit diagram shown according to an exemplary embodiment;

[0051] Figure 5 is a protection circuit diagram of a dual TVS tube structure shown according to an exemplary embodiment;

[0052] Figure 6 is one of the VF conversion circuit diagrams shown according to an exemplary embodiment;

[0053] Figure 7 is the second VF conversion circuit diagram shown according to an exemplary embodiment;

[0054] Figure 8 is one of the FV conversion circuit diagrams shown according to an exemplary embodiment;

[0055] Figure 9 is the second FV conversion circuit diagram shown according to an exemplary embodiment;

[0056] Figure 10 is a low-pass filter circuit diagram shown according to an exemplary embodiment;

[0057] Figure 11 is one of the linearization circuit diagrams shown according to an exemplary embodiment;

[0058] Figure 12 is the second linearization circuit diagram shown according to an exemplary embodiment;

[0059] Figure 13 is the third linearization circuit diagram shown according to an exemplary embodiment. Detailed implementation manners

[0060] The following description and the accompanying drawings fully disclose specific embodiments herein, enabling those skilled in the art to practice them. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The scope of the embodiments herein includes the entire scope of the claims and all available equivalents of the claims. In this document, the terms "first", "second", etc. are only used to distinguish one element from another, without requiring or implying any actual relationship or order between these elements. In fact, the first element can also be referred to as the second element, and vice versa. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, such that a structure, device or equipment comprising a series of elements not only includes those elements but also other elements not explicitly listed, or also includes elements inherent to such structure, device or equipment. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the structure, device or equipment comprising the said element. The embodiments herein are described in a progressive manner, with each embodiment highlighting the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0061] In this document, the orientation or positional relationships indicated by terms such as "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this document and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In the description herein, unless otherwise specified and defined, the terms "installed", "connected", "joined" shall be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the communication inside two elements. It can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0062] In this document, unless otherwise stated, the term "plurality" means two or more.

[0063] In this document, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0064] In this document, the term "and / or" is a description of the associative relationship of an object, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B these three relationships.

[0065] It should be understood that although the steps in the flowchart are sequentially shown according to the indication of the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0066] Each module in the device or system of the present application can be implemented in whole or in part by software, hardware and their combination. The above-mentioned modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0067] Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0068] Figure 1 An embodiment of an isolated thermoresistance temperature signal conditioning system of the present invention is shown.

[0069] In this alternative embodiment, the isolated thermoresistance temperature signal conditioning system includes:

[0070] A constant current source circuit 1, configured to provide a constant current for the thermoresistance temperature sensor and provide a constant current source for the VF conversion circuit.

[0071] An amplifier circuit 2, configured to transmit the voltage across the thermoresistance temperature sensor to the VF conversion circuit after proportional amplification.

[0072] A VF conversion circuit 3, configured to map an analog voltage to a frequency signal through a closed-loop mechanism of integration, comparison and reset.

[0073] An FV conversion circuit 4, configured to map the frequency signal back to an analog voltage through a chain process of frequency, pulse width and voltage.

[0074] A low-pass filter circuit 5, configured to use a low-pass filter to improve the stability of the analog voltage output by the FV conversion circuit.

[0075] A linearization circuit 6, configured to linearize the finally output voltage by adjusting the resistance;

[0076] The constant current source circuit, the amplifier circuit, the VF conversion circuit, the FV conversion circuit, and the low-pass filter circuit are sequentially and continuously connected.

[0077] In this alternative embodiment, the constant current source circuit includes: diode D3, triode Q17, resistor R36, resistor R67, diode D10, triode Q26, and resistor R37; wherein, one end of the resistor R37 is connected to the first end of the triode Q26, the second end of the triode Q26 is connected to the second end of the triode Q17, the third end of the triode Q17 is connected to the negative electrode of the diode D3, the first end of the triode Q17 is connected to one end of the resistor R36, the third end of the triode Q26 is connected to the negative electrode of the diode D10, and a resistor R67 is further provided on one side of the diode D10.

[0078] In this alternative embodiment, the amplifier circuit includes: resistor R38, resistor R39, resistor R40, amplifier U4A, resistor R36, resistor R68, resistor R66, and amplifier U4B; wherein, the first end of the amplifier U4A is sequentially connected to one end of the resistor R39 and one end of the resistor R40, the other end of the resistor R39 is connected to one end of the resistor R38, the other end of the resistor R38 is sequentially connected to the third end of the amplifier U4A and one end of the resistor R69, the other end of the resistor R69 is sequentially connected to the first end of the amplifier U4B and one end of the resistor R68, the other end of the resistor R68 is connected to one end of the resistor R66, and the other end of the resistor R66 is connected to the third end of the amplifier U4B.

[0079] In this alternative embodiment, the amplifier circuit further includes a dual TVS tube structure protection circuit, and the dual TVS tube structure protection circuit includes: capacitor C23 and diode Q22, and the diode C23 is connected in parallel with the first end and the second end of the diode Q22.

[0080] In this alternative embodiment, the VF conversion circuit includes: switching transistor Q13, switching transistor Q14, capacitor C12, amplifier U5A, resistor R30, resistor R29, resistor R26, capacitor C10, resistor R24, resistor R25, capacitor C14, resistor R35, resistor R41, chip U1, and capacitor C11; wherein, the second terminal of the switching transistor Q13 is sequentially connected to one end of the capacitor C12 and the second terminal of the amplifier U5A, the other end of the capacitor C12 is sequentially connected to the first terminal of the amplifier U5A, the second terminal of the amplifier Q14, one end of the capacitor C10, and one end of the resistor R24, the other end of the capacitor C10 is sequentially connected to the other end of the resistor R24, the resistor R25, and the first terminal of the chip U1, the C1 terminal of the chip U1 is connected to the capacitor C11; the second terminal of the chip U1 is connected to one end of the resistor R26, the other end of the resistor R26 is sequentially connected to one end of the resistor R30, one end of the resistor R29, and the first terminal of the switching transistor Q13, the other end of the resistor R30 is connected to the third terminal of the amplifier U5A, the third terminal of the switching transistor Q13 is connected to the third terminal of the switching transistor Q14, the first terminal of the switching transistor Q14 is sequentially connected to one end of the capacitor C14, one end of the resistor R35, and one end of the resistor R41, and the other end of the resistor R35 is connected to the other end of the capacitor C14.

[0081] In this alternative embodiment, the FV conversion circuit includes: chip U2, resistor R17, capacitor C8, capacitor C9, diode Q4, resistor R15, resistor R54, resistor R22, resistor R58, resistor R21, resistor R20, triode Q8, resistor R61, resistor R56, capacitor C21, amplifier U6A, and triode Q11; wherein, the A2 terminal of the chip U2 is connected to one end of the resistor R17, the other end of the resistor R17 is sequentially connected to one end of the capacitor C9, the A1 terminal and the B2 terminal of the chip U2, the C1 terminal of the chip U2 is connected to one end of the capacitor C8, and the other end of the capacitor C8 is connected to the other end of the capacitor C9; the first terminal of the triode Q8 is sequentially connected to the resistor R21, the resistor R20, and the resistor R58, the second terminal of the triode Q8 is sequentially connected to the second terminal of the amplifier U6A, one end of the capacitor C21, one end of the resistor R61, and one end of the resistor R22, the other end of the resistor R22 is connected to one end of the resistor R54, and the other end of the resistor R54 is sequentially connected to the resistor R15 and the diode Q4; the other end of the resistor R61 is connected to one end of the resistor R56, the other end of the resistor R56 is sequentially connected to the other end of the capacitor C21, the second terminal of the triode Q11, and the first terminal of the amplifier U6A, and the third terminal of the triode Q11 is connected to the third terminal of the triode Q8.

[0082] In this alternative embodiment, mapping the frequency signal back to an analog voltage through a chain process of frequency, pulse width, and voltage includes:

[0083] Isolating the output signal of the VF conversion circuit using an optocoupler, and shaping the output signal of the optocoupler into a square wave signal with the same frequency and fixed width as the -F conversion circuit through a pulse shaping circuit; when the input voltage is at a low level, the triode Q8 is cut off, and the input signal of the proportional amplifier circuit U6A is the reference voltage; when the input voltage is at a high level, the triode Q8 is turned on, and the reference voltage and the constant current source act on the proportional amplifier circuit U6A simultaneously; based on Kirchhoff's theorem, calculating the theoretical value of the output voltage, and obtaining the linear relationship between the output voltage of the FV circuit and the RTD resistance by means of the relationship between the frequency of the input voltage and the resistance of the thermal resistance temperature sensor.

[0084] In this alternative embodiment, the low-pass filter circuit includes: capacitor C6, resistor R5, resistor R7, resistor R55, resistor R11, capacitor C5, amplifier U1B, resistor R9, capacitor C4, and resistor R14; wherein, the third terminal of the amplifier U1B is sequentially connected to one end of the capacitor C4 and one end of the resistor R9, and the other end of the resistor R9 is connected to one end of the capacitor C6; the second terminal of the amplifier U1B is sequentially connected to one end of the capacitor C5 and the third terminal of the resistor R55, the second terminal of the resistor R55 is sequentially connected to one end of the resistor R11 and one end of the resistor R7, the other end of the resistor R7 is sequentially connected to the first terminal of the resistor R55 and one end of the resistor R5, the other end of the resistor R5 is sequentially connected to the other end of the capacitor C6 and one end of the resistor R14, and the other end of the resistor R14 is sequentially connected to the other end of the capacitor C5 and the first terminal of the amplifier U1B.

[0085] In this alternative embodiment, the linearization circuit includes: amplifier U1A, resistor R8, resistor R6, capacitor C2, voltage reference chip Q1, triode Q18, resistor R44, resistor R1, resistor R45, triode Q19, resistor R46, triode Q2, resistor R3, resistor R48, resistor R50, triode Q3, resistor R49, triode Q20, triode Q21, triode R52 and triode R51; wherein, the first end of the triode Q21 is sequentially connected to the third end of the triode Q21, one end of the resistor R52 and one end of the resistor R51, the other end of the resistor R51 is sequentially connected to one end of the resistor R48 and the first end of the triode Q20, the second end of the triode Q20 is connected to one end of the resistor R49, the other end of the resistor R49 is sequentially connected to one end of the resistor R50, one end of the resistor R46, one end of the resistor R45, the second end of the amplifier U1A and one end of the capacitor C1, the other end of the resistor R50 is connected to the second end of the triode Q3, the first end of the triode Q3 is sequentially connected to the other end of the resistor R48 and one end of the resistor R3, the other end of the resistor R3 is sequentially connected to the first end of the triode Q2 and one end of the resistor R1, the second end of the triode Q2 is connected to the other end of the resistor R46; the other end of the resistor R45 is connected to the second end of the triode Q19, the first end of the triode Q19 is sequentially connected to the other end of the resistor R1 and one end of the R44, the other end of the resistor R44 is connected to the first end and the third end of the triode Q18, the second end of the triode Q18 is connected to the first end of the voltage reference chip Q1; the third end of the amplifier U1A is connected to the resistor R8, the other end of the capacitor C1 is connected to the first end of the amplifier U1A, one end of the resistor R6 and one end of the capacitor C2, and the other end of the resistor R6 is connected to the other end of the capacitor C2.

[0086] In this alternative embodiment, by adjusting the resistors, the linearly output voltage includes:

[0087] By controlling the conduction states of the triodes Q20, Q3, Q2 and Q19, the internal resistors of the linearization circuit are adjusted to achieve the linearization adjustment of the finally output voltage.

[0088] To facilitate the understanding of the above technical solution of the present invention, the above technical solution of the present invention will be further described from the perspectives of architecture and principle as follows:

[0089] (1) To address the problem of insufficient power frequency interference suppression, an instrumentation amplifier with a high common-mode rejection ratio is used to suppress common-mode noise, and the hardware filtering design is optimized. Multistage low-pass filtering is employed to eliminate power frequency harmonics, and a mirror constant current source enhances stability.

[0090] (2) To address the problem that the lack of power supply misconnection protection is likely to damage equipment, the present invention uses a double TVS diode clamping method to add a reverse protection circuit and appropriately selects a power supply chip with a wide input voltage range.

[0091] (3) To address the problem of signal delay caused by multistage filtering, the present invention uses VF / FV conversion timing control and adopts a scheme of dynamically adjusting the cut-off frequency, automatically switching filtering parameters according to the signal rate of change, and balancing noise suppression and response speed.

[0092] As Figure 2 shown, the main trunk consists of an excitation current source, a proportional amplification circuit, a VF conversion circuit, an FV conversion circuit, a low-pass filter circuit, and a linearization circuit. Among them, the VF conversion circuit consists of two sub-circuits: an integrator, a monostable flip-flop, and a switching constant current source. The FV conversion circuit consists of a proportional amplification circuit U6A, a switching constant current source, a monostable flip-flop, and some sub-circuits. Figure 2 In the figure, the left side of the dotted line is the circuit before transformer isolation, and the right side of the dotted line is the circuit after transformer isolation.

[0093] 1. Constant current source circuit, as Figure 3 shown.

[0094] The function of this part of the circuit is to provide a constant 250 μA current for the RTD and at the same time provide a constant current source for the VF conversion circuit. Among them, the zener diode D3 can generate a constant 1.23 V voltage when it is broken down, and this voltage is used as the input of the amplification circuit. Two triodes Q17 and Q26 form a mirror current source. The emitter current of the Q26 tube is also 250 μA, and its collector current is also approximately 250 μA. The Q17 tube constant current source is used as the sensor excitation current source, and the Q26 tube provides a constant current source for the V / F conversion circuit.

[0095] 2. Amplification circuit, as Figure 4 shown.

[0096] The amplification circuit consists of two-stage proportional amplification circuits. Its function is to proportionally amplify the voltage across the RTD and then supply it to the V-F conversion circuit. The stable 1.23 V voltage generated by the breakdown of the zener diode D3 in the constant current source circuit is used as the input of the amplification circuit. The voltage across the RTD resistor is 22.4 mV. First, it is amplified by a first-stage inverting amplifier to increase the gain, and then by a non-inverting proportional amplification circuit to increase the output driving ability. After two-stage amplification, the output voltage is 0.9868 V. And U4 is selected as an amplifier with a high common-mode rejection ratio, which suppresses the common-mode noise and improves the problem of insufficient power frequency interference suppression of the RTD at the present stage.

[0097] A dual TVS tube structure protection circuit is added to the traditional proportional amplification circuit part, as follows Figure 5 shown. This part of the circuit is placed between the two ends of the input signal. Among them, the C23 capacitor is equivalent to a low-pass filter, which can filter out high-frequency noise caused by environmental changes; the two zener diodes are equivalent to a voltage protection circuit. When the input voltage is too high, the two zener diodes are broken down, so as to ensure that the input voltage will not be too high, and solve the problem that the device is easily damaged due to the lack of protection against incorrect power connection.

[0098] 3. The V-F conversion circuit is as Figures 6 - 7 shown. Figure 6 The line segment ① and the line segment ② in Figure 7 are respectively connected to the line segment ① and the line segment ② in

[0099] The VF conversion circuit includes two parts: an integrator, a monostable flip-flop, and a switched constant current source. The switched constant current source is composed of the aforementioned constant current source circuit and two switching transistors Q13 and Q14. The integrator integrates the input voltage, the reference voltage, and the constant current source. When Q13 is cut off and Q14 is turned on, the integrator integrates the input voltage and the reference voltage, and the integration capacitor is charged. When the output voltage of the integrator reaches the threshold voltage V L of the monostable flip-flop, the monostable flip-flop outputs a high level with a duration of 1.1R0C0, which makes Q13 conduct and Q14 cut off, and the integrator integrates the constant current source in the reverse direction, and the integration capacitor is discharged. Through the above closed-loop mechanism of integration-comparison-reset, the analog voltage is accurately mapped into a frequency signal, that is, the VF signal conversion is realized. R0 is the series resistance at the reset end of the timer, and C0 is the decoupling capacitor at the reset end.

[0100] 4. The F-V conversion circuit, as Figures 8 - 9 shown.

[0101] The FV conversion circuit includes a proportional amplification circuit U6A, a switched constant current source, and a monostable flip-flop as shown in Figures 8 - 9 , which is mirror-imaged to the VF circuit. In order to improve the anti-interference ability of the circuit, it is necessary to isolate the output signal after the VF conversion circuit, and the isolation effect can be achieved through opto-coupling. Since the system function of the opto-coupling circuit is non-linear, it is necessary to add a pulse shaping circuit after the opto-coupling circuit to shape the output signal of the opto-coupler into a square wave signal with the same frequency and fixed width as the VF conversion circuit, so as to completely transmit the output signal frequency of the VF conversion circuit and control the switching triode in the FV conversion circuit.

[0102] When the input voltage is at a low level, the triode Q8 is cut off, and the input signal of the proportional amplification circuit is the reference voltage. When the input voltage is at a high level, the triode Q8 is turned on, and the reference voltage and the constant current source act on the proportional amplification circuit simultaneously. The output voltage can be decomposed into a DC component and an AC component. Among them, the DC component carries the temperature information of the RTD resistor. Therefore, only considering the DC component, according to Kirchhoff's theorem, the current flowing through the resistor R f is equal to the difference between the current provided by the reference voltage and the average current provided by the constant current source.

[0103] Therefore, the theoretical value of the output voltage:

[0104]

[0105] where: f is the frequency of the input voltage, τ is the time of the high level in one period of the input voltage, T is the period of the input voltage, I c is the current provided by the constant current source, V z is the reference voltage, V O2 is the output voltage of the F / V conversion circuit. The high-level time τ of the input voltage is 22 μs, and the frequency f is 8.8 kHz. Therefore, the theoretical value of the DC component of the output voltage is V O2 = 390.3 mV.

[0106] According to the relationship between f and the RTD resistor, it can be known that:

[0107]

[0108] where: R(T) is the RTD circuit externally connected to the module of the present invention, I c is the current provided by the constant current source, V z is the reference voltage, A u is the amplification factor of the proportional amplification circuit.

[0109] It can be seen from this that the output voltage of the FV circuit is linearly related to the RTD resistor, and the proportional coefficient is related to the current provided by the constant current source. Through the above chain process of frequency - pulse width - voltage, the frequency information is mapped back to an analog voltage, that is, the FV conversion is realized.

[0110] 5. Low-pass filter circuit, as Figure 10 shown.

[0111] The average value of the output voltage of the FV circuit is 147.6 mV, and the difference between the maximum value and the minimum value is as high as 68.6 mV. Therefore, a low-pass filter must be added after the FV conversion circuit to stabilize the output voltage. This low-pass filter selects a second-order filter circuit, and this circuit is as Figure 10, which is composed of two sections of RC filter circuits and a non-inverting proportional amplifier circuit. A negative feedback is introduced between the output of the integrated operational amplifier and the non-inverting input of the integrated operational amplifier. At different frequency bands, the polarity of the feedback is different. When the signal frequency f >> f0 (f0 is the cut-off frequency), the phase shift of each stage of the RC circuit in the circuit tends to -90°, and the phase shift of the two-stage RC circuit reaches -180°. The phase of the output voltage of the circuit is opposite to that of the input voltage. Therefore, at this time, the feedback introduced to the non-inverting terminal of the integrated operational amplifier through the capacitor C5 is negative feedback, and the feedback signal will weaken the input signal, reducing the voltage amplification factor. So this feedback will cause the high-frequency end of the amplitude-frequency characteristic of the second-order active low-pass filter to decay rapidly, only allowing low-frequency end signals to pass, thereby achieving the purpose of filtering, and the present invention avoids the problem of signal delay caused by multi-stage filtering. It should be noted that the amplifier circuit in the low-pass filter circuit part is different from the amplifier circuit in the second part. This part is a single-stage non-inverting proportional amplifier circuit, while the amplifier circuit in the second part is a two-stage proportional amplifier.

[0112] 6. Linearization circuit, such as Figures 11 - 13 shown. Figure 11 The line segment ③ and the line segment ④ in Figure 12 are respectively connected to the line segment ③ and the line segment ④ in Figure 12 The line segment ⑤, the line segment ⑥ and the line segment ⑦ in Figure 13 are respectively connected to the line segment ⑤, the line segment ⑥ and the line segment ⑦ in

[0113] Q21 provides a constant current I e , and provides a constant voltage for the bases of the four transistors Q19, Q2, Q3 and Q20 through multiple resistors. At this time, the base voltages of the four transistors decrease gradually from left to right. At this time, the base voltage of Q20: U b4 = U b7 + I e R 49 = -0.1V,

[0114] U b4 is the base voltage of the transistor Q20, U b7 is the base voltage of the transistor Q21, I e R 49 is the product of the current and the resistance value of the series resistor of Q20.

[0115] Similarly, the base voltages of Q3, Q2, and Q19 are 0.5V, 1.1V, and 1.7V respectively; the input voltages that can turn on Q20, Q3, Q2, and Q19 are 0.6V, 1.2V, 1.8V, and 2.4V respectively. When the input voltage gradually increases, the emitter voltages of the four transistors increase, and the four transistors conduct in sequence from right to left.

[0116] When all four transistors are not conducting, V o = Vi 。

[0117] When Q20 conducts,

[0118] When Q3 conducts,

[0119] When Q2 conducts,

[0120] When Q19 conducts,

[0121] Where: V o is the output voltage, and V i is the input voltage. When the RTD resistance changes non-linearly with temperature, the internal resistance of the linearization circuit can be adjusted to make the final output voltage change linearly with temperature.

[0122] In summary, the constant current source excitation circuit provides a driving current to the RTD sensor. The VF conversion circuit and the FV conversion circuit form an isolated signal transmission channel. The constant current source excitation circuit adopts a mirror current source structure and integrates a temperature compensation resistor R1. The amplifier circuit is an instrumentation amplifier with a common mode rejection ratio ≥ 120 dB and a gain error ≤ 0.01%. The VF conversion circuit includes an integrator and a voltage comparator, and the output frequency satisfies f out = k1·V in , where k1 is the conversion coefficient, and V in is the input voltage of the VF circuit, and the non-linear error ≤ 0.05%. The FV conversion circuit adopts a phase-locked loop structure and includes a voltage-controlled oscillator and a phase comparator, and the conversion linearity ≥ 99.9%. The filter circuit is a three-stage cascaded filter, including: an anti-aliasing filter on the field side with a cut-off frequency f c1 = 1KHZ. A two-pole low-pass filter on the system side with a cut-off frequency f c2 = 100Hz.

[0123] The anti-aliasing filter uses a switched-capacitor filter with a clock frequency 100 times the cut-off frequency. The linearization circuit includes a digital correction module that corrects the non-linear characteristics of the RTD by the piecewise broken line approximation method, and the maximum fitting error ≤ 0.1°C. An opto-isolation module is set between the VF conversion circuit and the FV conversion circuit to improve the withstand voltage level. The power frequency interference rejection ratio of the overall module ≥ 80 dB, and the output ripple voltage ≤ 1mV pp , and the operating temperature range is -40°C - 85°C.

[0124] The present invention is not limited to the structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. An isolated thermal resistance temperature signal conditioning system, characterized in that, Comprising: A constant current source circuit, configured to provide a constant current for a thermal resistance temperature sensor and provide a constant current source for a VF conversion circuit; An amplification circuit, configured to proportionally amplify the voltage across the thermal resistance temperature sensor and transmit it to the VF conversion circuit; A VF conversion circuit, configured to map an analog voltage to a frequency signal through a closed-loop mechanism of integration, comparison, and reset; An FV conversion circuit, configured to map the frequency signal back to an analog voltage through a chain process of frequency, pulse width, and voltage; A low-pass filter circuit, configured to use a low-pass filter to improve the stability of the analog voltage output by the FV conversion circuit; A linearization circuit, configured to linearize the finally output voltage by adjusting the resistance; The constant current source circuit, the amplification circuit, the VF conversion circuit, the FV conversion circuit, the low-pass filter circuit, and the like are sequentially connected.

2. The isolated thermal resistance temperature signal conditioning system according to claim 1, wherein The constant current source circuit includes: diode D3, triode Q17, resistor R36, resistor R67, diode D10, triode Q26, and resistor R37; Wherein, one end of the resistor R37 is connected to the first end of the triode Q26, the second end of the triode Q26 is connected to the second end of the triode Q17, the third end of the triode Q17 is connected to the negative electrode of the diode D3, the first end of the triode Q17 is connected to one end of the resistor R36, the third end of the triode Q26 is connected to the negative electrode of the diode D10, and a resistor R67 is further provided on one side of the diode D10.

3. An isolated thermal resistance temperature signal conditioning system according to claim 1, characterized in that, The amplification circuit includes: resistor R38, resistor R39, resistor R40, amplifier U4A, resistor R36, resistor R68, resistor R66, and amplifier U4B; Wherein, the first end of the amplifier U4A is sequentially connected to one end of the resistor R39 and one end of the resistor R40, the other end of the resistor R39 is connected to one end of the resistor R38, the other end of the resistor R38 is sequentially connected to the third end of the amplifier U4A and one end of the resistor R69, the other end of the resistor R69 is sequentially connected to the first end of the amplifier U4B and one end of the resistor R68, the other end of the resistor R68 is connected to one end of the resistor R66, and the other end of the resistor R66 is connected to the third end of the amplifier U4B.

4. An isolated thermal resistance temperature signal conditioning system according to claim 1, characterized in that, The amplification circuit further includes a dual TVS tube structure protection circuit, and the dual TVS tube structure protection circuit includes: capacitor C23 and diode Q22, and the diode C23 is connected in parallel with the first end and the second end of the diode Q22.

5. An isolated thermal resistance temperature signal conditioning system according to claim 1, characterized in that, The VF conversion circuit includes: switch tube Q13, switch tube Q14, capacitor C12, amplifier U5A, resistor R30, resistor R29, resistor R26, capacitor C10, resistor R24, resistor R25, capacitor C14, resistor R35, resistor R41, chip U1, and capacitor C11; Among them, the second end of the switching transistor Q13 is sequentially connected to one end of the capacitor C12 and the second end of the amplifier U5A. The other end of the capacitor C12 is sequentially connected to the first end of the amplifier U5A, the second end of the amplifier Q14, one end of the capacitor C10, and one end of the resistor R24. The other end of the capacitor C10 is sequentially connected to the other end of the resistor R24, the resistor R25, and the first end of the chip U1. The C1 end of the chip U1 is connected to the capacitor C11; The second end of the chip U1 is connected to one end of the resistor R26. The other end of the resistor R26 is sequentially connected to one end of the resistor R30, one end of the resistor R29, and the first end of the switching transistor Q13. The other end of the resistor R30 is connected to the third end of the amplifier U5A. The third end of the switching transistor Q13 is connected to the third end of the switching transistor Q14. The first end of the switching transistor Q14 is sequentially connected to one end of the capacitor C14, one end of the resistor R35, and one end of the resistor R41. The other end of the resistor R35 is connected to the other end of the capacitor C14.

6. The isolation type thermal resistance temperature signal conditioning system according to claim 1, wherein The FV conversion circuit includes: chip U2, resistor R17, capacitor C8, capacitor C9, diode Q4, resistor R15, resistor R54, resistor R22, resistor R58, resistor R21, resistor R20, triode Q8, resistor R61, resistor R56, capacitor C21, amplifier U6A, and triode Q11; Among them, the A2 end of the chip U2 is connected to one end of the resistor R17. The other end of the resistor R17 is sequentially connected to one end of the capacitor C9, the A1 end and the B2 end of the chip U2. The C1 end of the chip U2 is connected to one end of the capacitor C8. The other end of the capacitor C8 is connected to the other end of the capacitor C9; The first end of the triode Q8 is sequentially connected to the resistor R21, the resistor R20, and the resistor R58. The second end of the triode Q8 is sequentially connected to the second end of the amplifier U6A, one end of the capacitor C21, one end of the resistor R61, and one end of the resistor R22. The other end of the resistor R22 is connected to one end of the resistor R54. The other end of the resistor R54 is sequentially connected to the resistor R15 and the diode Q4; The other end of the resistor R61 is connected to one end of the resistor R56. The other end of the resistor R56 is sequentially connected to the other end of the capacitor C21, the second end of the triode Q11, and the first end of the amplifier U6A. The third end of the triode Q11 is connected to the third end of the triode Q8.

7. The isolation type thermal resistance temperature signal conditioning system according to claim 1, characterized in that, The chain process of frequency, pulse width, and voltage to map the frequency signal back to an analog voltage includes: Using an optocoupler to isolate the output signal of the VF conversion circuit, and through a pulse shaping circuit, shaping the output signal of the optocoupler into a square wave signal with the same frequency and fixed width as the -F conversion circuit; When the input voltage is at a low level, the triode Q8 is cut off, and the input signal of the proportional amplification circuit U6A is the reference voltage; When the input voltage is at a high level, the triode Q8 is turned on, and the reference voltage and the constant current source act on the proportional amplification circuit U6A simultaneously; Based on Kirchhoff's theorem, calculate the theoretical value of the output voltage, and with the help of the relationship between the frequency of the input voltage and the resistance of the thermal resistance temperature sensor, obtain the linear relationship between the output voltage of the FV circuit and the RTD resistance.

8. An isolated thermal resistance temperature signal conditioning system according to claim 1, characterized in that, The low-pass filter circuit includes: capacitor C6, resistor R5, resistor R7, resistor R55, resistor R11, capacitor C5, amplifier U1B, resistor R9, capacitor C4, and resistor R14; Among them, the third terminal of the amplifier U1B is sequentially connected to one end of the capacitor C4 and one end of the resistor R9, and the other end of the resistor R9 is connected to one end of the capacitor C6; The second terminal of the amplifier U1B is sequentially connected to one end of the capacitor C5 and the third terminal of the resistor R55. The second terminal of the resistor R55 is sequentially connected to one end of the resistor R11 and one end of the resistor R7. The other end of the resistor R7 is sequentially connected to the first terminal of the resistor R55 and one end of the resistor R5. The other end of the resistor R5 is sequentially connected to the other end of the capacitor C6 and one end of the resistor R14. The other end of the resistor R14 is sequentially connected to the other end of the capacitor C5 and the first terminal of the amplifier U1B.

9. The isolated thermal resistance temperature signal conditioning system according to claim 1, characterized in that The linearization circuit includes: amplifier U1A, resistor R8, resistor R6, capacitor C2, voltage reference chip Q1, triode Q18, resistor R44, resistor R1, resistor R45, triode Q19, resistor R46, triode Q2, resistor R3, resistor R48, resistor R50, triode Q3, resistor R49, triode Q20, triode Q21, triode R52, and triode R51; Among them, the first terminal of the triode Q21 is sequentially connected to the third terminal of the triode Q21, one end of the resistor R52, and one end of the resistor R51. The other end of the resistor R51 is sequentially connected to one end of the resistor R48 and the first terminal of the triode Q20. The second terminal of the triode Q20 is connected to one end of the resistor R49. The other end of the resistor R49 is sequentially connected to one end of the resistor R50, one end of the resistor R46, one end of the resistor R45, the second terminal of the amplifier U1A, and one end of the capacitor C1. The other end of the resistor R50 is connected to the second terminal of the triode Q3. The first terminal of the triode Q3 is sequentially connected to the other end of the resistor R48 and one end of the resistor R3. The other end of the resistor R3 is sequentially connected to the first terminal of the triode Q2 and one end of the resistor R1. The second terminal of the triode Q2 is connected to the other end of the resistor R46; The other end of the resistor R45 is connected to the second end of the triode Q19. The first end of the triode Q19 is sequentially connected to the other end of the resistor R1 and one end of the R44. The other end of the resistor R44 is connected to the first end and the third end of the triode Q18. The second end of the triode Q18 is connected to the first end of the voltage reference chip Q1; The third end of the amplifier U1A is connected to the resistor R8. The other end of the capacitor C1 is connected to the first end of the amplifier U1A, one end of the resistor R6, and one end of the capacitor C2. The other end of the resistor R6 is connected to the other end of the capacitor C2.

10. A galvanically isolated thermal resistance temperature signal conditioning system according to claim 9, characterized in that, The method of linearizing the finally output voltage by adjusting the resistor includes: By controlling the conduction states of the triodes Q20, Q3, Q2, and Q19, the resistors inside the linearization circuit are adjusted to achieve the linearization adjustment of the finally output voltage.

Images