SRAM (Static Random Access Memory) reinforcement-oriented fine-grained write request processing method considering performance and reliability

Abstract

The SRAM reinforcement-oriented fine-grained write request processing method considering performance and reliability provided by the invention comprises the following steps: after receiving an external write request, judging whether the external write request is a fine-grained write request, and if the external write request is the fine-grained write request, converting the fine-grained write request into a read request; and according to the fine-grained write request, merging the corresponding fine-grained write data with the read return data corresponding to the read request, and writing the merged data item into the SRAM in a full write request mode. Compared with the prior art, the method has the advantages that the fine-grained write request is converted into the read request, so that the transmission bandwidth of an SRAM (Static Random Access Memory) is fully utilized, the resource waste is reduced, and the data reinforcement is realized; in the write processing process, main read-write ports are kept consistent with the SRAM, so that the difficulty of adjusting RTL codes is reduced, and the verification time is shortened; and meanwhile, different error correction algorithms are supported and matched.

Description

Technical Field

[0001] The present invention relates to the technical field of memory read and write processing, and particularly to a fine-grained write request processing method for SRAM hardening. Background Art

[0002] Fine-grained writing means that when writing data in a storage device (such as SRAM, DRAM, etc.), the bit width of the data to be written is significantly smaller than the transfer bit width of the memory. In many application scenarios, the update and management requirements for memory data are relatively strict, and independent write operations need to be performed on specific bits or data units, which results in data being written to the memory in fine granularity.

[0003] However, fine-grained writing also brings some difficulties and challenges: First, fine-grained writing will significantly reduce the utilization rate of the read and write bit width of the memory, resulting in performance degradation. And frequent fine-grained writing may cause data to be filled to the memory bit width, which is likely to cause errors during the transmission process and reduce data reliability. Second, fine-grained writing may lead to concurrent update problems. In a multi-threaded or parallel processing system, performing fine-grained write operations on different parts of the memory simultaneously may trigger race conditions and data consistency problems. Third, fine-grained writing may increase the complexity of memory management. Compared with overall writing, fine-grained writing requires more meticulous data management and control, introducing additional processing logics and algorithms.

[0004] In addition, fine-grained writing may cause memory wear and life problems. Frequent fine-grained write operations may accelerate the erasure and write times of the memory, reducing the service life of the memory.

[0005] Currently, the existing fine-grained write processing technologies for SRAM still have diversity, and there is a lack of unified and concise solutions to some common problems. This will lead to the following problems: increasing the workload of designers. Different designers need to first learn the knowledge of memory read and write access and then carry out the design, and the total design workload will increase; there are a large number of data consistency problems in the fine-grained write processing process of SRAM, and various details need to be properly handled to ensure the correct and reliable SRAM read and write process; Since the processing methods of different designers are different, the verification work for data writing to SRAM, background processing, and data consistency processing needs to be carried out separately, which will increase the verification difficulty and shorten the chip's time to market; if the processing mechanism is not properly handled, it will lead to a decline in the performance of SRAM read and write, and it will cause data to be vulnerable to external influences and errors during the data transmission process, resulting in a decrease in reliability, and at the same time affecting the logic control of the existing memory access pipeline, further exacerbating the difficulty of code modification.

[0006] Therefore, it is an urgent problem for those skilled in the art to provide a fine-grained write request processing method for solving the above problems. Summary of the Invention

[0007] The object of the present invention is to provide a fine-grained write request processing method for SRAM hardening that takes into account both performance and reliability. This method has clear logic, is safe, effective, reliable and easy to operate, and can effectively improve processing performance and reliability.

[0008] Based on the above object, the technical solution provided by the present invention is as follows: A fine-grained write request processing method for SRAM hardening that takes into account both performance and reliability, including the following steps: Receive an external write request and determine whether the external write request is a fine-grained write request; If so, write to the SRAM according to the different methods selected by the user according to the fine-grained write request; When the fast write mode is selected, according to the fine-grained write request, write the corresponding fine-grained write data into the SRAM, and use a preset signal as the fine-grained write identifier; When the reliable write mode is selected, convert the fine-grained write request into a read request; obtain the read return data corresponding to the read request; according to the fine-grained write request, merge the corresponding fine-grained write data with the read return data, and write it into the SRAM in a full write request mode.

[0009] Preferably, it further includes: If the fine-grained write request is in different scenarios, perform consistency processing on the corresponding fine-grained write data; Then the corresponding fine-grained write data is the fine-grained write data after consistency processing.

[0010] Preferably, the writing to the SRAM according to the different methods selected by the user according to the fine-grained write request includes the following steps: Determine whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer; If so, merge the corresponding fine-grained write data and the data of the corresponding item in the background buffer, and then insert the merged data item into the background buffer; When idle, write the merged data item from the background buffer to the SRAM in a full write request mode.

[0011] Preferably, after determining whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer, the following steps are further included: If not, compare whether the memory access address of the fine-grained write request is the same as the memory access address of the item to be written into the corresponding item in the background buffer; If the memory access addresses of the two are the same, the fine-grained write data is merged with the data to be written to the corresponding item in the background buffer, and the merged data item is inserted into the background buffer. When idle, the merged data item is written into the SRAM in the form of a full write request from the background buffer; If the memory access addresses of the two are different and the fast write mode is selected, the fine-grained write data is written to the corresponding address in the SRAM, and a preset signal is used as the fine-grained write identifier; If the memory access addresses of the two are different and the reliable write mode is selected, a read request is sent to the SRAM to obtain the read return data corresponding to the fine-grained write request address of the SRAM. After merging the read return data with the fine-grained write data, the merged data item is inserted into the background buffer. When idle, the merged data item is written into the SRAM in the form of a full write request from the background buffer.

[0012] Preferably, when the reliable write mode is selected, the fine-grained write request is converted into a read request; the read return data corresponding to the read request is obtained; according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data and written into the SRAM in the form of a full write request, including the following steps: Judge whether the first read request is caused by the fine-grained write request. If so, send the first read request to the SRAM to obtain the first read return data corresponding to the fine-grained write request address of the SRAM; Receive the second read request; After obtaining the first read return data corresponding to the fine-grained write request address of the SRAM, judge whether the memory access addresses of the first read request and the second read request are the same; If so, invalidate the second read request, and bypass the first read return data as the read return data of the second read request; If not, send the second read request to the SRAM to obtain the second read return data corresponding to the fine-grained write request address of the SRAM; After merging the second read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer; When idle, the merged data item is written into the SRAM in the form of a full write request from the background buffer.

[0013] Preferably, when the reliable write mode is selected, the fine-grained write request is converted into a read request; the read return data corresponding to the read request is obtained; according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data and written into the SRAM in the form of a full write request, further including the following steps: Determine whether the third read request is caused by the first fine-grained write request. If so, send the third read request to the SRAM and obtain the third read return data corresponding to the address of the first fine-grained write request of the SRAM. Receive the second fine-grained write request, and determine whether the second fine-grained write request is a full write request. If so, write to the SRAM when idle. If not, then determine whether the memory access addresses of the third write request and the second fine-grained write request are the same. If they are the same, invalidate the fourth read request converted from the second fine-grained write request, and bypass the third read return data as the fourth read return data. After merging the fourth read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer. Write the merged data item from the background buffer to the SRAM in the form of a full write request when idle.

[0014] Preferably, when the reliable write mode is selected, convert the fine-grained write request into a read request; obtain the read return data corresponding to the read request; according to the fine-grained write request, merge the corresponding fine-grained write data with the read return data, and write to the SRAM in the form of a full write request. The method further includes the following steps: Determine whether the first write request is the fine-grained write request. If so, send a fifth read request to the SRAM to obtain the fifth read return data corresponding to the address of the fine-grained write request of the SRAM. If not, send the first write request to the SRAM and write to the SRAM when idle. Before merging the fifth read return data with the data of the corresponding item to be written into the background buffer, determine whether a sixth read request is received. If so, compare whether the memory access addresses of the fifth read request and the sixth read request are the same. If they are the same, invalidate the sixth read request, and bypass the fifth read return data as the sixth read return data. If the sixth read request is not received, before inserting the merged data item into the background buffer, determine whether a seventh read request is received. If so, compare whether the merged data item and the memory access address of the seventh read request are the same. If they are the same, invalidate the seventh read request, and bypass the merged data item in the background buffer as the sixth read return data. If the seventh read request is not received, send the seventh read request to the SRAM to obtain the seventh read return data corresponding to the address of the fine-grained write request of the SRAM. After merging the sixth read return data or the seventh read return data with the fine-grained write data after consistency processing, inserting the merged data item into a background buffer; When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

[0015] Preferably, when the reliable write mode is selected, the fine-grained write request is converted into a read request; the read return data corresponding to the read request is obtained; according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request mode, and the following steps are also included: Determine whether the memory access addresses of the second write request and the third write request are the same; If they are the same, the second write request is invalidated, and it is determined whether the third write request is a fine-grained write; If yes, send an eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data; After merging the eighth read return data with the third fine-grained write data, inserting the merged data item into a background buffer; writing the merged data item from the background buffer into the SRAM in a full write request mode when idle; If they are not the same, determining whether the third write request is a fine-grained write; If yes, send the eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data; After merging the eighth read return data with the third fine-grained write data, inserting the merged data item into the background buffer; writing the merged data item from the background buffer to the SRAM in a full write request mode when idle; If the third write request is not a fine-grained write, the third write request is sent to the SRAM and written into the SRAM when idle.

[0016] The fine-grained write request processing method for SRAM reinforcement that takes into account both performance and reliability includes the following steps: after receiving an external write request, determining whether the external write request is a fine-grained write request, and if it is a fine-grained write request, converting the fine-grained write request into a read request; merging the corresponding fine-grained write data with the read return data corresponding to the read request according to the fine-grained write request, and writing the merged data item into the SRAM in a full write request manner.

[0017] Compared with the prior art, the present invention converts fine-grained write requests into read requests, fully utilizes the transmission bandwidth of SRAM, reduces resource waste, and realizes data hardening. During the write processing, the main read and write ports are consistent with SRAM, reducing the difficulty of adjusting RTL code and the verification time. At the same time, it supports different error correction algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a flowchart of a fine-grained write request processing method that takes into account both performance and reliability provided by an embodiment of the present invention; Figure 2 It is a flowchart of step S2 provided by an embodiment of the present invention; Figure 3 It is a flowchart after step A1 provided by an embodiment of the present invention; Figure 4 It is a flowchart of using reliable writing to process fine-grained write requests in the read-after-read scenario in step S32 provided by an embodiment of the present invention; Figure 5 It is a flowchart of using reliable writing to process fine-grained write requests in the read-after-write scenario in step S32 provided by an embodiment of the present invention; Figure 6 It is a flowchart of using reliable writing to process fine-grained write requests in the write-after-read scenario in step S32 provided by an embodiment of the present invention; Figure 7 It is a flowchart of using reliable writing to process fine-grained write requests in the write-after-write scenario in step S32 provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0021] The embodiments of the present invention are written in a progressive manner.

[0022] An embodiment of the present invention provides a fine-grained write request processing method, which mainly solves the technical problems of resource waste, high verification difficulty, and high difficulty in adjusting RTL code in the prior art.

[0023] As Figure 1 shown, a fine-grained write request processing method for SRAM hardening that takes into account both performance and reliability includes the following steps: S1. Receive an external write request and determine whether the external write request is a fine-grained write request; S2. If so, write to the SRAM according to the fine-grained write request in different ways selected by the user; In steps S1 to S2, when the front-end receives an external write request, it determines whether the external write request is a fine-grained write. When the fine-grained write signal is high, the corresponding written data is fine-grained write data. According to the fine-grained write request and the selected write method, it is written into the SRAM correspondingly; It should be noted that a static random access memory (SRAM) is a type of random access memory. The so-called "static" means that as long as this memory remains powered on, the data stored in it can be constantly maintained. SRAM is mainly used for level 2 cache (Level2 Cache). It uses transistors to store data. Compared with DRAM, SRAM is faster, but in the same area, the capacity of SRAM is smaller than that of other types of memory.

[0024] S31. When the fast write mode is selected, write the corresponding fine-grained write data into the SRAM according to the fine-grained write request, and use a preset signal as the fine-grained write identifier; S32. When the reliable write mode is selected, convert the fine-grained write request into a read request; obtain the read return data corresponding to the read request; according to the fine-grained write request, merge the corresponding fine-grained write data with the read return data, and write it into the SRAM in a full write request mode.

[0025] In steps S31 and S32, two write modes are designed. The first is fast write, that is, according to the fine-grained write request, the corresponding fine-grained write data is written into the SRAM, and a preset signal is used as the fine-grained write identifier; the second is reliable write, that is, the fine-grained write request is converted into a read request, the read return data corresponding to the read request is obtained, and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data and written into the SRAM in a full write request mode; In this embodiment, the fast writing method is specifically as follows: without using EDAC encoding, directly write the fine-grained write data into the SRAM, and at the same time use an additional bit signal as the fine-grained write identifier; while the reliable writing method is specifically as follows: convert the fine-grained write request into a read request; according to the fine-grained write request, merge the corresponding fine-grained write data with the read return data and then write it into the SRAM in a full write request manner through EDAC encoding.

[0026] Preferably, it further includes: If the fine-grained write requests are in different scenarios, perform consistency processing on the corresponding fine-grained write data; Then the corresponding fine-grained write data is the fine-grained write data after consistency processing.

[0027] In the actual operation process, when it is determined that the external write request is a fine-grained write request, during the execution of the fine-grained write processing, there may be a situation of data inconsistency. Correspondingly, perform data consistency processing according to different scenarios. Then step S31 corresponds to: when the fast writing method is selected, according to the fine-grained write request, write the corresponding fine-grained write data after consistency processing into the SRAM, and use a preset signal as the fine-grained write identifier; step S32 corresponds to: when the reliable writing method is selected, convert the fine-grained write request into a read request, obtain the read return data corresponding to the read request, and according to the fine-grained write request, merge the corresponding fine-grained write data after consistency processing with the read return data and write it into the SRAM in a full write request manner.

[0028] As Figure 2 shown, preferably, step S2 includes the following steps: A1. Determine whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer; A2. If so, merge the corresponding fine-grained write data with the data of the corresponding item in the background buffer, and then insert the merged data item into the background buffer; A3. When idle, write the merged data item from the background buffer into the SRAM in a full write request manner.

[0029] In steps A1 to A3, determine whether the address of the fine-grained write request is the same as the corresponding item in the background buffer. If the same, merge the fine-grained write data with the data of the corresponding item in the background buffer, and then insert the merged data item into the background buffer. When idle, write the merged data item from the background buffer into the SRAM in a full write request manner.

[0030] It should be noted that the background buffer module is used to manage the data and corresponding addresses after the read request corrects errors, as well as the data and corresponding addresses obtained by superimposing the fine-grained write data and the original position data. The background buffer will write the buffered data into the SRAM item by item according to the corresponding address and delete the corresponding entry in the buffer; In this embodiment, for a foreground fine-grained write request, first compare whether the address of the request is the same as the item in the background buffer. If they are the same, after merging the fine-grained write data and the data of the corresponding item in the background buffer, insert the merged data into the background buffer, and write the data item from the background buffer into the SRAM when the device is idle.

[0031] As Figure 3 shown, preferably, after step A1, the following steps are further included: B1. If not, then compare whether the memory access address of the fine-grained write request is the same as the memory access address of the item to be written into the corresponding item in the background buffer; B21. If the memory access addresses of both are the same, then merge the fine-grained write data and the data of the item to be written into the corresponding item in the background buffer, and insert the merged data item into the background buffer. When idle, write the merged data item from the background buffer into the SRAM in the form of a full write request; B22. If the memory access addresses of both are different, and when the fast write mode is selected, write the fine-grained write data to the corresponding address in the SRAM, and use a preset signal as the fine-grained write identifier; B23. If the memory access addresses of both are different, and when the reliable write mode is selected, send a read request to the SRAM to obtain the read return data corresponding to the fine-grained write request address of the SRAM. After merging the read return data and the fine-grained write data, insert the merged data item into the background buffer. When idle, write the merged data item from the background buffer into the SRAM in the form of a full write request.

[0032] In steps B1 to B23, after determining whether the address of the fine-grained write request is the same as the corresponding item in the background buffer, if the address of the fine-grained write request is different from the corresponding item in the background buffer, then compare whether the access address of the fine-grained write request is the same as the data of the corresponding item to be written into the background buffer; if both are the same, then merge the fine-grained write data and the data of the corresponding item to be written into the background buffer, insert the merged data item into the background buffer, and when idle, write the merged data item from the background buffer into the SRAM in the form of a full write request; if both are different, then divide it into two different cases of fast write and reliable write. When the fast write mode is selected, write the fine-grained write data to the corresponding address in the SRAM, and use a preset signal as the fine-grained write identifier; when the reliable write mode is selected, send a read request to the SRAM to obtain the read return data corresponding to the fine-grained write request address of the SRAM, merge the read return data and the fine-grained write data, insert the merged data item into the background buffer, and when idle, write the merged data item from the background buffer into the SRAM in the form of a full write request.

[0033] As Figure 4 shown, preferably, step S32 includes the following steps: C1. Determine whether the first read request is caused by a fine-grained write request. If so, send the first read request to the SRAM and obtain the first read return data corresponding to the fine-grained write request address of the SRAM; C2. Receive the second read request; C3. After obtaining the first read return data corresponding to the fine-grained write request address of the SRAM, determine whether the memory access addresses of the first read request and the second read request are the same; C41. If so, invalidate the second read request and output the first read return data through the bypass as the read return data of the second read request; C42. If not, send the second read request to the SRAM and obtain the second read return data corresponding to the fine-grained write request address of the SRAM; C5. After merging the second read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer; C6. When idle, write the merged data item from the background buffer to the SRAM in the full write request mode.

[0034] Steps C1 to C6 are specifically applied to the read-after-read scenario, that is, the situation where two read requests are successively sent to the SRAM due to receiving or a fine-grained write turning into a read; receive the first read request and the second read request, determine whether the received first read request is caused by a fine-grained write request. If so, send the first read request to the SRAM and obtain the first read return data corresponding to the fine-grained write request address of the SRAM; after obtaining the first read return data, determine whether the memory access addresses between the first read request and the second read request are the same. If the same, invalidate the second read request and output the first read return data through the bypass as the read return data of the second read request; if different, send the second read request to the SRAM and obtain the second read return data corresponding to the fine-grained write request address of the SRAM; In this embodiment, for the received read request 1, the device will first determine whether read request 1 is caused by a fine-grained write request. If so, send read request 1 to the SRAM, and the data returned by the SRAM is the first read request return data; if a new read request 2 is received before the current step, read request 2 will go through the same steps as read request 1 and then determine whether their memory access addresses are the same. If the same, invalidate read request 2 and output the read request 1 return data through the bypass as the read request 2 return data. Otherwise, at this time, read request 2 can be regarded as a new read request 1, and the data returned by the SRAM is the second read request return data.

[0035] As Figure 5 shown, preferably, step S32 further includes the following steps: D1. Determine whether the third read request is caused by the first fine-grained write request. If so, send the third read request to the SRAM to obtain the third read return data corresponding to the address of the first fine-grained write request of the SRAM. D21. Receive the second fine-grained write request, and determine whether the second fine-grained write request is a full write request. If so, write it into the SRAM when idle. D22. If not, determine whether the memory access addresses of the third write request and the second fine-grained write request are the same. D3. If they are the same, invalidate the fourth read request converted from the second fine-grained write request, and output the third read return data through bypass as the fourth read return data. D4. After merging the fourth read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer. D5. Write the merged data item from the background buffer into the SRAM in the form of a full write request when idle.

[0036] Steps D1 to D5 are applied to the read-after-write scenario, that is, the situation where a new write request is received after sending a read request to the SRAM due to receiving or converting from a fine-grained write to a read; determine whether the received third read request is caused by the first fine-grained write request. If so, send the third read request to the SRAM to obtain the third read return data corresponding to the address of the first fine-grained write request of the SRAM; receive the second fine-grained write request, and determine whether the second fine-grained write request is a full write request. If the second fine-grained write request is a full write request, write it into the SRAM when idle; if the second fine-grained write request is not a full write request, determine whether the memory access addresses of the third write request and the second fine-grained write request are the same; if they are the same, invalidate the fourth read request converted from the second fine-grained write request, and output the third read return data through bypass as the fourth read return data; after merging the fourth read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer, and write the merged data item from the background buffer into the SRAM in the form of a full write request when idle.

[0037] It should be noted that bypass means that two networks can be directly physically connected without passing through the network security device system through a specific trigger state (power-off or crash). Therefore, with bypass, when the network security device fails, the networks connected to this device can still be connected to each other. Of course, at this time, this network device will no longer process the packets in the network.

[0038] In this embodiment, for the received third read request, it is first determined whether the read request is caused by a fine-grained write request. A read request 1 is sent to the SRAM, and the data returned by the SRAM is the data returned by the read request 1. At this time, if a new second fine-grained write request is received, if the second fine-grained write request is a full write request, it is written into the SRAM when idle. If the second fine-grained write request is not a full write request, it is determined whether the memory access addresses of the read request and the second write request are the same. If they are the same, the read request 2 converted from the second write request is invalidated, and the data returned by the read request 1 is output bypassed as the data returned by the read request 2. The data returned by the read request 2 is merged with the fine-grained write data after consistency processing, and the merged data item is inserted into the background buffer; it is written into the SRAM when the device is idle.

[0039] As Figure 6 shown, preferably, step S32 further includes the following steps: E1. Determine whether the first write request is a fine-grained write request; E21. If so, send a fifth read request to the SRAM to obtain the fifth read return data corresponding to the fine-grained write request address of the SRAM; E22. If not, send the first write request to the SRAM and write it into the SRAM when idle; E3. Before merging the fifth read return data with the data of the corresponding item to be written into the background buffer, determine whether a sixth read request is received; E41. If so, compare whether the memory access addresses of the fifth read request and the sixth read request are the same; E51. If they are the same, invalidate the sixth read request, and output the fifth read return data bypassed as the sixth read return data; E42. If the sixth read request is not received, before inserting the merged data item into the background buffer, determine whether a seventh read request is received; E52. If so, compare whether the memory access addresses of the merged data item and the seventh read request are the same; E62. If they are the same, invalidate the seventh read request, and output the merged data item in the background buffer bypassed as the sixth read return data; E53. If the seventh read request is not received, send a seventh read request to the SRAM to obtain the seventh read return data corresponding to the fine-grained write request address of the SRAM; E7. After merging the sixth read return data or the seventh read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer; E8. Write the merged data item from the background buffer into the SRAM in the form of a full write request when idle.

[0040] Steps E1 to E8 are applied to the write-after-read scenario, that is, the situation where a new read request is received after a write request is received or a read request is sent to the SRAM due to a fine-grained write-to-read transition. Specifically, it is determined whether the received first write request is a fine-grained write request. If so, a fifth read request is sent to the SRAM to obtain the fifth read return data corresponding to the address of the fine-grained write request of the SRAM. If the first write request is not a fine-grained write request, the first write request is sent to the SRAM and written to the SRAM when idle; before merging the fifth read return data with the data of the corresponding item to be written to the background buffer, it is first determined whether a sixth read request is received. If a sixth read request is received, it is compared whether the memory access addresses between the fifth read request and the sixth read request are the same; if the two are the same, the sixth read request is invalidated, and the fifth read return data is output as the sixth read return data through the bypass; if the sixth read request is not received, the merged data item composed of the fifth read return data and the data of the corresponding item to be written to the background buffer is inserted into the background buffer. Before that, it is first determined whether a seventh read request is received. If a seventh read request is received, it is compared whether the memory access address of the merged data item is the same as that of the seventh read request. If the two are the same, the seventh read request is invalidated, and the merged data item in the background buffer is output as the sixth read return data through the bypass; if the seventh read request is not received, a seventh read request is sent to the SRAM to obtain the seventh read return data corresponding to the address of the fine-grained write request of the SRAM. After merging the sixth read return data or the seventh read return data with the fine-grained write data after consistency processing, the merged data item is inserted into the background buffer and written to the SRAM in the form of a full write request from the background buffer when idle.

[0041] In this embodiment, for the received first write request, it is first determined whether the write request is a fine-grained write. If so, a fifth read request 1 is sent to the SRAM, and the data returned by the SRAM is the data returned by the fifth read request 1. If not, the first write request is sent to the SRAM, and the data is written to the SRAM when idle; the fifth read return data is merged with the data to be written. If a new sixth read request is received before that, the memory access addresses of the two are compared. If they are the same, the sixth read request 2 is invalidated, and the merged data is output as the data returned by the sixth read request 2 through the bypass; if there is no new read request, the merged data item is inserted into the background buffer. If a new seventh read request is received before that, the memory access addresses of the two are compared. If they are the same, the seventh read request 2 is invalidated, and the background buffer data is output as the data returned by the read request 2 through the bypass; if there is no new read request, the data returned by the SRAM is the data returned by the read request 2. After merging the read return data with the fine-grained write data after consistency processing, the merged data item is inserted into the background buffer and written to the SRAM in the form of a full write request from the background buffer when idle.

[0042] As Figure 7 shown, preferably, step S32 further includes the following steps: F1. Determine whether the memory access addresses of the second write request and the third write request are the same; F21. If they are the same, invalidate the second write request and determine whether the third write request is a fine-grained write; F31. If so, send an eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data; F4. After merging the eighth read return data and the third fine-grained write data, insert the merged data item into the background buffer; when idle, write the merged data item from the background buffer to the SRAM in the form of a full write request; F22. If they are not the same, determine whether the third write request is a fine-grained write; F32. If so, send an eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data; F4. After merging the eighth read return data and the third fine-grained write data, insert the merged data item into the background buffer; when idle, write the merged data item from the background buffer to the SRAM in the form of a full write request; F33. If the third write request is not a fine-grained write, send the third write request to the SRAM and write it to the SRAM when idle.

[0043] Steps F1 to F4 are applied to the write-after-write scenario, that is, the situation where a new write request is received after a write request. Specifically, for the received second write request and the newly received third write request, first determine whether the memory access addresses of the two are the same. If they are the same, invalidate the second write request and determine whether the third write request is a fine-grained write. If the third write request is a fine-grained write, send an eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and correspondingly obtain the third fine-grained write data; after merging the eighth read return data and the third fine-grained write data, insert the merged item into the background buffer, and when idle, write the merged data item from the background buffer to the SRAM in the form of a full write request; if the memory access addresses of the second write request and the third write request are different, determine whether the third write request is a fine-grained write. If the third write request is a fine-grained write, send an eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request of the SRAM, and obtain the third fine-grained write data. After merging the eighth read return data and the third fine-grained write data, insert the merged data item into the background buffer. If the third write request is not a fine-grained write, send the third write request to the SRAM and write it to the SRAM when idle.

[0044] In this embodiment, for the received second write request 1, if a new third write request 2 is received at this time, it will first determine whether the memory access addresses of the two are the same. If they are the same, the second write request 1 will be invalidated. Then it will determine whether the third write request 2 is a fine-grained write. If so, a read request will be sent to the SRAM, and the data returned by the SRAM is the read request return data. Correspondingly, the third fine-grained write data will be obtained, the read request return data will be merged with the fine-grained write request data, the merged data item will be inserted into the background buffer, and when idle, the merged data item will be written into the SRAM in the form of a full write request from the background buffer. If the memory access addresses of the second write request 1 and the third write request 2 are different, it will determine whether the third write request 2 is a fine-grained write. If so, a read request will be sent to the SRAM, and the data returned by the SRAM is the read request return data. Correspondingly, the third fine-grained write data will be obtained, the read request return data will be merged with the fine-grained write request data, the merged data item will be inserted into the background buffer, and when idle, the merged data item will be written into the SRAM in the form of a full write request from the background buffer. If the third write request 2 is not a fine-grained write, a third write request will be sent to the SRAM and written into the SRAM when idle.

[0045] In the embodiments provided in the present application, it should be understood that the disclosed method can be implemented in other ways. The above-described embodiments are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed with each other can be through some interfaces, indirect coupling or communication connection of devices or modules, and can be electrical, mechanical, or other forms.

[0046] In addition, in each embodiment of the present invention, each functional module can be all integrated in one processor, or each module can be separately used as a device alone, or two or more modules can be integrated in one device; each functional module in each embodiment of the present invention can be implemented in the form of hardware, or can be implemented in the form of hardware plus software functional units.

[0047] Those of ordinary skill in the art can understand that all or part of the steps to implement the above method embodiments can be completed through program instructions and related hardware. The foregoing program instructions can be stored in a computer-readable storage medium. When the program instructions are executed, the steps including the above method embodiments are executed; and the foregoing storage medium includes: various media such as removable storage devices, read-only memory (ROM), magnetic disks, or optical discs that can store program codes.

[0048] As shown in this application and the claims, unless the context clearly indicates otherwise, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. A method or device may also include other steps or elements. An element defined by the statement "comprising one..." does not exclude the existence of other identical elements in the process, method, article, or device that includes the element.

[0049] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0050] If a flowchart is used in this application, the flowchart is used to illustrate the operations performed by the system according to the embodiments of this application. It should be understood that the operations before or after may not necessarily be executed precisely in sequence. On the contrary, the steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes, or one or several steps may be removed from these processes.

[0051] The above has introduced in detail a fine-grained write request processing method for SRAM hardening that takes into account both performance and reliability provided by the present invention. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will conform to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fine-grained write request processing method for SRAM hardening that takes into account both performance and reliability, characterized in that, It includes the following steps: Receive an external write request and determine whether the external write request is a fine-grained write request; If so, write to the SRAM in different ways selected by the user according to the fine-grained write request; When the fast write mode is selected, according to the fine-grained write request, write the corresponding fine-grained write data into the SRAM, and use a preset signal as the fine-grained write identifier; When the reliable write mode is selected, convert the fine-grained write request into a read request; Obtain the read return data corresponding to the read request; According to the fine-grained write request, merge the corresponding fine-grained write data with the read return data and write it into the SRAM in a full write request manner.

2. The fine-grained write request processing method for SRAM reinforcement taking into account both performance and reliability as claimed in claim 1, characterized in that: It also includes: If the fine-grained write request is in different scenarios, perform consistency processing on the corresponding fine-grained write data; Then the corresponding fine-grained write data is the fine-grained write data after consistency processing.

3. The fine-grained write request processing method for SRAM reinforcement taking into account both performance and reliability as claimed in claim 1, characterized in that: The writing to the SRAM in different ways selected by the user according to the fine-grained write request includes the following steps: Determine whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer; If so, merge the corresponding fine-grained write data and the data of the corresponding item in the background buffer, and insert the merged data item into the background buffer; When idle, write the merged data item from the background buffer to the SRAM in a full write request manner.

4. The fine-grained write request processing method for SRAM reinforcement taking into account both performance and reliability as claimed in claim 3, characterized in that: After determining whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer, the following steps are also included: If not, compare whether the memory access address of the fine-grained write request is the same as the memory access address of the item to be written into the corresponding item in the background buffer; If the memory access addresses of both are the same, merge the fine-grained write data with the data of the item to be written into the corresponding item in the background buffer, insert the merged data item into the background buffer, and when idle, write the merged data item from the background buffer to the SRAM in a full write request manner; If the memory access addresses of both are different, and when the fast write mode is selected, write the fine-grained write data to the corresponding address in the SRAM and use a preset signal as the fine-grained write identifier; If the memory access addresses of both are different, and when the reliable write mode is selected, send a read request to the SRAM, obtain the read return data corresponding to the fine-grained write request address of the SRAM, merge the read return data with the fine-grained write data, insert the merged data item into the background buffer, and when idle, write the merged data item from the background buffer to the SRAM in a full write request manner.

5. The fine-grained write request processing method for SRAM reinforcement taking into account both performance and reliability as claimed in claim 1, characterized in that: When the reliable write mode is selected, convert the fine-grained write request into a read request; obtain the read return data corresponding to the read request; according to the fine-grained write request, merge the corresponding fine-grained write data with the read return data and write it into the SRAM in a full write request manner, including the following steps: Determine whether the first read request is caused by the fine-grained write request. If so, send the first read request to the SRAM and obtain the first read return data corresponding to the fine-grained write request address of the SRAM; Receive the second read request; After obtaining the first read return data corresponding to the fine-grained write request address of the SRAM, determine whether the memory access addresses of the first read request and the second read request are the same; If so, invalidate the second read request, and bypass the first read return data as the read return data of the second read request; If not, send a second read request to the SRAM to obtain the second read return data corresponding to the fine-grained write request address of the SRAM; After merging the second read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer; When idle, write the merged data item from the background buffer to the SRAM in a full write request manner.

6. The fine-grained write request processing method for SRAM reinforcement taking into account both performance and reliability as claimed in claim 1, characterized in that: When the reliable write mode is selected, convert the fine-grained write request into a read request; obtain the read return data corresponding to the read request; according to the fine-grained write request, merge the corresponding fine-grained write data with the read return data, and write it to the SRAM in a full write request manner, and further includes the following steps: Determine whether the third read request is caused by the first fine-grained write request. If so, send the third read request to the SRAM to obtain the third read return data corresponding to the first fine-grained write request address of the SRAM; Receive the second fine-grained write request, and determine whether the second fine-grained write request is a full write request. If so, write it to the SRAM when idle; If not, determine whether the memory access addresses of the third write request and the second fine-grained write request are the same; If they are the same, invalidate the fourth read request converted from the second fine-grained write request, and bypass the third read return data as the fourth read return data; After merging the fourth read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer; When idle, write the merged data item from the background buffer to the SRAM in a full write request manner.

7. The fine-grained write request processing method for SRAM reinforcement taking into account both performance and reliability as claimed in claim 1, characterized in that: When the reliable write mode is selected, convert the fine-grained write request into a read request; obtain the read return data corresponding to the read request; according to the fine-grained write request, merge the corresponding fine-grained write data with the read return data, and write it to the SRAM in a full write request manner, and further includes the following steps: Determine whether the first write request is the fine-grained write request; If so, send a fifth read request to the SRAM to obtain the fifth read return data corresponding to the fine-grained write request address of the SRAM. If not, send the first write request to the SRAM and write it to the SRAM when idle; Before merging the fifth read return data with the data of the corresponding item to be written into the background buffer, determine whether the sixth read request is received. If so, compare whether the memory access addresses of the fifth read request and the sixth read request are the same; If they are the same, invalidate the sixth read request, and bypass the fifth read return data as the sixth read return data; If the sixth read request is not received, before inserting the merged data item into the background buffer, determine whether the seventh read request is received. If so, compare whether the memory access addresses of the merged data item and the seventh read request are the same; If they are the same, invalidate the seventh read request, and output the merged data item in the background buffer as the sixth read return data through bypass. If the seventh read request is not received, send the seventh read request to the SRAM to obtain the seventh read return data corresponding to the fine-grained write request address of the SRAM. After merging the sixth read return data or the seventh read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer. When idle, write the merged data item from the background buffer to the SRAM in the form of a full write request.

8. The fine-grained write request processing method for SRAM reinforcement taking into account both performance and reliability as claimed in claim 1, characterized in that: When the reliable write mode is selected, convert the fine-grained write request into a read request; obtain the read return data corresponding to the read request; according to the fine-grained write request, merge the corresponding fine-grained write data with the read return data and write it to the SRAM in the form of a full write request, and further include the following steps: Judge whether the memory access addresses of the second write request and the third write request are the same. If they are the same, invalidate the second write request, and judge whether the third write request is a fine-grained write. If so, send an eighth read request to the SRAM to obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data. After merging the eighth read return data with the third fine-grained write data, insert the merged data item into the background buffer; when idle, write the merged data item from the background buffer to the SRAM in the form of a full write request. If they are not the same, judge whether the third write request is a fine-grained write. If so, send the eighth read request to the SRAM to obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data. After merging the eighth read return data with the third fine-grained write data, insert the merged data item into the background buffer; when idle, write the merged data item from the background buffer to the SRAM in the form of a full write request. If the third write request is not a fine-grained write, send the third write request to the SRAM and write it to the SRAM when idle.

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