A carry chain optimization method and device for FPGA synthesis tools for consecutive additions of the same number

Abstract

The present application provides a method and device for optimizing the carry chain in an FPGA synthesis tool for consecutive additions of the same number. The method includes: obtaining the same signal and the number of consecutive additions n in a first addition unit; obtaining a binary array b[0-log2n] of the number of consecutive additions; if b[i]=1, generating a left-shift operation unit and mapping it into a list of trigger units, storing its output signal in array N1; generating log2n second addition units based on array N1, storing their output signals in array C, and obtaining sets N2 and N3; obtaining a mapping set of output signals that do not need to be processed in the first stage to second addition units, and updating sets N2 and N3; traversing each signal sig in sets N2 and N3, and mapping the second addition unit corresponding to the signal sig into a carry chain unit list. The present application can optimize the resource allocation of the carry chain and reduce the number of logic resources after synthesis.

Description

Technical Field

[0001] The present application belongs to the field of FPGA software design technology, and in particular relates to an FPGA synthesis tool carry chain optimization method and device for consecutive additions of identical numbers. Background Art

[0002] Logic synthesis is a critical step in the FPGA (Field Programmable Gate Array) EDA (Electronic Design Automation) software design process. It converts user-entered behavioral-level or register-transfer-level (RTL) Verilog / VHDL circuit files into a netlist consisting of basic FPGA logic elements, such as look-up tables (LUTs) and flip-flops (FFs). FPGA logic synthesis consists of two phases: synthesis and mapping. Synthesis converts the behavioral-level or RTL circuit file into a logic netlist consisting of gate circuits; mapping maps the gate-based logic netlist into a netlist consisting of basic FPGA logic elements.

[0003] Area, or the number of resources, is a key metric for FPGA logic synthesis tools. Reducing the number of resources after FPGA logic synthesis is crucial for improving the routability and timing performance of FPGA software. The carry chain unit is the fundamental logic unit used by FPGA synthesis tools to implement addition and subtraction operations. Adding multiple identical numbers is called consecutive addition, a common design in application circuits. Traditional FPGA synthesis tools still use the standard carry chain method for consecutive additions of identical numbers, failing to account for the special rules governing consecutive additions of identical numbers, resulting in excessive use of logic units.

[0004] Therefore, it is crucial to provide a solution to the problem in FPGA synthesis that too many logic units are occupied because ordinary carry chains do not consider the special rules when adding consecutive numbers of the same number. Summary of the Invention

[0005] The present application discloses a carry chain optimization method and device for an FPGA synthesis tool for consecutive additions of the same number, which can optimize the resource allocation of the carry chain, reduce the number of logic resources after synthesis, and optimize the FPGA synthesis area.

[0006] Other purposes and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] To achieve one, part, or all of the above-mentioned purposes or other purposes, in a first aspect, the present application provides an FPGA synthesis tool carry chain optimization method for consecutive additions of identical numbers, the method comprising:

[0008] Obtain each adding unit with the same number of consecutive additions in the circuit netlist as the first adding unit, and count the same signal sig and the number of consecutive additions n in the first adding unit;

[0009] Get the binary representation array b[0-log2n] of the number of consecutive additions of each first addition unit;

[0010] For each bit i in the array b[0-log2n], if b[i]=1, a left shift operation unit is generated;

[0011] Mapping each generated left shift operation unit into a trigger unit linked list, and storing the output signal of the trigger unit linked list into the signal array N1;

[0012] Generate log2n adding units according to the signal array N1 as second adding units, store the output signals of the second adding units into array C, use the output signal C[log2n] of the last second adding unit as the output signal of the first adding unit, and obtain a set N2 and a set N3, wherein the set N2 and the set N3 are mutually disjoint;

[0013] Obtain a mapping set of the output signals of the first stage that do not need to be processed to the second adding unit through iterative analysis, and update the set N2 and the set N3;

[0014] Traverse each signal sig in the updated set N2 and set N3, and starting from the first bit, map the second addition unit corresponding to the signal sig into a carry chain unit linked list.

[0015] In one embodiment, the input A-end signal of the left shift operation unit is equal to the signal sig, and the input B-end signal of the left shift operation unit is equal to log2n-i+1, indicating the number of bits that the left shift operation unit needs to shift left.

[0016] In one embodiment, mapping each generated left shift operation unit into a trigger unit linked list, and storing the output signal of the trigger unit linked list into the signal array N1, includes:

[0017] Get the input A-end signal sig_a, the input B-end signal sig_b, and the output Y-end signal sig_y of the left shift operation unit, where the bit width of the signal sig_a is w;

[0018] Convert signal sig_b to integer variable m;

[0019] Loop through variables i=0 to m-1 and set signal sig_y[i] equal to 0;

[0020] The loop traverses the variables i=m to m+w-1 to generate a trigger unit, where the input D-end signal of the trigger unit is equal to the signal sig_a[im], and the output Q-end signal is equal to the signal sig_y[i].

[0021] In one embodiment, log2n adding units are generated according to the signal array N1 as second adding units, the output signals of the second adding units are stored in an array C, and the output signal C[log2n] of the last second adding unit is used as the output signal of the first adding unit, thereby obtaining a set N2 and a set N3, including:

[0022] Create a new signal array C, set C[0]=N1[0], traverse each bit i in the array N1, i from 0 to log2n-1, and map the addition operation C[i]+N1[i+1] to the second addition unit with the output signal C[i+1];

[0023] If log2n is greater than 2, set the 0th bit of each signal between C[1] and C[log2n-1] to 0, and insert the mapping of each signal to its corresponding second addition unit into set N2; if b[log2n]=0, set the 0th bit of C[log2n] to 0, and insert the mapping of C[log2n] to its corresponding second addition unit into set N2; otherwise, set the 0th bit of C[log2n] equal to the 0th bit of C[log2n-1], and insert the mapping of C[log2n] to its corresponding second addition unit into set N3.

[0024] In one embodiment, obtaining a mapping set of output signals of the first stage that do not need to be processed to the second adding unit through iterative analysis and updating the set N2 and the set N3 includes:

[0025] Traverse the second adding unit in the circuit netlist. If both the input A-end signal and the input B-end signal of the second adding unit can be found in set N2, then insert the mapping relationship from the output signal of the second adding unit to the second adding unit into set N2. Otherwise, if both the input A-end signal and the input B-end signal of the second adding unit can be found in set N3, then insert the mapping relationship from the output signal of the second adding unit to the second adding unit into set N3. If there is a change in set N2, enter the next iteration.

[0026] In one embodiment, a method of mapping the second addition unit into a carry chain unit linked list includes:

[0027] Obtain the input A-end signal sig_a, the input B-end signal sig_b, and the output Y-end signal sig_y of the second adding unit, and obtain the minimum bit width w1 of the signal sig_a;

[0028] Traverse variable i from 0 to w1-1;

[0029] Create a first logic unit c1 of a combinational logic type, assign the input port signals of the first logic unit c1 to sig_a[i] and sig_b[i], assign the output port signal of the first logic unit c1 to sig_y[i], and generate a carry output signal;

[0030] If i=0, set the lookup table mask equal to the first mask value; otherwise, generate a carry input signal for the first logic unit c1 and assign it to the carry output signal of the previous level unit, and set the lookup table mask equal to the second mask value;

[0031] In one embodiment, the method of mapping the second addition unit into a carry chain unit linked list further includes:

[0032] Get the maximum bit width w2 of signal sig_b, and traverse i from w1 to w2-1;

[0033] Create a second logic unit c2 of combinational logic type. The input signal of the second logic unit c2 is assigned to the i-th bit of the signal with the larger bit width of sig_a and sig_b. The output port signal of the second logic unit c2 is assigned to sig_y[i]. A carry-out signal is generated. A carry-in signal is generated and assigned to the carry-out signal of the previous level unit. The lookup table mask is set to the third mask value.

[0034] Create a third logic unit c3 of a combinational logic type, assign the output port signal of the third logic unit c3 to sig_y[w2], generate a carry input signal and assign it to the carry output signal of the previous level unit, and set the lookup table mask equal to the fourth mask value.

[0035] In a second aspect, the present application provides an FPGA synthesis tool carry chain optimization device for consecutive additions of the same number, the device being used to implement the FPGA synthesis tool carry chain optimization method for consecutive additions of the same number according to any one of the first aspects, the device comprising:

[0036] The adding unit acquisition and analysis module is used to obtain each adding unit with the same number of consecutive additions in the circuit netlist as the first adding unit, count the same signal sig and the number of consecutive additions n in the first adding unit; obtain the binary representation array b[0-log2n] of the number of consecutive additions of each first adding unit;

[0037] a trigger unit linked list generation module, configured to generate a left shift operation unit for each bit i in the array b[0-log2n], if b[i]=1; map each generated left shift operation unit into a trigger unit linked list, and store the output signal of the trigger unit linked list into the signal array N1;

[0038] A signal processing and generation module generates log2n adding units according to the signal array N1 as second adding units, stores the output signals of the second adding units in an array C, uses the output signal C[log2n] of the last second adding unit as the output signal of the first adding unit, and obtains a set N2 and a set N3, wherein the set N2 and the set N3 are mutually disjoint; obtains a mapping set of the output signals of the first stage that do not need to be processed to the second adding units through iterative analysis, and updates the set N2 and the set N3;

[0039] The carry chain unit linked list generation module is used to traverse each signal sig in the updated set N2 and set N3, starting from the first bit, and map the second addition unit corresponding to the signal sig into the carry chain unit linked list.

[0040] In a third aspect, the present application provides a computer-readable storage medium having program code stored therein, and the program code is called by a processor to execute the carry chain optimization method for FPGA synthesis tools for consecutive additions of the same number according to any one of the first aspects.

[0041] In a fourth aspect, the present application provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the carry chain optimization method for FPGA synthesis tools for consecutive additions of the same number as any one of the first aspects.

[0042] The above-mentioned FPGA synthesis tool carry chain optimization method and device for consecutive additions of the same number generates corresponding left shift operation units and addition units through the binary representation of the number of consecutive additions, making resource allocation more precise, avoiding unnecessary adder generation, reducing the occupancy of adder resources in the FPGA, and lowering resource consumption. In addition, the use of a trigger unit linked list and a carry chain unit linked list structure makes signal transmission more orderly and efficient, thereby improving resource utilization efficiency.

[0043] In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 This is a flow chart of a carry chain optimization method for an FPGA synthesis tool for consecutive additions of the same number in this application.

[0046] Figure 2 This is a flow chart of mapping a left shift operation unit into a trigger unit linked list in the present application.

[0047] Figure 3 This is a flow chart of a signal array generating adding unit according to the present application.

[0048] Figure 4 This is a flowchart of the present application for obtaining a set of carry chain signals that do not need to be processed at the first stage.

[0049] Figure 5 This is a flowchart of mapping an addition unit into a carry chain unit list in the present application.

[0050] Figure 6 This is a block diagram of a carry chain optimization device for an FPGA synthesis tool for consecutive additions of the same number in this application. DETAILED DESCRIPTION

[0051] The aforementioned and other technical contents, features, and functions of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first," "second," and the like in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, and this is merely a way of distinguishing objects of the same attributes when describing them in the embodiments of the present application.

[0052] refer to Figure 1 The embodiment of the present application provides an FPGA synthesis tool carry chain optimization method for consecutive additions of the same number, including the following steps:

[0053] Step 1: traverse each add type logic unit in the circuit netlist, analyze the first add unit of each same number of consecutive additions, and count the same signal sig and the number of consecutive additions n in the first add unit; execute steps 2-5.

[0054] Step 2: For each first adding unit of consecutive additions of the same number, obtain an array b[0-log2n] representing the binary representation of the number of consecutive additions n of the first adding unit.

[0055] Step 3: For each bit i in the array b[0-log2n], where i ranges from 0 to log2n, if b[i]=1, a left shift operation (shl) unit s is generated. The input A signal of the left shift operation unit s is equal to the signal sig, and the input B signal of the left shift operation unit s is equal to log2n-i+1, which indicates the number of bits that the left shift operation unit s needs to shift left.

[0056] Step 4: Map each left shift operation unit s generated in step 3 into a number of levels of flip-flop (DFF) unit lists d, and store the output signals of the flip-flop unit lists d into the signal array N1.

[0057] Step 5: Generate log2n adding units according to the signal array N1 as the second adding unit a2. The output signal of the second adding unit a2 is stored in the array C. The output signal C[log2n] of the last second adding unit a2 is used as the output signal of the first adding unit a1 to obtain the set N2 and the set N3, where the set N2 and the set N3 do not intersect with each other.

[0058] Create a new signal array C and set C[0]=N1[0]; traverse each bit i in the signal array N1, where i ranges from 0 to log2n-1, and map the addition operation C[i]+N1[i+1] to an addition unit with an output signal of C[i+1]; use C[log2n] as the output signal of the first addition unit;

[0059] If log2n>2, assign the 0th bit of each signal from C[1] to C[log2n-1] to 0, and insert the mapping of each signal to its addition unit into the set N2;

[0060] If b[log2n]=0, set the 0th bit of C[log2n] to 0 and insert the mapping from C[log2n] to its addition unit into set N2;

[0061] Otherwise, assign the 0th bit of C[log2n] to the 0th bit of C[log2n-1], and insert the mapping from C[log2n] to its addition unit into the set N3.

[0062] Step 6: Obtain the mapping set of the output signals that do not need to be processed in the first stage to the adding units through iterative analysis, and update the set N2 and the set N3.

[0063] Iterate through each second adding unit a2 in the circuit netlist, obtain the input A-end signal sig1 and the input B-end signal sig2 of the second adding unit a2, and if both sig1 and sig2 can be found in the set N2, insert the mapping relationship from the output signal of the second adding unit a2 to the second adding unit a2 into the set N2; otherwise, if sig1 or sig2 can be found in the set N2, insert the mapping relationship from the output signal of the second adding unit a2 to the second adding unit a2 into the set N3; if there is a change in the N2 set, enter the next iteration; otherwise, exit this step.

[0064] Step 7: Traverse each signal sig in set N2 and set N3, starting from the first bit, and map the addition unit corresponding to the signal sig into a carry chain unit list.

[0065] In this embodiment, the corresponding left-shift operation unit and addition unit are generated by using the binary representation of the number of consecutive additions, making resource allocation more accurate, avoiding unnecessary adder generation, and reducing the occupancy of adder resources in the FPGA. In addition, the left-shift operation unit is mapped into a trigger unit linked list, which can more efficiently utilize the trigger resources and reduce the redundant use of triggers, thereby reducing the number of logic resources after FPGA synthesis and reducing the area of ​​FPGA synthesis.

[0066] At the same time, the use of a linked list of trigger units and a linked list of carry chains makes signal transmission more orderly and efficient, improving resource utilization. Through the hierarchical construction and mapping of the carry chain, a clear, resource-efficient, and flexible carry management system is achieved. This reduces the number of delay nodes in the carry chain, shortens the signal propagation path, and enables faster generation and transmission of carry signals, thereby accelerating the execution of consecutive addition operations with the same number.

[0067] In an optional embodiment, each left shift operation unit s generated in step 4 is mapped into a plurality of levels of trigger unit linked lists d, and the output signals of the trigger unit linked lists d are stored in the signal array N1. Figure 2 , the specific steps are as follows:

[0068] Step 41: Obtain the input A-end signal sig_a, the input B-end signal sig_b, and the output Y-end signal sig_y of the left shift operation unit s, wherein the bit width of the signal sig_a is w.

[0069] Step 42: Convert the signal sig_b into an integer variable m.

[0070] Step 43: Loop through variables i=0 to m-1 and set signal sig_y[i]=0.

[0071] Step 44: Loop through variables i=m to m+w-1 and execute step 45.

[0072] Step 45: Generate a trigger unit, the input D-end signal of the trigger unit is equal to the signal sig_a[im], and the output Q-end signal is equal to the signal sig_y[i].

[0073] In this embodiment, by obtaining the input and output signals of the left-shift operation unit, then determining the left-shift bit number by converting the signal, and then performing a filling operation on the low bit, and then using the trigger unit to store and transmit the left-shifted signal, the left-shift operation of the input signal is realized, and the signal bit width is kept unchanged, thereby mapping the left-shift operation unit into a trigger unit linked list, which can more efficiently utilize the trigger resources, reduce the redundant use of triggers, and reduce the resource consumption of the FPGA.

[0074] In an optional embodiment, in step 5, log2n adding units are generated according to the signal array N1 as the second adding unit, and the output signal of the last second adding unit a2 is used as the output signal of the first adding unit a1. Figure 3 , the detailed steps are as follows:

[0075] Step 51: Create a new signal array C and set C[0]=N1[0].

[0076] Step 52: Traverse each bit i in array N1, where i ranges from 0 to log2n-1, and execute steps 53-54.

[0077] Step 53: Map the addition operation C[i]+N1[i+1] into an adding unit with an output signal of C[i+1] as the second adding unit a2.

[0078] Step 54: If i>0, set the 0th bit of C[i] to 0 (i.e., if log2n>2, set the 0th bit of each signal from C[1] to C[log2n-1] to 0), and insert the mapping of C[i] to its second addition unit a2 into the set N2.

[0079] Step 55: Use C[log2n] as the output signal of the first adding unit a1.

[0080] Step 56: If b[log2n]=0, go to step 57; otherwise go to step 58.

[0081] Step 57: Set the 0th bit of C[log2n] to 0, and insert the mapping of C[log2n] to its second addition unit a2 into the set N2.

[0082] Step 58: Set the 0th bit of C[log2n] = the 0th bit of C[log2n-1], and insert the mapping of C[log2n] to its second addition unit a2 into the set N3.

[0083] In this embodiment, the addition unit and the processing signal bit are dynamically generated according to the value of log2n, so that the method can adapt to the same-number continuous addition operations of different scales, has good scalability, and avoids the generation of unnecessary addition units, thereby saving adder resources in the FPGA.

[0084] In an alternative embodiment, referring to Figure 4 The specific method of obtaining the sets N2 and N3 that do not need to be processed at the first level through iterative analysis in step 6 includes the following steps:

[0085] Step 61: traverse each second adding unit a2 in the circuit netlist and execute steps 62-64.

[0086] Step 62: Obtain the input A-end signal sig1 and the input B-end signal sig2 of the second adding unit a2.

[0087] Step 63: If both the signal sig1 and the signal sig2 can be found in the set N2, the mapping relationship from the output signal of the second adding unit a2 to the second adding unit a2 is inserted into the set N2, and step 65 is executed; otherwise, step 64 is executed.

[0088] Step 64: If the signal sig1 or the signal sig2 can be found in the set N2, the mapping relationship from the output signal of the second adding unit a2 to the second adding unit a2 is inserted into the set N3; otherwise, the processing of the addition a is exited and the processing of the next adding unit is entered.

[0089] Step 65: If the carry chain signal N2 set changes, go to step 1 and enter the next iteration; otherwise, exit this process.

[0090] In this embodiment, by iteratively analyzing and obtaining sets N2 and N3 that do not require processing at the first stage, the carry chain structure can be streamlined, removing those parts that do not need to be processed. This optimization reduces redundant nodes in the carry chain, making the carry chain more efficient. By inspecting and classifying the input signals, the generation of unnecessary adder units is avoided. The mapping relationship between signals and adder units is inserted into sets N2 or N3, making signal management more efficient and avoiding resource waste.

[0091] In an alternative embodiment, Figure 5As shown, in step 7, each signal sig in the set N2 and the set N3 is traversed, and the add unit corresponding to sig is mapped into a carry chain unit list starting from the first bit, wherein the method of mapping a second addition unit a2 into the carry chain unit list specifically includes the following steps:

[0092] Step 71: Obtain the input A-end signal sig_a, the input B-end signal sig_b, and the output Y-end signal sig_y of the second adding unit a2, and obtain the minimum bit width w1 of the signal sig_a and the maximum bit width w2 of the signal sig_b.

[0093] Step 72: Traverse variable i from 0 to w1-1 and execute steps 73-74.

[0094] Step 73: Create a first logic unit c1 of the combinational logic (LCELL_COMB) type, assign the input port signals of the first logic unit c1 to sig_a[i] and sig_b[i], assign the output port signal to sig_y[i], and generate a carry output (COUT) signal.

[0095] Step 74: If i=0, the lookup table mask lut_mask=6688; otherwise, a carry input (CIN) signal is generated for the first logic unit c1 = the COUT signal of the previous level unit, and the lookup table mask lut_mask=96E8 is set.

[0096] Step 75: Traverse i from w1 to w2-1 and execute step 76.

[0097] Step 76: Create a second logic unit c2 of type LCELL_COMB. The input signal of the second logic unit c2 is assigned to the i-th bit of the signal with the larger bit width of sig_a and sig_b. The output port signal is assigned to sig_y[i]. A COUT carry output signal and a CIN carry input signal = the COUT signal of the previous level unit are generated. Set the lookup table mask lut_mask = 5AA0.

[0098] Step 77: Create a third logic unit c3 of LCELL_COMB type, assign the output port signal of the third logic unit c3 to sig_y[w2], generate a CIN input port signal = COUT signal of the previous level unit, and set the lookup table mask lut_mask = F0F0.

[0099] In this embodiment, an independent combinational logic unit is created for each bit according to the bit width of the input signal, and different lookup table mask values ​​are set to distinguish different functions, thereby speeding up the execution of the addition operation, reducing unnecessary circuit parts, and improving resource utilization efficiency; and by generating a carry output signal for each bit, the carry signal can be quickly generated and transmitted, reducing the delay caused by bit-by-bit carry.

[0100] It should be understood that at least part of the steps in the flowcharts involved in the various embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0101] Based on the same inventive concept, an embodiment of the present application also provides an FPGA synthesis tool carry chain optimization device for consecutive additions of the same number. The implementation solution of the device to solve the problem is similar to the implementation solution recorded in the above method. Therefore, the specific limitations can be found in the above limitations on the FPGA synthesis tool carry chain optimization method for consecutive additions of the same number, which will not be repeated here.

[0102] refer to Figure 6 The embodiment of the present application provides an FPGA synthesis tool carry chain optimization device for consecutive additions of identical numbers, the device comprising:

[0103] The adding unit acquisition and analysis module is used to obtain each adding unit with the same number of consecutive additions in the circuit netlist as the first adding unit, count the same signal sig and the number of consecutive additions n in the first adding unit; obtain the binary representation array b[0-log2n] of the number of consecutive additions of each first adding unit;

[0104] A trigger unit linked list generation module is used to generate a left shift operation unit for each bit i in the array b[0-log2n] if b[i]=1; each generated left shift operation unit is mapped into a trigger unit linked list, and the output signal of the trigger unit linked list is stored in the signal array N1;

[0105] The signal processing and generation module generates log2n adding units based on the signal array N1 as the second adding units. The output signals of the second adding units are stored in the array C. The output signal C[log2n] of the last second adding unit is used as the output signal of the first adding unit to obtain sets N2 and N3, where sets N2 and N3 do not intersect with each other. The module obtains the mapping set of the second-stage output signals that do not need to be processed to the second adding units through iterative analysis, and updates sets N2 and N3.

[0106] The carry chain unit linked list generation module is used to traverse each signal sig in the updated set N2 and set N3, starting from the first bit, and map the second addition unit corresponding to the signal sig into the carry chain unit linked list.

[0107] In one embodiment, the present application also provides a computer-readable storage medium having a program code stored therein, and the program code is called by a processor to execute any of the above-mentioned carry chain optimization methods for FPGA synthesis tools for consecutive additions of the same number.

[0108] In one embodiment, the present application also provides an electronic device, which includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute any of the above-mentioned carry chain optimization methods for FPGA synthesis tools for consecutive additions of the same number.

[0109] It should be noted that, for those skilled in the art, various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention. It should be understood that certain features of the present invention described in the context of separate embodiments for the sake of clarity may also be provided in combination in a single embodiment. Conversely, various features of the present invention described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present invention.

Claims

1. A carry chain optimization method for FPGA synthesis tools for consecutive additions of the same number, characterized in that: The method comprises: Obtain each adding unit with the same number of consecutive additions in the circuit netlist as the first adding unit, and count the same signal sig and the number of consecutive additions n in the first adding unit; Get the binary representation array b[0-log2n] of the number of consecutive additions of each first addition unit; For each bit i in the array b[0-log2n], if b[i]=1, a left shift operation unit is generated; Mapping each generated left shift operation unit into a trigger unit linked list, and storing the output signal of the trigger unit linked list into the signal array N1; Generate log2n adding units according to the signal array N1 as second adding units, store the output signals of the second adding units into array C, use the output signal C[log2n] of the last second adding unit as the output signal of the first adding unit, and obtain a set N2 and a set N3, wherein the set N2 and the set N3 are mutually disjoint; Obtain a mapping set of the output signals of the first stage that do not need to be processed to the second adding unit through iterative analysis, and update the set N2 and the set N3; Traverse each signal sig in the updated set N2 and set N3, and starting from the first bit, map the second addition unit corresponding to the signal sig into a carry chain unit list; wherein, the method of mapping the second addition unit into the carry chain unit list includes: obtaining the input A-end signal sig_a, the input B-end signal sig_b and the output Y-end signal sig_y of the second addition unit, and obtaining the minimum bit width w1 of the signal sig_a; traverse the variable i from 0 to w1-1; create a first logic unit c1 of a combinational logic type, assign the input port signal of the first logic unit c1 to sig_a[i] and sig_b[i], assign the output port signal of the first logic unit c1 to sig_y[i], and generate a carry output signal; if i=0, set the lookup table mask equal to the first mask value, otherwise, generate a carry input signal for the first logic unit c1 and assign it to the carry output signal of the previous level unit, and set the lookup table mask equal to the second mask value.

2. The FPGA synthesis tool carry chain optimization method for consecutive additions of the same number according to claim 1, characterized in that: The input A-end signal of the left-shift operation unit is equal to the signal sig, and the input B-end signal of the left-shift operation unit is equal to log2n-i+1, indicating the number of bits that the left-shift operation unit needs to shift left.

3. The FPGA synthesis tool carry chain optimization method for consecutive additions of the same number according to claim 2, characterized in that: The step of mapping each generated left shift operation unit into a trigger unit linked list and storing the output signal of the trigger unit linked list into the signal array N1 includes: Get the input A-end signal sig_a, the input B-end signal sig_b, and the output Y-end signal sig_y of the left shift operation unit, where the bit width of the signal sig_a is w; Convert signal sig_b to integer variable m; Loop through variables i=0 to m-1 and set signal sig_y[i] equal to 0; The loop traverses the variables i=m to m+w-1 to generate a trigger unit, where the input D-end signal of the trigger unit is equal to the signal sig_a[im], and the output Q-end signal is equal to the signal sig_y[i].

4. The FPGA synthesis tool carry chain optimization method for consecutive additions of the same number according to claim 1, characterized in that: The method generates log2n adding units according to the signal array N1 as second adding units, stores the output signals of the second adding units in the array C, and uses the output signal C[log2n] of the last second adding unit as the output signal of the first adding unit, thereby obtaining sets N2 and N3, including: Create a new signal array C, set C[0]=N1[0], traverse each bit i in the array N1, i from 0 to log2n-1, and map the addition operation C[i]+N1[i+1] to the second addition unit with the output signal C[i+1]; If log2n is greater than 2, set the 0th bit of each signal between C[1] and C[log2n-1] to 0, and insert the mapping of each signal to its corresponding second addition unit into set N2; if b[log2n]=0, set the 0th bit of C[log2n] to 0, and insert the mapping of C[log2n] to its corresponding second addition unit into set N2; otherwise, set the 0th bit of C[log2n] equal to the 0th bit of C[log2n-1], and insert the mapping of C[log2n] to its corresponding second addition unit into set N3.

5. The FPGA synthesis tool carry chain optimization method for consecutive additions of the same number according to claim 1, characterized in that: The step of obtaining a mapping set of output signals of the first stage that do not need to be processed to the second adding unit through iterative analysis and updating the set N2 and the set N3 comprises: Traverse the second adding unit in the circuit netlist. If both the input A-end signal and the input B-end signal of the second adding unit can be found in set N2, then insert the mapping relationship from the output signal of the second adding unit to the second adding unit into set N2. Otherwise, if both the input A-end signal and the input B-end signal of the second adding unit can be found in set N3, then insert the mapping relationship from the output signal of the second adding unit to the second adding unit into set N3. If there is a change in set N2, enter the next iteration.

6. The FPGA synthesis tool carry chain optimization method for consecutive additions of the same number according to claim 1, characterized in that: The method of mapping the second addition unit into a carry chain unit linked list further includes: Get the maximum bit width w2 of signal sig_b, and traverse i from w1 to w2-1; Create a second logic unit c2 of combinational logic type. The input signal of the second logic unit c2 is assigned to the i-th bit of the signal with the larger bit width of sig_a and sig_b. The output port signal of the second logic unit c2 is assigned to sig_y[i]. A carry-out signal is generated. A carry-in signal is generated and assigned to the carry-out signal of the previous level unit. The lookup table mask is set to the third mask value. Create a third logic unit c3 of a combinational logic type, assign the output port signal of the third logic unit c3 to sig_y[w2], generate a carry input signal and assign it to the carry output signal of the previous level unit, and set the lookup table mask equal to the fourth mask value.

7. A carry chain optimization device for FPGA synthesis tools for consecutive additions of the same number, characterized in that: The device is used to implement the FPGA synthesis tool carry chain optimization method for consecutive additions of the same number as described in any one of claims 1 to 6, and the device includes: The adding unit acquisition and analysis module is used to obtain each adding unit with the same number of consecutive additions in the circuit netlist as the first adding unit, count the same signal sig and the number of consecutive additions n in the first adding unit; obtain the binary representation array b[0-log2n] of the number of consecutive additions of each first adding unit; a trigger unit linked list generation module, configured to generate a left shift operation unit for each bit i in the array b[0-log2n], if b[i]=1; map each generated left shift operation unit into a trigger unit linked list, and store the output signal of the trigger unit linked list into the signal array N1; A signal processing and generation module generates log2n adding units according to the signal array N1 as second adding units, stores the output signals of the second adding units in an array C, uses the output signal C[log2n] of the last second adding unit as the output signal of the first adding unit, and obtains a set N2 and a set N3, wherein the set N2 and the set N3 are mutually disjoint; obtains a mapping set of the output signals of the first stage that do not need to be processed to the second adding units through iterative analysis, and updates the set N2 and the set N3; A carry chain unit linked list generation module is used to traverse each signal sig in the updated set N2 and set N3, and starting from the first bit, map the second addition unit corresponding to the signal sig into a carry chain unit linked list; wherein the method of mapping the second addition unit into the carry chain unit linked list includes: obtaining the input A-end signal sig_a, the input B-end signal sig_b and the output Y-end signal sig_y of the second addition unit, and obtaining the minimum bit width w1 of the signal sig_a; traversing the variable i from 0 to w1-1; creating a first logic unit c1 of a combinational logic type, assigning the input port signals of the first logic unit c1 to sig_a[i] and sig_b[i], assigning the output port signal of the first logic unit c1 to sig_y[i], and generating a carry output signal; if i=0, setting the lookup table mask equal to the first mask value; otherwise, generating a carry input signal for the first logic unit c1 and assigning it to the carry output signal of the previous level unit, and setting the lookup table mask equal to the second mask value.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program code, and the program code is called by a processor to execute the carry chain optimization method for FPGA synthesis tools for consecutive additions of the same number as described in any one of claims 1 to 6.

9. An electronic device, characterized in that: including one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the carry chain optimization method for FPGA synthesis tools for consecutive additions of the same number as described in any one of claims 1 to 6.

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