Digital analog hybrid circuit simulation method and device

Abstract

The present invention discloses a digital-analog mixed circuit simulation method and device, which includes: reading in a digital circuit source file, an analog circuit source file and circuit configuration information for parsing, and establishing a mixed signal hierarchical structure including a digital circuit part and an analog circuit part; determining the mixed signal boundaries of the mixed signal hierarchical structure, optimizing the mixed signal boundaries according to the signal connection conditions between each mixed signal boundary, and inserting corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries; the digital-to-analog conversion unit is used for signal synchronization during simulation; splitting the optimized mixed signal hierarchical structure to obtain two digital circuits and analog circuits with the same circuit structure, and generating a digital circuit netlist file and an analog circuit netlist file, so that a digital simulator and an analog simulator can read the corresponding netlist files for simulation respectively, and call a communication interface based on the digital-to-analog conversion unit for signal synchronization.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of circuit simulation, and in particular to a digital-analog hybrid circuit simulation method and device. Background Art

[0002] A hybrid chip is a special type of integrated circuit (IC) consisting of both analog and digital circuits. It integrates analog and digital signal processing functions on the same chip. This design allows the chip to simultaneously process continuously changing analog signals and discrete digital signals within the same physical package. The analog circuit is the core component, while the digital circuit controls the analog circuit to implement specific algorithms. Hybrid chips have a wide range of applications:

[0003] Communications: In wireless communications and demodulation, hybrid digital-analog chips are used to receive and process analog signals, converting them into digital signals for further processing. Wired communications, such as ADSL / fiber modems, local area networks (LANs), and wide area networks (WANs), also require hybrid digital-analog chips to convert analog signals into digital signals.

[0004] Media field: used for operations such as audio and video encoding and decoding, signal extraction, synthesis, and noise reduction, which require converting analog signals into digital signals for editing and management on electronic devices.

[0005] Image processing field: In the application of image sensors, hybrid analog-digital chips are responsible for converting analog signals into digital signals, thereby improving image quality. They are commonly found in products such as digital audio players, digital audio collectors, and digital audio mixers.

[0006] Other application areas: In the automotive industry, complex mixed-analog and digital chips can be used for vehicle diagnosis, driver assistance systems and vehicle networking technology; in the medical field, they can be used for heart monitoring and medical imaging processing; in the industrial field, they may be used for applications such as motor control, robot control and automation control.

[0007] In summary, hybrid digital-analog chips are not only widely used in the fields mentioned above, but also play a key role in many modern electronic devices. Simulation tool software for hybrid digital-analog chips has a huge application demand.

[0008] Among existing technical solutions, foreign EDA companies, led by Synopsys, Cadence, and Siemens EDA (Mentor Graphics), all provide simulation and verification solutions for mixed-signal (AMS) circuits. For example, Synopsys uses its digital simulator VCS and analog simulator XA for AMS simulation; Cadence uses its digital simulator Xcelium and analog simulator Spectre for AMS simulation. However, these tools are based on two independent, mature digital and analog simulators, combined through internal synchronization mechanisms. These include segmenting mixed-signal circuits and synchronizing data during the simulation phase. However, existing tools have the following problems:

[0009] Existing tools require automatic or manual segmentation of the circuit design's hierarchical structure, assigning digital modules to a digital simulator and analog modules to an analog simulator. These two components establish independent topologies and connections. With the increasing complexity of circuit designs, such as those with multiple levels of nested digital and analog modules, this hierarchical segmentation approach can fragment the entire circuit design. The same signal is repeatedly segmented throughout the circuit topology, increasing the complexity of circuit simulation and even leading to inaccurate simulation results. Simulation tools also require extensive additional checks to patch and merge the segmented circuits. This inevitably results in differences between the modified circuit and the original circuit, increasing the complexity of simulator design and debugging. When simulation results are inaccurate, both digital and analog simulators only process the segmented circuit after segmentation, failing to capture complete circuit information. This makes it difficult to simply reproduce the fault using either the digital or analog simulator to locate the problem. Furthermore, the existing hierarchical segmentation of mixed-signal digital-analog circuits will further exacerbate the fragmentation of low-power circuit design, increase the difficulty of simulator design, and increase the complexity of circuit debugging. Summary of the Invention

[0010] In view of the above problems, embodiments of the present invention are proposed to provide a digital-analog hybrid circuit simulation method and apparatus that overcome the above problems or at least partially solve the above problems.

[0011] According to one aspect of an embodiment of the present invention, a method for simulating a digital-analog hybrid circuit is provided, the method comprising:

[0012] Read in digital circuit source files, analog circuit source files and circuit configuration information for parsing, and establish a mixed signal hierarchical structure including digital circuit parts and analog circuit parts;

[0013] Determine the mixed signal boundaries of the mixed signal hierarchical structure, optimize the mixed signal boundaries according to the signal connection between each mixed signal boundary, and insert corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries; the digital-to-analog conversion units are used for signal synchronization during simulation;

[0014] The mixed signal hierarchical structure after split optimization processing is obtained to obtain two digital circuits and analog circuits with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file, wherein the digital circuit netlist file contains digital behavior and digital signals, and the analog circuit netlist file contains analog behavior and analog signals; the mixed signal boundary of the digital circuit netlist file and the analog circuit netlist file contains a digital-to-analog conversion unit, so that the digital simulator and the analog simulator can read the corresponding netlist files for simulation respectively, and call the communication interface based on the digital-to-analog conversion unit for signal synchronization.

[0015] Optionally, reading in the digital circuit source file, the analog circuit source file, and the circuit configuration information for parsing, and establishing a mixed signal hierarchical structure including the digital circuit part and the analog circuit part further includes:

[0016] Using a preset circuit analysis program to read in digital circuit source files, analog circuit source files and circuit configuration information;

[0017] The connection information contained in the digital circuit source file, the analog circuit source file and the circuit configuration information is parsed to establish a mixed signal hierarchical structure including the digital circuit part and the analog circuit part.

[0018] Optionally, determining mixed signal boundaries of the mixed signal hierarchical structure, optimizing the mixed signal boundaries according to signal connections between the mixed signal boundaries, and inserting corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries further includes:

[0019] Perform topological expansion on the mixed signal hierarchical structure and perform signal analysis on the behavior of the circuit structure based on the topological relationship of the signals. Signals affected by digital behavior are marked as digital circuits, signals affected by analog behavior are marked as analog circuits, and signals affected by both digital and analog behaviors are marked as mixed signal boundaries.

[0020] Based on the mixed signal boundary, determine whether the analog circuits at the boundary of two mixed signals are connected to analog devices, or whether the digital circuits are connected to digital devices;

[0021] If not, insert a corresponding signal connection between the two mixed signal boundaries;

[0022] If so, a digital-to-analog conversion unit is inserted between the boundaries of the two mixed signals.

[0023] Optionally, splitting the optimized mixed-signal hierarchical structure to obtain two digital circuits and analog circuits with the same circuit structure, and generating a digital circuit netlist file and an analog circuit netlist file further includes:

[0024] According to the flattened mixed-signal hierarchical structure after optimization, mapping is performed into two digital circuits and analog circuits with the same circuit structure, deleting the analog behavior and analog signals in the digital circuit to obtain a digital circuit that retains the digital behavior and digital signals as well as a digital-to-analog conversion unit, and deleting the digital behavior and digital signals in the analog circuit to obtain an analog circuit that retains the analog behavior and analog signals as well as a digital-to-analog conversion unit;

[0025] A digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and the files are submitted to the digital simulator and the analog simulator for simulation respectively.

[0026] Optionally, the method further comprises:

[0027] Read digital circuit source files, analog circuit source files, circuit configuration information, and power consumption design files for parsing, and establish a mixed-signal hierarchical structure including digital circuit parts and analog circuit parts, as well as a voltage domain structure including power supply connection relationships;

[0028] The voltage domain structure is split to obtain digital circuits and analog circuits containing power network information and connection module information, and digital circuit netlist files and analog circuit netlist files containing power network information are generated; the power network information includes signal voltage, current, load strength and / or reference voltage.

[0029] Optionally, splitting the voltage domain structure to obtain digital circuits and analog circuits containing power network information and connection module information, and generating a digital circuit netlist file and an analog circuit netlist file containing the power network information further includes:

[0030] According to the voltage domain structure, the analog circuit part and the digital circuit part in the voltage domain structure are split to obtain a digital circuit including the digital circuit part and an analog circuit including the analog circuit part; wherein the digital circuit and the analog circuit also include power network information and corresponding connection module information;

[0031] A digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and the files are submitted to the digital simulator and the analog simulator for simulation respectively.

[0032] According to another aspect of an embodiment of the present invention, a digital-analog hybrid circuit simulation device is provided, comprising:

[0033] A construction module is suitable for reading digital circuit source files, analog circuit source files and circuit configuration information for parsing, and establishing a mixed signal hierarchical structure including digital circuit parts and analog circuit parts;

[0034] Boundary optimization module, suitable for determining mixed signal boundaries of mixed signal hierarchical structure, optimizing mixed signal boundaries according to signal connections between mixed signal boundaries, and inserting corresponding signal connections or digital-to-analog conversion units between mixed signal boundaries; digital-to-analog conversion units are used for signal synchronization during simulation;

[0035] The splitting module is suitable for splitting the mixed signal hierarchical structure after optimization processing to obtain two digital circuits and analog circuits with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file, wherein the digital circuit netlist file contains digital behavior and digital signals, and the analog circuit netlist file contains analog behavior and analog signals; the mixed signal boundary of the digital circuit netlist file and the analog circuit netlist file contains a digital-to-analog conversion unit, so that the digital simulator and the analog simulator can read the corresponding netlist files for simulation respectively, and call the communication interface based on the digital-to-analog conversion unit for signal synchronization.

[0036] According to another aspect of an embodiment of the present invention, there is provided a computing device, comprising: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus;

[0037] The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute operations corresponding to the above-mentioned digital-analog hybrid circuit simulation method.

[0038] According to another aspect of the embodiments of the present invention, a computer storage medium is provided, wherein the storage medium stores at least one executable instruction, and the executable instruction enables a processor to execute operations corresponding to the above-mentioned digital-analog hybrid circuit simulation method.

[0039] According to another aspect of the embodiments of the present invention, a computer program product is provided, comprising at least one executable instruction, wherein the executable instruction enables a processor to execute operations corresponding to the above-mentioned digital-analog hybrid circuit simulation method.

[0040] According to the digital-analog mixed circuit simulation method and device provided in the embodiments of the present invention, a mixed signal hierarchical structure is constructed, the digital-analog mixed circuit structure and signal transmission are considered from a global perspective, the mixed signal boundaries are optimized, the insertion of digital-analog conversion units is minimized, and the impact of the mixed signal boundaries on the circuit is minimized. Through unified circuit analysis and parsing, two digital circuits and analog circuits with the same circuit structure are obtained, thereby ensuring the consistency and integrity of the signals on the digital simulator and the analog simulator, reducing the coupling between the digital simulator and the analog simulator, facilitating the compatibility of various versions of simulators, reducing the development difficulty and system overhead of the entire simulation system, and improving user usability.

[0041] The above description is only an overview of the technical solutions of the embodiments of the present invention. In order to more clearly understand the technical means of the embodiments of the present invention, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific implementation methods of the embodiments of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the embodiments of the present invention. The same reference numerals are used throughout the accompanying drawings to denote the same components. In the accompanying drawings:

[0043] Figure 1 A flow chart of a digital-analog hybrid circuit simulation method according to an embodiment of the present invention is shown;

[0044] Figure 2 A schematic diagram of building a mixed signal hierarchical structure is shown;

[0045] Figure 3 shows a schematic diagram of signal boundaries;

[0046] Figure 4 shows a schematic diagram of signal boundary optimization;

[0047] Figure 5 Shows a schematic diagram of circuit splitting;

[0048] Figure 6 It shows a schematic diagram of converting a circuit into a netlist file for simulation by a simulator;

[0049] Figure 7 A flow chart of a digital-analog hybrid circuit simulation method according to another embodiment of the present invention is shown;

[0050] Figure 8 shows a schematic diagram of the voltage domain structure;

[0051] Figure 9 A schematic diagram of the first circuit and the second circuit obtained by splitting is shown;

[0052] Figure 10 A schematic structural diagram of a digital-analog hybrid circuit simulation device according to an embodiment of the present invention is shown;

[0053] Figure 11 A schematic structural diagram of a computing device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0054] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0055] Figure 1 FIG. 1 shows a flow chart of a digital analog hybrid circuit simulation method according to an embodiment of the present invention. Figure 1 As shown, the method includes the following steps:

[0056] Step S101 : Read in a digital circuit source file, an analog circuit source file, and circuit configuration information, perform analysis, and establish a mixed signal hierarchical structure including a digital circuit part and an analog circuit part.

[0057] Existing technology for processing mixed digital and analog circuits involves manual or automatic segmentation. The digital and analog circuits are then parsed and compiled in two different simulators, one for digital and one for analog, respectively, each forming an independent circuit structure. Both the digital and analog simulators only process their respective parts of the circuit, resulting in severe fragmentation. This prevents users from understanding the complete circuit and complicates circuit debugging. Here, both analog and digital simulators refer to existing circuit simulation software.

[0058] Based on the above problems, this embodiment can use a preset circuit parsing program to read in digital circuit source files, analog circuit source files, and circuit configuration information. The circuit configuration information records the classification of each circuit, such as recording that circuit xx is an analog circuit and uses an analog description language, circuit zz is a digital circuit and uses a digital description language, etc. The digital circuit source files and analog circuit source files record information such as the components, pins, ports, networks, circuit descriptions, and connection relationships in the circuit. By parsing the digital circuit source files, analog circuit source files, and circuit configuration information, the circuit is constructed based on the connection relationship, etc., to obtain a mixed signal hierarchical structure including a digital circuit part and an analog circuit part. In the mixed signal hierarchical structure, the digital circuit part and the analog circuit part can be determined based on the circuit configuration information. The connections within the digital circuit part and the analog circuit part, and the connections between the digital circuit part and the analog circuit part are constructed based on the information contained in the digital circuit source files and the analog circuit source files. The preset circuit parsing program can use tools such as integrated circuits, which are not limited here.

[0059] like Figure 2 As shown, circuit configuration information, digital circuit source files (digital behavior description source files in the figure, such as Verilog, System Verilog, VHDL, Verilog-A, Verilog-AMS, etc., among which Verilog-A and Verilog-AMS files can also describe analog circuits), and analog circuit source files (analog design source files in the figure, such as SPICE, Spectre, etc.) are read in. Based on the read files, the mixed signal hierarchical structure on the right can be obtained, among which red is the analog circuit part and blue is the digital circuit part.

[0060] Step S102 : determining mixed signal boundaries of the mixed signal hierarchical structure, optimizing the mixed signal boundaries according to signal connections between the mixed signal boundaries, and inserting corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries.

[0061] After obtaining the mixed signal hierarchical result, the mixed signal hierarchical structure can be topologically expanded, and the behavior of the circuit structure can be analyzed based on the topological relationship of each signal in the mixed signal hierarchical structure. The signals affected by digital behavior are marked as digital circuits, the signals affected by analog behavior are marked as analog circuits, and the signals affected by both digital and analog behaviors are marked as mixed signal boundaries. Figure 2 The red part is the analog circuit part, and the blue part is the digital circuit part. Through analysis, it is determined that the signal boundaries include A, B, C, D, E, F, G, and H. Further analysis of each signal boundary, such as Figure 3As shown, signal boundaries A, B, C, and D are connected to a unified signal I, indicating that I is influenced by both digital and analog behavior. I is the boundary of a mixed-signal signal, possessing the dual properties of digital and analog signals. Signal I can appear in both digital and analog circuits. E and G only connect two analog behaviors, so they only appear in analog circuits. F and H only connect two digital behaviors, so they only appear in digital circuits. In summary, based on the mixed signal boundaries, it is possible to determine whether the analog circuits between two mixed signal boundaries are connected to analog devices, or whether the digital circuits are connected to digital behaviors. If analog devices, such as resistors or capacitors, exist in the analog circuits between the two mixed signal boundaries, a digital-to-analog conversion unit should be inserted between the two mixed signal boundaries. Alternatively, if the digital circuits between the two mixed signal boundaries are connected to digital behaviors, a digital-to-analog conversion unit should be inserted between the two mixed signal boundaries. If there are no analog devices or digital behavior connected between two mixed signal boundaries, there is no need to insert a digital-to-analog conversion unit between the two mixed signal boundaries. Instead, only the corresponding signal connection, either digital or analog, can be inserted. This reduces the need for multiple digital-to-analog conversions as in the prior art, and avoids the situation where the same signal is divided into multiple segments. The digital-to-analog conversion unit is used for signal synchronization during simulation, such as between a digital simulator and an analog simulator, to convert analog signals into digital signals, or vice versa.

[0062] Specifically, the digital circuit source file is as follows:

[0063]

[0064]

[0065] The analog circuit source file is as follows:

[0066]

[0067] The circuit configuration information is as follows:

[0068]

[0069] By reading the above file, we can get Figure 4The mixed signal hierarchical structure shown. Among them, including digital circuits V1, div10, and analog circuit iana. According to the above hierarchical structure, the boundaries of each mixed signal can be determined. For example, the signal connection includes top.vdd (digital circuit) -> top.iana.VI_P (analog circuit) -> top.iana.X2.in (digital circuit). The signal crosses the digital-analog mixed signal boundary twice, from digital circuit -> analog circuit -> digital circuit. The existing technology needs to implement two digital-to-analog conversions D2A (Digital to Analog) and A2D (Analog to Digital). In this embodiment, it can be seen through judgment that the signal VI_P is not connected to any analog device in the analog circuit. It can be determined that the signal is a digital signal. There is no need to add the above two digital-to-analog conversion units. The digital signal connection can be directly inserted. For the signal connection top.iana.X2.out[0] (digital circuit) -> top.iana.U2_out0 (analog circuit), the digital part is connected to the assignment operation #delay out = count, which contains digital behavior; the analog part is connected to a capacitor device C1 U2_out0 0 1p, and the mixed signal boundary needs to insert a digital-to-analog conversion unit D2A. The information connection top.iana.X1.out[3] (digital circuit) -> top.iana.U1_out3 (analog circuit) is connected to a resistor device R1 in the analog circuit, and the mixed signal boundary needs to insert a digital-to-analog conversion unit D2A. The signal connection top.iana.X2.out[1] (digital circuit) -> top.iana.U2_out1 (analog circuit) crosses the mixed digital-to-analog signal boundary. There is no analog device connected to it in the analog circuit, so there is no need to insert a digital-to-analog conversion unit. The above is an example, and the specific settings will be based on the implementation situation and are not limited here.

[0070] By optimizing the mixed signal boundary, it is avoided to cut the same signal into multiple segments and perform multiple digital-to-analog conversions, thereby solving the problems of analog simulator solution failure to converge, inconsistent values ​​of the same signal in different segments, and performance degradation introduced by redundant digital-to-analog conversion modules. For the digital-to-analog conversion unit inserted during the optimization process, when the signal is connected to the analog device, the signal value will be affected by the analog circuit analysis (A2D, analog to digital), or the signal value will affect the analog circuit solution (D2A, digital to analog). Depending on the signal value, if it is driven by a digital simulator, the signal needs to load the D2A digital-to-analog event. If the signal value is read by the digital simulator, the signal needs to load the A2D analog-to-digital event, etc. The signal is at the hierarchical digital-to-analog boundary, but does not involve the digital-to-analog conversion unit. It still exists in the entire circuit structure, and its corresponding logic value and analog signal state are solved by the digital simulator and the analog simulator respectively. There are no parts within a digital circuit or analog circuit that are connected or interact with each other. During simulation, these parts can be used as signal points within the digital circuit or analog circuit. They only exist in one data state, digital or analog. This is not explained in detail here.

[0071] Step S103, split the mixed signal hierarchical structure after optimization processing to obtain two digital circuits and analog circuits with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file for the digital simulator and the analog simulator to read the corresponding netlist files for simulation respectively, and call the communication interface based on the digital-to-analog conversion unit for signal synchronization.

[0072] After optimization, the mixed signal hierarchical structure can be split to obtain two digital circuits and analog circuits with the same circuit structure. Figure 5 As shown, the left side shows a mixed-signal hierarchical structure, which is mapped into two identical circuit structures on the right side, a digital circuit and an analog circuit. The upper right side is the digital circuit. After mapping, the analog behavior and analog signals in the digital circuit are deleted, resulting in a digital circuit that retains the digital behavior, digital signals, and digital-to-analog conversion unit. The lower right side is the analog circuit. The digital behavior and digital signals in the analog circuit are deleted, resulting in an analog circuit that retains the analog behavior, analog signals, and digital-to-analog conversion unit. The digital and analog circuits have the same circuit structure and are vertically mapped. The missing analog portion of the digital circuit matches the analog portion of the analog circuit, and the missing digital portion of the analog circuit matches the digital portion of the digital circuit.

[0073] After obtaining the digital circuit and analog circuit, such as Figure 6As shown, a digital circuit netlist file is generated based on the digital circuit, and an analog circuit netlist file is generated based on the analog circuit, and these files are submitted to the digital simulator and analog simulator for simulation, respectively. The mixed signal boundary between the digital circuit and the analog circuit includes a digital-to-analog conversion unit. When the digital simulator performs simulation and involves the analog part, or when the analog simulator performs simulation and involves the digital part, the digital-to-analog conversion unit is used to synchronize signals between the digital simulator and the analog simulator, thereby completing the collaborative simulation of the entire digital-analog mixed circuit. During operation, the digital simulator and the analog simulator can synchronize simulation data to ensure the consistency and integrity of the signals on the digital simulator and the analog simulator, which also facilitates debugging.

[0074] According to the digital-analog mixed circuit simulation method provided by an embodiment of the present invention, a mixed signal hierarchical structure is constructed, the digital-analog mixed circuit structure and signal transmission are considered from a global perspective, the mixed signal boundary is optimized, the insertion of digital-analog conversion units is minimized, and the impact of the mixed signal boundary on the circuit is minimized. Through unified circuit analysis and parsing, two digital circuits and analog circuits with the same circuit structure are obtained, thereby ensuring the consistency and integrity of the signals on the digital simulator and the analog simulator, reducing the coupling between the digital simulator and the analog simulator, facilitating the compatibility of various versions of simulators, reducing the development difficulty and system overhead of the entire simulation system, and improving user usability.

[0075] Figure 7 FIG. 4 shows a flow chart of a digital analog hybrid circuit simulation method according to another embodiment of the present invention. Figure 7 As shown, the method includes the following steps:

[0076] Step S701 , read in digital circuit source files, analog circuit source files, circuit configuration information and power consumption design files for parsing, and establish a mixed signal hierarchical structure including digital circuit parts, analog circuit parts, and a voltage domain structure including power supply connection relationships.

[0077] Digital circuit design typically does not include information related to the power supply network, and a low-power design file is required as a supplement to describe the power supply network behavior related to the digital circuit. The analog circuit design itself already includes a description of the power supply behavior. For mixed-signal digital-analog circuits, the description of the power supply behavior may overlap or even conflict with the power supply behavior already included in the analog circuit design. To address this issue, this embodiment combines the power supply design file with the circuit structure. The final digital circuit netlist file and analog circuit netlist file can include power supply network information, eliminating the need to modify the power supply design file based on the mixed-signal circuit structure.

[0078] Specifically, such as Figure 2As shown, when a preset circuit parsing program is used to read in digital circuit source files, analog circuit source files, and circuit configuration information, the power consumption design file UPF (Unified Power Format) can be read in for parsing. The power consumption design file includes power supply network, voltage domain design, power supply description, etc. Based on the power consumption design file, a voltage domain structure including digital circuit part and analog circuit part can be established. The voltage domain structure can be as follows Figure 8 As shown, this includes the power management unit (PMU), analog circuits (red), and digital circuits (blue). Green lines represent the power network, and yellow dots represent connection modules. The voltage domain structure also includes power connections, connecting analog and digital circuits via the power network.

[0079] Step S702 : determining mixed signal boundaries of the mixed signal hierarchical structure, optimizing the mixed signal boundaries according to signal connections between the mixed signal boundaries, and inserting corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries.

[0080] This step is described with reference to step S102 and will not be repeated here.

[0081] Step S703 , splitting the optimized mixed signal hierarchical structure and the voltage domain structure to obtain digital circuits and analog circuits containing power network information and connection module information, and generating digital circuit netlist files and analog circuit netlist files containing power network information.

[0082] For splitting the mixed signal hierarchical structure, refer to the description of step S103 and will not be repeated here. The resulting digital circuit and analog circuit are two digital circuits and analog circuits with the same circuit structure. While splitting the mixed signal hierarchical structure, the voltage domain structure is also split. The resulting digital circuit and analog circuit contain not only the circuit structure but also power network information and connection module information.

[0083] For the splitting of the voltage domain structure, specifically, according to Figure 8 The voltage domain structure shown in the figure splits the analog circuit part and the digital circuit part in the voltage domain structure to obtain Figure 9 The digital circuit and analog circuit shown in the figure. The left side is the analog circuit, which includes the analog circuit part, and the right side is the digital circuit, which includes the digital circuit part. The digital circuit and analog circuit also include power network information ( Figure 9 The lines in ) and the corresponding connection module information ( Figure 9 yellow dot in the middle).

[0084] A digital circuit netlist file is generated based on the digital circuit, and an analog circuit netlist file is generated based on the analog circuit. The digital circuit netlist file contains digital behavior and digital signals, while the analog circuit netlist file contains analog behavior and analog signals. The mixed-signal boundaries of the digital and analog circuit netlist files contain digital-to-analog conversion units. In addition, the digital and analog circuit netlist files contain power network information and corresponding connection module information. This power network information includes signal voltage, current, load strength, and reference voltage. This power network information is used by the connection module to transmit the power network information between the digital and analog simulators during simulation. It performs digital-to-analog conversion of voltage, current signal, and equivalent resistance based on the reference voltage. The connection module information corresponding to the yellow dot indicates the location where the conversion needs to occur. When the digital and analog simulators reach the corresponding yellow dot, they perform the corresponding conversion based on the power network information.

[0085] Furthermore, when simulating, the analog simulator runs before the digital simulator, that is, the simulation time position of the analog simulator is greater than or equal to the simulation time position of the digital simulator. The analog circuit of the analog simulator performs circuit initialization first. At this time, if there is a digital-to-analog conversion unit and an A2D event is sent, the A2D data conversion is sent to the digital simulator, otherwise the current waiting time of the analog simulator is sent and the digital simulator returns information. The digital circuit of the digital simulator initializes the digital circuit after receiving the A2D data conversion or the current waiting time of the analog simulator. If D2A data conversion is required, the digital simulator sends D2A data conversion to the analog simulator, otherwise the scheduled time of the next event of the digital simulator is sent and the analog simulator returns information. If the analog simulator receives the D2A data conversion, it needs to perform another initialization update based on the initial value of the digital circuit. If not received, the simulation starts. The analog simulator runs continuously and does not exceed the simulation time position specified by the scheduled time of the next event of the digital simulator. During this period, if an A2D event is received, A2D synchronization is required, A2D data conversion is sent to the digital simulator, and the return information is waited for. If there is no A2D event, when the next moment of the analog simulator exceeds the simulation time position specified by the scheduled time of the next event of the digital simulator, the analog simulator pauses, sends the current waiting time of the analog simulator to the digital simulator, and waits for the return information. If the analog simulation is completed, the analog simulator has ended event is sent to the digital simulator. The digital simulator receives the A2D data conversion, adds an A2D event to the time specified by the analog simulator on the timeline, and starts the operation of the digital simulator, and does not exceed the simulation time position specified by the current waiting time of the analog simulator. If the digital simulator encounters a D2A event, D2A synchronization is required, D2A data conversion is sent to the analog simulator, and the return information is waited for. If there is no D2A event, when the digital simulator runs to the moment specified by the current waiting time of the analog simulator, the digital circuit simulation is paused, and the scheduled time of the next digital simulator event at the next moment is sent to the analog simulator. If the digital simulation is finished, a digital simulator end event is sent to the analog simulator. If the digital simulator has no subsequent events to process, a scheduled time of the next event of the digital simulator at the maximum moment (such as -1) is sent to ensure that the analog simulator continues to run until the analog simulator ends. The above is the communication process of the analog simulator and the digital simulator according to the digital circuit netlist file and the analog circuit netlist file for simulation. The above is an example. The specific setting depends on the implementation situation and is not limited here.

[0086] According to the digital-analog mixed circuit simulation method provided by an embodiment of the present invention, a voltage domain structure including a power supply connection relationship is constructed, and splitting is performed based on the voltage domain structure to obtain a digital circuit including a digital circuit part and an analog circuit including an analog circuit part. Based on the digital circuit netlist file and the analog circuit netlist file corresponding to the digital circuit and the analog circuit, the consistency of the power supply signal in the simulation process can be guaranteed when the digital simulator and the analog simulator run the simulation. During the process, there is no need to supplement the power consumption design file separately for the digital circuit, and there is no need to make modifications due to overlap and conflict with the power supply behavior of the analog circuit.

[0087] Figure 10 FIG. 1 shows a schematic diagram of the structure of a digital analog hybrid circuit simulation device provided by an embodiment of the present invention. Figure 10 As shown, the device includes:

[0088] A construction module 1010 is adapted to read in a digital circuit source file, an analog circuit source file, and circuit configuration information for parsing, and to establish a mixed signal hierarchical structure including a digital circuit portion and an analog circuit portion;

[0089] Boundary optimization module 1020 is adapted to determine mixed signal boundaries of a mixed signal hierarchical structure, optimize the mixed signal boundaries based on signal connections between the mixed signal boundaries, and insert corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries; the digital-to-analog conversion units are used for signal synchronization during simulation;

[0090] The splitting module 1030 is suitable for splitting the mixed signal hierarchical structure after optimization processing to obtain two digital circuits and analog circuits with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file, wherein the digital circuit netlist file contains digital behavior and digital signals, and the analog circuit netlist file contains analog behavior and analog signals; the mixed signal boundary of the digital circuit netlist file and the analog circuit netlist file contains a digital-to-analog conversion unit, so that the digital simulator and the analog simulator can read the corresponding netlist files for simulation respectively, and call the communication interface based on the digital-to-analog conversion unit for signal synchronization.

[0091] Optionally, the building block 1010 is further adapted to:

[0092] Using a preset circuit analysis program to read in digital circuit source files, analog circuit source files and circuit configuration information;

[0093] The connection information contained in the digital circuit source file, the analog circuit source file and the circuit configuration information is parsed to establish a mixed signal hierarchical structure including the digital circuit part and the analog circuit part.

[0094] Optionally, the boundary optimization module 1020 is further adapted to:

[0095] Perform topological expansion on the mixed signal hierarchical structure and perform signal analysis on the behavior of the circuit structure based on the topological relationship of the signals. Signals affected by digital behavior are marked as digital circuits, signals affected by analog behavior are marked as analog circuits, and signals affected by both digital and analog behaviors are marked as mixed signal boundaries.

[0096] Based on the mixed signal boundary, determine whether the analog circuits at the boundary of two mixed signals are connected to analog devices, or whether the digital circuits are connected to digital devices;

[0097] If not, insert a corresponding signal connection between the two mixed signal boundaries;

[0098] If so, a digital-to-analog conversion unit is inserted between the boundaries of the two mixed signals.

[0099] Optionally, the splitting module 1030 is further adapted to:

[0100] According to the flattened mixed-signal hierarchical structure after optimization, mapping is performed into two digital circuits and analog circuits with the same circuit structure, deleting the analog behavior and analog signals in the digital circuit to obtain a digital circuit that retains the digital behavior and digital signals as well as a digital-to-analog conversion unit, and deleting the digital behavior and digital signals in the analog circuit to obtain an analog circuit that retains the analog behavior and analog signals as well as a digital-to-analog conversion unit;

[0101] A digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and the files are submitted to the digital simulator and the analog simulator for simulation respectively.

[0102] Optionally, the device also includes: a voltage domain splitting module 1040, which is suitable for reading in digital circuit source files, analog circuit source files, circuit configuration information and power consumption design files for parsing, establishing a mixed signal hierarchical structure including a digital circuit part and an analog circuit part, and a voltage domain structure including a power connection relationship; splitting the voltage domain structure to obtain digital circuits and analog circuits including power network information and connection module information, and generating a digital circuit netlist file and an analog circuit netlist file including power network information; the power network information includes signal voltage, current, load strength and / or reference voltage.

[0103] Optionally, the voltage domain splitting module 1040 is further adapted to:

[0104] According to the voltage domain structure, the analog circuit part and the digital circuit part in the voltage domain structure are split to obtain a digital circuit including the digital circuit part and an analog circuit including the analog circuit part; wherein the digital circuit and the analog circuit also include power network information and corresponding connection module information;

[0105] A digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and the files are submitted to the digital simulator and the analog simulator for simulation respectively.

[0106] The description of each module above refers to the corresponding description in the method embodiment and will not be repeated here.

[0107] An embodiment of the present invention further provides a non-volatile computer storage medium storing at least one executable instruction, which can execute operations corresponding to the digital-analog hybrid circuit simulation method in any of the above method embodiments.

[0108] An embodiment of the present application provides a computer program product, which includes at least one executable instruction or computer program, which can enable a processor to perform operations corresponding to the digital analog mixed circuit simulation method in any of the above method embodiments.

[0109] Figure 11 A schematic structural diagram of a computing device according to an embodiment of the present invention is shown. The specific implementation of the computing device is not limited to the specific implementation of the computing device in the specific embodiment of the present invention.

[0110] like Figure 11 As shown, the computing device may include a processor 1102 , a communication interface 1104 , a memory 1106 , and a communication bus 1108 .

[0111] in:

[0112] The processor 1102 , the communication interface 1104 , and the memory 1106 communicate with each other via a communication bus 1108 .

[0113] The communication interface 1104 is used to communicate with other devices such as clients or other servers.

[0114] The processor 1102 is configured to execute the program 1110 , and specifically to execute the relevant steps in the above-mentioned embodiment of the digital-analog hybrid circuit simulation method.

[0115] Specifically, the program 1110 may include program codes, which include computer operation instructions.

[0116] Processor 1102 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. The one or more processors included in a computing device may be of the same type, such as one or more CPUs, or may be of different types, such as one or more CPUs and one or more ASICs.

[0117] The memory 1106 is used to store the program 1110. The memory 1106 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0118] Program 1110 can be specifically used to enable processor 1102 to execute the digital analog mixed circuit simulation method in any of the above-mentioned method embodiments. The specific implementation of each step in program 1110 can refer to the corresponding descriptions in the corresponding steps and units in the above-mentioned digital analog mixed circuit simulation embodiment, and will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-mentioned devices and modules can refer to the corresponding process description in the above-mentioned method embodiment, and will not be repeated here.

[0119] The algorithm or display provided herein is not inherently related to any particular computer, virtual system or other device. Various general-purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the embodiment of the present invention is not directed to any specific programming language. It should be understood that various programming languages ​​can be utilized to implement the content of the embodiment of the present invention described herein, and the above description of specific languages ​​is for the purpose of disclosing the preferred implementation of the embodiment of the present invention.

[0120] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0121] Similarly, it should be understood that in order to streamline the embodiments of the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the embodiments of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed approach should not be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all of the features of the individual embodiments disclosed above. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0122] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition may be divided into multiple submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed herein may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0123] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims below, any of the claimed embodiments may be used in any combination.

[0124] The various component embodiments of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components according to the embodiments of the present invention. The embodiments of the present invention can also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for executing part or all of the methods described herein. Such a program implementing an embodiment of the present invention can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0125] It should be noted that the above embodiments illustrate rather than limit the embodiments of the invention, and that a person skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The embodiments of the invention may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names. The steps in the above embodiments should not be understood as limiting the order of execution unless otherwise specified.

Claims

1. A digital analog hybrid circuit simulation method, characterized in that the method include: Read in digital circuit source files, analog circuit source files and circuit configuration information for parsing, and establish a mixed signal hierarchical structure including digital circuit parts and analog circuit parts; Determine the mixed signal boundaries of the mixed signal hierarchical structure, optimize the mixed signal boundaries according to the signal connection conditions between each mixed signal boundary, and insert corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries; the digital-to-analog conversion unit is used for signal synchronization during simulation; wherein, the mixed signal hierarchical structure is topologically expanded, and the behavior of the circuit structure is subjected to signal analysis according to the topological relationship of the signal, and the signal affected by the digital behavior is marked as a digital circuit, the signal affected by the analog behavior is marked as an analog circuit, and the signal affected by both digital and analog behaviors is marked as a mixed signal boundary; based on the mixed signal boundary, determine whether the analog circuits at the two mixed signal boundaries are connected to analog devices, or whether the digital circuits are connected to digital behaviors; if not, insert a corresponding signal connection between the two mixed signal boundaries; if so, insert a digital-to-analog conversion unit between the two mixed signal boundaries; Split the optimized mixed signal hierarchical structure to obtain two digital circuits and analog circuits with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file, wherein, according to the flattened mixed signal hierarchical structure after optimization, it is mapped into two digital circuits and analog circuits with the same circuit structure, delete the analog behavior and analog signal in the digital circuit, obtain a digital circuit that retains the digital behavior and digital signal and a digital-to-analog conversion unit, delete the digital behavior and digital signal in the analog circuit, obtain an analog circuit that retains the analog behavior and analog signal and a digital-to-analog conversion unit; generate a digital circuit netlist file based on the digital circuit, and generate an analog circuit netlist file based on the analog circuit, and submit them to a digital simulator and an analog simulator for simulation respectively; the digital circuit netlist file contains digital behavior and digital signal, and the analog circuit netlist file contains analog behavior and analog signal; the mixed signal boundary of the digital circuit netlist file and the analog circuit netlist file contains the digital-to-analog conversion unit, so that the digital simulator and the analog simulator can read the corresponding netlist files for simulation respectively, and call the communication interface for signal synchronization based on the digital-to-analog conversion unit.

2. The method according to claim 1, characterized in that The step of reading in the digital circuit source file, the analog circuit source file and the circuit configuration information for parsing to establish a mixed signal hierarchical structure including the digital circuit part and the analog circuit part further includes: Using a preset circuit analysis program to read in digital circuit source files, analog circuit source files and circuit configuration information; The connection information contained in the digital circuit source file, the analog circuit source file and the circuit configuration information is parsed to establish a mixed signal hierarchical structure including a digital circuit part and an analog circuit part.

3. The method according to claim 1 or 2, characterized in that The method further comprises: Read digital circuit source files, analog circuit source files, circuit configuration information, and power consumption design files for parsing, and establish a mixed-signal hierarchical structure including digital circuit parts and analog circuit parts, as well as a voltage domain structure including power supply connection relationships; The voltage domain structure is split to obtain digital circuits and analog circuits containing power network information and connection module information, and a digital circuit netlist file and an analog circuit netlist file containing power network information are generated; the power network information includes signal voltage, current, load strength and / or reference voltage.

4. The method according to claim 3, characterized in that The step of splitting the voltage domain structure to obtain digital circuits and analog circuits including power network information and connection module information, and generating a digital circuit netlist file and an analog circuit netlist file including the power network information further includes: According to the voltage domain structure, the analog circuit portion and the digital circuit portion in the voltage domain structure are split to obtain a digital circuit including the digital circuit portion and an analog circuit including the analog circuit portion; wherein the digital circuit and the analog circuit further include power network information and corresponding connection module information; A digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and the files are submitted to a digital simulator and an analog simulator for simulation respectively.

5. A digital analog hybrid circuit simulation device, characterized in that: The device includes: A construction module is suitable for reading digital circuit source files, analog circuit source files and circuit configuration information for parsing, and establishing a mixed signal hierarchical structure including digital circuit parts and analog circuit parts; A boundary optimization module is adapted to determine the mixed signal boundaries of the mixed signal hierarchical structure, optimize the mixed signal boundaries according to the signal connection conditions between the mixed signal boundaries, and insert corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries; the digital-to-analog conversion units are used for signal synchronization during simulation; wherein, the mixed signal hierarchical structure is topologically unfolded, and the behavior of the circuit structure is subjected to signal analysis according to the topological relationship of the signal, and the signals affected by digital behavior are marked as digital circuits, the signals affected by analog behavior are marked as analog circuits, and the signals affected by both digital and analog behaviors are marked as mixed signal boundaries; based on the mixed signal boundaries, it is determined whether the analog circuits at the two mixed signal boundaries are connected to analog devices, or whether the digital circuits are connected to digital behaviors; if not, a corresponding signal connection is inserted between the two mixed signal boundaries; if so, a digital-to-analog conversion unit is inserted between the two mixed signal boundaries; A splitting module is suitable for splitting the mixed signal hierarchical structure after optimization processing to obtain two digital circuits and analog circuits with the same circuit structure, and generating a digital circuit netlist file and an analog circuit netlist file. According to the flattened mixed signal hierarchical structure after optimization processing, it is mapped into two digital circuits and analog circuits with the same circuit structure, the analog behavior and analog signal in the digital circuit are deleted, and the digital circuit retains the digital behavior and digital signal as well as the digital-to-analog conversion unit is obtained; the digital behavior and digital signal in the analog circuit are deleted, and the analog circuit retains the analog behavior and analog signal as well as the digital-to-analog conversion unit is obtained; a digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and they are submitted to a digital simulator and an analog simulator for simulation respectively; wherein the digital circuit netlist file contains digital behavior and digital signal, and the analog circuit netlist file contains analog behavior and analog signal; the mixed signal boundary of the digital circuit netlist file and the analog circuit netlist file contains the digital-to-analog conversion unit, so that the digital simulator and the analog simulator can read the corresponding netlist file for simulation respectively, and call the communication interface for signal synchronization based on the digital-to-analog conversion unit.

6. A computing device, characterized in that include: A processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the digital-analog hybrid circuit simulation method according to any one of claims 1 to 4.

7. A computer storage medium, characterized in that The storage medium stores at least one executable instruction, and the executable instruction enables the processor to execute operations corresponding to the digital-analog hybrid circuit simulation method according to any one of claims 1 to 4.

8. A computer program product, characterized in that The method comprises at least one executable instruction, wherein the executable instruction enables a processor to execute operations corresponding to the digital-analog mixed circuit simulation method according to any one of claims 1 to 4.

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