Display driving circuit and method, chip and computer equipment
By dynamically adjusting the read timing according to the memory state in the display driver circuit, the memory resource waste caused by DE timing jitter is solved, and data drivers without interruption and correct output under small memory conditions are achieved.
Patent Information
- Application Number
- CN202510803654.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-16
- Publication Date
- 2025-07-25
AI Technical Summary
In the prior art, the display driver circuit needs a large amount of memory to ensure the correct output of image data when facing DE timing jitter, resulting in wasted memory resources.
By dynamically adjusting the reading timing of image data according to the memory state, ensuring that the pixel data of each row is stored in memory before being read, and using a smaller memory capacity to achieve data driving without interruption, including the combination of write control module, memory state module, DEB control module and read control module.
It ensures the correct output of image data under smaller memory conditions, saves memory resources, and adapts to dysfunction of DE timing, avoids display errors.
Smart Images
Figure CN120375744A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technologies, and particularly to a display driving circuit, method, chip, and computer device. Background Art
[0002] In the field of display technologies, image data in a host needs to be transmitted to a display panel via a Display Driver Integrated Circuit (DDI) to drive the display panel to display an image. Summary of the Invention
[0003] This application provides a display driving circuit, method, chip, and computer device for driving and displaying image data using a smaller memory.
[0004] In a first aspect, a display driving circuit is provided, and the display driving circuit is configured to:
[0005] Adjust the reading timing of image data according to the memory state of a memory, where the image data includes pixel data of N rows, the capacity of the memory is used to store pixel data of g rows, g is a positive integer greater than 1, the memory state indicates the amount of data stored in the memory, and the reading timing indicates the reading time of pixel data for each row;
[0006] Read the pixel data in the memory based on the reading timing, and the read pixel data is used to drive the display panel to display an image.
[0007] In a possible implementation, the reading timing includes a data enable blank (DEB) time period for each row, and the length of the DEB time period of the (i - g + 1)-th row is negatively correlated with the amount of data in the memory after writing the pixel data of the i-th row, and the reading time of the pixel data of the (i - g + 2)-th row is after the end time of the DEB time period of the (i - g + 1)-th row, where i is a positive integer greater than or equal to g and less than or equal to N.
[0008] In a possible implementation, the display driving circuit includes a writing control module, a memory state module, a DEB control module, and a reading control module;
[0009] The writing control module is configured to: write the pixel data of the i-th row into the memory;
[0010] The memory state module is configured to: determine the memory state of the memory;
[0011] The DEB control module is configured to: adjust the DEB time period of the (i - g + 1)-th row according to the memory state;
[0012] The read control module is configured to: after the end time of the DEB time period of the (i - g + 1)-th row is reached, read the pixel data of the (i - g + 2)-th row in the memory.
[0013] In a possible implementation, when the amount of data stored in the memory is less than the first threshold, the DEB time period in the adjusted read timing is increased by a first time period compared to the DEB time period in the read timing before adjustment;
[0014] When the amount of data stored in the memory is greater than or equal to the first threshold and less than the second threshold, the DEB time period in the adjusted read timing is increased by a second time period compared to the DEB time period in the read timing before adjustment, where the first threshold is less than the second threshold;
[0015] When the amount of data stored in the memory is greater than or equal to the second threshold and less than the third threshold, the DEB time period in the adjusted read timing remains unchanged compared to the DEB time period in the read timing before adjustment, where the second threshold is less than the third threshold;
[0016] When the amount of data stored in the memory is greater than or equal to the third threshold and less than the fourth threshold, the DEB time period in the adjusted read timing is decreased by a third time period compared to the DEB time period in the read timing before adjustment, where the third threshold is less than the fourth threshold;
[0017] When the amount of data stored in the memory is greater than or equal to the fourth threshold, the DEB time period in the adjusted read timing is decreased by a fourth time period compared to the DEB time period in the read timing before adjustment.
[0018] In a possible implementation, when the number of rows of the image data stored in the memory is less than the fifth threshold, the DEB time period in the adjusted read timing is increased by a fifth time period compared to the DEB time period in the read timing before adjustment;
[0019] When the number of rows of the image data stored in the memory is greater than or equal to the fifth threshold and less than the sixth threshold, the DEB time period in the adjusted read timing remains unchanged compared to the DEB time period in the read timing before adjustment, where the fifth threshold is less than the sixth threshold;
[0020] When the number of rows of the image data stored in the memory is greater than or equal to the sixth threshold and less than or equal to g, the DEB time period in the adjusted read timing is decreased by a sixth time period compared to the DEB time period in the read timing before adjustment.
[0021] Second aspect, a display driving method is provided, and the display driving method includes:
[0022] Adjust the reading timing of the image data according to the memory state of the memory. The image data includes pixel data of N rows, and the capacity of the memory is used to store pixel data of g rows, where g is a positive integer greater than 1. The memory state indicates the amount of data stored in the memory, and the reading timing indicates the reading time of each row of pixel data.
[0023] Read the pixel data in the memory based on the reading timing, and the read pixel data is used to drive the display panel to display an image.
[0024] In a possible implementation, the reading timing includes a data enable blank (DEB) time period for each row. The length of the DEB time period of the (i - g + 1)-th row is negatively correlated with the amount of data in the memory after writing the pixel data of the i-th row. The reading time of the pixel data of the (i - g + 2)-th row is after the end time of the DEB time period of the (i - g + 1)-th row, where i is a positive integer greater than or equal to g and less than or equal to N.
[0025] In a possible implementation, the adjusting the reading timing of the image data according to the memory state of the memory includes:
[0026] Write the pixel data of the i-th row into the memory, and determine the memory state of the memory.
[0027] Adjust the DEB time period of the (i - g + 1)-th row according to the memory state.
[0028] The reading the data in the memory based on the reading timing for output includes:
[0029] After reaching the end time of the DEB time period of the (i - g + 1)-th row, read the pixel data of the (i - g + 2)-th row in the memory for output.
[0030] In a possible implementation, when the amount of data stored in the memory is less than the first threshold, the DEB time period in the adjusted reading timing is increased by a first time period compared to the DEB time period in the unadjusted reading timing.
[0031] When the amount of data stored in the memory is greater than or equal to the first threshold and less than the second threshold, the DEB time period in the adjusted reading timing is increased by a second time period compared to the DEB time period in the unadjusted reading timing, where the first threshold is less than the second threshold.
[0032] When the amount of data stored in the memory is greater than or equal to the second threshold and less than the third threshold, the DEB time period in the adjusted read timing remains unchanged compared to the DEB time period in the read timing before adjustment, where the second threshold is less than the third threshold;
[0033] When the amount of data stored in the memory is greater than or equal to the third threshold and less than the fourth threshold, the DEB time period in the adjusted read timing is reduced by a third time period compared to the DEB time period in the read timing before adjustment, where the third threshold is less than the fourth threshold;
[0034] When the amount of data stored in the memory is greater than or equal to the fourth threshold, the DEB time period in the adjusted read timing is reduced by a fourth time period compared to the DEB time period in the read timing before adjustment.
[0035] In a possible implementation, when the number of rows of image data stored in the memory is less than the fifth threshold, the DEB time period in the adjusted read timing is increased by a fifth time period compared to the DEB time period in the read timing before adjustment;
[0036] When the number of rows of image data stored in the memory is greater than or equal to the fifth threshold and less than the sixth threshold, the DEB time period in the adjusted read timing remains unchanged compared to the DEB time period in the read timing before adjustment, where the fifth threshold is less than the sixth threshold;
[0037] When the number of rows of image data stored in the memory is greater than or equal to the sixth threshold and less than or equal to g, the DEB time period in the adjusted read timing is reduced by a sixth time period compared to the DEB time period in the read timing before adjustment.
[0038] In a third aspect, a chip is further provided, and the chip includes the display driving circuit described in the first aspect above.
[0039] In a possible implementation, the chip is a DDI.
[0040] In a fourth aspect, a computer device is further provided, and the computer device includes the display driving circuit described in the first aspect above.
[0041] The technical solution provided by this application can at least bring the following beneficial effects:
[0042] In this technical solution, the reading timing of image data can be dynamically adjusted according to the memory state. The change in the reading timing is manifested as the change in the data reading speed. The memory state is determined by the data storage speed, so that the data reading speed matches the data storage speed. Thus, without storing a large number of rows of pixel data in the memory, the reading speed can be dynamically adjusted to ensure that each row of pixel data read has been stored in the memory, that is, to ensure that the data reading time is not earlier than the storage time, achieving the effect of uninterrupted data driving and saving memory resources. Brief Description of the Drawings
[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings.
[0044] Figure 1 is a schematic diagram of data transmission provided by an embodiment of the present application;
[0045] Figure 2 is a timing diagram of a synchronization signal provided by an embodiment of the present application;
[0046] Figure 3 is another timing diagram of a synchronization signal provided by an embodiment of the present application;
[0047] Figure 4 is another timing diagram of a synchronization signal provided by an embodiment of the present application;
[0048] Figure 5 is another timing diagram of a synchronization signal provided by an embodiment of the present application;
[0049] Figure 6 is a schematic structural diagram of a display driving circuit provided by an embodiment of the present application;
[0050] Figure 7 is a schematic diagram of adjusting the DEB time provided by an embodiment of the present application;
[0051] Figure 8 is a schematic diagram of the timing comparison of a synchronization signal provided by an embodiment of the present application;
[0052] Figure 9 is a flowchart of a display driving method provided by an embodiment of the present application. Detailed Embodiments
[0053] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the drawings.
[0054] In the field of display technology, DDI is an integrated circuit that drives a display panel or a display screen to perform image display. Exemplarily, referring to Figure 1 , DDI receives an image signal output by a host, converts the image signal into a display signal for driving a display panel (Display), and sends the display signal to the display panel so that the display panel drives the display of an image according to the display signal. Taking a liquid crystal display panel (Liquid Crystal Display, LCD) as an example, DDI receives an image signal from a host, converts the image signal into a gate signal and a source signal for driving the LCD, and sends the gate signal and the source signal to the LCD to drive the pixels on the LCD to emit light, thereby driving the LCD to display an image.
[0055] Among them, the above-mentioned image signal or display signal both belong to image data, and the image data needs to be transmitted based on a synchronization signal. Optionally, the synchronization signal includes, but is not limited to, a vertical synchronization (Vsync) signal, a horizontal synchronization (Hsync) signal, and a data enable (DE) signal. The Vsync signal is used to indicate the start of a frame of images; the Hsync signal is used to indicate the start of a line in a frame of images; the DE signal is used to distinguish between a valid data interval and a blanking interval, and the blanking interval is an interval that does not include valid data.
[0056] Exemplarily, the timing diagram of the synchronization signal can be as Figure 2 shown. The Vsync presents a periodic pulse signal, and the low level indicates the start of a new frame of images. Taking a display panel that performs display based on cathode ray tube (CRT) technology as an example, during each low-level pulse, the electron gun of the display panel will return to the top of the screen to prepare for the scanning process of a new frame. For the DE signal, when the DE is at a high level, it represents the valid data interval in 1 line, which means that the data transmitted within this interval is valid and can be received and displayed by the display panel, and this stage is called the DE time period; when the DE is at a low level, it represents the blanking interval in 1 line, which means that the data transmitted within this interval is invalid and belongs to the interval between the valid data of rows, such as black screen data, and this stage is called the data enable blank (DEB) time period.
[0057] If the timing of the DE signal for DDI to transmit image data is stable, then generally the image data output by DDI to the display panel will not be incorrect. However, there are at least the following several situations that will cause the timing of the DE signal to be unstable, which is simply referred to as unstable DE timing. Among them, stable DE timing means that the lengths of the DEB time periods of different lines in the same frame are the same, for example Figure 2As shown; unstable DE timing means that the lengths of the DEB time periods of different lines in the same frame are different. For example Figure 3 As shown
[0058] Case 1: The host transmits image data to the DDI based on unstable DE timing
[0059] For example, the operating frequency of the host will change according to the external temperature or the change of the output data, and the change of the operating frequency will cause the DE timing of the image data output by the host to jitter. Taking the synchronization signal of the image data input from the host to the DDI as Figure 3 As shown in the example, it can be seen that the lengths of the DEB time periods between different lines are different, that is, the DE timing is unstable
[0060] Case 2: The DDI needs to output with a size smaller than the image size output by the host
[0061] For example, the DDI includes a scaling module, and the scaling module is used to perform scaling processing on the received image data. Scaling processing means reducing the size of the image. In this case, even if the host inputs image data to the scaling module of the DDI with stable DE timing, the number of rows of the image data will decrease after the scaling processing, resulting in jitter of the DE timing of the image data output by the scaling module. Refer to Figure 4 The input timing and output timing of the scaling module shown. It can be seen that the number of DE time periods in the DE signal decreases proportionally, that is, the number of lines decreases proportionally, resulting in different lengths of the DEB time periods between different lines. Among them, the reduced number of lines is proportional to the reduction ratio of the image size
[0062] Case 3: Since the current consumption of the DDI will change according to the output mode or the change of the input image, which in turn causes the change of the internal working temperature of the DDI, the change of the internal working temperature will also change the internal working frequency of the DDI, and the change of the working frequency makes the DE timing of the image data output by the DDI jitter
[0063] In view of the above-mentioned instability of the DEB time, the time for the DDI to output image data needs to be after the time when the host inputs the corresponding image data to the DDI, so as to ensure that the image data output by the DDI is error-free, and further ensure that the display panel displays the image correctly. Otherwise, since the DDI has not received the image data input by the host, the DDI has no accurate image data to output to the display panel, resulting in a display error on the display panel. For example, since the image data includes pixel data in multiple lines, if the host has not input the pixel data of the 10th line to the DDI, and the DE signal of the DDI indicates the valid data of the pixel data of the 10th line output by the DDI, causing the display panel to display according to the pixel data of the 10th line, but since the DDI actually does not output the valid pixel data of the 10th line, it results in a display error on the display panel. Therefore, during the process of the DDI transmitting image data, it is necessary to adjust the DE timing according to different transmission situations of the image data to ensure that the DDI outputs valid image data according to the correct DE timing.
[0064] In the related art, a memory is set in the DDI to cope with the jitter of the DE timing. Exemplarily, if the resolution of the display panel is 400x2000, then 1 frame of image includes 2000 lines, and 1 line includes 400 sub-pixels. In a 4-pixel structure, the DDI processes the pixel data of 4 sub-pixels simultaneously in each clock cycle. Therefore, for each frame of image, the DDI processes 100x2000 pixel units, and each pixel unit includes 4 sub-pixels, which is equivalent to running at a resolution of 100x2000, that is, 1 frame of image includes 2000 lines, and 1 line includes 100 pixel units.
[0065] Taking the jitter of the DE timing caused by the above-mentioned case three as an example, see Figure 5 , for the normal timing input from the host to the DDI, the transmission time of the pixel data of 1 line includes a 100us DE time period and a 100us DEB time period. Among them, the DE time period refers to the time period of the valid data in the pixel data of 1 line, and the DEB time period refers to the time period of the invalid data in the pixel data of 1 line. Thus, the transmission time of the pixel data of 1 line is 200us, and the transmission time of the pixel data of 2000 lines is 200*2000 = 400000us.
[0066] In a possible situation, due to some reason, the internal working frequency of the DDI is faster than that of the host, such as Figure 5As shown, in the DE1 signal output by the DDI to the display panel, the transmission time of the pixel data in one row is less than 200 us. For example, taking the jitter of one pixel time per row as an example, one pixel time refers to the transmission time corresponding to the pixel data of one sub-pixel. If one pixel time is 1 us (microsecond), the transmission time of the pixel data in each row will be reduced by 1 us. Through accumulation, the transmission time of the pixel data of 2000 rows will be reduced by 2000 us, that is, the pixel data of 2000 rows will be output and completed 2000 us earlier. Therefore, if the DDI outputs data according to this DE1 timing sequence, when outputting the pixel data of the second row, since the host has not input the pixel data of the second row, an error will occur in the DDI output.
[0067] That is to say, since the DDI needs to output image data after the host inputs the image data, therefore, in Figure 5 the case where the working frequency of the DDI shown is faster than that of the host, the DDI needs to wait for the host to input the image signal, and then convert the image signal into a display signal and output it to the display panel. To ensure that the DDI can output the display signal normally, the DDI needs to output according to Figure 5 the DE2 signal shown. In this case, for the image data input by the host to the DDI, the DDI needs to write the pixel data of the first 10 rows into the memory, and then starting from when the host inputs the pixel data of the 11th row, while writing the pixel data of the 11th row into the memory, while reading the pixel data from the first row of pixel data in the memory and outputting them in order, so that the end time of the DDI outputting one frame of image is aligned with the end time of the host inputting one frame of image. Therefore, in the case where one row of memory is used to store the pixel data of 400 sub-pixels, 10 rows of memory need to be set inside the DDI to store the pixel data of 10 rows.
[0068] However, a large amount of memory is required in the related art to ensure the correct output of image data. The embodiment of the present application provides a display driving circuit, which can be applied to the DDI and can use a smaller memory to respond to the jitter of the DE timing sequence to ensure the correct output of image data.
[0069] In the embodiment of the present application, the display driving circuit is configured to: adjust the reading timing sequence of the image data according to the memory state of the memory. The image data includes the pixel data of N rows, the capacity of the memory is used to store the pixel data of g rows, g is a positive integer greater than 1, the memory state indicates the amount of data stored in the memory, and the reading timing sequence indicates the reading time of the pixel data of each row; read the pixel data in the memory based on the reading timing sequence, and the read pixel data is used to drive the display panel to display an image. Wherein, the memory is connected to the display driving circuit, and the display driving circuit can write image data into the memory and can also read image data from the memory, that is, the memory is used to temporarily store image data.
[0070] The display driving circuit can dynamically adjust the reading timing of image data according to the memory state. The change in the reading timing is manifested as the change in the data reading speed. The memory state is determined by the data storage speed, so that the data reading speed matches the data storage speed. Thus, without storing a large number of rows of pixel data in the memory, it is possible to ensure that each row of pixel data read has been stored in the memory by dynamically adjusting the reading speed, that is, to ensure that the data reading time is not earlier than the data storage time, achieving the effect of uninterrupted display driving and saving memory resources.
[0071] Optionally, the reading timing includes the DEB time period of each row. The length of the DEB time period of the (i - g + 1)-th row is negatively correlated with the amount of data in the memory after writing the pixel data of the i-th row. The reading time of the pixel data of the (i - g + 2)-th row is after the end time of the DEB time period of the (i - g + 1)-th row, where i is a positive integer greater than or equal to g and less than or equal to N.
[0072] Among them, the implementation manner of the reading time of the pixel data of the (i - g + 2)-th row being after the end time of the DEB time period of the (i - g + 1)-th row: it can be that when the end time of the DEB time period of the (i - g + 1)-th row is reached, the pixel data of the (i - g + 2)-th row is immediately read from the memory; or, it can also be that after the end time of the DEB time period of the (i - g + 1)-th row is reached, in response to the rising edge or falling edge of the clock signal being triggered, the pixel data of the (i - g + 2)-th row is read from the memory.
[0073] Exemplarily, taking g = 2 as an example, when writing the pixel data of the i-th row into the memory, the memory state of the memory is obtained. At this time, the pixel data of the previous i rows is stored in the memory; the DEB time period of the (i - 1)-th row is adjusted according to the memory state, so that the length of the DEB time period is negatively correlated with the amount of data stored in the memory; after the end of the DEB time period of the (i - 1)-th row, the pixel data of the i-th row in the memory is read.
[0074] Thus, when writing the pixel data of the next row into the memory, the display driving circuit can dynamically adjust the DEB time period of the previous row by querying the memory state. The change in the DEB time period is manifested as the change in the data reading speed, so that the data reading speed matches the memory state, and the effect of error-free data reading can be achieved. That is, the reading of each row of pixel data is after the pixel data of that row is written into the memory, and the memory only needs to store the pixel data of 2 rows, saving memory resources.
[0075] Optionally, when the memory capacity is sufficient, g can be 3. In this case, when the pixel data of the i-th row is input, the DEB time period of the (i - 2)-th row can be adjusted according to the memory state. After the DEB time period of the (i - 2)-th row ends, the pixel data of the (i - 1)-th row in the memory is read. At this time, the memory needs to store the pixel data of 3 rows.
[0076] In a possible implementation manner, the display driving circuit is further configured to: when writing the pixel data before the i-th row into the memory, not read the pixel data from the memory; after writing the pixel data of the N-th row into the memory, no longer adjust the DEB time period, and continuously read the subsequent pixel data according to the current DEB time period.
[0077] Exemplarily, refer to Figure 6 the structural schematic diagram of the display driving circuit shown. The display driving circuit includes a writing control module, a memory state module, a DEB control module, and a reading control module.
[0078] Among them, the writing control module is configured to: write the pixel data of the i-th row into the memory. The memory state module is configured to: determine the memory state of the memory. The DEB control module is configured to: adjust the DEB time period of the (i - g + 1)-th row according to the memory state. The reading control module is configured to: after reaching the end time of the DEB time period of the (i - g + 1)-th row, read the pixel data of the (i - g + 2)-th row in the memory.
[0079] Optionally, the writing control module is further configured to generate image data. The way to generate image data can be to receive a row of image signals output by the host, and the image data written into the memory here is the image signal; or, the way to generate image data can also be to receive a row of image signals output by the scaling module. The scaling module receives a row of image signals output by the host, performs scaling processing on the image signals and then outputs them. The application of the scaling module can be referred to the foregoing description and will not be elaborated here. The way for the reading control module to output image data can be to convert the read row of image signals into a row of display signals for driving the display screen, and output the row of display signals to the display screen to drive the display screen to display.
[0080] Optionally, the memory state can be divided into empty, almost empty, normal, almost full, and full in terms of the amount of data stored. For example, when the amount of data stored in the memory is less than the first threshold, the memory state is empty; when the amount of data stored in the memory is greater than or equal to the first threshold and less than the second threshold, the memory state is almost empty; when the amount of data stored in the memory is greater than or equal to the second threshold and less than the third threshold, the memory state is normal; when the amount of data stored in the memory is greater than or equal to the third threshold and less than the fourth threshold, the memory state is almost full; when the amount of data stored in the memory is greater than or equal to the fourth threshold, the memory state is full.
[0081] Among them, the first threshold is less than the second threshold, the second threshold is less than the third threshold, and the third threshold is less than the fourth threshold. Optionally, the specific values of the first threshold, the second threshold, the third threshold, and the fourth threshold can be flexibly adjusted according to the application scenario. For example, the first threshold is 5%, the second threshold is 10%, the third threshold is 90%, and the fourth threshold is 95%.
[0082] In the embodiments of the present application, the working frequency of the DDI can be adaptively adjusted according to different memory states, and the change in the working frequency of the DDI leads to a change in the read timing of a row of pixel data. The read timing of a row of pixel data includes the DE period + the DEB period. For example, when the memory state is empty, the DEB period slows down the first period; when the memory state is almost empty, the DEB period slows down the second period; when the memory state is normal, the DEB period remains unchanged; when the memory state is almost full, the DEB period speeds up the third period; when the memory state is full, the DEB period speeds up the fourth period.
[0083] Optionally, the first period is greater than the second period, the third period is less than the fourth period, and the specific values of the first period, the second period, the third period, and the fourth period can be flexibly adjusted according to the application scenario. For example, the first period is 2 pixel times, the second period is 1 pixel time, the third period is 1 pixel time, and the fourth period is 2 pixel times; or, the first period is 4 pixel times, the second period is 2 pixel times, the third period is 2 pixel times, and the fourth period is 4 pixel times; or, the first period is 3 pixel times, the second period is 1 pixel time, the third period is 2 pixel times, and the fourth period is 5 pixel times. According to the foregoing content, 1 pixel time refers to the transmission time corresponding to the pixel data of 1 sub-pixel, and then 2 pixel times refers to the transmission time corresponding to the pixel data of 2 sub-pixels.
[0084] When the read timing includes a DEB time period for each row and the amount of data stored in the memory is less than the first threshold, the memory state is empty. At this time, the DEB time period needs to be increased by a first time period to make the memory state reach an almost empty state or a normal state. When the amount of data stored in the memory is greater than or equal to the first threshold and less than the second threshold, the memory state is almost empty. At this time, the DEB time period can be increased by a second time period to make the memory state reach a normal state.
[0085] When the amount of data stored in the memory is greater than or equal to the second threshold and less than the third threshold, the memory state is normal. At this time, the DEB time period can be kept unchanged. When the amount of data stored in the memory is greater than or equal to the third threshold and less than the fourth threshold, the memory state is almost full. At this time, the DEB time period can be decreased by a third time period to make the memory state reach a normal state. When the amount of data stored in the memory is greater than or equal to the fourth threshold, the memory state is full. At this time, the DEB time period can be decreased by a fourth time period to make the memory state reach an almost full state or a normal state.
[0086] Then, the relationship between the memory state and the read timing satisfies: when the amount of data stored in the memory is less than the first threshold, the DEB time period in the adjusted read timing is increased by a first time period compared to the DEB time period in the unadjusted read timing; when the amount of data stored in the memory is greater than or equal to the first threshold and less than the second threshold, the DEB time period in the adjusted read timing is increased by a second time period compared to the DEB time period in the unadjusted read timing, where the first threshold is less than the second threshold; when the amount of data stored in the memory is greater than or equal to the second threshold and less than the third threshold, the DEB time period in the adjusted read timing remains unchanged compared to the DEB time period in the unadjusted read timing, where the second threshold is less than the third threshold; when the amount of data stored in the memory is greater than or equal to the third threshold and less than the fourth threshold, the DEB time period in the adjusted read timing is decreased by a third time period compared to the DEB time period in the unadjusted read timing, where the third threshold is less than the fourth threshold; when the amount of data stored in the memory is greater than or equal to the fourth threshold, the DEB time period in the adjusted read timing is decreased by a fourth time period compared to the DEB time period in the unadjusted read timing.
[0087] Exemplarily, as Figure 7 shown, after data is written into the memory, the memory state is obtained; when the memory state is empty, the DEB time period is increased by 2 pixel times; when the memory state is almost empty, the DEB time period is increased by 1 pixel time; when the memory state is normal, the DEB time period remains unchanged; when the memory state is almost full, the DEB time period is decreased by 1 pixel time; when the memory state is full, the DEB time period is decreased by 2 pixel times. Thus,Figure 5 Taking the DE timing jitter shown as an example, the comparison chart between the DE signal output in the related art and the DE signal output in the embodiment of the present application is as Figure 8 shown. Among them, in the related art, 10 rows of pixel data need to be stored, while only 2 rows of pixel data need to be stored in the embodiment of the present application. That is, the embodiment of the present application uses less memory to cope with the DE timing jitter.
[0088] In another possible implementation, the amount of data stored in the memory can be measured according to the number of rows of image data stored in the memory. In this case, the relationship between the memory state and the read timing satisfies: when the number of rows of image data stored in the memory is less than the fifth threshold, the DEB time period in the adjusted read timing is increased by the fifth time period compared with the DEB time period in the read timing before adjustment; when the number of rows of image data stored in the memory is greater than or equal to the fifth threshold and less than the sixth threshold, the DEB time period in the adjusted read timing remains unchanged compared with the DEB time period in the read timing before adjustment, and the fifth threshold is less than the sixth threshold; when the number of rows of image data stored in the memory is greater than or equal to the sixth threshold and less than or equal to g, the DEB time period in the adjusted read timing is decreased by the sixth time period compared with the DEB time period in the read timing before adjustment.
[0089] Similar to the above method, the fifth threshold and the sixth threshold can be flexibly defined as any values less than g. Taking g = 5 as an example, the fifth threshold is 2 and the sixth threshold is 4. The fifth time period and the sixth time period can also be flexibly defined. For example, the fifth time period is 1 pixel time and the sixth time period is 2 pixel time.
[0090] In summary, the embodiment of the present application adaptively adjusts the DEB time period, which can significantly reduce the memory size for coping with the DE timing jitter caused by frequency changes, etc., and simplify the timing setting of the display driving circuit.
[0091] See Figure 9 , Figure 9 which is a flowchart of a display driving method provided by the present application. As Figure 9 shown, the method includes but is not limited to the following steps 901 and 902.
[0092] Step 901: Adjust the read timing of the image data according to the memory state of the memory. The image data includes N rows of pixel data, the capacity of the memory is used to store g rows of pixel data, g is a positive integer greater than 1, the memory state indicates the amount of data stored in the memory, and the read timing indicates the read time of each row of pixel data.
[0093] Step 902: Read the pixel data in the memory based on the read timing, and the read pixel data is used to drive the display panel to display an image.
[0094] In a possible implementation, the read timing includes a DEB time period for each row. The length of the DEB time period of the (i - g + 1)-th row is negatively correlated with the amount of data in the memory after writing the pixel data of the i-th row. The read time of the pixel data of the (i - g + 2)-th row is after the end time of the DEB time period of the (i - g + 1)-th row, where i is a positive integer greater than or equal to g and less than or equal to N.
[0095] In a possible implementation, according to the memory state of the memory, adjusting the read timing of the image data includes: writing the pixel data of the i-th row into the memory and determining the memory state of the memory; adjusting the DEB time period of the (i - g + 1)-th row according to the memory state; then reading the pixel data in the memory based on the read timing, including: reading the pixel data of the (i - g + 2)-th row in the memory after reaching the end time of the DEB time period of the (i - g + 1)-th row.
[0096] In a possible implementation, when the amount of data stored in the memory is less than the first threshold, the DEB time period in the adjusted read timing is increased by a first time period compared with the DEB time period in the unadjusted read timing; when the amount of data stored in the memory is greater than or equal to the first threshold and less than the second threshold, the DEB time period in the adjusted read timing is increased by a second time period compared with the DEB time period in the unadjusted read timing, where the first threshold is less than the second threshold; when the amount of data stored in the memory is greater than or equal to the second threshold and less than the third threshold, the DEB time period in the adjusted read timing remains unchanged compared with the DEB time period in the unadjusted read timing, where the second threshold is less than the third threshold; when the amount of data stored in the memory is greater than or equal to the third threshold and less than the fourth threshold, the DEB time period in the adjusted read timing is decreased by a third time period compared with the DEB time period in the unadjusted read timing, where the third threshold is less than the fourth threshold; when the amount of data stored in the memory is greater than or equal to the fourth threshold, the DEB time period in the adjusted read timing is decreased by a fourth time period compared with the DEB time period in the unadjusted read timing.
[0097] In a possible implementation, when the number of rows of the image data stored in the memory is less than the fifth threshold, the DEB time period in the adjusted read timing is increased by a fifth time period compared to the DEB time period in the read timing before adjustment; when the number of rows of the image data stored in the memory is greater than or equal to the fifth threshold and less than the sixth threshold, the DEB time period in the adjusted read timing remains unchanged compared to the DEB time period in the read timing before adjustment, and the fifth threshold is less than the sixth threshold; when the number of rows of the image data stored in the memory is greater than or equal to the sixth threshold and less than or equal to g, the DEB time period in the adjusted read timing is decreased by a sixth time period compared to the DEB time period in the read timing before adjustment.
[0098] Exemplarily, this method can be applied to the above display driving circuit. For other implementations and beneficial effects of this method, reference can be made to the relevant descriptions of the above display driving circuit, which will not be elaborated here.
[0099] An embodiment of the present application also provides a chip, which includes the above display driving circuit. Exemplarily, the chip can be a DDI.
[0100] An embodiment of the present application also provides a computer device, which includes the above display driving circuit. Exemplarily, the computer device includes the above chip, and the chip includes the above display driving circuit.
[0101] The terms "first", "second", "third", "fourth", etc. in the description, claims and drawings of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.
[0102] The above are only optional embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principle of the present application shall be included in the protection scope of the present application.
Claims
1. A display driving circuit, characterized in that, The display driving circuit is configured to: Adjust the reading timing of the image data according to the memory state of the memory. The image data includes pixel data of N rows, and the capacity of the memory is used to store pixel data of g rows. Here, g is a positive integer greater than 1. The memory state indicates the amount of data stored in the memory, and the reading timing indicates the reading time of the pixel data of each row. Read the pixel data in the memory based on the reading timing, and the read pixel data is used to drive the display panel to display an image.
2. The circuit according to claim 1, wherein, The reading timing includes a data enable blank (DEB) time period for each row. The length of the DEB time period of the (i - g + 1)-th row is negatively correlated with the amount of data in the memory after writing the pixel data of the i-th row. The reading time of the pixel data of the (i - g + 2)-th row is after the end time of the DEB time period of the (i - g + 1)-th row, where i is a positive integer greater than or equal to g and less than or equal to N.
3. The circuit according to claim 2, wherein The display driving circuit includes a writing control module, a memory state module, a DEB control module, and a reading control module. The writing control module is configured to: write the pixel data of the i-th row into the memory. The memory state module is configured to: determine the memory state of the memory. The DEB control module is configured to: adjust the DEB time period of the (i - g + 1)-th row according to the memory state. The reading control module is configured to: read the pixel data of the (i - g + 2)-th row in the memory after reaching the end time of the DEB time period of the (i - g + 1)-th row.
4. The circuit according to any one of claims 1-3, characterized in that, When the amount of data stored in the memory is less than the first threshold, the DEB time period in the adjusted reading timing increases by a first time period compared to the DEB time period in the unadjusted reading timing. When the amount of data stored in the memory is greater than or equal to the first threshold and less than the second threshold, the DEB time period in the adjusted reading timing increases by a second time period compared to the DEB time period in the unadjusted reading timing. Here, the first threshold is less than the second threshold. When the amount of data stored in the memory is greater than or equal to the second threshold and less than the third threshold, the DEB time period in the adjusted reading timing remains unchanged compared to the DEB time period in the unadjusted reading timing. Here, the second threshold is less than the third threshold. When the amount of data stored in the memory is greater than or equal to the third threshold and less than the fourth threshold, the DEB time period in the adjusted reading timing decreases by a third time period compared to the DEB time period in the unadjusted reading timing. Here, the third threshold is less than the fourth threshold. When the amount of data stored in the memory is greater than or equal to the fourth threshold, the DEB time period in the adjusted reading timing decreases by a fourth time period compared to the DEB time period in the unadjusted reading timing.
5. The circuit according to any one of claims 1-3, characterized in that When the number of rows of the image data stored in the memory is less than the fifth threshold, the DEB time period in the adjusted reading timing increases by a fifth time period compared to the DEB time period in the unadjusted reading timing. When the number of rows of the image data stored in the memory is greater than or equal to the fifth threshold and less than the sixth threshold, the DEB period in the adjusted read timing remains unchanged compared to the DEB period in the read timing before adjustment, where the fifth threshold is less than the sixth threshold; When the number of rows of the image data stored in the memory is greater than or equal to the sixth threshold and less than or equal to g, the DEB period in the adjusted read timing is reduced by a sixth period compared to the DEB period in the read timing before adjustment.
6. A display driving method, characterized in that, The method includes: Adjusting the read timing of the image data according to the memory state of the memory, where the image data includes pixel data of N rows, the capacity of the memory is used to store pixel data of g rows, g is a positive integer greater than 1, the memory state indicates the amount of data stored in the memory, and the read timing indicates the read time of the pixel data of each row; Reading the pixel data in the memory based on the read timing, and the read pixel data is used to drive a display panel to display an image.
7. The method according to claim 6, wherein The read timing includes a data enable blank (DEB) period for each row, and the length of the DEB period of the (i - g + 1)-th row is negatively correlated with the amount of data in the memory after writing the pixel data of the i-th row. The read time of the pixel data of the (i - g + 2)-th row is after the end time of the DEB period of the (i - g + 1)-th row, where i is a positive integer greater than or equal to g and less than or equal to N.
8. The method according to claim 7, characterized in that, The adjusting the read timing of the image data according to the memory state of the memory includes: Writing the pixel data of the i-th row into the memory and determining the memory state of the memory; Adjusting the DEB period of the (i - g + 1)-th row according to the memory state; The reading the pixel data in the memory based on the read timing includes: After reaching the end time of the DEB period of the (i - g + 1)-th row, reading the pixel data of the (i - g + 2)-th row in the memory.
9. The method according to any one of claims 6-8, characterized in that, When the amount of data stored in the memory is less than the first threshold, the DEB period in the adjusted read timing is increased by a first period compared to the DEB period in the read timing before adjustment; When the amount of data stored in the memory is greater than or equal to the first threshold and less than the second threshold, the DEB period in the adjusted read timing is increased by a second period compared to the DEB period in the read timing before adjustment, where the first threshold is less than the second threshold; When the amount of data stored in the memory is greater than or equal to the second threshold and less than the third threshold, the DEB period in the adjusted read timing remains unchanged compared to the DEB period in the read timing before adjustment, where the second threshold is less than the third threshold; When the amount of data stored in the memory is greater than or equal to the third threshold and less than the fourth threshold, the DEB period in the adjusted read timing is reduced by a third period compared to the DEB period in the read timing before adjustment, where the third threshold is less than the fourth threshold; When the amount of data stored in the memory is greater than or equal to the fourth threshold, the DEB time period in the adjusted read timing is reduced by a fourth time period compared to the DEB time period in the read timing before adjustment.
10. The method according to any one of claims 6-8, characterized in that When the number of rows of the image data stored in the memory is less than the fifth threshold, the DEB time period in the adjusted read timing is increased by a fifth time period compared to the DEB time period in the read timing before adjustment; When the number of rows of the image data stored in the memory is greater than or equal to the fifth threshold and less than the sixth threshold, the DEB time period in the adjusted read timing remains unchanged compared to the DEB time period in the read timing before adjustment, and the fifth threshold is less than the sixth threshold; When the number of rows of the image data stored in the memory is greater than or equal to the sixth threshold and less than or equal to g, the DEB time period in the adjusted read timing is reduced by a sixth time period compared to the DEB time period in the read timing before adjustment.
11. A display driving chip, characterized in that, The chip includes the display driving circuit according to any one of claims 1-5.
12. A computer device, characterized in that, The computer device includes the display driving circuit according to any one of claims 1-5.