Driving architecture of display panel
In the driving architecture of the display panel, the controller sets the level of the data timing signal according to whether the driver needs to update the data and sends a enable signal, which solves the time-consuming problem in the prior art and achieves efficient data update and power saving.
Patent Information
- Application Number
- CN202510123920.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-25
- Filing Date
- 2025-01-26
- Publication Date
- 2025-07-25
AI Technical Summary
In a display panel with multiple drivers, the prior art requires reoperating the update data signal from the first driver, which consumes a lot of time and leads to inefficient data updates.
The controller sets the level of the data timing signal according to whether the driver needs to update data, and sends the enable signal to the driver that needs to be updated according to the timing of the data signal, simplifies signal timing control and reduces the data update operation time.
It greatly improves the data update efficiency of the display panel, reduces the time required for data updates, and saves power consumption.
Smart Images
Figure CN120375752A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a driving architecture, and more particularly to a driving architecture for a display panel. Background Art
[0002] In a display panel having a plurality of drivers, a controller of the display panel sends a plurality of clock signals to the drivers, so that the drivers operate according to the timing of the clock signals to drive the light-emitting elements.
[0003] The controller sends data signals in each cycle of the data clock signal. When the driver receives the enable signal, the driver receives the data signal according to the timing of the data clock signal. After the first driver receives the data signal, it sends another enable signal to notify the second driver to start receiving the data signal. In this way, the operation of receiving data by the drivers in the same row is completed in sequence. If it is necessary to restart transmitting the data signal, the controller first sends a low-level enable signal, so that the drivers in the same row all send low-level enable signals, and then the controller sends a high-level enable signal to the first driver, and then starts receiving the data signal from the first driver.
[0004] In the above display panel having a plurality of drivers, a large number of drivers are usually mounted in the display panel. When the data signal of one of the drivers needs to be updated, according to the above operation, it is necessary to start from the first driver and re-operate, which consumes a lot of time and reduces the efficiency of updating the data signal.
[0005] Based on the above, the present invention provides a driving architecture for a display panel, which can solve the above-mentioned time-consuming technical problem, increase the efficiency of updating the data signal of the display panel, and reduce the time required for updating the data. Summary of the Invention
[0006] An object of the present invention is to provide a driving architecture for a display panel, which includes a controller and at least one driver, and the controller sets the signal level of the data clock signal according to whether at least one driver needs to update data.
[0007] An object of the present invention is to provide a driving architecture for a display panel, and the controller sets the signal levels of the data clock signal and the data signal according to whether at least one driver needs to update data.
[0008] An object of the present invention is to provide a driving architecture for a display panel, and the driver sends an enable signal according to the change of the level of the data signal and transmits it to the driver that needs to update the data, greatly reducing the operation time of data update, and thus achieving the technical effect of saving power.
[0009] The present invention provides a driving architecture for a display panel, which includes a controller and at least one driver. The controller and at least one driver are disposed on the display panel. The controller generates a data signal and a data clock signal, and at least one driver receives the data signal and the data clock signal. The controller sets the signal level of the data clock signal according to whether at least one driver needs to update data. By using the driving architecture of the present invention to drive the display panel, the signal level of the data clock signal can be set according to whether the driver needs to update data, and an enable signal can be sent to the driver that needs to update data according to the timing of the data signal, greatly reducing the operation time of data update of the display panel, increasing the efficiency of data update, and thus achieving the technical effect of power saving. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 : It is a schematic diagram of the driving architecture of a display panel according to the present invention; Figure 2 : It is a partial schematic diagram of the driving architecture according to an embodiment of the present invention; Figure 3 : It is a schematic diagram of the timing of the clock signal according to an embodiment of the present invention; Figure 4 : It is a schematic diagram of the timing of the clock signal according to another embodiment of the present invention; Figure 5 : It is a schematic diagram of the timing of the clock signal according to another embodiment of the present invention.
Description of Drawing Number Correspondence
[0011] In order to have a further understanding and recognition of the structural features and achieved effects of the present invention, preferred embodiments and detailed descriptions are used as follows:
[0012] In the description and claims, certain terms are used to refer to specific elements. However, those of ordinary skill in the art to which the present invention pertains should understand that manufacturers may use different names to refer to the same element. Moreover, the description and claims of the present specification do not use the difference in names as a way to distinguish elements, but rather use the difference in the overall technology of the elements as the criterion for distinction. The term "comprising" mentioned throughout the description and claims is an open-ended term and should thus be interpreted as "comprising but not limited to". Furthermore, the term "coupled" herein includes any direct and indirect connection means. Therefore, if the text describes that a first device is coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other connection means.
[0013] Please refer to Figure 1 , which is a schematic diagram of the driving architecture of a display panel according to the present invention. The driving architecture of the present invention is used to drive a display panel 100 to display images. The display panel 100 includes a controller 110 and at least one driver 120. In this embodiment, the drivers are exemplified by a plurality of drivers 120. The controller 110 is disposed on the display panel 100 and is coupled to at least one driver 120. At least one driver 120 is disposed on the display panel 100, and a plurality of drivers 120 in the same row are connected in series with each other.
[0014] Please refer to Figure 2 and Figure 3 , which are a partial schematic diagram of the driving architecture according to an embodiment of the present invention and a timing signal timing schematic diagram according to an embodiment of the present invention. The controller 110 generates data signals D0 and D1, a data clock signal DCK, a display clock signal PWMCK, and an enable signal ENRD1. The controller 110 sends the data signals D0 and D1, the data clock signal DCK, and the display clock signal PWMCK to at least one driver 120. The controller 110 sends the enable signal ENRD1 to at least one driver 120 adjacent to the controller 110.
[0015] In this embodiment, data signals D0 and D1 are display data. The display data can be serial data and includes a plurality of pixel data for the display panel 100 to display an image. For the purpose of illustration, two data lines for transmitting the data signals D0 and D1 are used here. The data signals D0 and D1 are two data signals as an example. The number of data lines can be any number according to the panel size or application scenario, and the present invention is not limited thereto. For example, one data line can be used to transmit one data signal. The data clock signal DCK is a timing signal, and the driver 120 receives the data signals D0 and D1 according to the timing of the data clock signal DCK. The display clock signal PWMCK is a timing signal, and the driver 120 drives the light-emitting elements to turn on or off according to the timing of the display clock signal PWMCK. The enable signals ENRD1 and ENRD2 are timing signals. The driver 120 starts to receive the data signals D0 and D1, the data clock signal DCK, and the display clock signal PWMCK according to the corresponding enable signals. For example, when the first driver 120 receives the high level of the corresponding enable signal ENRD1, it means that it is selected and starts to receive the data signals D0 and D1, the data clock signal DCK, and the display clock signal PWMCK generated by the driver 120. After the driver 120 of the current stage receives the data signals D0 and D1, it will send another enable signal to the driver 120 of the next stage, so that the driver 120 of the next stage receives the corresponding enable signal and starts the receiving operation. For example, after the first driver 120 receives the data signals D0 and D1, it sends the enable signal ENRD2 to the second driver 120. After the second driver 120 receives the high level of the enable signal ENRD2, it starts to receive the data signals D0 and D1, the data clock signal DCK, and the display clock signal PWMCK. The driver 120 of the current stage and the driver 120 of the next stage are coupled in series with each other, as Figure 1 and Figure 2 shown.
[0016] Please refer to Figure 4 , which is a timing diagram of the clock signal of another embodiment of the present invention. Please also refer to Figure 2 and Figure 4 . In this embodiment, for the convenience of description, it is taken as an example that the (M + 1)-th driver 120 needs to update data. The controller 110 sets the signal level of the data clock signal DCK according to whether at least one driver 120 needs to update data. For example, the data clock signal DCK and the data signal D1 are set to a fixed level, and the data signal D0 is set to a timing signal. The driver 120 receives the data clock signal DCK and the data signal D1 with a fixed level, and the driver 120 sends an enable signal according to the timing of the data signal D0.
[0017] In this embodiment, when the first driver 120 starts receiving the data clock signal DCK and the data signals D0 and D1 after receiving the enable signal ENRD1 generated by the controller 110, and when the first driver 120 receives the data clock signal DCK and the data signal D1 that are fixed at a high level, the first driver 120 sends the enable signal ERND2 to the next driver 120, that is, the second driver 120, according to the timing of the data signal D0, and so on. For example, the first driver 120 transmits the enable signal ERND2 to the next driver 120 according to the level change of the data signal D0. The level change is, for example, from a low level to a high level or from a high level to a low level. When the Mth driver transmits the (M + 1)th enable signal ENRDM+1 to the (M + 1)th driver 120, that is, when the enable signal is transmitted to the driver 120 that needs to update data, the controller 110 sets the data clock signal DCK as the timing signal, and the data signals D0 and D1 are set to the data transmission state. The data signals D0 and D1 are pixel data, as Figure 4 shown by the dotted circle in Figure 4 . After receiving the (M + 1)th enable signal ENRDM+1 at a high level, the (M + 1)th driver starts receiving the data clock signal DCK and the data signals D0 and D1, and the (M + 1)th driver updates the data, completing the operation of updating the data of the (M + 1)th driver.
[0018] In an embodiment, the controller 110 sets the data clock signal DCK and the data signal D0 to a fixed level, and the data signal D1 is set as the timing signal. The driver 120 receives the data clock signal DCK and the data signal D0 at a fixed level, and the driver 120 sends the enable signal according to the timing of the data signal D1.
[0019] In an embodiment, the driver 120 sends the enable signal according to the number of level changes of the data signal. For example, the first driver 120 transmits the enable signal ERND2 to the second driver 120 according to the number of level changes of the data signal D0 or the number of level changes of the data signal D1. The number of level changes is, for example, 3 times from a low level to a high level or 3 times from a high level to a low level. The number of changes can be any number, and the present invention is not limited thereto.
[0020] In one embodiment, the driver 120 sends an enabling signal according to the level change of a data signal. For example, the first driver 120 sends an enabling signal ERND2 to the second driver 120 according to the level change of the data signal D0 or the data signal D1. In this embodiment, the controller 110 sets the data clock signal DCK to a fixed level and sets the data signal D0 or the data signal D1 as a timing signal. Taking the signal timing diagram of the fourth figure as an example, the data clock signal DCK is set to a fixed level, and the data signal D0 is set as a timing signal. After receiving the data clock signal DCK with a fixed level, the driver 120 sends an enabling signal according to the timing change of the data signal D0. Using the operation mode of this embodiment can simplify the signal timing control and update the data of the driver with a smaller number of signals.
[0021] Please refer to Figure 5 , which is a schematic diagram of the clock signal timing of another embodiment of the present invention. Please also refer to Figure 2 and Figure 5 , in this embodiment, for the convenience of description, it is taken as an example that the (M + 1)-th driver 120 needs to update data. The controller 110 sets the signal level of the data clock signal DCK according to whether at least one driver 120 needs to update data. For example, the data clock signal DCK is set to a fixed level, and the data signals D0 and D1 are set as timing signals. For example, the levels of the timing signals of the data signals D0 and D1 are set to be inverted. The driver 120 receives the data clock signal DCK with a fixed level, and the driver 120 sends an enabling signal according to the timing of the data signals D0 and D1. In this embodiment, the levels of the timing signals of the data signals D0 and D1 can be set to other levels according to the actual situation, such as being set to the same phase. The present invention is not limited thereto.
[0022] In this embodiment, when the first driver 120 receives the enabling signal ENRD1 generated by the controller 110, it starts to receive the data clock signal DCK and the data signals D0 and D1. When the first driver 120 receives the data clock signal DCK fixed at a high level, the first driver 120 sends an enabling signal ERND2 to the next driver 120, that is, the second driver 120, and so on. For example, the first driver 120 transmits the enabling signal ERND2 to the next driver 120 according to the level change of the data signals D0 and D1. When the M-th driver transmits the (M + 1)-th enabling signal ENRDM+1 to the (M + 1)-th driver 120, that is, when the enabling signal is transmitted to the driver 120 that needs to update data, the controller 110 sets the data clock signal DCK as a timing signal, and the data signals D0 and D1 are set to the data transmission state. The data signals D0 and D1 are pixel data, as Figure 4As shown by the dashed circle, after receiving the high-level (M + 1)th enable signal ENRDM+1, the (M + 1)th driver starts to receive the data clock signal DCK and the data signals D0 and D1, and the (M + 1)th driver updates the data, completing the operation of updating the data of the (M + 1)th driver.
[0023] The display panel 100 of the present invention may be a micro light-emitting diode (micro LED) panel, a mini light-emitting diode (mini LED) panel, or other light-emitting element display panels.
[0024] Through the driving architecture of the display panel in this case, when the driver therein needs to update data, the levels of the data clock signal and the data signal can be set so that other drivers that do not need to update data send enable signals according to the timing of the data signal until the driver that needs to update data performs the data update operation, which can greatly increase the overall data update efficiency of the display panel, reduce the time required for data update, and further reduce the power consumed by the display panel, achieving the technical effect of power saving.
[0025] The above is only the preferred embodiment of the present invention and is not used to limit the scope of implementation of the present invention. All equivalent changes and modifications made according to the shape, structure, features, and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.
Claims
1. A driving architecture for a display panel, characterized in that, It includes: a controller disposed on the display panel, generating a data signal and a data clock signal; and at least one driver disposed on the display panel, the at least one driver receiving the data signal and the data clock signal, wherein the controller sets the signal level of the data clock signal according to whether the at least one driver needs to update data.
2. The drive architecture according to claim 1, characterized in that, Wherein the at least one driver receives the data signal according to the timing of the data clock signal.
3. The drive architecture according to claim 1, characterized in that, Wherein the controller sets the signal levels of the data clock signal and the data signal according to whether the at least one driver needs to update data.
4. The drive architecture according to claim 1, wherein Wherein the at least one driver includes a first driver and a second driver, the controller generating a first enable signal to the first driver, and the first driver sending a second enable signal to the second driver according to the data clock signal and the data signal.
5. The drive architecture according to claim 4, characterized in that, Wherein the first driver starts to receive the data signal and the data clock signal according to the first enable signal, and the second driver starts to receive the data signal and the data clock signal according to the second enable signal.
6. The drive architecture according to claim 1, wherein Wherein the data signal includes a first data signal and a second data signal, the data clock signal and the second data signal are at fixed levels, and the at least one driver sends an enable signal according to the level change of the first data signal.
7. The drive architecture according to claim 6, characterized in that, Wherein when the at least one driver updates data and receives the enable signal, the first data signal and the second data signal change to the transmission data state.
8. The drive architecture according to claim 1, characterized in that, Wherein the data signal includes a first data signal and a second data signal, the data clock signal and the first data signal are at fixed levels, and the at least one driver sends an enable signal according to the level change of the second data signal.
9. The drive architecture according to claim 8, characterized in that, Wherein when the at least one driver updates data and receives the enable signal, the first data signal and the second data signal change to the transmission data state.
10. The drive architecture according to claim 1, wherein Wherein the data signal includes a first data signal and a second data signal, the data clock signal is at a fixed level, the levels of the first data signal and the second data signal can be in antiphase or in phase, and the at least one driver sends an enable signal according to the level changes of the first data signal and the second data signal.
11. The drive architecture according to claim 10, wherein, Wherein when the at least one driver updates data and receives the enable signal, the first data signal and the second data signal change to the transmission data state.