Asynchronous storage circuit and electronic device
By designing an asynchronous memory circuit, and optimizing bit line signal transformation using read/write circuits, write operation charge pre-charging circuits, and word signal gating circuits, the limitations of traditional SRAM cells in terms of high-speed, low-power storage requirements are overcome, achieving faster data transmission and lower power consumption, making it suitable for various memory interconnection scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2025-06-25
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional dual-port SRAM cells have significant inherent limitations in meeting the requirements of high-speed, low-power storage, making it difficult to meet the performance and power consumption requirements of modern storage systems.
An asynchronous memory circuit design is adopted, including read/write circuits, write operation charge pre-charging circuit, read operation charge pre-charging circuit, and word signal gating circuit. The bit line signal transformation is optimized by pre-charging, shortening the data write and read time. The word signal gating circuit controls the conduction and cutoff of the tail current to reduce power consumption.
It improves the operating speed of storage systems, reduces power consumption, meets the requirements of high-speed and low-power storage, and is suitable for storage interconnects such as chip-to-chip, chip-to-module, and die-to-die.
Smart Images
Figure CN120375884B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to an asynchronous memory circuit and electronic device. Background Technology
[0002] In the field of integrated circuit design, dual-port static random access memory (DRAM) plays a crucial role in high-performance computing, network communication, and multi-core processor caching, among other scenarios requiring high-bandwidth data access, due to its ability to allow two ports to perform independent and concurrent read and write operations.
[0003] Currently, traditional dual-port SRAM cells generally adopt a structure based on 8 transistors (8T). Although this structure enables independent access to both ports, it has significant inherent limitations in terms of performance and power consumption, making it difficult to meet the growing demand for high-speed, low-power storage.
[0004] There is an urgent need in this field for an innovative dual-port storage circuit design that can effectively overcome the inherent defects of the traditional 8T structure in terms of speed and power consumption, significantly improve read and write speed and reduce standby power consumption, so as to better meet the application requirements of modern high-speed, low-power storage systems. Summary of the Invention
[0005] This application provides an asynchronous storage circuit that can improve the operating speed of the storage system and reduce its power consumption.
[0006] The technical solution of this application embodiment is implemented as follows:
[0007] In a first aspect, embodiments of this application provide an asynchronous storage circuit, the asynchronous storage circuit comprising:
[0008] Read / write circuitry is used to perform data read or write operations.
[0009] A write operation charge pre-charging circuit is provided, wherein a first terminal of the write operation charge pre-charging circuit is connected to the main output terminal of the read / write circuit, and a second terminal of the write operation charge pre-charging circuit is connected to the inverting output terminal of the read / write circuit; the write operation charge pre-charging circuit is used to charge the first terminal or the second terminal when a write operation for the read / write circuit is initiated, such that the voltage of the first terminal or the second terminal after charging is a first voltage;
[0010] A read operation charge pre-charging circuit is provided, wherein the third terminal of the read operation charge pre-charging circuit is connected to the main output terminal of the read / write circuit, and the fourth terminal of the read operation charge pre-charging circuit is connected to the inverting output terminal of the read / write circuit; the read operation charge pre-charging circuit is used to charge the third terminal or the fourth terminal when a read operation is initiated for the read / write circuit, such that the voltage of the third terminal or the fourth terminal after charging is a second voltage;
[0011] A word signal gating circuit, wherein the tail current transistor of the word signal gating circuit is connected to the read / write circuit, and is used to control the tail current transistor to be turned on or off based on the word signal of the read operation and / or the word signal of the write operation, and the output signal of the NOR operation in the word signal gating circuit.
[0012] In some embodiments, the write operation charge pre-charge circuit includes at least: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; the source of the fourth transistor is the second terminal of the write operation charge pre-charge circuit, and the source of the fifth transistor is the first terminal of the write operation charge pre-charge circuit.
[0013] In some embodiments, if the data stored at the first terminal is "1" and a write data enable signal is triggered, the write operation precharge voltage and balance voltage are controlled to be low level so that the write operation charge precharge circuit charges the second terminal.
[0014] In some embodiments, the voltage corresponding to the gate of the third transistor is the write operation precharge voltage.
[0015] In some embodiments, the voltage at the connection between the first transistor and the fourth transistor is the read bit line voltage;
[0016] The voltage at the connection point between the second transistor and the fifth transistor is the write bit line voltage.
[0017] In some embodiments, the voltage at the junction of the fourth and fifth transistors is a balanced voltage.
[0018] In some embodiments, the write operation charge pre-charge circuit includes a first charge pre-charge sub-circuit and a first charge balancing circuit; wherein the first charge pre-charge sub-circuit includes: a first transistor, a second transistor and a third transistor; the gate of the first transistor is connected to the gate of the second transistor, and the gate of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, respectively.
[0019] In some embodiments, the first charge balancing circuit includes a fourth transistor and a fifth transistor, wherein the gate of the fourth transistor is connected to the gate of the fifth transistor.
[0020] In some embodiments, the fourth transistor and the fifth transistor act on the inverting output terminal and the output terminal of the read / write circuit, respectively, to achieve high switching between the inverting output terminal and the output terminal.
[0021] In some embodiments, the read operation charge pre-charge circuit includes at least: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the drain of the sixth transistor is connected to the fourth terminal of the read operation charge pre-charge circuit, and the drain of the seventh transistor is connected to the third terminal of the read operation charge pre-charge circuit.
[0022] In some embodiments, if the data stored at the third terminal is "1", the write bit line voltage is controlled to be low, the read bit line voltage is controlled to be high, and the write operation precharge voltage and balance voltage are controlled to be high, and the read operation precharge voltage is controlled to be low, so as to trigger the read operation enable signal.
[0023] In some embodiments, the voltage corresponding to the gate of the eighth transistor is the read operation precharge voltage.
[0024] In some embodiments, the read operation charge pre-charge circuit includes a second charge pre-charge sub-circuit and a pre-charge enable circuit; wherein the second charge pre-charge sub-circuit includes: the sixth transistor, the seventh transistor and the eighth transistor; the gate of the sixth transistor is connected to the gate of the seventh transistor, and the gate of the eighth transistor is connected to the gate of the sixth transistor and the gate of the seventh transistor, respectively.
[0025] In some embodiments, the precharge enable circuit includes: the ninth transistor and the tenth transistor; the gate of the ninth transistor is connected to the gate of the tenth transistor.
[0026] In some embodiments, the ninth transistor and the tenth transistor act on the read word line signal to accelerate the charging or discharging of the read word line signal.
[0027] In some embodiments, when either the word signal of the read operation or the word signal of the write operation is high, and the output signal of the NOR operation in the word signal gate circuit is low, a high-level output signal is output based on the NOT operation in the word signal gate circuit, so that the tail current transistor of the word signal gate circuit is turned on.
[0028] In some embodiments, both the word signal of the read operation and the word signal of the write operation are at a low level. A low-level output signal is output based on the NOR-NOT operation in the word signal gating circuit, so as to turn off the tail current transistor of the word signal gating circuit.
[0029] In some embodiments, the word signal gating circuit includes at least: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein,
[0030] The drain of the eleventh transistor is connected to the source of the twelfth transistor, and the gate of the eleventh transistor is connected to the gate of the thirteenth transistor.
[0031] The drain of the twelfth transistor is connected to the drain of the fourteenth transistor and the drain of the thirteenth transistor;
[0032] The gate of the twelfth transistor is connected to the gate of the fourteenth transistor;
[0033] The source of the thirteenth transistor and the source of the fourteenth transistor are grounded.
[0034] In some embodiments, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all NMOS transistors.
[0035] Secondly, embodiments of this application provide an electronic device, which includes the aforementioned asynchronous storage circuit.
[0036] The asynchronous storage circuit provided in this application includes: a read / write circuit for performing data read or write operations; a write operation charge pre-charge circuit, the first terminal of which is connected to the main output terminal of the read / write circuit, and the second terminal of which is connected to the inverting output terminal of the read / write circuit; a write operation charge pre-charge circuit for charging the first or second terminal when a write operation is initiated; a read operation charge pre-charge circuit, the third terminal of which is connected to the main output terminal of the read / write circuit, and the fourth terminal of which is connected to the inverting output terminal of the read / write circuit; a read operation charge pre-charge circuit for charging the third or fourth terminal when a read operation is initiated; and a tail current transistor of a word signal gating circuit connected to the read / write circuit for controlling the tail current transistor to be turned on or off based on the word signal of the read operation and / or the word signal of the write operation, and the output signal of the NOR operation in the word signal gating circuit. This application's embodiments utilize charge pre-charging technology to design corresponding write operation charge pre-charging circuits and read operation charge charging circuits based on the write and read operation processes. By pre-charging, the slow bit line signal transitions in traditional storage circuit structures are addressed, shortening data writing and reading times to meet the high-speed requirements of storage scenarios. Simultaneously, the word signal gating circuit controls the conduction and cutoff of the tail current of the storage circuit according to its state, reducing circuit power consumption. This improves storage performance in terms of data read / write speed and power consumption, meeting the low-power storage requirements of high-computational-scale applications. It is fully applicable to various storage interconnect fields such as chip-to-chip (C2C), chip-to-module (C2M), and die-to-die (D2D). Attached Figure Description
[0037] Figure 1 This is a schematic diagram of one possible structure of the asynchronous storage circuit provided in an embodiment of this application;
[0038] Figure 2 This is a schematic diagram of the composition structure of the read / write circuit provided in the embodiments of this application;
[0039] Figure 3 This is a schematic diagram of the composition structure of the write operation charge pre-charge circuit provided in an embodiment of this application;
[0040] Figure 4 This is a schematic diagram of the composition structure of the read operation charge pre-charge circuit provided in an embodiment of this application;
[0041] Figure 5 This is a schematic diagram of the composition structure of the word signal gating circuit provided in the embodiments of this application. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0043] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0044] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.
[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0046] It should be understood that in the various embodiments of this application, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0047] A schematic diagram of the composition structure of an asynchronous memory circuit provided in this application embodiment is shown below. Figure 1 As shown, it includes at least:
[0048] The read / write circuit 10 is used to perform data read or write operations;
[0049] A write operation charge pre-charge circuit 20 is provided. The first terminal of the write operation charge pre-charge circuit 20 is connected to the main output terminal of the read / write circuit 10, and the second terminal of the write operation charge pre-charge circuit 20 is connected to the inverting output terminal of the read / write circuit 10. The write operation charge pre-charge circuit 20 is used to charge either the first terminal or the second terminal when a write operation is initiated for the read / write circuit 10, such that the voltage of the first terminal or the second terminal after charging is a first voltage. The first voltage can be flexibly set according to the actual application scenario. In some embodiments, the first terminal is a Q terminal, and the second terminal is a QB terminal.
[0050] A read operation charge pre-charge circuit 30 is provided. The third terminal of the read operation charge pre-charge circuit 30 is connected to the main output terminal of the read / write circuit 10, and the fourth terminal is connected to the inverting output terminal of the read / write circuit 10. The read operation charge pre-charge circuit 30 is used to charge either the third or fourth terminal when a read operation is initiated for the read / write circuit 10, such that the voltage of the charged third or fourth terminal is a second voltage. The second voltage can be flexibly set according to the actual application scenario. In some embodiments, the third terminal is a Q terminal, and the fourth terminal is a QB terminal.
[0051] A word signal gating circuit 40, wherein the tail current transistor of the word signal gating circuit 40 is connected to the read / write circuit, is used to control the tail current transistor to be turned on or off based on the word signal of the read operation and / or the word signal of the write operation, and the output signal of the NOR operation in the word signal gating circuit.
[0052] In some embodiments, the schematic diagram of the composition structure of the read / write circuit 10 is as follows: Figure 2 As shown, the latch includes: a core latch composed of two PMOS transistors (P1, P2) and two NMOS transistors (N3, N4) cross-coupled; a first inverter composed of P1 and N3 connected in series, with its input terminal being QB and its output terminal being Q; and a second inverter composed of P2 and N4 connected in series, with its input terminal being Q and its output terminal being QB. The cross-connection of the first and second inverters creates a bistable state: when the value at Q is 1, the value at QB is 0, and vice versa, thus achieving continuous data storage.
[0053] The read / write circuit 10 consists of four NMOS transistors (N1, N2, N5, N6), two word lines (wlw, whr), and four column lines (blw_n, bhr_n, bhr_p, blw_p). Word line wlw controls N1 and N6; word line whr controls N2 and N5 (high level for on, low level for off). Bit lines blw_n and blw_p are complementary bit lines on one side, and bhr_n and bhr_p are complementary bit lines on the other side (n can correspond to a low level, p to a high level, used to transmit read / write signals).
[0054] In the read / write circuit 10, the drain of N1 is connected to the QB terminal, the source of N1 is connected to blw_n, and the gate of N1 is connected to wlw. The drain of N2 is connected to the QB terminal, the source of N2 is connected to blr_n, and the gate of N2 is connected to wlr. The drain of N5 is connected to the Q terminal, the source of N5 is connected to blr_p, and the gate of N5 is connected to wlr; the drain of N6 is connected to the Q terminal, the source of N6 is connected to blw_p, and the gate of N6 is connected to wlw.
[0055] The write operation process based on the read / write circuit 10 is as follows: write operation (modify stored data), taking writing Q=1 and QB=0 as an example.
[0056] 1) Configure bit lines: Set blw_p to high (VDD) and blw_n to low (GND). blr_n and blr_p can be pre-charged or left idle; assume wlw is activated for writing.
[0057] 2) Activate word line: Set wlw to high level to turn on N1 (connected to blw_n) and N6 (connected to blw_p).
[0058] 3) Forced flip latch:
[0059] N6 is on: Q terminal is connected to blw_p (high level), forcing Q terminal to become 1;
[0060] N1 is on: QB terminal is connected to blw_n (low level), forcing QB terminal to become 0.
[0061] 4) Latching the new state: The cross-coupled inverters spontaneously maintain the new state (P1 is turned on and Q is pulled high, N4 is turned on and QB is pulled low, forming a stable cycle).
[0062] 5) Turn off word line: When wlw is set low, the access transistor is cut off, and the latch holds the new data.
[0063] The read operation process based on the read / write circuit 10 is as follows: read operation (reading stored data), taking writing Q=1 and QB=0 as an example.
[0064] 1) Precharge bit lines: Precharge blw_n, blw_p, blr_n, and blr_p to the intermediate voltage (e.g., VDD / 2) to eliminate interference.
[0065] 2) Activate word lines: set wlw high, turn on N1 and N6, and connect Q and QB to blw_p and blw_n respectively.
[0066] 3) Voltage variation on bit lines:
[0067] Q=1 is pulled high by N6 to blw_p;
[0068] QB=0 is pulled low by N1 to blw_n;
[0069] 4) A voltage difference appears on the bit line (blw_p high, blw_n low).
[0070] 5) Sensitive amplifier detection: The external circuit determines the stored data as 1 by detecting the difference in bit line voltage (if Q=0, then blw_p is pulled low and blw_n is pulled high, which is judged as 0).
[0071] 6) Turn off word lines: set wlw low, the bit lines return to precharge state, and wait for the next operation.
[0072] In some embodiments, the core function of the write operation charge precharge circuit 20 is to charge the bit line to a stable high level (typically the power supply voltage VDD) before the write operation, providing a reference potential for data writing. A schematic diagram of the write operation charge precharge circuit 20 is shown below. Figure 3 As shown, it includes: a first charge precharge sub-circuit composed of a first transistor 301, a second transistor 302, and a third transistor 303, wherein the source of the first transistor 301 is grounded, the drain of the first transistor 301 is connected to the source of the fourth transistor 304 and the drain of the third transistor 303, and the gate of the first transistor 301 is connected to the gate of the third transistor 303. The gate of the second transistor 302 is connected to the gate of the third transistor 303, and the voltage corresponding to the gate of the third transistor 303 is the precharge voltage for the write operation; the drain of the second transistor 302 is connected to the source of the fifth transistor 305 and the source of the third transistor 303, and the gate of the fourth transistor 304 is connected to the gate of the fifth transistor 305; the drain of the fourth transistor 304 is connected to the QB terminal (second terminal) of the read / write circuit 10, and the source of the fourth transistor 304 is connected to the low bit line (blw_n) of the write operation. The drain of the fifth transistor 305 is connected to the Q terminal (first terminal) of the read / write circuit 10, and the source of the fifth transistor 305 is connected to the high bit line (blw_p) of the write operation.
[0073] During the pre-charge phase, the first transistor 301 is turned on, pulling the gate of the third transistor 303 low to GND. The third transistor 303 is then turned off, and blw_p remains high (requires an external power supply, such as pre-charge via other circuitry). During the non-pre-charge phase, the first transistor 301 is turned off, the gate of the third transistor 303 is pulled high via a recessive pull-up, and the third transistor 303 is turned on, pulling blw_p low to GND.
[0074] The write operation charge pre-charge circuit 20 also includes a first charge balancing circuit composed of a fourth transistor 304 and a fifth transistor 305. The source of the fourth transistor 304 is connected to the QB terminal (second terminal) of the read / write circuit 10, the drain of the fourth transistor 304 is connected to the low-order write line (blw_n), and the gate of the fourth transistor 304 is connected to the word line write signal (wlw). The drain of the fifth transistor 305 is connected to the high-order write line (blw_p), the source of the fifth transistor 305 is connected to the Q terminal (first terminal) of the read / write circuit 10, and the gate of the fifth transistor 305 is connected to the word line write signal (wlw).
[0075] The specific operation process of the write operation charge pre-charge circuit 20 is as follows: In the pre-charge stage (preparing to write), the first transistor 301 is turned on (gate is low level), pulling the gate of the third transistor 303 low to GND, and the third transistor 303 is turned on. blw_p remains high or low. wlw=0 (not activated), the fourth transistor 304 and the fifth transistor 305 are turned off, and blw_n and blw_p are isolated from the read / write circuit 10. Write stage (PCG=1, wlw=1). Pre-charge control: PCG=1, the first transistor 301 is turned off, the third transistor 303 is turned off, blw_p continues to be charged to VDD, or blw_p is pulled down to GND.
[0076] Word line activation: When wlw=1, transistors 304 and 305 are turned on.
[0077] In the scenario of writing 0: blw_p=GND (directly grounded via the fifth transistor 305), the data is transmitted to the Q terminal of the read / write circuit 10 through the fifth transistor 305, forcing Q=0; blw_n=GND (directly grounded via the fourth transistor 304), the data is transmitted to the QB terminal, forcing QB=1.
[0078] In the scenario of writing 1: blw_p is externally set high in advance, the third transistor 303 is always cut off, blw_p=VDD is written to the Q terminal through the fifth transistor 305, forcing Q=1; when blw_n is set high, QB is forced to be 1.
[0079] In this embodiment, the first terminal of the write operation charge pre-charge circuit 20 is the Q terminal, and the second terminal is the QB terminal. If the data stored in the Q terminal is "1", the write data enable signal (also called the word line write signal wlw) is pulled high, and the write operation pre-charge voltage Vpre_w and the balance voltage Vop are low, thus starting the pre-charge process of the QB terminal. The Q terminal signal passes through... Figure 1 Discharge occurs via the P1-N6 path, and the QB terminal discharges based on the pre-charge voltage value. Figure 1 The N1-N4 path in the transistor accelerates the charging process of the QB terminal and the discharging process of the Q terminal. Finally, after the transistor N4 is turned off, the Q terminal signal becomes a "0" signal and the QB terminal signal becomes a "1" signal.
[0080] In some embodiments, the core function of the read operation charge precharge circuit 30 is to precharge the read operation bit lines (such as blr_p, blr_n) to a stable intermediate level (approximately the difference between the power supply voltage VDD and the NMOS threshold voltage Vth, i.e., VDD-Vth) before reading data. This provides a reference for voltage difference detection during data reading, ensuring that the sensitive amplifier can accurately identify the logic state of the memory cell. A schematic diagram of the read operation charge precharge circuit 30 is shown below. Figure 4As shown, the transistors include: a sixth transistor 401, a seventh transistor 402, an eighth transistor 403, a ninth transistor 404, and a tenth transistor 405. The source of the sixth transistor 401 is connected to ground (GND), its drain is connected to the high-order read operation line (blr_p), and its gate is connected to the precharge control signal (PCG). The source of the seventh transistor 402 is connected to ground (GND), its drain is connected to the low-order read operation line (blr_n), and its gate is connected to the gate of the eighth transistor 403. The gate of the eighth transistor 403 is also connected to the gate of the sixth transistor 401. The sixth transistor 401 and the seventh transistor 402 are controlled by the PCG; when turned on, they connect their bit lines to GND and participate in the voltage division process. The eighth transistor 403, the ninth transistor 404, and the tenth transistor 405 can also be referred to as load transistors. The source of the eighth transistor 403 is connected to the drain of the seventh transistor 402, and the source of the eighth transistor 403 is connected to the high-order read line (blr_p), while the drain of the eighth transistor 403 is connected to the low-order read line (blr_n). The source of the ninth transistor 404 is connected to GND, the drain of the ninth transistor 404 is connected to blr_n, and the gate of the ninth transistor 404 is connected to the word line whr. The source of the tenth transistor 405 is connected to ground (GND), the drain of the tenth transistor 405 is connected to the source of the eighth transistor 403, and the gate of the tenth transistor 405 is connected to the word line (wlr).
[0081] The specific operation process of the read operation charge pre-charge circuit 30 is as follows: During the pre-charge stage (initializing the bit line), the pre-charge control signal PCG=1 (high level), and the sixth transistor 401, the seventh transistor 402, and the tenth transistor 405 are turned on (the gate of the tenth transistor 405 is connected to PCG). The path through the sixth transistor 401 is: VDD current passes through the eighth transistor 403 to blr_p, and then through the sixth transistor 401 to GND. The path through the ninth transistor 404 is: VDD current passes through the ninth transistor 404 to blr_n, and then through the seventh transistor 402 to GND. The path through the tenth transistor 405 is: VDD current passes through the eighth transistor 403 and the tenth transistor 405 to GND. The on-resistance (equivalent to load resistance) of the eighth transistor 403 and the ninth transistor 404, along with the on-resistance of the sixth transistor 401, the seventh transistor 402, and the tenth transistor 405, divide the voltage, stabilizing blr_p and blr_n at an intermediate level. This intermediate level is approximately the difference between the power supply voltage VDD and the NMOS threshold voltage Vth, i.e., VDD-Vth. This voltage difference is amplified by subsequent circuitry to obtain the amplified voltage, which is then read from the stored value at the Q terminal.
[0082] The specific operation process of the read operation charge pre-charge circuit 30 is as follows: After the pre-charge is completed, the sixth transistor 401, the seventh transistor 402, and the tenth transistor 405 are turned off, and the bit line is disconnected from GND; the word line (wlr) is set high. If the stored data Q=1 and QB=0: Q=1 is connected to blr_p, and due to the large load resistance of the eighth transistor 403 (weak pull-up), blr_p is pulled high to VDD; QB=0 is connected to blr_n, and blr_n is pulled low to GND. If the stored data Q=0 and QB=1: blr_p is pulled low to GND, and blr_n is pulled high to VDD.
[0083] In this embodiment, during the pre-charge stage, the tenth transistor 405 is turned on and connected in parallel to the path of the sixth transistor 401, increasing the pull-down current of blr_p and accelerating the establishment of the intermediate level.
[0084] In this embodiment of the application, during the read and write operations, the word signal gating circuit is always in the on state and is controlled by the write word line signal and the read word line signal.
[0085] In some embodiments, both the word signal of the read operation (also referred to as the read operation word signal) and the word signal of the write operation (also referred to as the write operation word signal) are at a low level. Based on the NOR-NOT operation in the word signal gate circuit, a low-level output signal is output to turn off the tail current transistor M14 of the word signal gate circuit.
[0086] In some embodiments, when either the word signal of the read operation or the word signal of the write operation is high, and the output signal of the NOR operation in the word signal gating circuit is low, a high-level output signal is generated based on the NOT operation output in the word signal gating circuit, thereby turning on the tail current transistor of the word signal gating circuit. The word signal gating circuit uses word line signals to control the power consumption of the memory system to avoid additional power consumption in non-operational or non-write operation states, thereby reducing the power consumption of the memory system.
[0087] Based on this, the signal relationship of the word signal gating circuit provided in the embodiments of this application can be shown in Table 1 below.
[0088] Table 1. Signal Relationships of Word Signal Gating Circuits
[0089]
[0090] In this embodiment, the word signal gate circuit 40 is used to select the word lines of the read / write circuit. A schematic diagram of the structure of the word signal gate circuit 40 is shown below. Figure 5As shown, the circuit includes: an eleventh transistor 501, a twelfth transistor 502, a thirteenth transistor 503, a fourteenth transistor 504, and a fifteenth transistor 505. The source of the eleventh transistor 501 is connected to ground (VDD), and its drain is connected to the source of the twelfth transistor 502. The gate of the eleventh transistor 501 is connected to the gate of the thirteenth transistor 503. The source of the twelfth transistor 502 is connected to the drain of the eleventh transistor 501, and its drain is connected to the drains of the fourteenth transistor 504 and the thirteenth transistor 503. The gate of the twelfth transistor 502 is connected to the word signal (wlr) of the read operation and to the gate of the fourteenth transistor 504. The sources of the thirteenth transistor 503 and the fourteenth transistor 504 are grounded (GND). When both the word signal of the read operation and the word line signal of the write operation are high, the eleventh transistor 501 and the twelfth transistor 502 are turned off, transmitting the ground signal to subsequent circuitry. The source of the fourteenth transistor 504 is connected to ground, its drain is connected to the drain of the twelfth transistor 502, and its gate is connected to the gate of the twelfth transistor 502. When the thirteenth transistor 503 and the fourteenth transistor 504 are turned on, the word signal for the front-end read operation or the word signal for the write operation is transmitted to the fifteenth transistor 505. The gate of the fifteenth transistor 505 is connected to the output of the inverter, and its source is connected to the power supply VDD, ensuring that the fifteenth transistor 505 is always turned on as a pull-down path. Its on-state is determined by its source potential.
[0091] The word signal gating circuit 40 operates as follows: When both the read and write word signals are high, the eleventh transistor 501 and the twelfth transistor 502 are turned off; when either the read or write word signal is high, either the eleventh transistor 501 or the twelfth transistor 502 is turned off. The current path is as follows: the read or write word signal turns on the thirteenth transistor 503 or the fourteenth transistor 504, turning off the eleventh transistor 501 or the twelfth transistor 502. The first output is low, which, through the inverter, drives the fifteenth transistor 505 to turn on, and VDD outputs current through the drain of the fifteenth transistor 505. If both the read and write word signals are low, the eleventh transistor 501 and the twelfth transistor 502 are turned off.
[0092] The source voltage of the fifteenth transistor 505 is pulled low to GND, the gate voltage of the fifteenth transistor 505 is equal to VDD (on), the drain of the fifteenth transistor 505 is pulled low to GND, the word line is activated, and the read and write operation for the read and write circuit 10 is triggered.
[0093] It should be noted that in the above embodiments of this application, the asynchronous storage circuit provided in the embodiments of this application is described with the data stored at the Q terminal as "1". In specific implementation, the asynchronous storage circuit provided in the embodiments of this application can also be described with the data stored at the QB terminal as "1", which will not be repeated here.
[0094] In this embodiment, corresponding write operation charge pre-charging circuits and read operation charge charging circuits are designed using charge pre-charging technology according to the write and read operation processes. This pre-charging method solves the problem of slow bit line signal transformation in traditional storage circuit structures, shortening the data writing and reading time to meet the high-speed requirements of storage scenarios. Simultaneously, the word signal gating circuit controls the conduction and cutoff of the tail current of the storage circuit according to the state of the storage circuit, reducing circuit power consumption. This improves storage performance in terms of data read / write speed and power consumption, meeting the low-power storage requirements of high-computational-scale applications. It is fully applicable to various storage interconnect fields such as chip-to-chip (C2C), chip-to-module (C2M), and die-to-die (D2D).
[0095] This application also provides an electronic device, which includes the above-described components. Figures 1 to 5 The asynchronous storage circuit shown.
[0096] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.
Claims
1. An asynchronous storage circuit, characterized in that, The asynchronous storage circuit includes: Read / write circuitry is used to perform data read or write operations. A write operation charge pre-charging circuit includes at least: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; the drain of the fourth transistor is the second terminal of the write operation charge pre-charging circuit and is connected to the inverting output terminal of the read / write circuit; the drain of the fifth transistor is the first terminal of the write operation charge pre-charging circuit and is connected to the output terminal of the read / write circuit; if the data stored at the first terminal is "1" and a write data enable signal is triggered, the write operation pre-charging voltage and the balance voltage are controlled to be low level, so that the write operation charge pre-charging circuit charges the second terminal; the write operation charge pre-charging circuit is used to enable write operations for the read / write circuit. During operation, the first terminal or the second terminal is charged, such that the voltage of the first terminal or the second terminal after charging is a first voltage; the write operation charge pre-charge circuit includes a first charge pre-charge sub-circuit and a first charge balancing circuit; wherein, the first charge pre-charge sub-circuit includes: a first transistor, a second transistor and a third transistor; the gate of the first transistor is connected to the gate of the second transistor, and the gate of the third transistor is connected to the gate of the first transistor and the gate of the second transistor respectively; the first charge balancing circuit includes a fourth transistor and a fifth transistor, and the gate of the fourth transistor is connected to the gate of the fifth transistor; The read operation charge pre-charge circuit includes at least a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the drain of the sixth transistor is connected to the fourth terminal of the read operation charge pre-charge circuit, and the drain of the seventh transistor is connected to the third terminal of the read operation charge pre-charge circuit; if the data stored at the third terminal is "1", the write bit line voltage is controlled to be low, the read bit line voltage is controlled to be high, and the write operation pre-charge voltage and balance voltage are controlled to be high, and the read operation pre-charge voltage is controlled to be low, so as to trigger the read operation enable signal; the read operation charge pre-charge circuit is used to charge the third terminal or the fourth terminal when the read operation for the read-write circuit is started, so that the voltage of the third terminal or the fourth terminal after charging is a second voltage; A word signal gating circuit, wherein the tail current transistor of the word signal gating circuit is connected to the read / write circuit, and is used to control the tail current transistor to be turned on or off based on the word signal of the read operation and / or the word signal of the write operation, and the output signal of the NOR operation in the word signal gating circuit; The write operation charge pre-charging circuit works in conjunction with the word signal gating circuit. During the write operation, the voltage flipping of the second terminal is accelerated by pre-charging, and the tail current tube is turned off during non-operation periods by the word signal gating circuit to reduce static power consumption.
2. The asynchronous storage circuit according to claim 1, characterized in that, The voltage corresponding to the gate of the third transistor is the write operation precharge voltage.
3. The asynchronous storage circuit according to claim 1, characterized in that, The voltage at the connection between the first transistor and the fourth transistor is the read line voltage; The voltage at the connection point between the second transistor and the fifth transistor is the write bit line voltage.
4. The asynchronous storage circuit according to claim 1, characterized in that, The voltage at the connection between the fourth and fifth transistors is a balanced voltage.
5. The asynchronous storage circuit according to claim 1, characterized in that, The fourth transistor and the fifth transistor act on the inverting output terminal and the output terminal of the read / write circuit, respectively, to achieve high-frequency conversion between the inverting output terminal and the output terminal.
6. The asynchronous storage circuit according to claim 1, characterized in that, The voltage corresponding to the gate of the eighth transistor is the read operation precharge voltage.
7. The asynchronous storage circuit according to claim 1, characterized in that, The read operation charge pre-charge circuit includes a second charge pre-charge sub-circuit and a pre-charge enable circuit; wherein, the second charge pre-charge sub-circuit includes: the sixth transistor, the seventh transistor and the eighth transistor; the gate of the sixth transistor is connected to the gate of the seventh transistor, and the gate of the eighth transistor is connected to the gate of the sixth transistor and the gate of the seventh transistor respectively.
8. The asynchronous storage circuit according to claim 7, characterized in that, The precharge enable circuit includes: the ninth transistor and the tenth transistor; the gate of the ninth transistor is connected to the gate of the tenth transistor.
9. The asynchronous storage circuit according to claim 1, characterized in that, When either the word signal of the read operation or the word signal of the write operation is high, and the output signal of the OR operation in the word signal gate circuit is low, a high-level output signal is output based on the NOT operation in the word signal gate circuit, so that the tail current transistor of the word signal gate circuit is turned on.
10. The asynchronous storage circuit according to claim 1, characterized in that, Both the word signal of the read operation and the word signal of the write operation are at a low level. Based on the NOR-NOT operation in the word signal gate circuit, a low-level output signal is output to turn off the tail current transistor of the word signal gate circuit.
11. The asynchronous storage circuit according to claim 1, characterized in that, The word signal gating circuit includes at least: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein, The drain of the eleventh transistor is connected to the source of the twelfth transistor, and the gate of the eleventh transistor is connected to the gate of the thirteenth transistor. The drain of the twelfth transistor is connected to the drain of the fourteenth transistor and the drain of the thirteenth transistor; The gate of the twelfth transistor is connected to the gate of the fourteenth transistor; The source of the thirteenth transistor and the source of the fourteenth transistor are grounded.
12. The asynchronous storage circuit according to claim 1, characterized in that, The sixth, seventh, and eighth transistors are PMOS transistors, while the ninth and tenth transistors are both N-type metal-oxide-semiconductor (NMOS) transistors.
13. An electronic device, characterized in that, The electronic device includes: the asynchronous storage circuit according to any one of claims 1 to 12.