A control method and system for an ultra-small high-precision servo-driven turntable

Abstract

The present invention provides a control method and system for an ultra-small, high-precision servo-driven turntable, which relates to the technical field of servo-driven turntables. The method includes determining each segmented chip image and each segmented chip information based on an image of a wafer to be inspected; determining multiple first risk chips based on each segmented chip information; clustering using a clustering algorithm based on the multiple first risk chip information to obtain K clusters and a representative chip of each cluster; obtaining X-ray inspection information of the representative chip of each cluster; determining multiple risk clusters and multiple second risk chips in each risk cluster based on the multiple first risk chip information and the X-ray inspection information of the representative chip of each cluster; determining a final detection path based on the multiple second risk chip images in each risk cluster; and controlling the ultra-small, high-precision servo-driven turntable to perform electrical performance testing based on the final detection path. The method can quickly and accurately determine the optimal wafer detection path.

Description

Technical Field

[0001] The present invention relates to the technical field of servo-driven turntables, and in particular to a control method and system for an ultra-small high-precision servo-driven turntable. Background Art

[0002] With the continuous advancement of semiconductor manufacturing processes, the number of chips integrated on wafers is rapidly increasing, and the requirements for chip quality inspection are also increasing. Traditional wafer inspection methods mainly rely on manual quality inspection or automated inspection equipment with fixed paths. These methods suffer from low inspection efficiency, high missed detection rates, and poor adaptability. Especially in high-density integrated circuits, where chip sizes are shrinking and defect characteristics are becoming more subtle, traditional inspection methods are no longer able to meet the quality control requirements of modern semiconductor manufacturing. Existing technologies generally use a full inspection mode, which involves inspecting all chips on the wafer one by one. While this method can ensure high inspection coverage, it is time-consuming and resource-intensive. However, defects in semiconductor manufacturing often cluster in certain areas. Using random inspection methods can easily miss high-risk areas, leading to quality risks. Furthermore, existing automated inspection equipment often uses a preset fixed inspection path and cannot dynamically adjust to the actual defect distribution. When encountering new defect patterns, the defect detection accuracy of fixed-path inspection decreases significantly.

[0003] Therefore, how to quickly and accurately determine the optimal wafer inspection path is an urgent problem to be solved. Summary of the Invention

[0004] The main technical problem solved by the present invention is how to quickly and accurately determine the optimal wafer detection path.

[0005] According to a first aspect, the present invention provides a control method for an ultra-small high-precision servo-driven turntable, comprising: obtaining a picture of a wafer to be inspected; determining each split chip picture and each split chip information based on the picture of the wafer to be inspected; determining a plurality of first risk chips based on the information of each split chip; clustering based on the information of the plurality of first risk chips using a clustering algorithm to obtain K clusters and a representative chip of each cluster; controlling the ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; determining a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster; determining a final detection path based on the pictures of the plurality of second risk chips in each risk cluster; and controlling the ultra-small high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

[0006] In one possible implementation, the method of determining the final detection path based on multiple second risk chip images in each risk cluster includes: determining the necessary detection components, secondary detection components, and optional detection components in the second risk chip based on the multiple second risk chip images in each risk cluster and the information of each second risk chip; generating multiple alternative detection paths, detection information of each alternative detection path, and the difference of the detection information of each alternative detection path based on the position of each second risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chip; constructing a detection map, the detection map including multiple detection path nodes and multiple edges between the multiple detection path nodes, the node features of each detection path node including an alternative detection path and the detection information of each alternative detection path, and the edges between the detection path nodes are the difference of the detection information of each alternative detection path; processing the detection map based on a graph neural network to determine the final detection path.

[0007] In a possible implementation, the representative chip of each cluster is the chip closest to the centroid of each cluster.

[0008] In a possible implementation, the clustering algorithm is a K-means clustering algorithm.

[0009] According to a second aspect, the present invention provides a control system for an ultra-small, high-precision servo-driven turntable, comprising: an acquisition module for acquiring an image of a wafer to be inspected; an information segmentation module for determining an image of each segmented chip and information of each segmented chip based on the image of the wafer to be inspected; a first determination module for determining a plurality of first-risk chips based on information of each segmented chip; a clustering module for clustering based on information of a plurality of first-risk chips using a clustering algorithm to obtain K clusters and a representative chip of each cluster; a ray inspection module for controlling the ultra-small, high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; a second determination module for determining a plurality of risk clusters and a plurality of second-risk chips in each risk cluster based on information of the plurality of first-risk chips and X-ray inspection information of the representative chip of each cluster; a path planning module for determining a final detection path based on images of the plurality of second-risk chips in each risk cluster; and an electrical detection module for controlling the ultra-small, high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

[0010] In one possible implementation, the path planning module is also used to: determine the necessary detection components, secondary detection components, and optional detection components in the second risk chip based on multiple second risk chip images and each second risk chip information in each risk cluster; generate multiple alternative detection paths, detection information of each alternative detection path, and the difference of detection information of each alternative detection path based on the position of each second risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chip; construct a detection map, the detection map includes multiple detection path nodes and multiple edges between the multiple detection path nodes, the node features of each detection path node include an alternative detection path, the detection information of each alternative detection path, and the edges between the detection path nodes are the difference of the detection information of each alternative detection path; process the detection map based on a graph neural network to determine the final detection path.

[0011] In a possible implementation, the representative chip of each cluster is the chip closest to the centroid of each cluster.

[0012] In a possible implementation, the clustering algorithm is a K-means clustering algorithm.

[0013] According to a third aspect, an embodiment of the present invention provides an electronic device, comprising: a processor; a memory; and a computer program; wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method as described above, the method comprising: obtaining a picture of a wafer to be inspected; determining each split chip picture and each split chip information based on the picture of the wafer to be inspected; determining multiple first risk chips based on each split chip information; clustering based on the multiple first risk chip information using a clustering algorithm to obtain K clusters and a representative chip for each cluster; controlling an ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; determining multiple risk clusters and multiple second risk chips in each risk cluster based on the multiple first risk chip information and the X-ray inspection information of the representative chip of each cluster; determining a final detection path based on the multiple second risk chip pictures in each risk cluster; and controlling the ultra-small high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

[0014] According to the fourth aspect, this embodiment provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the control method for the ultra-small high-precision servo-driven turntable provided above, the method comprising: obtaining a picture of a wafer to be inspected; determining each split chip picture and each split chip information based on the picture of the wafer to be inspected; determining a plurality of first risk chips based on the information of each split chip; clustering using a clustering algorithm based on the information of the plurality of first risk chips to obtain K clusters and a representative chip of each cluster; controlling the ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; determining a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster; determining a final detection path based on the pictures of the plurality of second risk chips in each risk cluster; and controlling the ultra-small high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

[0015] The present invention provides a control method and system for an ultra-small high-precision servo-driven turntable, which includes obtaining a picture of a wafer to be inspected; determining each split chip picture and each split chip information based on the picture of the wafer to be inspected; determining multiple first risk chips based on the information of each split chip; clustering using a clustering algorithm based on the information of multiple first risk chips to obtain K clusters and a representative chip of each cluster; controlling the ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; determining multiple risk clusters and multiple second risk chips in each risk cluster based on the multiple first risk chip information and the X-ray inspection information of the representative chip of each cluster; determining a final detection path based on the pictures of multiple second risk chips in each risk cluster; and controlling the ultra-small high-precision servo-driven turntable to perform electrical performance testing based on the final detection path. This method can quickly and accurately determine the optimal wafer detection path. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic flow chart of a control method for an ultra-small high-precision servo-driven turntable provided by an embodiment of the present invention;

[0017] Figure 2 A schematic diagram of a wafer provided by an embodiment of the present invention;

[0018] Figure 3 A schematic diagram of K-means clustering provided by an embodiment of the present invention;

[0019] Figure 4 A schematic diagram of a process for determining a final detection path provided by an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of constructing a detection map provided by an embodiment of the present invention;

[0021] Figure 6 A schematic diagram of a control system for an ultra-small high-precision servo-driven turntable provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present invention to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present invention are not shown or described in the specification. This is to avoid the core of the present invention being overwhelmed by excessive descriptions, and for those skilled in the art, it is not necessary to describe these related operations in detail. They can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0023] In an embodiment of the present invention, there is provided Figure 1 A control method for an ultra-small high-precision servo-driven turntable is shown, and the control method for the ultra-small high-precision servo-driven turntable includes steps S1 to S8:

[0024] Step S1, obtaining a picture of the wafer to be inspected.

[0025] The wafer to be inspected is a silicon wafer that has completed the main process processing in the semiconductor manufacturing process. Figure 2 A schematic diagram of a wafer provided in an embodiment of the present invention. The surface of the wafer to be inspected contains a large number of duplicate integrated circuit chips, such as CPUs and memory chips. For example, a 12-inch wafer can contain hundreds of identical chips on its surface.

[0026] The image of the wafer to be inspected is an image of the wafer surface captured by a high-resolution industrial camera.

[0027] Step S2: determining each split chip image and each split chip information based on the image of the wafer to be inspected.

[0028] In some embodiments, an information segmentation model can be used based on the image of the wafer to be inspected to determine each segmented chip image and each segmented chip information. The information segmentation model is a convolutional neural network model. The input of the information segmentation model is the image of the wafer to be inspected, and the output of the information segmentation model is each segmented chip image and each segmented chip information.

[0029] The convolutional neural network (CNN) model is a deep learning model that can process grid-structured data such as images. It can automatically extract data features through components such as convolutional layers, pooling layers, and fully connected layers.

[0030] Each segmented chip image is an image corresponding to each individual chip segmented from the entire image of the wafer to be inspected, output by the information segmentation model. The segmented chip image contains all the detailed features of the chip.

[0031] Each segmented chip information is structured information corresponding to each segmented chip image, extracted from the image of the wafer to be inspected using the information segmentation model. This information characterizes the physical properties, location characteristics, and preliminary inspection features of the segmented chip. The segmented chip information includes information such as the physical properties and preliminary inspection features of the segmented chip.

[0032] The physical property information includes the geometric dimensions of the split chips, the row and column positions of the split chips in the wafer, the pixel coordinate range of the split chips, the surface texture characteristics and other information.

[0033] The preliminary detection features are preliminary information on defects on the surface of the split chip, such as scratches, particle attachment, and abnormal position and morphology of the metal layer, extracted based on the split chip image, as well as process identification information such as the batch number and process version mark of the split chip.

[0034] The convolutional neural network model uses its unique hierarchical feature extraction mechanism to analyze images of the wafers being inspected. The convolutional neural network uses the convolutional layers to identify basic image features, such as edges and texture, and then uses the deep network to construct complete chip outline features. During the feature extraction process, the pooling layer reduces computational complexity while preserving key spatial information. Ultimately, the convolutional neural network outputs a precise boundary mask for each segmented chip image and extracts the corresponding segmented chip information for each segmented chip image.

[0035] Step S3: determining a plurality of first risk chips based on the information of each segmented chip.

[0036] In some embodiments, a first risk determination model can be used to determine multiple first risk chips based on the information of each segmented chip. The first risk determination model is a Transformer model. The input of the first risk determination model is the information of each segmented chip, and the output of the first risk determination model is multiple first risk chips.

[0037] The Transformer model is a deep learning model based on the self-attention mechanism. The Transformer model can effectively capture the long-distance dependencies between elements in the input sequence through components such as multi-head self-attention mechanism, position encoding, feedforward neural network, residual connection and layer normalization, thereby completing deep feature extraction and semantic understanding of the data.

[0038] The first risk chip is a chip with potential quality risk that is screened out by the first risk determination model.

[0039] Potential quality risks can include particle contamination, scratches, bridges, opens and shorts.

[0040] Segmented chip information includes information about the chip's physical properties and preliminary detection features, and these features contain complex nonlinear relationships. The Transformer model's multi-head self-attention mechanism automatically learns and captures the weights and correlations between these dimensions. For example, when features such as chip dimensional deviation, surface roughness, and texture complexity in key areas exhibit anomalies simultaneously, the Transformer model can discern these anomalies and assign them a higher risk weight. Furthermore, there is a spatial dependency between chip location and risk. For example, chips at the wafer edge are more susceptible to defects due to factors such as stress. The Transformer model's position encoding technology effectively preserves the chip's spatial coordinate information and, combined with the self-attention mechanism, deeply mines these spatial features to accurately identify chips with potential risks.

[0041] Step S4: clustering is performed using a clustering algorithm based on the information of the plurality of first risk chips to obtain K clusters and a representative chip for each cluster.

[0042] The first risk chip information is information corresponding to the first risk chip extracted from all the split chip information.

[0043] The clustering algorithm is the K-means clustering algorithm. The K-means clustering algorithm is an unsupervised machine learning algorithm that can divide a given dataset into K distinct clusters, ultimately ensuring that data points within the same cluster have high similarity, while data points between different clusters are significantly different. The K-means clustering algorithm effectively groups data by iteratively adjusting cluster centers and minimizing the sum of the squared distances from each data point to its cluster center.

[0044] In some embodiments, the K value in the K-means clustering algorithm can be obtained by artificially setting in advance.

[0045] In some embodiments, the specific execution process of clustering using the K-means clustering algorithm based on multiple first-risk chip information is as follows: first, K chips are randomly selected from the first-risk chip information data set as initial cluster centers, and then the Euclidean distance is used to calculate the distance between each first-risk chip information and these K initial cluster centers, and the chips are divided into corresponding clusters according to the principle of closest distance. After all first-risk chips are divided, the average value of each feature of the chip in each cluster is recalculated to update the cluster center of each cluster. The above division and update steps are repeated until the change in the cluster center is less than a preset threshold. At this time, the clustering process converges, and finally K clusters are obtained, thereby completing K-means clustering.

[0046] Each cluster can represent a set of first risk chips with similar risk characteristics. Figure 3 FIG. 1 is a schematic diagram of a K-means clustering method according to an embodiment of the present invention. Figure 3 As shown, Figure 3 Clusters 1, 2, 3, 4, and 5 are clusters of similarly spaced data points. The commonalities within each cluster can be quantified using the average characteristics, distribution range, or key indicators of the data within the cluster. These similarities can be reflected in multiple dimensions, including the chip's physical defect type, electrical performance parameters, and location distribution patterns.

[0047] For example, one cluster may contain chips with tiny cracks in the edge area of ​​the wafer, while another cluster may be mainly composed of chips with unstable performance in the central area due to material impurities. Some clusters are significantly concentrated in the high-stress area at the edge of the wafer, while others are concentrated in the low-defect density area in the center.

[0048] The representative chip of each cluster is the chip closest to the centroid of each cluster. The representative chip of each cluster serves as a typical sample of the risk chip of that type, and the representative chip can collectively reflect the common characteristics of the corresponding cluster.

[0049] Clustering the first risk chips improves detection efficiency and analysis accuracy. Dividing a large number of discrete risk chips into a limited number of clusters simplifies the data structure, avoiding the tedious process of analyzing each chip individually and focusing detection resources on critical areas. The representative chip in each cluster serves as a priority for subsequent in-depth testing, allowing us to infer the potential risks of other chips within the cluster by simply testing the representative chip.

[0050] Step S5 , controlling the ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and performing X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster.

[0051] An ultra-compact, high-precision servo-driven turntable is a mechanical device with high-precision motion control capabilities. Driven by a servo motor, it achieves micron-level positioning and motion control, enabling precise movement and rotation within three-dimensional space.

[0052] X-ray inspection information for each cluster's representative chip is obtained by precisely positioning the X-ray inspection equipment at the representative chip in each cluster using an ultra-compact, high-precision servo-driven turntable to scan its internal structure. This X-ray inspection information includes quantitative data on physical characteristics such as the connectivity of the chip's internal metal interconnects, the structural integrity of the silicon substrate, and the morphology of solder balls or bonds used in the wafer-level packaging process. Furthermore, structural information such as defect type, the defect's 3D position in the chip coordinate system, and defect size, derived from X-ray image analysis, is also included.

[0053] Step S6 : determining a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster.

[0054] In some embodiments, a second risk determination model can be used to determine multiple risk clusters and multiple second risk chips in each risk cluster based on the multiple first risk chip information and the X-ray inspection information of the representative chip of each cluster. The second risk determination model is a deep neural network model. The input of the second risk determination model is the multiple first risk chip information and the X-ray inspection information of the representative chip of each cluster. The output of the second risk determination model is multiple risk clusters and multiple second risk chips in each risk cluster.

[0055] Deep neural network models include deep neural networks (DNNs), which are machine learning models developed based on artificial neural network architectures. DNNs can automatically learn complex feature representations and patterns from massive amounts of data. DNNs consist of an input layer, multiple hidden layers, and an output layer, with neurons in each layer connected by learnable weights.

[0056] Risk clusters are clusters of chips with more significant risk characteristics, selected from all clusters by the second risk determination model. Risk clusters focus on chip sets with more severe defects and higher probability of functional failure.

[0057] The plurality of second-risk chips in the risk cluster are chips output by the second risk determination model and are further determined to be high-risk in the risk cluster.

[0058] The information on multiple first-risk chips includes external risk characteristics such as surface defects and physical properties, while the X-ray inspection data of the representative chip in each cluster reveals internal structural defects. These first-risk chip information and the X-ray inspection data of the representative chip in each cluster complement each other, respectively, by providing macro-level risk manifestations and micro-level defect characteristics. By integrating these two types of information, the model can automatically discover correlations between surface risks and internal defects, clustering chips with similar high-risk characteristics, such as surface scratches and internal solder joint defects, into risk clusters. Furthermore, the model can further screen out higher-risk second-risk chips within the cluster based on defect severity.

[0059] Deep neural networks can uncover complex hidden connections between data, including first-risk chip information such as chip geometry and appearance defect probability, and internal structure and defect characteristics from X-ray inspections. Trained on large amounts of labeled data, deep neural networks can learn the mapping between different risk characteristics and chip risk levels, enabling them to accurately classify chips into different risk clusters and identify second-risk chips within each cluster.

[0060] Step S7: determining a final detection path based on multiple second risk chip images in each risk cluster.

[0061] In some embodiments, Figure 4 A schematic diagram of a process for determining a final detection path provided by an embodiment of the present invention, wherein determining the final detection path includes steps S71 to S74:

[0062] Step S71 : determining necessary detection components, secondary detection components, and optional detection components in the second risk chip based on the multiple second risk chip images in each risk cluster and the information of each second risk chip.

[0063] The multiple second risk chip images in the risk cluster are images corresponding to the second risk chip extracted from all the segmented chip images, and the second risk chip images contain all detailed features of the second risk chip.

[0064] The second risk chip information is structured information corresponding to the second risk chip extracted from all the segmented chip information.

[0065] In some embodiments, a component analysis model can be used to determine necessary detection components, secondary detection components, and optional detection components in the second risk chip based on multiple second risk chip images and each second risk chip information in each risk cluster. The component analysis model is a convolutional neural network model. The input of the component analysis model is multiple second risk chip images and each second risk chip information in each risk cluster, and the output of the component analysis model is the necessary detection components, secondary detection components, and optional detection components in the second risk chip.

[0066] The necessary inspection components are components in the second risk chip that are determined to have a high probability of functional failure risk through the output of the component analysis model.

[0067] Secondary inspection components are components that have a certain risk output by the component analysis model, but the probability is lower than that of necessary inspection components.

[0068] Optional detection components are components with extremely low risk probability output by the component analysis model. The risk probability of optional detection components is lower than that of necessary detection components and secondary detection components.

[0069] Convolutional neural networks can perform component-level risk assessment through a multi-scale feature fusion mechanism. First, the convolutional neural network extracts component-level microscopic features from the second-risk chip image through a convolutional layer. It then combines this information with the second-risk chip to construct a multidimensional feature vector space. Finally, a fully connected layer learns the mapping between feature combinations and risk levels in historical defect samples.

[0070] In some embodiments, the component analysis model includes a component analysis layer, an information association layer, and a priority division layer. The input of the component analysis layer is multiple second risk chip images in each risk cluster. The output of the component analysis layer is the distribution position, size and shape of each component, and the interconnection relationship between components. The input of the information association layer is the distribution position, size and shape of each component, and the interconnection relationship between components. The output of the information association layer is component functional positioning information, position sensitivity coefficient, risk probability, failure propagation coefficient, and detectability score. The input of the priority division layer is component functional positioning information, position sensitivity coefficient, risk probability, failure propagation coefficient, and detectability score. The output of the priority division layer is necessary detection components, secondary detection components, and optional detection components in the second risk chip.

[0071] The interconnection relationship between components is the electrical connection path formed by the components in the chip through metal wiring, for example, pin 1 of resistor R1 is connected to pin 3 of capacitor C2.

[0072] Functional positioning information is information used to describe the specific function of each component.

[0073] Position sensitivity coefficient is used to quantify the impact of the physical location of a component on its reliability.

[0074] The failure propagation coefficient is a value used to evaluate the extent of the chain reaction of a single component failure on the surrounding circuits.

[0075] The detectability score is an assessment of the difficulty of detecting a component based on its physical characteristics. A higher detectability score indicates that the component is easier to detect.

[0076] Different layers are responsible for different levels of information abstraction and processing. The component analysis layer extracts component distribution, location, size, shape, and interconnections from chip images. The information association layer generates assessment metrics such as risk probability and location sensitivity coefficient. The prioritization layer determines component inspection priority based on risk indicators. This layered approach allows for more efficient processing of complex chip inspection information. Building multiple layers increases the system's modularity and enables more efficient information processing, thereby improving system accuracy and efficiency.

[0077] Step S72: Generate multiple alternative detection paths, detection information of each alternative detection path, and the difference of the detection information of each alternative detection path based on the position of each second risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chip.

[0078] The position of the second risk chip is obtained by extracting the row, column and coordinate position of the second risk chip in the wafer from the second risk chip information.

[0079] In some embodiments, a generative adversarial network can be used to generate multiple alternative detection paths, detection information of each alternative detection path, and the degree of difference of the detection information of each alternative detection path based on the position of each second-risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chip. The input of the generative adversarial network is the position of each second-risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chip, and the output of the generative adversarial network is multiple alternative detection paths, detection information of each alternative detection path, and the degree of difference of the detection information of each alternative detection path.

[0080] Generative Adversarial Networks (GANs) are deep learning models that generate data through a game-based learning mechanism. They consist of two neural networks: a generator and a discriminator. The generator learns the distribution of real data to generate simulated data that closely resembles real samples, while the discriminator verifies the authenticity of input data and distinguishes between real data and the samples output by the generator. The generator and discriminator compete against each other during iterative training, ultimately reaching a Nash equilibrium. This ensures that the generator's output closely resembles real data in terms of distribution and characteristics.

[0081] The multiple candidate detection paths are combinations of multiple detection strategy paths for the second risk chip generated by the generative adversarial network, wherein each candidate detection path passes through all necessary detection components, as well as some secondary detection components and optional detection components.

[0082] The test information for each candidate test path describes the execution details and quantitative indicators of each test path. This information includes component coverage strategy, test execution sequence, estimated resource consumption, efficiency indicators, path reliability score, and other information.

[0083] The component coverage strategy is the detection coverage rules formulated for the necessary detection components, secondary detection components and optional detection components in the second risk chip.

[0084] As an example, necessary inspection components need to undergo 100% full inspection to ensure that no high-risk areas are missed. Secondary inspection components can be sampled and inspected at a ratio of 50% to 80% to balance risk and inspection efficiency. Optional inspection components can be sampled and inspected at a rate of no more than 30% to optimize resource allocation.

[0085] The test execution sequence is the order in which the various components on the chip are tested within the alternative test paths. This sequence includes the order in which the test instrument tests essential, secondary, and optional components, as well as the order in which the different test steps are connected.

[0086] The estimated resource consumption is a quantitative value of the resource inputs such as the equipment operating time and energy loss that are expected to be consumed during the detection process when executing an alternative detection path.

[0087] The efficiency index is a quantitative indicator that measures the amount of detection per unit time of an alternative detection path or the time consumed for single sample detection.

[0088] The path reliability score is an indicator used to quantitatively evaluate the stability and accuracy of alternative detection paths during execution.

[0089] The difference in detection information for each candidate detection path is a numerical value output by the GAN that quantifies the degree of difference in detection information between candidate detection paths. Difference can be expressed as a value between 0 and 1, with higher values ​​indicating greater difference in detection information between candidate detection paths.

[0090] The generator of the generative adversarial network can learn the characteristic patterns of the detection path based on data such as the location of the second-risk chip and the distribution of components, thereby generating multiple alternative detection paths and corresponding detection information. The discriminator can reversely optimize the generator by continuously distinguishing between the real path data and the generated path data, so that the generator's output is more in line with actual needs. In addition, the discriminator of the generative adversarial network can also convert different detection path information into feature vectors, and then calculate the degree of difference between the alternative detection paths by measuring the distribution differences between the vectors.

[0091] Step S73, construct a detection map, which includes multiple detection path nodes and multiple edges between the multiple detection path nodes. The node features of each detection path node include an alternative detection path and detection information of each alternative detection path. The edges between the detection path nodes are the differences in the detection information of each alternative detection path.

[0092] A test graph is a visual data structure consisting of test path nodes and the edges connecting them. Test path nodes, as basic units, store specific candidate test paths and detailed test information, such as component coverage strategies and test execution order. Edges between nodes quantify the degree of difference in test information between two corresponding candidate test paths. Figure 5 A schematic diagram of constructing a detection spectrum provided by an embodiment of the present invention. Figure 5 As shown, Figure 5It includes detection path node A, detection path node B, detection path node C, and detection path node D. The edge between two detection path nodes is the difference in detection information of the paths contained in these two detection path nodes.

[0093] By constructing a detection map as a data organization form, multiple complex alternative detection paths and their interrelationships can be presented in an intuitive and clear manner.

[0094] Step S74: Process the detection map based on the graph neural network to determine the final detection path.

[0095] A graph neural network (GNN) is a machine learning model that can process non-Euclidean data. It can learn from topological data such as detection graphs, which have nodes and edges, and effectively extract structural features and semantic information from the data. The input of the GNN is the detection graph, and the output is the final detection path.

[0096] The final detection path is the one that best meets the detection objectives and requirements, selected by the graph neural network from multiple candidate detection paths. The final detection path is the specific path used when actually performing the detection task.

[0097] The final detection path can achieve the optimal configuration of detection resources while ensuring the detection quality.

[0098] Each node in the detection graph corresponds to an alternative detection path. Nodes are fundamental units for analysis and provide data support for determining the final detection path. Nodes allow multiple alternative detection paths to be stored and represented as discrete units. Nodes enable the graph neural network to independently process each path and efficiently extract features, allowing for a comprehensive consideration of all alternative paths.

[0099] Node features contain information about each candidate inspection path, such as component coverage strategy, inspection execution order, and estimated resource consumption. This information can provide a basis for decision-making in the graph neural network. Based on node features, the graph neural network can learn the pros and cons of different paths in meeting inspection objectives, thereby determining the value of each path in determining the final inspection path.

[0100] Edges between detection path nodes numerically represent the differences in detection information for each candidate detection path. Using this quantified information, graph neural networks can analyze the connections and differences between paths and identify redundant or complementary path combinations. Edges help graph neural networks globally weigh the relationships between paths, thereby more accurately determining the final detection path with the best overall performance.

[0101] The information contained in the nodes and edges of the detection graph is well-suited to the processing model of graph neural networks. Graph neural networks can leverage the detailed information about alternative detection paths in node features, combined with the path differences represented by edges, to learn the importance and relevance of different detection paths within the entire graph through layer-by-layer information transmission and aggregation. In this way, graph neural networks can comprehensively evaluate all alternative detection paths from a global perspective, weighing various detection metrics to output the final detection path that best meets the detection objectives.

[0102] Step S8: Based on the final detection path, the ultra-small high-precision servo drive turntable is controlled to perform electrical performance detection.

[0103] Once the final inspection path is determined, the information contained in the final inspection path, such as the coordinates of the test chips and the inspection sequence, is converted into control instructions for the ultra-small, high-precision servo-driven turntable through a motion control algorithm. These instructions include parameters such as rotation angle, displacement distance, and movement speed. The ultra-small, high-precision servo-driven turntable precisely adjusts the probe station's probe positions based on these instructions, allowing the probes to be precisely aligned with the chip pads on the wafer to be inspected, sequentially according to the planned sequence, thereby completing the electrical performance test of the chips on the wafer to be inspected.

[0104] Based on the same inventive concept, Figure 6 A schematic diagram of a control system for an ultra-small high-precision servo-driven turntable provided in an embodiment of the present invention. The control system for the ultra-small high-precision servo-driven turntable includes:

[0105] An acquisition module 61 is used to acquire an image of the wafer to be inspected;

[0106] An information segmentation module 62 is configured to determine each segmented chip image and each segmented chip information based on the image of the wafer to be inspected;

[0107] A first determining module 63 is configured to determine a plurality of first risk chips based on each segmented chip information;

[0108] A clustering module 64 is configured to perform clustering based on the information of the plurality of first risk chips using a clustering algorithm to obtain K clusters and a representative chip for each cluster;

[0109] X-ray inspection module 65, used to control the ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster;

[0110] A second determining module 66 is configured to determine a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster;

[0111] a path planning module 67, configured to determine a final detection path based on a plurality of second risk chip images in each risk cluster;

[0112] The electrical detection module 68 is used to control the ultra-small high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

[0113] It should be noted that, in order to simplify the presentation of this specification and facilitate understanding of one or more embodiments of the invention, the foregoing descriptions of the embodiments of this specification sometimes combine multiple features into a single embodiment, figure, or description thereof. However, this disclosure method does not imply that the subject matter of this specification requires more features than those recited in the claims. In fact, an embodiment may have fewer features than all of the features of a single disclosed embodiment.

[0114] Finally, it should be understood that the embodiments described in this specification are intended only to illustrate the principles of the embodiments of this specification. Other variations may also fall within the scope of this specification. Therefore, by way of example and not limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments explicitly described and illustrated in this specification.

Claims

1. A control method for an ultra-small high-precision servo-driven turntable, characterized in that: include: Get a picture of the wafer to be inspected; Determine each split chip image and each split chip information based on the image of the wafer to be inspected; determining a plurality of first risk chips based on each of the split chip information; Clustering is performed using a clustering algorithm based on the information of the plurality of first risk chips to obtain K clusters and a representative chip of each cluster; Controlling an ultra-small high-precision servo-driven turntable to move to a representative chip of each cluster and performing X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; determining a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster; determining a final detection path based on a plurality of second risk chip images in each risk cluster; An ultra-small high-precision servo-driven turntable is controlled based on the final detection path to perform electrical performance detection.

2. The control method of the ultra-small high-precision servo-driven turntable according to claim 1, characterized in that: Determining the final detection path based on the plurality of second risk chip images in each risk cluster includes: Determine necessary detection components, secondary detection components, and optional detection components in the second risk chip based on multiple second risk chip images in each risk cluster and each second risk chip information; Generate multiple alternative detection paths, detection information of each alternative detection path, and the difference of the detection information of each alternative detection path based on the position of each second risk chip, the necessary detection components, the secondary detection components, and the optional detection components in the second risk chip; Constructing a detection graph, wherein the detection graph includes a plurality of detection path nodes and a plurality of edges between the plurality of detection path nodes, wherein the node features of each detection path node include an alternative detection path and detection information of each alternative detection path, and the edges between the detection path nodes represent the difference of the detection information of each alternative detection path; The detection map is processed based on a graph neural network to determine the final detection path.

3. The control method of the ultra-small high-precision servo-driven turntable according to claim 1, characterized in that: The representative chip of each cluster is the chip closest to the centroid of each cluster.

4. The control method of the ultra-small high-precision servo-driven turntable according to claim 1, characterized in that: The clustering algorithm is the K-means clustering algorithm.

5. A control system for an ultra-small high-precision servo-driven turntable, characterized in that: include: An acquisition module is used to obtain images of the wafer to be inspected; An information segmentation module, configured to determine each segmented chip image and each segmented chip information based on the image of the wafer to be inspected; A first determining module, configured to determine a plurality of first risk chips based on each of the split chip information; A clustering module, configured to perform clustering based on the information of the plurality of first risk chips using a clustering algorithm to obtain K clusters and a representative chip for each cluster; The X-ray inspection module is used to control the ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; a second determining module, configured to determine a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster; a path planning module, configured to determine a final detection path based on multiple second risk chip images in each risk cluster; The electrical detection module is used to control the ultra-small high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

6. The control system of the ultra-small high-precision servo-driven turntable according to claim 5, characterized in that: The path planning module is also used to: Determine necessary detection components, secondary detection components, and optional detection components in the second risk chip based on multiple second risk chip images in each risk cluster and each second risk chip information; Generate multiple alternative detection paths, detection information of each alternative detection path, and the difference of the detection information of each alternative detection path based on the position of each second risk chip, the necessary detection components, the secondary detection components, and the optional detection components in the second risk chip; Constructing a detection graph, wherein the detection graph includes a plurality of detection path nodes and a plurality of edges between the plurality of detection path nodes, wherein the node features of each detection path node include an alternative detection path and detection information of each alternative detection path, and the edges between the detection path nodes represent the difference of the detection information of each alternative detection path; The detection map is processed based on a graph neural network to determine the final detection path.

7. The control system of the ultra-small high-precision servo-driven turntable according to claim 5, characterized in that: The representative chip of each cluster is the chip closest to the centroid of each cluster.

8. The control system of the ultra-small high-precision servo-driven turntable according to claim 5, characterized in that: The clustering algorithm is the K-means clustering algorithm.

9. An electronic device, characterized in that: include: processor; Memory; and a computer program; wherein the computer program is stored in the memory and is configured to be executed by the processor to implement the control method of the ultra-small high-precision servo-driven turntable according to any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the control method of the ultra-small high-precision servo-driven turntable according to any one of claims 1 to 4 is implemented.

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