Numerical control delayer, four-digit numerical control delayer and manufacturing method of chip of four-digit numerical control delayer

Abstract

The invention provides a numerical control delayer, a four-digit numerical control delayer and a manufacturing method of a chip of the four-digit numerical control delayer. The delayer comprises a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit, the first single-pole double-throw switch comprises two stages of triodes S1 and S2 which are connected in parallel; the second single-pole double-throw switch comprises a triode S3 and a triode S4 which are connected in parallel; one end of the delay unit is connected with the drain electrode of S1, and the other end is connected with the drain electrode of S3; one end of the reference unit is connected with the drain of S2, and the other end is connected with the drain of S4; drain electrodes of the S1 and the S2 are connected with a radio frequency signal input port; drain electrodes of the S3 and the S4 are connected with a radio frequency signal output port; source electrodes of the S1, the S2, the S3 and the S4 are all in direct current grounding, grid electrodes of the S1, the S2, the S3 and the S4 are all connected with a voltage control unit, and on and off of each triode are controlled by controlling grid electrode voltage, so that the delayer is switched between a reference state and a delay state. According to the invention, the insertion loss of the delayer in the millimeter wave frequency band can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of delayers, and particularly to a numerical control delayer, a four-bit numerical control delayer and a manufacturing method of a chip thereof. Background Art

[0002] In a broadband phased array antenna, due to the aperture effect, the pointing direction of the antenna scanning beam will drift with the change of the operating frequency, thus deteriorating the frequency response of the antenna to broadband signals and further restricting the instantaneous bandwidth of the phased array antenna. Therefore, the core technology to be solved in antenna broadband imaging is how to eliminate the beam spatial pointing dispersion problem caused by broadband large aperture and large scanning angle during large-angle two-dimensional scanning of the antenna array surface and improve the beam pointing accuracy. To solve this problem, it is necessary to perform delay compensation on the received / transmitted signals of the phased array antenna, that is, to achieve broadband consistency by adjusting the time difference of radio frequency signal transmission. A numerical control delayer is a commonly used microwave passive two-port device, and its main function is to delay an electromagnetic wave for a constant time during transmission between two ports to compensate for the phase difference caused by different frequencies. It has a wide range of applications in many fields, such as satellite communication, antenna systems and phased array antenna arrays. The numerical control delayer is mainly used to compensate for the beam spatial pointing dispersion problem caused by broadband large-angle scanning, and when processing broadband and ultra-wideband array signals, the time delay difference between the received and transmitted signals of each antenna element must be compensated to a reasonable range.

[0003] In the related art, a low-frequency numerical control delayer is proposed. Its chip structure usually consists of a switching circuit, a delay branch and a reference branch, and the switching circuit is controlled to realize the switching of the delayer between the reference state and the delay state; specifically, the switching circuit includes two groups of series-parallel single-pole double-throw (SPDT) switches. Each branch of each group of series-parallel single-pole double-throw switches is composed of a first-level series triode and one or two levels of parallel triodes. Each triode serves as a microwave switch. When the triode is turned on, the triode is equivalent to a small resistor at this time; when the triode is turned off, the triode works in a high-impedance state (off state), and at this time the triode is equivalent to a parallel structure of a high resistor and a small capacitor; the reference branch and the delay branch require two groups of series-parallel single-pole double-throw switches to work complementarily in the reference state and the delay state to achieve the delay function.

[0004] However, as the operating frequency of the antenna transceiver system increases, the output power and efficiency of the power source decrease, the losses of the receiving link devices and transmission lines increase, and higher requirements are also put forward for the insertion loss of the delay chip. Especially in millimeter-wave system antennas, millimeter waves (such as frequency bands 32 - 40 GHz) have high communication speed and small antenna size, but high-frequency signals are prone to attenuation, and traditional low-frequency numerically controlled delayers have extremely high losses in the millimeter-wave band. If a traditional low-frequency numerically controlled delayer is used in the millimeter-wave band, when the switch is turned on, the equivalent resistance of the series-connected triode increases, resulting in a relatively large switch insertion loss at high frequencies (the insertion loss of each switch is about 2 dB). If it is a four-bit delayer, the total switch insertion loss caused by multi-stage series connection is as high as about 16 dB. Coupled with other insertion losses, the total loss is as high as 30 dB. Summary of the Invention

[0005] An embodiment of the present invention provides a numerically controlled delayer, a four-bit numerically controlled delayer and a manufacturing method of its chip to solve the problem that traditional low-frequency numerically controlled delayers have extremely high losses in the millimeter-wave band.

[0006] In a first aspect, an embodiment of the present invention provides a numerically controlled delayer, including: a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit;

[0007] The first single-pole double-throw switch includes: two stages of parallel-connected triodes S1 and S2;

[0008] The second single-pole double-throw switch includes: two stages of parallel-connected triodes S3 and S4;

[0009] The drain of the triode S1 is connected to one end of the delay unit, and the other end of the delay unit is connected to the drain of the triode S3;

[0010] The drain of the triode S2 is connected to one end of the reference unit, and the other end of the reference unit is connected to the drain of the triode S4;

[0011] The drains of the triodes S1 and S2 are both connected to the radio frequency signal input port;

[0012] The drains of the triodes S3 and S4 are both connected to the radio frequency signal output port;

[0013] The sources of the triodes S1, S2, S3 and S4 are all directly grounded, and the gates are all connected to a voltage control unit to control the on and off of each triode by controlling the gate voltage, so that the delayer switches between the reference state and the delay state.

[0014] In a possible implementation manner, the delay unit includes a coplanar waveguide transmission line, and the delay amount of the radio frequency signal is positively correlated with the physical path length of the coplanar waveguide transmission line.

[0015] In a possible implementation, the delay amount of the radio frequency signal where L represents the physical path length of the coplanar propagation wire, ε r represents the relative dielectric constant of the medium of the coplanar propagation wire, and c represents the speed of light.

[0016] In a possible implementation, a high-low impedance microstrip line is used to connect the drains of the triodes S1 and S2 to the radio frequency signal input port.

[0017] In a possible implementation, the reference unit includes: a Π-type attenuation equalization network;

[0018] The Π-type attenuation equalization network includes: a resistor R1, a resistor R2, and a resistor R3;

[0019] One end of the resistor R1 is connected to the drain of the triode S2, and the other end is connected to the drain of the triode S4;

[0020] One end of the resistor R2 is connected to one end of the resistor R1, one end of the resistor R3 is connected to the other end of the resistor R1, and the other ends of the resistors R2 and R3 are grounded respectively.

[0021] In a possible implementation, the digital control delay line further includes: a control logic unit;

[0022] The control logic unit is connected to the gates of the triodes S1, S2, S3, and S4, and is used to control the gate voltages of the triodes S1, S2, S3, and S4 to be 0V or -5V respectively according to a preset truth table.

[0023] In a possible implementation, the gates of the triodes S1, S2, S3, and S4 are all connected to the voltage control unit through isolation resistors.

[0024] In a possible implementation, the triode is a GaAs PHEMT triode.

[0025] In a second aspect, an embodiment of the present invention provides a four-bit digital control delay line, including: four digital control delay lines provided in the first aspect of the present invention: wherein, the four digital control delay lines are connected in a cascaded manner: the radio frequency output port of the previous-stage digital control delay line is connected to the radio frequency input port of the next-stage digital control delay line;

[0026] wherein, the step value of the four-bit digital control delay line is 1λ, λ is the wavelength of the radio frequency signal, and the delay amount realized by the delay unit of each digital control delay line is 2 n λ, and the values of n are 0, 1, 2, and 3 respectively.

[0027] In a third aspect, an embodiment of the present invention provides a manufacturing method of a numerically controlled delay chip based on the numerically controlled delay device provided in the first aspect or the four-bit numerically controlled delay device provided in the second aspect of the present invention, including:

[0028] Setting multiple cascaded common-ground via isolation bands in the layout of the chip for electromagnetic space isolation;

[0029] Setting filter capacitors on the DC transmission line to prevent digital noise coupling.

[0030] An embodiment of the present invention provides a numerically controlled delay device, including: a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit, and a reference unit; the first single-pole double-throw switch includes two parallel-connected triodes S1 and S2; the second single-pole double-throw switch includes two parallel-connected triodes S3 and S4; one end of the delay unit is connected to the drain of S1 and the other end is connected to the drain of S3; one end of the reference unit is connected to the drain of S2 and the other end is connected to the drain of S4; the drains of S1 and S2 are connected to the RF signal input port; the drains of S3 and S4 are connected to the RF signal output port; the sources of S1, S2, S3, and S4 are all grounded directly, and the gates are all connected to a voltage control unit. By controlling the gate voltage, the on and off of each triode are controlled, so that the delay device switches between the reference state and the delay state. The embodiment of the present invention adopts a single-pole double-throw switch with a pure parallel structure, avoiding the problem of excessive insertion loss of the switch caused by the large equivalent resistance due to the series connection of triodes, thereby greatly reducing the insertion loss of the delay device when used in the millimeter-wave band. Description of the Drawings

[0031] Figure 1 is a schematic structural diagram of a single-pole double-throw switch with a series-parallel structure provided by the prior art;

[0032] Figure 2 is an equivalent circuit diagram of a basic unit of a delay constant-resistance network provided by the prior art;

[0033] Figure 3 is a schematic structural diagram of a single-pole double-throw switch with a pure parallel structure provided by an embodiment of the present invention;

[0034] Figure 4 is a schematic structural diagram of the numerically controlled delay device provided by an embodiment of the present invention;

[0035] Figure 5 is a schematic structural diagram of the numerically controlled delay device provided by another embodiment of the present invention;

[0036] Figure 6 is a schematic structural diagram of the numerically controlled delay device provided by yet another embodiment of the present invention;

[0037] Figure 7It is a schematic structural diagram of a four-bit numerically controlled delay line provided by an embodiment of the present invention;

[0038] Figure 8 It is a comparative curve graph of the insertion loss of the new and old single-pole double-throw switches provided by an embodiment of the present invention;

[0039] Figure 9 It is a comparative curve graph of the insertion loss of the 8-wavelength positions of the delay unit provided by an embodiment of the present invention;

[0040] Figure 10 It is an insertion loss curve graph of the four-bit numerically controlled delay line provided by an embodiment of the present invention;

[0041] Figure 11 It is an amplitude fluctuation curve graph of each state of the four-bit numerically controlled delay line provided by an embodiment of the present invention;

[0042] Figure 12 It is a delay amount curve graph of the four-bit numerically controlled delay line provided by an embodiment of the present invention;

[0043] Figure 13 It is a delay accuracy curve graph of the four-bit numerically controlled delay line provided by an embodiment of the present invention;

[0044] Figure 14 It is a curve graph of the input voltage standing wave ratio of the reference state and the delayed state of the four-bit numerically controlled delay line provided by an embodiment of the present invention;

[0045] Figure 15 It is a curve graph of the output voltage standing wave ratio of the reference state and the delayed state of the four-bit numerically controlled delay line provided by an embodiment of the present invention. Detailed implementation manners

[0046] In order to enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below in conjunction with the accompanying drawings in the embodiments of this solution. Obviously, the described embodiments are some, rather than all, of the embodiments of this solution. Based on the embodiments in this solution, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this solution.

[0047] The term "including" in the description and claims of this solution and the above-mentioned accompanying drawings, as well as any other variations, means "including but not limited to", and is intended to cover non-exclusive inclusion, not limited to the examples listed in the text. In addition, terms such as "first" and "second" are used to distinguish different objects, rather than to describe a specific order.

[0048] In a broadband phased array antenna, due to the aperture effect, the pointing direction of the antenna scanning beam drifts with the change of the operating frequency, which deteriorates the frequency response of the antenna to broadband signals and further restricts the instantaneous bandwidth of the phased array antenna. Therefore, the core technology to be solved in antenna broadband imaging is how to eliminate the beam spatial pointing dispersion problem caused by broadband large aperture and large scanning angle during large-angle two-dimensional scanning of the antenna array surface and improve the beam pointing accuracy. To solve this problem, it is necessary to perform delay compensation on the received and transmitted signals of the phased array antenna. A numerically controlled delay line is a commonly used microwave passive two-port device, and its main function is to make the electromagnetic wave delay for a constant time when transmitting between the two ports to compensate for the phase difference caused by different frequencies. It has a wide range of applications in many fields, such as satellite communication, antenna systems, and phased array antenna arrays. The delay line is mainly used to compensate for the beam spatial pointing dispersion caused by broadband large-angle scanning, and when processing broadband and ultra-wideband array signals, the time delay difference between the received and transmitted signals of each antenna element must be compensated to a reasonable range.

[0049] In a millimeter-wave (such as 32 - 40 GHz) system antenna, the millimeter-wave system antenna has the characteristics of small antenna aperture, small volume, light weight, and high spatial resolution, and has strong penetration and anti-crosstalk capabilities. Due to the small wavelength of millimeter waves, the millimeter-wave antenna can identify very small targets or multi-targets. However, due to technical difficulties, the development of millimeter-wave antennas has been restricted for a while. These technical difficulties mainly lie in: as the operating frequency increases, the output power and efficiency of the power source decrease, the losses of the receiving link devices and transmission lines increase, and higher requirements are also put forward for the insertion loss of the delay line chip. As an important device in the radio frequency transceiver delay module (T / R delay module), high-frequency signals in the millimeter-wave band are prone to attenuation, and if traditional delay lines are still used, it will cause extremely large losses.

[0050] Therefore, to solve the problem that traditional delay lines have extremely high losses in the millimeter-wave band, it is difficult to develop the application of millimeter-wave system antennas, and thus cannot meet the actual application requirements, the present invention proposes the following concept:

[0051] First of all, for traditional delay lines, it is necessary to find out the reasons for their large losses and which components in the circuit structure will cause the loss to increase. Based on this idea, further study the circuit structure and working principle of traditional delay lines. The traditional low-frequency numerically controlled delay line consists of two groups of single-pole double-throw switches, a reference branch, and a delay network branch. As Figure 1 shown, it is the circuit structure of a group of single-pole double-throw switches of a traditional delay line. Each branch of the switch is composed of a first-stage series transistor and a second-stage parallel transistor, and the input port of the switch is connected to the radio frequency signal input (RF in) The output of the first branch (RFout1) can be connected to the reference branch, and the output of the second branch (RFout2) can be connected to the delay network branch. By controlling the conduction or cut-off of each triode on each branch, the input RF signal can be controlled to flow to RFout1 or RFout2. Each triode acts as a microwave switch. When the triode is conducting, it is equivalent to a small resistor; when the triode is cut off, it operates in a high-impedance state (cut-off state), and at this time, the triode is equivalent to a parallel structure of a high resistor and a small capacitor. If this digital control delay line is used in the millimeter wave band, when the switch is conducting, the equivalent resistance of the series-connected triodes increases, resulting in a relatively large switch insertion loss at high frequencies. Through experimental detection, it is found that the insertion loss of each single-pole double-throw switch at high frequencies is about 2 dB. A single-bit digital control delay line requires two single-pole double-throw switches, and the switch insertion loss is 4 dB. If it is a four-bit digital control delay line, 8 single-pole double-throw switches are required, and then the total switch insertion loss is as high as 16 dB. As Figure 2 shown, it is the equivalent circuit diagram of the basic unit of the delay constant-resistance network of the traditional delay line, including an inductor Ls and a capacitor C P and C g , the use of inductors and capacitors in this constant-resistance network reduces the size of the chip. However, as the frequency of the millimeter wave RF signal increases, the parasitic effects of the inductor and capacitor constant-resistance network used at low frequencies are serious at high frequencies, which will affect the insertion loss of the delay unit and increase the loss; and the frequency response is limited by the parameters of the capacitor and inductor, and the response bandwidth is narrow. For example, the parasitic parameters of the inductor and capacitor at high frequencies (such as the distributed capacitance of Ls, C P and C g 's equivalent series resistance) cause phase errors and losses, and the delay amount of the delay constant-resistance network will exacerbate beam dispersion as the frequency changes. For example, the delay amount of an 8λ (wavelength) delay line is 8×λ / 32 GHz at 32 GHz and 8×λ / 40 GHz at 40 GHz. Through experimental detection, the insertion loss of this delay constant-resistance network at high frequencies is 7.1 dB.

[0052] Based on the above problems, the solution proposed by the present invention mainly includes the following two aspects:

[0053] First aspect: Improve the structure of the single-pole double-throw switch to avoid the increase in equivalent resistance caused by the series connection of switches (triodes). A single-pole double-throw switch with a pure parallel structure is adopted. The circuit structure of the single-pole double-throw switch with a pure parallel structure is as Figure 3As shown, each branch uses two - stage parallel - connected triodes. A single - bit digital - controlled delay unit requires two groups of single - pole double - throw switches with a pure parallel structure. In this way, whether the digital - controlled delay unit is in the reference state or the delay state, the situation of triode series connection will not occur, avoiding the problem of increased equivalent resistance caused by the conduction of series - connected triodes, thereby reducing the switch insertion loss of the digital - controlled delay unit when used in millimeter - wave (i.e., high - frequency signals). After experimental verification, Figure 3 For this kind of single - pole double - throw switch with a pure parallel structure, the insertion loss of each group of switches at high frequencies is only 1 dB. Compared with the traditional single - pole double - throw switch with a series - parallel structure, the insertion loss can be reduced by half.

[0054] Secondly, for the improvement of the delay network unit, in the traditional constant - resistance network delay unit, parasitic inductance and capacitance will affect the insertion loss of the delay unit. In order to reduce the insertion loss, the delay unit in millimeter - wave uses a coplanar waveguide transmission line (Symmetric Coplanar Waveguide Transmission Line, CPWTL) to achieve the delay function. It has been experimentally proven that taking an 8λ (wavelength) delay line as an example, the insertion loss can be reduced from the original 7.1 dB loss to 5.7 dB.

[0055] Through the improvement of the switch component and the delay unit, the inventor of the present invention has greatly reduced the loss of the digital - controlled delay unit when used in the millimeter - wave band. Further, corresponding improvements are also made to other components in the delay - unit circuit, making the finally designed digital - controlled delay unit more widely applicable and having more excellent performance.

[0056] Next, the implementation of the present invention will be described in detail with specific drawings and experimental data:

[0057] Figure 4 is a schematic structural diagram of the digital - controlled delay unit provided by the embodiment of the present invention; referring to Figure 4 this digital - controlled delay unit includes: a first single - pole double - throw switch, a second single - pole double - throw switch, a delay unit, and a reference unit;

[0058] The first single - pole double - throw switch includes: two - stage parallel - connected triodes S1 and S2;

[0059] The second single - pole double - throw switch includes: two - stage parallel - connected triodes S3 and S4;

[0060] The drain of the triode S1 is connected to one end of the delay unit, and the other end of the delay unit is connected to the drain of the triode S3;

[0061] The drain of the triode S2 is connected to one end of the reference unit, and the other end of the reference unit is connected to the drain of the triode S4;

[0062] The drains of the triodes S1 and S2 are both connected to the RF signal input port;

[0063] The drains of the triodes S3 and S4 are both connected to the RF signal output port;

[0064] The sources of the triodes S1, S2, S3, and S4 are all grounded DC, and the gates are all connected to a voltage control unit to control the on and off of each triode by controlling the gate voltage, so that the delay element switches between the reference state and the delay state.

[0065] In this embodiment, the gates of the triodes S1, S2, S3, and S4 are all connected to a voltage control unit. The voltage control unit provides a control voltage (0V or -5V) for the gates of the triodes, and adjusts the channel conductivity between the source and the drain through the control voltage; when the gate control voltage is 0V, the channel between the source and the drain of the triode is conducting, and at this time the triode is in the on state; when the gate control voltage is -5V, the channel between the source and the drain of the triode is non-conducting, and at this time the triode is in the off state.

[0066] Specifically, as Figure 4 shown, the gate voltages of the triodes S1 and S3 are represented as the reverse terminal voltage V N , and the gate voltages of S2 and S4 are the forward terminal voltage V P . The RF signal is input into the circuit through the input port RF in . When V N = 0 and V P = -5, the triodes S1 and S3 are conducting, and S2 and S4 are off. At this time, the RF signal travels through the reference branch, and the digital control delay element is in the reference state; when V N = -5 and V P = 0, S1 and S3 are off, and S2 and S4 are conducting. The RF signal travels through the delay branch, and the digital control delay element is in the delay state; the RF signal passing through the delay branch or the reference branch finally outputs through the output port RF out .

[0067] In this embodiment, regardless of whether the digital control delay element is in the reference state or the delay state, the triodes are in a pure parallel structure. By using a single-pole double-throw switch with a pure parallel structure, the problem of excessive switch insertion loss caused by the large equivalent resistance due to the series connection of triodes is avoided, thereby greatly reducing the switch insertion loss of the delay element when used in the millimeter-wave band.

[0068] In a possible implementation manner, the triode is a GaAs PHEMT triode.

[0069] Specifically, the GaAs PHEMT transistor is a high-performance transistor made of GaAs material, with high electron mobility and low-noise characteristics. The GaAs PHEMT transistor operates in a passive mode. The source is usually in direct contact with the substrate (GaAs) and is grounded directly to provide an entry for electrons. The drain is symmetrically distributed with respect to the source to collect the electrons passing through the channel. The gate is located at the middle position between the source and the drain. The control voltage (0V or -5V) is connected through a metallization layer to adjust the channel conductivity. When the gate voltage is 0V, the transistor channel is turned on, equivalent to a low resistance (R≈10Ω), and the signal has low loss when passing through. When the gate voltage is -5V, the reverse bias voltage exceeds the pinch-off voltage (Vp≈-2V), the channel is pinched off, equivalent to a high resistance (R≈10kΩ) and a small capacitance (C≈0.2pF), highly isolating the signal.

[0070] In this embodiment, grounding the source of the GaAs PHEMT transistor can provide a low-impedance signal path, reduce reflection loss, and the symmetrical distribution of the drain and the source ensures balanced signal transmission. By controlling the gate voltage (0V / -5V) to control the on or off state of the transistor, low insertion loss control can be achieved, thus realizing the low-loss and high-isolation performance of the switch in the millimeter wave band.

[0071] Figure 5 It is a schematic structural diagram of a numerically controlled delay line provided by another embodiment of the present invention.

[0072] In a possible implementation, the delay unit includes a coplanar waveguide transmission line, and the delay amount of the radio frequency signal is positively correlated with the physical path length of the coplanar waveguide transmission line.

[0073] In this embodiment, as shown in Figure 5, a coplanar waveguide transmission line CPWTL is used to achieve delay, and the delay is directly realized through the physical path length of the transmission line. The structural composition of the coplanar waveguide transmission line CPWTL includes: a center conductor, a ground plane, a dielectric layer, and an air bridge.

[0074] In a possible implementation, the center conductor is a rectangular metal strip with a width W = 50μm; the ground plane is a symmetric metal layer on both sides, and the distance between the metal layers on both sides from the center conductor is 25μm; the dielectric layer is a GaAs substrate with a thickness of 635μm, and the relative dielectric constant ε r = 12.9; the air bridge connects the upper and lower metal layers to avoid short circuits.

[0075] Exemplarily, the physical length of a 1λ delay line corresponds to one wavelength, and the physical length of an 8λ delay line is 8 × wavelength. When the frequency f = 36GHz, the wavelength corresponding to 1λ is: The physical length L of the 8λ delay line = 8 × 8.33 = 66.6mm.

[0076] In a possible implementation, the delay amount of the radio frequency signal where L represents the physical path length of the coplanar propagation wire, ε r represents the relative dielectric constant of the medium of the coplanar propagation wire, and c represents the speed of light.

[0077] When designing the chip layout, the coplanar waveguide transmission line can reduce its size by folding the path.

[0078] In this embodiment, the loss of the coplanar waveguide transmission line is mainly conductor loss (copper loss) and dielectric loss. At 36 GHz, the loss per centimeter of the transmission line is about 0.1 dB, and the loss is relatively low. By adopting this distributed parameter design of the coplanar waveguide transmission line instead of the traditional constant resistance delay network, the parasitic effects of capacitance and inductance are avoided, the insertion loss of the delay unit is reduced, and a wideband response is supported in the 32 - 40 GHz millimeter wave band.

[0079] In a possible implementation, a high - low impedance microstrip line is used to connect the drains of the triode S1 and the triode S2 to the radio frequency signal input port.

[0080] In this embodiment, since the switch is a pure parallel structure, it is difficult to match the input circuit. Therefore, a high - low impedance microstrip line is used to achieve the input matching of the switch circuit to optimize the signal transmission efficiency and reduce the return loss.

[0081] Exemplarily, the width of the high - impedance line is 10 μm and the characteristic impedance is 100 Ω; the width of the low - impedance line is 50 μm and the characteristic impedance is 50 Ω.

[0082] In a possible implementation, the impedance transformation method of the microstrip line can be but is not limited to 50 Ω → 100 Ω → 50 Ω to achieve wide - band matching.

[0083] In this embodiment, by designing the high - low impedance microstrip line to match the input and output impedances of the parallel switch, in the 32 - 40 GHz band, the return loss can be improved from - 10 dB to - 15 dB, reducing the reflection loss, optimizing the signal transmission efficiency, and achieving wide - band and low - loss matching in the millimeter wave band through the distributed parameter design.

[0084] As Figure 5 shown, in a possible implementation, the reference unit includes: a Π - type attenuation equalization network;

[0085] The Π - type attenuation equalization network includes: resistor R1, resistor R2, and resistor R3;

[0086] One end of the resistor R1 is connected to the drain of the triode S2, and the other end is connected to the drain of the triode S4;

[0087] One end of the resistor R2 is connected to one end of the resistor R1, one end of the resistor R3 is connected to the other end of the resistor R1, and the other ends of the resistors R2 and R3 are grounded respectively.

[0088] Exemplarily, R1 = 50Ω, R2 = 100Ω, R3 = 100Ω.

[0089] In this embodiment, by adding a Π-type attenuation equalization network to the reference branch, the transmission line loss in the high-frequency band can be compensated, the amplitude response can be stabilized, so that the amplitude fluctuation of the delay line in the 32 - 40 GHz frequency band is reduced from ±1.2 dB to ±0.5 dB.

[0090] In a possible implementation manner, the gates of the triodes S1, S2, S3, and S4 are all connected to the voltage control unit through isolation resistors.

[0091] As Figure 5 shown, the gates of all triodes are connected to an isolation resistor Rg, and Rg is at least 1.5 kΩ, which is used to isolate the radio frequency signal from the control circuit.

[0092] In a possible implementation manner, as Figure 6 shown, the digital control delay line further includes: a control logic unit;

[0093] The control logic unit is connected to the gates of the triodes S1, S2, S3, and S4, and is used to control the gate voltages of the triodes S1, S2, S3, and S4 to be 0V or -5V respectively according to a preset truth table.

[0094] In a possible implementation manner, the control logic unit is connected to the gates of the four triodes through metal wires. The control logic unit receives digital signals, converts the digital signals into control signals according to the truth table and inputs them to the gates of the triodes. The corresponding relationship between the logical control and the control level in the truth table is shown in Table 1. When the value is 0, the corresponding control level is the low level -5V, which controls the triode to turn off; when the value is 1, the corresponding control level is the high level 0V, which controls the triode to turn on.

[0095] Table 1

[0096] Logical value Control level 0 -5V 1 0V

[0097] In this embodiment, digital control of the delay line is realized through the control logic unit, and the stability is high.

[0098] It should be noted that the digital controlled delay line in the above embodiments is a single-bit digital controlled delay line. The delay amount that the single-bit digital controlled delay line can achieve is determined by the length of the coplanar waveguide transmission line of the delay unit. Digital controlled delay lines with various delay amounts such as 1λ digital controlled delay line, 2λ digital controlled delay line, 3λ digital controlled delay line, 4λ digital controlled delay line, 8λ digital controlled delay line, etc. can all be achieved by changing the length of the coplanar waveguide transmission line.

[0099] In this embodiment, by adopting a single-pole double-throw switch with a two-stage pure parallel structure and using high-low impedance microstrip lines to achieve the matching of the switch circuit, the insertion loss of a group of single-pole double-throw switches finally designed is only 1 dB, (the insertion loss of the traditional series-parallel structure single-pole double-throw switch is 2 dB). For a four-bit digital controlled delay line, 8 single-pole double-throw switches are required, and the switch insertion loss can be reduced from 16 dB to 8 dB. By detecting the insertion losses of the two types of switches through experiments, the comparison curves of the insertion losses of the two types of switches finally obtained are as Figure 8 shown. The red curve is the insertion loss curve of the traditional series-parallel structure single-pole double-throw switch. From the red curve, it can be seen that the minimum insertion loss of the traditional series-parallel structure single-pole double-throw switch is 1.5 dB in the 25 - 45 GHz frequency band, and as the frequency increases, the insertion loss becomes larger and larger, and the average insertion loss is about 2 dB; the blue curve is the insertion loss curve of the pure parallel structure single-pole double-throw switch designed by the present invention. It can be seen that in the entire 25 - 45 GHz frequency band, the insertion loss changes very little. Especially in the millimeter wave 32 - 40 GHz frequency band, the insertion loss is almost stable at 1 dB.

[0100] Furthermore, in this embodiment, by adopting a coplanar waveguide transmission line as the delay unit, compared with the traditional constant-resistance delay network unit, the insertion loss of the delay unit is reduced. Taking the 8-wavelength delay line as an example, the insertion loss is reduced from the original 7.1 dB loss to 5.7 dB. The comparison curves of the 8λ-bit insertion losses of the two types of delay units are as Figure 9 shown. The blue curve is the insertion loss curve of the traditional constant-resistance delay network unit, and the red curve is the insertion loss curve of the coplanar waveguide transmission line designed by the present invention. It can be seen that in the entire 25 - 45 GHz frequency band, the insertion loss of the constant-resistance delay network unit is higher than that of the coplanar waveguide transmission line.

[0101] Figure 7 is the structural schematic diagram of the four-bit digital controlled delay line provided by the embodiment of the present invention.

[0102] Based on the single-bit digital controlled delay line in the above embodiments, in this embodiment, a four-bit digital controlled delay line is obtained by cascading four single-bit digital controlled delay lines.

[0103] In a possible implementation, four numerically controlled delay elements are connected in a cascaded manner: the RF output port of the previous numerically controlled delay element is connected to the RF input port of the next numerically controlled delay element;

[0104] Among them, the step value of the four-bit numerically controlled delay element is 1λ, where λ is the wavelength of the RF signal, and the delay amount implemented by the delay unit of each numerically controlled delay element is 2 n λ, and the values of n are 0, 1, 2, and 3 respectively.

[0105] As Figure 7 shown, the four numerically controlled delay elements are respectively denoted as T1, T2, T3, and T4. The four numerically controlled delay elements are respectively provided with coplanar waveguide transmission lines of different lengths. The delay unit of T1 implements a 1λ delay, the delay unit of T2 implements a 2λ delay, the delay unit of T3 implements a 4λ delay, and the delay unit of T4 implements an 8λ delay. With a 1λ step for four bits, the control logic unit receives a four-bit digital signal (0000 - 1111), selects a delay amount (0 - 15λ) according to the digital signal, and then converts the 4-bit digital signal into 8 groups of control signals according to the truth table to respectively control the gate voltages of 8 single-pole double-throw switches, that is, V N1 、V N2 、V N3 、V N4 、V P1 、V P2 、V P3 and V P4 levels, so as to control the corresponding numerically controlled delay element to be in the delay state or the reference state.

[0106] Exemplarily, if a 3λ delay is to be achieved, the input digital signal is determined to be (0011) through binary transformation. The control logic unit determines according to the truth table that T1 and T2 need to work in the delay state, and T3 and T4 need to work in the reference state, and then generates 8 groups of control signals which are respectively (00111100). The eight groups of control signals are respectively input to the ports V N1 、V N2 、V N3 、V N4 、V P1 、V P2 、V P3 and V P4 , and control the gate voltages V N1 、V N2 to be -5V, V P1 、V P2 to be 0V, V N3 、V N4 to be 0V, V P3 、V P4 to be -5V, so that the delay branches of T1 and T2 are superimposed, thereby achieving a 3λ delay.

[0107] In this embodiment, the control signal output by the control logic unit closely cooperates with other parts, collaborates with the pure parallel single-pole double-throw switch group to accurately control the signal path and ensure the accuracy of the delay; cooperates with the coplanar waveguide delay line to select a delay line with a corresponding length according to the required delay amount; and collaborates with the attenuation equalization network to ensure the stability of the signal amplitude while adjusting the delay. Moreover, this four-bit numerically controlled delay line supports numerically controlled delay functions with a minimum step of 1 times the wavelength (1λ) and a maximum delay of 15 times the wavelength (15λ). In a millimeter-wave system, the phase of the signal can be precisely adjusted through λ-level delay control, solving the problem of beam pointing dispersion during broadband large-angle scanning and improving the performance of the antenna system.

[0108] In a possible implementation manner, a manufacturing method of a numerically controlled delay line chip includes:

[0109] Set multiple groups of cascaded common-ground via isolation bands in the layout of the chip for electromagnetic space isolation;

[0110] Set filter capacitors on the DC transmission line to prevent digital noise coupling.

[0111] Specifically, electromagnetic compatibility issues should be fully considered in the layout. In the design, add isolation bands formed by multiple groups of cascaded common-ground vias to achieve electromagnetic space isolation and prevent signal crosstalk. At the same time, reduce the intersection of microwave transmission lines and DC transmission lines, and add filter capacitors on the DC transmission line to reduce the crosstalk coupling of external signals to the internal circuit. In the layout, first connect the RF transmission path, then connect the DC path, and finally make full use of the flexibility of the control terminal signal to layout the layout to achieve the control of the attenuator, significantly improving the efficiency of the layout.

[0112] Furthermore, the coplanar waveguide transmission line and the high-low impedance microstrip line in the numerically controlled delay line can both adopt a folded path design to reduce the size of the chip.

[0113] In a possible implementation manner, it is manufactured using GaAs PHEMT microwave monolithic integrated circuit process technology. The main process steps of the GaAs process include mesa isolation, ohmic contact, gate trenching and metallization, device passivation, metal lift-off, air bridge preparation, backside chemical thinning, via process, etc.

[0114] Furthermore, based on the four-bit numerically controlled delay line provided by the present invention, its performance is tested. The chip is tested using a microwave probe platform, and its performance is verified through experiments. Set the reference state and delay state of the four-bit numerically controlled delay line according to Table 1 of the truth table. The amplitude difference between the delay state and the reference state yields the amplitude fluctuation curve of the delay, and the phase difference between the delay state and the reference state is converted into the delay amount, that is, the delay error curve of the delay is obtained, etc. The performance test curve graph of the finally obtained four-bit numerically controlled delay line is asFigures 10 - 15 As shown Figure 10 is the insertion loss curve, where the abscissa is the millimeter-wave frequency (32 - 40 GHz) and the ordinate is the insertion loss (dB). Figure 11 is the amplitude fluctuation curve for each state, and the ordinate IL Vanation represents the amplitude fluctuation of the insertion loss. Figure 12 is the delay quantity curve. Figure 13 is the delay accuracy curve, and the ordinate TP error represents the delay quantity error. Figure 14 is the input voltage standing wave ratio curve for the reference state and the delayed state. Figure 15 is the output voltage standing wave ratio curve for the reference state and the delayed state.

[0115] According to Figures 10 - 15 the test results show that in the millimeter-wave frequency range of 32 GHz to 40 GHz, the insertion loss of the four-bit numerically controlled delay line is less than 15.8 dB, the insertion loss fluctuation is less than ±0.5 dB, the phase delay error is less than 25°, the delay accuracy is as high as 4‰, and the input and output standing waves in the full state are both less than 1.8 (close to ideal matching).

[0116] Through the above innovations in this embodiment, the finally obtained numerically controlled delay line realizes low-loss and high-precision delay in the millimeter-wave frequency band, providing key technical support for the next-generation wireless communication system.

[0117] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A numerical control time delay device, characterized in that, Comprising: A first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit, and a reference unit; The first single-pole double-throw switch comprises: two stages of parallel-connected triodes S1 and S2; The second single-pole double-throw switch comprises: two stages of parallel-connected triodes S3 and S4; The drain of the triode S1 is connected to one end of the delay unit, and the other end of the delay unit is connected to the drain of the triode S3; The drain of the triode S2 is connected to one end of the reference unit, and the other end of the reference unit is connected to the drain of the triode S4; The drains of the triode S1 and the triode S2 are both connected to the RF signal input port; The drains of the triode S3 and the triode S4 are both connected to the RF signal output port; The sources of the triodes S1, S2, S3, and S4 are all grounded directly, and the gates are all connected to a voltage control unit to control the on and off of each triode by controlling the gate voltage, so that the delay device switches between a reference state and a delay state.

2. The numerical control delay device according to claim 1, wherein The delay unit comprises a coplanar waveguide transmission line, and the delay amount of the RF signal is positively correlated with the physical path length of the coplanar waveguide transmission line.

3. The digital control delay device according to claim 2, wherein The delay amount of the radio frequency signal where L represents the physical path length of the coplanar propagation wire, ε r represents the relative dielectric constant of the medium of the coplanar propagation wire, and c represents the speed of light.

4. The numerical control delay device according to claim 1, wherein The drains of the triode S1 and the triode S2 are connected to the RF signal input port by a high-low impedance microstrip line.

5. The digital control delay device according to claim 1, wherein, The reference unit comprises: a Π-type attenuation equalization network; The Π-type attenuation equalization network comprises: a resistor R1, a resistor R2, and a resistor R3; One end of the resistor R1 is connected to the drain of the triode S2, and the other end is connected to the drain of the triode S4; One end of the resistor R2 is connected to one end of the resistor R1, one end of the resistor R3 is connected to the other end of the resistor R1, and the other ends of the resistor R2 and R3 are respectively grounded.

6. The CNC delay timer according to claim 1, characterized in that, Further comprising: A control logic unit; The control logic unit is connected to the gates of the triodes S1, S2, S3, and S4, and is used to respectively control the gate voltages of the triodes S1, S2, S3, and S4 to be 0V or -5V according to a preset truth table.

7. The digital control delay device according to claim 1, wherein The gates of the triodes S1, S2, S3, and S4 are all connected to the voltage control unit through isolation resistors.

8. The digital control delay device according to any one of claims 1-7, characterized in that, The triode is a GaAs PHEMT triode.

9. A four-digit numerically controlled delay device, characterized in that, Comprising four digital control delay devices according to any one of claims 1-8; Wherein, the four digital control delay devices are connected in a cascaded manner: the RF output port of the previous-stage digital control delay device is connected to the RF input port of the next-stage digital control delay device; Among them, the step value of the four-digit numerically controlled delay unit is 1λ, where λ is the wavelength of the radio frequency signal, and the delay amount realized by the delay unit of each numerically controlled delay unit is 2 n λ, and the values of n are 0, 1, 2, and 3 respectively.

10. A manufacturing method of a numerically controlled delay chip for a numerically controlled delay device according to any one of claims 1-8 or a four-bit numerically controlled delay device according to claim 9, characterized in that, Comprising: Setting multiple groups of cascaded common-ground via isolation bands in the layout of the chip to perform electromagnetic space isolation; Setting filter capacitors on the DC transmission line to prevent digital noise coupling.

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