Two-way voice simultaneous transmission wireless receiving and transmitting system

Abstract

The invention discloses a double-channel voice simultaneous transmission wireless transceiving system, which comprises a transmitting part and a receiving part, and is characterized in that the transmitting part comprises a low-frequency amplification circuit, a frequency synthesis oscillation circuit, a resonance hybrid circuit and an impedance matching transmitting circuit which are connected in sequence; the receiving part comprises a signal receiving circuit, a frequency modulation circuit, a frequency mixing and discriminating circuit and a power amplification circuit which are connected in sequence; the impedance matching transmitting circuit is in communication connection with the signal receiving circuit; the low-frequency amplification circuit is used for receiving double-path voice input signals, and the power amplification circuit is used for outputting double-path voice signals; the method has the advantages that the communication instantaneity is high, the spectrum utilization rate is high, and the communication efficiency is high.

Description

Technical Field

[0001] The present invention relates to the field of wireless transmission communication, and more particularly to a dual-channel voice simultaneous transmission wireless transceiver system. Background Art

[0002] With the development and progress of society, human activities increasingly rely on the services provided by wireless communication technologies. Wireless communication technologies have received great attention and developed rapidly due to their characteristics of being fast, convenient, and mobile. Among them, the wireless transmission of voice signals is a basic requirement. In the wireless transmission of ordinary voice signals, usually only one voice signal can be transmitted at a time, which greatly reduces the communication and exchange efficiency and timeliness in communication. Moreover, the traditional voice stereo wireless transmission scheme has a complex circuit and low spectrum utilization rate, and it is impossible to flexibly allocate the transmission frequency band. Therefore, there is an urgent need for a wireless transceiver system for dual-channel voice simultaneous transmission to solve the problems encountered in people's daily lives and improve the communication efficiency.

[0003] Chinese Patent Grant Publication No. CN210225414U discloses a wireless transceiver system for dual-channel voice simultaneous transmission, including a dual-channel voice wireless transmission device and a dual-channel voice wireless reception device. Two voice signals are input into the dual-channel voice wireless transmission device, and the dual-channel voice wireless transmission device combines the two signals into a combined signal, and wirelessly transmits the combined signal to the dual-channel voice wireless reception device after FM modulation. The dual-channel voice wireless reception device receives the FM signal sent by the transmission device, demodulates it to obtain the combined signal, and then separates the combined signal to obtain two voice signals. This system can transmit dual-channel voice signals with high quality, greatly improving the timeliness. Through the program digital control method of the microcontroller, it can flexibly allocate the occupied frequency band and modulation bandwidth, improving the spectrum utilization rate. The modulation and demodulation adopt the FM method, which has extremely high anti-interference characteristics and meets the requirements of dual-channel transmission of baseband voice signals. However, in this patent, voice signal A is input from the first multiplier, and voice signal B is input from the adder. The input interfaces of the two voice signals are different, which may cause the two voice signals to be input simultaneously but not output simultaneously, greatly reducing the communication and exchange efficiency and timeliness in communication. Moreover, it does not give a specific scheme for allocating the transmission frequency band, resulting in low spectrum utilization rate and low communication efficiency of the overall scheme. Summary of the Invention

[0004] The technical problem to be solved by the present invention is that the existing dual-channel voice wireless transceiver system has problems of low communication timeliness, low spectrum utilization rate, and low communication efficiency.

[0005] The present invention solves the above technical problems through the following technical means: A dual-channel simultaneous voice transmission wireless transceiver system includes a transmitting part and a receiving part. The transmitting part includes a low-frequency amplification circuit, a frequency synthesis oscillation circuit, a resonance mixing circuit, and an impedance matching transmitting circuit connected in sequence. The receiving part includes a signal receiving circuit, a frequency modulation circuit, a mixing and frequency discrimination circuit, and a power amplification circuit connected in sequence. The impedance matching transmitting circuit is communicatively connected to the signal receiving circuit. The low-frequency amplification circuit receives a dual-channel voice input signal, and the power amplification circuit outputs a dual-channel voice signal. Among them, the frequency synthesis oscillation circuit includes a resistor R11, a crystal oscillator JT1, and a diode VD1. One end of the resistor R11 is connected to the low-frequency amplification circuit, and the other end of the resistor R11 is respectively connected to one end of the crystal oscillator JT1 and the cathode of the diode VD1. The other end of the crystal oscillator JT1 and the anode of the diode VD1 are both connected to the resonance mixing circuit.

[0006] In the present invention, the low-frequency amplification circuit receives a dual-channel voice input signal, and the power amplification circuit outputs a dual-channel voice signal. The input ends of the two voice signals are the same, and the two voice signals are input simultaneously. After being processed by the transmitting part and the receiving part, stable dual-channel voice signals are output, and the communication instantaneity is relatively high. Two different frequencies are modulated by the frequency synthesis oscillation circuit and respectively loaded onto the dual-channel voice input signals to increase the frequency of the voice signals, which is convenient for signal transmission, has a high spectrum utilization rate, and a relatively high communication efficiency.

[0007] Further, the low-frequency amplification circuit includes a capacitor C1, a capacitor C2, a capacitor C3, resistors R1 to R4 with sequential numbers, a microphone MK1, a resistor R9, a resistor R10, a resistor R12, a capacitor C13, a capacitor C14, a capacitor C6, a triode VT4, and a triode VT5. The microphone MK1 receives two amplitude-modulated dual-channel voice input signals. One end of the microphone MK1 is respectively connected to one end of the capacitor C13 and one end of the resistor R1. The other end of the capacitor C13 is respectively connected to one end of the resistor R9 and the base of the triode VT4. The other end of the resistor R9, one end of the resistor R2, the collector of the triode VT4, and one end of the capacitor C14 are connected. The other end of the capacitor C14 is respectively connected to one end of the resistor R10 and the base of the triode VT5. The other end of the resistor R10, one end of the resistor R3, the positive electrode of the capacitor C6, and the collector of the triode VT5 are connected. The negative electrode of the capacitor C6 is connected to the frequency synthesis oscillation circuit. One end of the resistor R12, the emitter of the triode VT5, the emitter of the triode VT4, and the other end of the microphone MK1 are connected and grounded. The other end of the resistor R12 is connected to one end of the resistor R4. The other ends of the resistors R1 to R4, the positive electrode of the capacitor C1, the positive electrode of the capacitor C2, and one end of the capacitor C3 are all connected. One end of the capacitor C3 is connected to the resonance mixing circuit. The negative electrode of the capacitor C1, the negative electrode of the capacitor C2, and the other end of the capacitor C3 are grounded. One end of the resistor R11 is connected to the negative electrode of the capacitor C6.

[0008] Further, the resonant hybrid circuit includes a resistor R6, a capacitor C4, an inductor L1, a resistor R7, a capacitor C5, an inductor L2, a capacitor C7, an inductor L3, transistors VT1 to VT3 with sequential numbers, a capacitor C12, a capacitor C15, resistors R14 to R17 with sequential numbers, a capacitor C20, a capacitor C21, and a capacitor C22. One end of the resistor R6, one end of the resistor R14, one end of the capacitor C15, and the base of the transistor VT1 are connected and connected to the other end of the crystal oscillator JT1; the collector of the transistor VT1, one end of the capacitor C4, one end of the inductor L1, and one end of the capacitor C12 are connected; the emitter of the transistor VT1, the other end of the capacitor C15, one end of the resistor R15, and one end of the capacitor C20 are connected; the other end of the capacitor C12, one end of the resistor R7, one end of the resistor R16, one end of the capacitor C21, and the base of the transistor VT2 are connected; the collector of the transistor VT2, one end of the capacitor C5, one end of the inductor L2, and one end of the capacitor C7 are connected; the other end of the capacitor C7, one end of the resistor R17, one end of the capacitor C22, and the base of the transistor VT3 are connected; the collector of the transistor VT3 is connected to one end of the inductor L3; the other ends of the resistors R14 to R17, the other end of the capacitor C20, the other end of the capacitor C21, the other end of the capacitor C22, and the emitter of the transistor VT3 are all connected together; the other end of the resistor R6, the other end of the capacitor C4, the other end of the inductor L1, the other end of the resistor R7, the other end of the capacitor C5, the other end of the inductor L2, and the other end of the inductor L3 are all connected together, and the other end of the inductor L3 and the emitter of the transistor VT3 are both connected to the impedance matching transmission circuit.

[0009] Further, the impedance matching transmission circuit includes capacitors C8 to C11 with sequential numbers, an inductor L4, an inductor L5, an inductor L6, a resistor R8, capacitors C16 to C19 with sequential numbers, an indicator lamp LED1, and an antenna E1. One end of the capacitor C8 is connected to one end of the inductor L3; the other end of the capacitor C8, one end of the inductor L4, and one end of the capacitor C16 are connected; the other end of the inductor L4 is connected to one end of the capacitor C9; the other end of the capacitor C9, one end of the inductor L5, and one end of the capacitor C17 are connected; the other end of the inductor L5, one end of the inductor L6, and one end of the capacitor C18 are connected; the other end of the inductor L6, the antenna E1, and one end of the capacitor C19 are connected; one end of the resistor R8, the positive electrode of the capacitor C10, and one end of the capacitor C11 are all connected to the other end of the inductor L3 and connected to the power supply +6V; the other end of the resistor R8 is connected to the anode of the indicator lamp LED1, and the emitter of the transistor VT3, the other ends of the capacitors C16 to C19, the cathode of the indicator lamp LED1, the negative electrode of the capacitor C10, and the other end of the capacitor C11 are all connected and grounded.

[0010] Further, the signal receiving circuit includes antenna E2, capacitors C31 to C36 with sequential numbers, transformer T3, resistors R31 to R35 with sequential numbers, triode VT6, and triode VT7. One end of antenna E2 is connected to one end of capacitor C31. The other end of capacitor C31, one end of capacitor C32, and the same-name end of the primary coil of transformer T3 are connected. The other end of capacitor C32 is connected to the different-name end of the primary coil of transformer T3. One end of capacitor C33 is connected to the same-name end of the secondary coil of transformer T3. The other end of capacitor C33, one end of resistor R31, and the base of triode VT6 are connected. The other end of resistor R31, the collector of triode VT6, the emitter of triode VT7, one end of capacitor C35, one end of resistor R33, and one end of resistor R35 are connected. The emitter of triode VT6, one end of capacitor C34, and one end of resistor R32 are connected. The collector of triode VT7 is connected to one end of resistor R34. A capacitor C36 is connected between the other end of resistor R34 and the other end of resistor R35. The other end of resistor R34 and the other end of resistor R35 are both connected to the frequency modulation circuit. The different-name end of the secondary coil of transformer T3, the other end of capacitor C34, the other end of resistor R32, the other end of capacitor C35, and the other end of resistor R33 are all connected and grounded.

[0011] Further, the frequency modulation circuit includes transformer T2, chip U1, capacitor C37, resistor R36, capacitor C49, crystal oscillators JT3 to JT6 with sequential numbers, capacitors C39 to C42 with sequential numbers, resistor R61, resistor R41, resistor R44, and capacitor C51. The same-name end of the primary coil of transformer T2 is connected to the other end of resistor R34. The different-name end of the primary coil of transformer T2 is connected to the other end of resistor R35. The same-name end of the secondary coil of transformer T2 is connected to the first pin of chip U1. The different-name end of the secondary coil of transformer T2 is connected to the thirteenth pin of chip U1. One end of capacitor C42 is connected to the second pin of chip U1. The other end of capacitor C42 is grounded. One end of crystal oscillator JT4 is connected to the seventh pin of chip U1. The other end of crystal oscillator JT4, the sixth pin of chip U1, and the eighth pin of chip U1 are all connected. One end of resistor R41 is connected to one end of crystal oscillator JT4. The other end of resistor R41 is connected to the tenth pin of chip U1. One end of capacitor C51 is connected to the eleventh pin of chip U1. The other end of capacitor C51 is connected to the twelfth pin of chip U1.

[0012] One end of capacitor C37, one end of resistor R36, one end of capacitor C49, and the fifteenth pin of chip U1 are connected; the other end of capacitor C49, one end of crystal oscillator JT3, and the sixteenth pin of chip U1 are connected; one end of crystal oscillator JT6 is connected to the eighteenth pin of chip U1, and the other end of crystal oscillator JT6, the seventeenth pin of chip U1, and the nineteenth pin of chip U1 are connected; one end of capacitor C40 is connected to the twenty-first pin of chip U1, and the other end of capacitor C40, one end of capacitor C39, and the twentieth pin of chip U1 are connected; one end of capacitor C41, the twenty-second pin of chip U1, and one end of potentiometer R62 are connected; one end of resistor R61 is connected to the twenty-third pin of chip U1, one end of crystal oscillator JT5, and one end of resistor R44 are both connected to the twenty-fourth pin of chip U1; the other ends of capacitor C37, resistor R36, crystal oscillator JT3, the eighteenth pin of chip U1, the other end of capacitor C39, the other end of capacitor C41, the other end of potentiometer R62, the control terminal of potentiometer R62, the other end of resistor R61, the other end of crystal oscillator JT5, and the other end of resistor R44 are all connected to the neutral point of the primary coil of transformer T2.

[0013] Further, the model of the chip U1 is MC3362.

[0014] Further, the mixing and frequency discrimination circuit includes a transformer T1, a resistor R38, a capacitor C43, a triode VT8, a capacitor C46, a resistor R63, a capacitor C64, a crystal oscillator JT2, a resistor R39, a capacitor C68, a variable capacitor C48, a capacitor C44, a capacitor C61 and a capacitor C62. The homonymous end of the primary coil of the transformer T1 is connected to the fourth pin of the chip U1, and the heteronymous end of the primary coil of the transformer T1 is connected to the third pin of the chip U1. The homonymous end of the secondary coil of the transformer T1, one end of the resistor R38, one end of the capacitor C43, one end of the resistor R39 and one end of the capacitor C44 are connected. The other end of the capacitor C44 is grounded, and the other end of the capacitor C43 is connected to the heteronymous end of the secondary coil of the transformer T1. The collector of the triode VT8 is connected to the neutral point of the secondary coil of the transformer T1. The emitter of the triode VT8, one end of the capacitor C46, one end of the resistor R63 and one end of the capacitor C64 are connected. The other end of the capacitor C64, the base of the triode VT8, one end of the crystal oscillator JT2 and the other end of the resistor R39 are connected; the other end of the crystal oscillator JT2, one end of the capacitor C68 and one end of the variable capacitor C48 are connected. The other end of the capacitor C46, the other end of the resistor R63, the other end of the capacitor C68 and the other end of the variable capacitor C48 are connected and grounded; the other end of the resistor R38, the seventh pin of the chip U1, the positive electrode of the capacitor C61 and one end of the capacitor C62 are all connected to the neutral point of the primary coil of the transformer T2. The negative electrode of the capacitor C61 and the other end of the capacitor C62 are connected and grounded.

[0015] Further, the power amplifier circuit includes a chip U2 and capacitors C55 to C58 numbered in sequence. The sixth pin of the chip U2 is connected to the twenty-third pin of the chip U1, and the eighth pin of the chip U2 is grounded; the third pin of the chip U2, one end of the capacitor C62, the positive electrode of the capacitor C57 and one end of the capacitor C58 are connected and connected to the power supply +6V. The negative electrode of the capacitor C57 and the other end of the capacitor C58 are connected and grounded. The positive electrode of the capacitor C55 is connected to the fourth pin of the chip U2, the negative electrode of the capacitor C55 is grounded, and both ends of the capacitor C56 are connected to two filters. The output ends of the two filters are respectively connected to a speaker, and the two speakers respectively output a voice signal.

[0016] Further, the model of the chip U2 is LM386.

[0017] The advantages of the present invention are as follows:

[0018] (1) The low-frequency amplification circuit of the present invention receives a dual-channel voice input signal, and the power amplification circuit outputs a dual-channel voice signal. The input ends of the two voice signals are the same, and the two voice signals are input simultaneously. After being processed by the transmitting part and the receiving part, two stable voice signals are output, with high communication instantaneity. Two different frequencies are modulated by the frequency synthesis oscillator circuit and respectively loaded onto the dual-channel voice input signal to increase the frequency of the voice signal, facilitate signal transmission, have a high spectrum utilization rate, and a high communication efficiency.

[0019] (2) The low-frequency amplification circuit of the present invention amplifies the weak voice signal captured by the microphone and then inputs it to the next stage, ensuring that the amplified signal is distortion-free during the amplification process.

[0020] (3) In the resonant mixing circuit of the present invention, the triode VT1 and the capacitor C4 select the third harmonic frequency. The triode VT2 and the capacitor C5 etc. form a class C amplifier to amplify the signal, and the triode VT3 and the inductor L3 form a buffer amplification circuit to buffer and amplify the signal.

[0021] (4) The impedance matching transmitting circuit of the present invention filters out small-signal interference through successive filtering. The Π-type impedance matching network minimizes the input impedance so that the antenna can obtain the maximum output power and greatly reduces the antenna radiation loss.

[0022] (5) The tiny signal received by the signal receiving circuit of the present invention is a high-frequency small signal. The transformer T3 and the capacitor C32 form a frequency selection circuit to select the required frequency for reception, exclude signals of other frequency bands received by the antenna, make the resonant frequency of the circuit consistent with the received signal frequency, reduce interference from other signals, and the triodes VT6 and VT7 form a two-stage amplification circuit to amplify the received signal and input it to the next stage.

[0023] (6) The frequency modulation circuit of the present invention uses the chip U1 to generate a local oscillation consistent with the internal frequency of the transmitting part, facilitating the demodulation of high-frequency small signals.

[0024] (7) The mixing and frequency discrimination circuit of the present invention separates the intermediate signals through circuit mixing and frequency discrimination, facilitating the power amplification of the signals by the subsequent stage and then restoring the voice signals, preventing signal overlap and avoiding inaccurate output results.

[0025] (8) The power amplification circuit of the present invention amplifies the already separated signals output by the mixing and frequency discrimination circuit through power amplification, increases the output current, and filters out the two different frequencies of the signals loaded onto the dual-channel voice input signal by connecting two filters at the output end, restores the original dual-channel voice signals, and outputs the voice signals through the speakers respectively. Description of the Drawings

[0026] Figure 1Block diagram of the transmitting part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0027] Figure 2 Block diagram of the receiving part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of the low-frequency amplification circuit in the transmitting part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of the frequency synthesis oscillation circuit in the transmitting part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of the resonance hybrid circuit in the transmitting part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0031] Figure 6 Schematic diagram of the impedance matching transmitting circuit in the transmitting part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0032] Figure 7 Schematic diagram of the signal receiving circuit in the receiving part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0033] Figure 8 Schematic diagram of the frequency modulation circuit in the receiving part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0034] Figure 9 Schematic diagram of the mixing and frequency discrimination circuit in the receiving part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention;

[0035] Figure 10 Schematic diagram of the power amplification circuit in the receiving part of a dual-channel simultaneous voice interpretation wireless transceiver system disclosed in an embodiment of the present invention. Detailed implementation manners

[0036] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] Such as Figure 1 AndFigure 2 As shown in the figure, a dual-channel simultaneous interpretation wireless transceiver system includes a transmitting part and a receiving part. The transmitting part includes a low-frequency amplification circuit 1, a frequency synthesis oscillation circuit 2, a resonance mixing circuit 3, and an impedance matching transmitting circuit 4 connected in sequence. The receiving part includes a signal receiving circuit 5, a frequency modulation circuit 6, a mixing and frequency discrimination circuit 7, and a power amplification circuit 8 connected in sequence. The impedance matching transmitting circuit 4 is communicatively connected to the signal receiving circuit 5. The low-frequency amplification circuit 1 receives a dual-channel voice input signal, and the power amplification circuit 8 outputs a dual-channel voice signal.

[0038] As Figure 3 shown in the figure, the low-frequency amplification circuit 1 includes a capacitor C1, a capacitor C2, a capacitor C3, resistors R1 to R4 numbered in sequence, a microphone MK1, a resistor R9, a resistor R10, a resistor R12, a capacitor C13, a capacitor C14, a capacitor C6, a triode VT4, and a triode VT5. The microphone MK1 receives two channels of amplitude-modulated dual-channel voice input signals. The front end of the microphone MK1 can be connected to a 30KHZ amplitude modulation circuit and a 40KHZ amplitude modulation circuit. The dual-channel voice signals after amplitude modulation are then transmitted to the low-frequency amplification circuit 1 through the microphone MK1. One end of the microphone MK1 is respectively connected to one end of the capacitor C13 and one end of the resistor R1. The other end of the capacitor C13 is respectively connected to one end of the resistor R9 and the base of the triode VT4. The other end of the resistor R9, one end of the resistor R2, the collector of the triode VT4, and one end of the capacitor C14 are connected. The other end of the capacitor C14 is respectively connected to one end of the resistor R10 and the base of the triode VT5. The other end of the resistor R10, one end of the resistor R3, the positive electrode of the capacitor C6, and the collector of the triode VT5 are connected. The negative electrode of the capacitor C6 is connected to the frequency synthesis oscillation circuit 2. One end of the resistor R12, the emitter of the triode VT5, the emitter of the triode VT4, and the other end of the microphone MK1 are connected and grounded. The other end of the resistor R12 is connected to one end of the resistor R4. The other ends of the resistors R1 to R4, the positive electrode of the capacitor C1, the positive electrode of the capacitor C2, and one end of the capacitor C3 are all connected. One end of the capacitor C3 is connected to the resonance mixing circuit 3. The negative electrode of the capacitor C1, the negative electrode of the capacitor C2, and the other end of the capacitor C3 are grounded. The triodes VT4 and VT5 amplify the input voice signals in two stages. Among them, resistors and capacitors form a filter circuit to ensure the stability of signal transmission and filter out signal interference.

[0039] As Figure 4As shown, the frequency synthesis oscillator circuit 2 includes a resistor R11, a crystal oscillator JT1, and a diode VD1. One end of the resistor R11 is connected to the negative electrode of a capacitor C6, and the other end of the resistor R11 is respectively connected to one end of the crystal oscillator JT1 and the cathode of the diode VD1. The other end of the crystal oscillator JT1 and the anode of the diode VD1 are both connected to the resonance hybrid circuit 3. The frequency of the crystal oscillator JT1 is one-third of 48.5 MHZ. The frequency synthesis oscillator circuit 2 modulates two different frequencies and respectively loads them onto the dual-channel voice input signals to increase the voice signal frequency and facilitate signal transmission.

[0040] As Figure 5As shown, the resonant hybrid circuit 3 includes a resistor R6, a capacitor C4, an inductor L1, a resistor R7, a capacitor C5, an inductor L2, a capacitor C7, an inductor L3, transistors VT1 to VT3 numbered in sequence, a capacitor C12, a capacitor C15, resistors R14 to R17 numbered in sequence, a capacitor C20, a capacitor C21, and a capacitor C22. One end of the resistor R6, one end of the resistor R14, one end of the capacitor C15, and the base of the transistor VT1 are connected and connected to the other end of the crystal oscillator JT1; the collector of the transistor VT1, one end of the capacitor C4, one end of the inductor L1, and one end of the capacitor C12 are connected; the emitter of the transistor VT1, the other end of the capacitor C15, one end of the resistor R15, and one end of the capacitor C20 are connected; the other end of the capacitor C12, one end of the resistor R7, one end of the resistor R16, one end of the capacitor C21, and the base of the transistor VT2 are connected; the collector of the transistor VT2, one end of the capacitor C5, one end of the inductor L2, and one end of the capacitor C7 are connected; the other end of the capacitor C7, one end of the resistor R17, one end of the capacitor C22, and the base of the transistor VT3 are connected; the collector of the transistor VT3 is connected to one end of the inductor L3; the other ends of the resistors R14 to R17, the other end of the capacitor C20, the other end of the capacitor C21, the other end of the capacitor C22, and the emitter of the transistor VT3 are all connected together; the other end of the resistor R6, the other end of the capacitor C4, the other end of the inductor L1, the other end of the resistor R7, the other end of the capacitor C5, the other end of the inductor L2, and the other end of the inductor L3 are all connected together; the other end of the inductor L3 and the emitter of the transistor VT3 are both connected to the impedance matching transmission circuit 4. The transistor VT1 and the capacitor C4 etc. form a frequency doubling circuit to select the triple frequency of the resonant hybrid circuit 3. The transistor VT2 and the capacitor C5 etc. form a class C amplifier for power amplification. The transistor VT3 and the inductor L3 etc. form a buffer amplifier circuit to further buffer and amplify the signal. In this way, the signal after being amplified step by step can meet the radiation frequency of the antenna, enabling the antenna E2 of the receiving part to receive the signal transmitted by the transmitting part. Without signal amplification, the signal is too weak, and considering the certain distance between the transmitting part and the receiving part during the transmission process, it is very easy for the receiving part to have difficulty receiving the voice signal.

[0041] As Figure 6As shown, the impedance matching transmitting circuit 4 includes capacitors C8 to C11 numbered in sequence, inductor L4, inductor L5, inductor L6, resistor R8, capacitors C16 to C19 numbered in sequence, indicator lamp LED1, and antenna E1. One end of capacitor C8 is connected to one end of inductor L3, and the other end of capacitor C8, one end of inductor L4, and one end of capacitor C16 are connected. The other end of inductor L4 is connected to one end of capacitor C9, and the other end of capacitor C9, one end of inductor L5, and one end of capacitor C17 are connected. The other end of inductor L5, one end of inductor L6, and one end of capacitor C18 are connected. The other end of inductor L6, antenna E1, and one end of capacitor C19 are connected. One end of resistor R8, the positive electrode of capacitor C10, and one end of capacitor C11 are all connected to the other end of inductor L3 and connected to the power supply +6V. The other end of resistor R8 is connected to the anode of indicator lamp LED1. The emitter of triode VT3, the other ends of capacitors C16 to C19, the cathode of indicator lamp LED1, the negative electrode of capacitor C10, and the other end of capacitor C11 are all connected and grounded. The impedance matching transmitting circuit 4 filters out small-signal interference through step-by-step filtering. The Π-type impedance matching network minimizes the input impedance, so as to facilitate the antenna to obtain the maximum output power and greatly reduce the antenna radiation loss.

[0042] As Figure 7As shown, the signal receiving circuit 5 includes antenna E2, capacitors C31 to C36 with sequential numbers, transformer T3, resistors R31 to R35 with sequential numbers, triode VT6, and triode VT7. One end of antenna E2 is connected to one end of capacitor C31. The other end of capacitor C31, one end of capacitor C32, and the same-named end of the primary coil of transformer T3 are connected. The other end of capacitor C32 is connected to the opposite-named end of the primary coil of transformer T3. One end of capacitor C33 is connected to the same-named end of the secondary coil of transformer T3. The other end of capacitor C33, one end of resistor R31, and the base of triode VT6 are connected. The other end of resistor R31, the collector of triode VT6, the emitter of triode VT7, one end of capacitor C35, one end of resistor R33, and one end of resistor R35 are connected. The emitter of triode VT6, one end of capacitor C34, and one end of resistor R32 are connected. The collector of triode VT7 is connected to one end of resistor R34. A capacitor C36 is connected between the other end of resistor R34 and the other end of resistor R35. Both the other end of resistor R34 and the other end of resistor R35 are connected to the frequency modulation circuit 6. The opposite-named end of the secondary coil of transformer T3, the other end of capacitor C34, the other end of resistor R32, the other end of capacitor C35, and the other end of resistor R33 are all connected and grounded. The tiny signal received by the signal receiving circuit 5 is a high-frequency small signal. Transformer T3 and capacitor C32 form a frequency selection circuit to select the required frequency for reception, exclude signals of other frequency bands received by the antenna, make the circuit resonance frequency consistent with the received signal frequency, reduce interference from other signals. Triode VT6 and triode VT7 form a two-stage amplification circuit to amplify the received signal and input it to the next stage.

[0043] As Figure 8As shown, the frequency modulation circuit 6 includes a transformer T2, a chip U1, a capacitor C37, a resistor R36, a capacitor C49, crystal oscillators JT3 to JT6 with sequential numbers, capacitors C39 to C42 with sequential numbers, a resistor R61, a resistor R41, a resistor R44, and a capacitor C51. The model of the chip U1 is MC3362. The same-name end of the primary coil of the transformer T2 is connected to the other end of the resistor R34, the opposite-name end of the primary coil of the transformer T2 is connected to the other end of the resistor R35, the same-name end of the secondary coil of the transformer T2 is connected to the first pin of the chip U1, the opposite-name end of the secondary coil of the transformer T2 is connected to the thirteenth pin of the chip U1, one end of the capacitor C42 is connected to the second pin of the chip U1, and the other end of the capacitor C42 is grounded; one end of the crystal oscillator JT4 is connected to the seventh pin of the chip U1, the other end of the crystal oscillator JT4, the sixth pin of the chip U1, and the eighth pin of the chip U1 are all connected, one end of the resistor R41 is connected to one end of the crystal oscillator JT4, and the other end of the resistor R41 is connected to the tenth pin of the chip U1; one end of the capacitor C51 is connected to the eleventh pin of the chip U1, and the other end of the capacitor C51 is connected to the twelfth pin of the chip U1;

[0044] One end of capacitor C37, one end of resistor R36, one end of capacitor C49, and the fifteenth pin of chip U1 are connected; the other end of capacitor C49, one end of crystal oscillator JT3, and the sixteenth pin of chip U1 are connected; one end of crystal oscillator JT6 is connected to the eighteenth pin of chip U1, and the other end of crystal oscillator JT6, the seventeenth pin of chip U1, and the nineteenth pin of chip U1 are connected; one end of capacitor C40 is connected to the twenty-first pin of chip U1, and the other end of capacitor C40, one end of capacitor C39, and the twentieth pin of chip U1 are connected; one end of capacitor C41, the twenty-second pin of chip U1, and one end of potentiometer R62 are connected; one end of resistor R61 is connected to the twenty-third pin of chip U1, one end of crystal oscillator JT5, and one end of resistor R44 are both connected to the twenty-fourth pin of chip U1; the other end of capacitor C37, the other end of resistor R36, the other end of crystal oscillator JT3, the eighteenth pin of chip U1, the other end of capacitor C39, the other end of capacitor C41, the other end of potentiometer R62, the control terminal of potentiometer R62, the other end of resistor R61, the other end of crystal oscillator JT5, and the other end of resistor R44 are all connected to the neutral point of the primary coil of transformer T2. The frequency modulation circuit 6 generates a local oscillation consistent with the internal frequency of the transmitting part by using chip U1, which is convenient for demodulating high-frequency small signals. The input high-frequency signal enters the first mixer inside MC3362 after passing through the signal receiving circuit 5 and is amplified and converted into a first intermediate frequency signal of 10.7Mhz. After the first intermediate frequency signal is filtered by an external band-pass ceramic filter, it is then input into the second mixer inside MC3362 for further amplification and mixed to convert into a second intermediate frequency signal of 455KHZ. After the second intermediate frequency signal is filtered by an external band-pass ceramic filter, it is input into the internal limiting amplifier and the frequency detection circuit, and output to the next-stage mixing and frequency discrimination circuit 7. The message signal is restored and the signal is separated through the mixing and frequency discrimination circuit 7, and finally output by the speaker.

[0045] Such as Figure 9As shown in the figure, the mixing and frequency discrimination circuit 7 includes a transformer T1, a resistor R38, a capacitor C43, a triode VT8, a capacitor C46, a resistor R63, a capacitor C64, a crystal oscillator JT2, a resistor R39, a capacitor C68, a variable capacitor C48, a capacitor C44, a capacitor C61 and a capacitor C62. The same-named end of the primary coil of the transformer T1 is connected to the fourth pin of the chip U1, and the different-named end of the primary coil of the transformer T1 is connected to the third pin of the chip U1. The same-named end of the secondary coil of the transformer T1, one end of the resistor R38, one end of the capacitor C43, one end of the resistor R39 and one end of the capacitor C44 are connected. The other end of the capacitor C44 is grounded, and the other end of the capacitor C43 is connected to the different-named end of the secondary coil of the transformer T1. The collector of the triode VT8 is connected to the neutral point of the secondary coil of the transformer T1. The emitter of the triode VT8, one end of the capacitor C46, one end of the resistor R63 and one end of the capacitor C64 are connected. The other end of the capacitor C64, the base of the triode VT8, one end of the crystal oscillator JT2 and the other end of the resistor R39 are connected; the other end of the crystal oscillator JT2, one end of the capacitor C68 and one end of the variable capacitor C48 are connected. The other end of the capacitor C46, the other end of the resistor R63, the other end of the capacitor C68 and the other end of the variable capacitor C48 are connected and grounded; the other end of the resistor R38, the seventh pin of the chip U1, the positive electrode of the capacitor C61 and one end of the capacitor C62 are all connected to the neutral point of the primary coil of the transformer T2. The negative electrode of the capacitor C61 and the other end of the capacitor C62 are connected and grounded. The mixing and frequency discrimination circuit 7 separates the intermediate signals through circuit mixing and frequency discrimination, facilitating the power amplification of the signals by the subsequent stage and then restoring the voice signals, preventing signal overlap and avoiding inaccurate output results.

[0046] As Figure 10 shown in the figure, the power amplification circuit 8 includes a chip U2 and capacitors C55 to C58 numbered in sequence. The model of the chip U2 is LM386. The sixth pin of the chip U2 is connected to the twenty-third pin of the chip U1, and the eighth pin of the chip U2 is grounded; the third pin of the chip U2, one end of the capacitor C62, the positive electrode of the capacitor C57 and one end of the capacitor C58 are connected and connected to the power supply +6V. The negative electrode of the capacitor C57 and the other end of the capacitor C58 are connected and grounded. The positive electrode of the capacitor C55 is connected to the fourth pin of the chip U2, the negative electrode of the capacitor C55 is grounded, and both ends of the capacitor C56 are connected to two filters. The output ends of the two filters are respectively connected to a speaker, and the two speakers respectively output a voice signal. The power amplification circuit 8 amplifies the power of the separated signals output by the mixing and frequency discrimination circuit 7, increases the output current, and filters out two signals with different frequencies loaded on the dual-channel voice input signals respectively by connecting two filters at the output end, restores the original dual-channel voice signals, and outputs the voice signals through the speakers respectively.

[0047] Through the above technical solution, the low-frequency amplification circuit 1 of the present invention receives a dual-channel voice input signal, and the power amplification circuit 8 outputs a dual-channel voice signal. The input ends of the two voice signals are the same, and the two voice signals are input simultaneously. After being processed by the transmitting part and the receiving part, two stable voice signals are output, with high communication instantaneity. Two different frequencies are modulated by the frequency synthesis oscillator circuit 2 and respectively loaded onto the dual-channel voice input signal to increase the frequency of the voice signal, facilitate signal transmission, have a high spectrum utilization rate, and a high communication efficiency.

[0048] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-channel simultaneous voice translation wireless transceiver system, characterized in that It includes a transmitting part and a receiving part. The transmitting part includes a low-frequency amplification circuit, a frequency synthesis oscillator circuit, a resonance mixing circuit, and an impedance matching transmitting circuit connected in sequence. The receiving part includes a signal receiving circuit, a frequency modulation circuit, a mixing and frequency discrimination circuit, and a power amplification circuit connected in sequence. The impedance matching transmitting circuit is communicatively connected to the signal receiving circuit. The low-frequency amplification circuit receives a dual-channel voice input signal, and the power amplification circuit outputs a dual-channel voice signal. Among them, the frequency synthesis oscillator circuit includes a resistor R11, a crystal oscillator JT1, and a diode VD1. One end of the resistor R11 is connected to the low-frequency amplification circuit, and the other end of the resistor R11 is respectively connected to one end of the crystal oscillator JT1 and the cathode of the diode VD1. The other end of the crystal oscillator JT1 and the anode of the diode VD1 are both connected to the resonance mixing circuit.

2. The dual-channel simultaneous interpretation wireless transceiver system according to claim 1, characterized in that, The low-frequency amplification circuit includes capacitors C1, C2, C3, resistors R1 to R4 with sequential numbers, a microphone MK1, resistors R9, R10, R12, capacitors C13, C14, C6, a triode VT4, and a triode VT5. The microphone MK1 receives two dual-channel voice input signals that have been amplitude-modulated. One end of the microphone MK1 is respectively connected to one end of the capacitor C13 and one end of the resistor R1. The other end of the capacitor C13 is respectively connected to one end of the resistor R9 and the base of the triode VT4. The other end of the resistor R9, one end of the resistor R2, the collector of the triode VT4, and one end of the capacitor C14 are connected. The other end of the capacitor C14 is respectively connected to one end of the resistor R10 and the base of the triode VT5. The other end of the resistor R10, one end of the resistor R3, the positive electrode of the capacitor C6, and the collector of the triode VT5 are connected. The negative electrode of the capacitor C6 is connected to the frequency synthesis oscillator circuit. One end of the resistor R12, the emitter of the triode VT5, the emitter of the triode VT4, and the other end of the microphone MK1 are connected and grounded. The other end of the resistor R12 is connected to one end of the resistor R4. The other ends of the resistors R1 to R4, the positive electrode of the capacitor C1, the positive electrode of the capacitor C2, and one end of the capacitor C3 are all connected. One end of the capacitor C3 is connected to the resonance mixing circuit. The negative electrode of the capacitor C1, the negative electrode of the capacitor C2, and the other end of the capacitor C3 are grounded. One end of the resistor R11 is connected to the negative electrode of the capacitor C6.

3. A dual-channel simultaneous interpretation wireless transceiver system according to claim 2, characterized in that, The resonant hybrid circuit includes resistor R6, capacitor C4, inductor L1, resistor R7, capacitor C5, inductor L2, capacitor C7, inductor L3, transistors VT1 to VT3 with sequential numbers, capacitor C12, capacitor C15, resistors R14 to R17 with sequential numbers, capacitor C20, capacitor C21, and capacitor C22. One end of resistor R6, one end of resistor R14, one end of capacitor C15, and the base of transistor VT1 are connected and connected to the other end of crystal oscillator JT1; the collector of transistor VT1, one end of capacitor C4, one end of inductor L1, and one end of capacitor C12 are connected; the emitter of transistor VT1, the other end of capacitor C15, one end of resistor R15, and one end of capacitor C20 are connected; the other end of capacitor C12, one end of resistor R7, one end of resistor R16, one end of capacitor C21, and the base of transistor VT2 are connected; the collector of transistor VT2, one end of capacitor C5, one end of inductor L2, and one end of capacitor C7 are connected; the other end of capacitor C7, one end of resistor R17, one end of capacitor C22, and the base of transistor VT3 are connected; the collector of transistor VT3 is connected to one end of inductor L3; the other ends of resistors R14 to R17, the other end of capacitor C20, the other end of capacitor C21, the other end of capacitor C22, and the emitter of transistor VT3 are all connected together; the other end of resistor R6, the other end of capacitor C4, the other end of inductor L1, the other end of resistor R7, the other end of capacitor C5, the other end of inductor L2, and the other end of inductor L3 are all connected together; the other end of inductor L3 and the emitter of transistor VT3 are both connected to the impedance matching emission circuit.

4. A dual-channel simultaneous interpretation wireless transceiver system according to claim 3, characterized in that, The impedance matching emission circuit includes capacitors C8 to C11 with sequential numbers, inductor L4, inductor L5, inductor L6, resistor R8, capacitors C16 to C19 with sequential numbers, display lamp LED1, and antenna E1. One end of capacitor C8 is connected to one end of inductor L3; the other end of capacitor C8, one end of inductor L4, and one end of capacitor C16 are connected; the other end of inductor L4 is connected to one end of capacitor C9; the other end of capacitor C9, one end of inductor L5, and one end of capacitor C17 are connected; the other end of inductor L5, one end of inductor L6, and one end of capacitor C18 are connected; the other end of inductor L6, antenna E1, and one end of capacitor C19 are connected; one end of resistor R8, the positive electrode of capacitor C10, and one end of capacitor C11 are all connected to the other end of inductor L3 and connected to power supply +6V; the other end of resistor R8 is connected to the anode of display lamp LED1; the emitter of transistor VT3, the other ends of capacitors C16 to C19, the cathode of display lamp LED1, the negative electrode of capacitor C10, and the other end of capacitor C11 are all connected and grounded.

5. A two-way simultaneous interpretation wireless transceiver system according to claim 4, wherein The signal receiving circuit includes antenna E2, capacitors C31 to C36 with sequential numbers, transformer T3, resistors R31 to R35 with sequential numbers, triode VT6, and triode VT7. One end of antenna E2 is connected to one end of capacitor C31. The other end of capacitor C31, one end of capacitor C32, and the same-named end of the primary coil of transformer T3 are connected. The other end of capacitor C32 is connected to the different-named end of the primary coil of transformer T3. One end of capacitor C33 is connected to the same-named end of the secondary coil of transformer T3. The other end of capacitor C33, one end of resistor R31, and the base of triode VT6 are connected. The other end of resistor R31, the collector of triode VT6, the emitter of triode VT7, one end of capacitor C35, one end of resistor R33, and one end of resistor R35 are connected. The emitter of triode VT6, one end of capacitor C34, and one end of resistor R32 are connected. The collector of triode VT7 is connected to one end of resistor R34. A capacitor C36 is connected between the other end of resistor R34 and the other end of resistor R35. The other end of resistor R34 and the other end of resistor R35 are both connected to the frequency modulation circuit. The different-named end of the secondary coil of transformer T3, the other end of capacitor C34, the other end of resistor R32, the other end of capacitor C35, and the other end of resistor R33 are all connected and grounded.

6. The dual-channel simultaneous interpretation wireless transceiver system according to claim 5, wherein The frequency modulation circuit includes transformer T2, chip U1, capacitor C37, resistor R36, capacitor C49, crystal oscillators JT3 to JT6 with sequential numbers, capacitors C39 to C42 with sequential numbers, resistor R61, resistor R41, resistor R44, and capacitor C51. The same-named end of the primary coil of transformer T2 is connected to the other end of resistor R34. The different-named end of the primary coil of transformer T2 is connected to the other end of resistor R35. The same-named end of the secondary coil of transformer T2 is connected to the first pin of chip U1. The different-named end of the secondary coil of transformer T2 is connected to the thirteenth pin of chip U1. One end of capacitor C42 is connected to the second pin of chip U1. The other end of capacitor C42 is grounded. One end of crystal oscillator JT4 is connected to the seventh pin of chip U1. The other end of crystal oscillator JT4, the sixth pin of chip U1, and the eighth pin of chip U1 are all connected. One end of resistor R41 is connected to one end of crystal oscillator JT4. The other end of resistor R41 is connected to the tenth pin of chip U1. One end of capacitor C51 is connected to the eleventh pin of chip U1. The other end of capacitor C51 is connected to the twelfth pin of chip U1. One end of capacitor C37, one end of resistor R36, one end of capacitor C49, and the fifteenth pin of chip U1 are connected; the other end of capacitor C49, one end of crystal oscillator JT3, and the sixteenth pin of chip U1 are connected; one end of crystal oscillator JT6 is connected to the eighteenth pin of chip U1, and the other end of crystal oscillator JT6, the seventeenth pin of chip U1, and the nineteenth pin of chip U1 are connected; one end of capacitor C40 is connected to the twenty-first pin of chip U1, and the other end of capacitor C40, one end of capacitor C39, and the twentieth pin of chip U1 are connected; one end of capacitor C41, the twenty-second pin of chip U1, and one end of potentiometer R62 are connected; one end of resistor R61 is connected to the twenty-third pin of chip U1, and one end of crystal oscillator JT5 and one end of resistor R44 are both connected to the twenty-fourth pin of chip U1; the other end of capacitor C37, the other end of resistor R36, the other end of crystal oscillator JT3, the eighteenth pin of chip U1, the other end of capacitor C39, the other end of capacitor C41, the other end of potentiometer R62, the control terminal of potentiometer R62, the other end of resistor R61, the other end of crystal oscillator JT5, and the other end of resistor R44 are all connected to the neutral point of the primary coil of transformer T2.

7. A dual-channel simultaneous interpretation wireless transceiver system according to claim 6, characterized in that The model of the chip U1 is MC3362.

8. A dual-channel simultaneous interpretation wireless transceiver system according to claim 6, characterized in that, The mixing and frequency discrimination circuit includes transformer T1, resistor R38, capacitor C43, triode VT8, capacitor C46, resistor R63, capacitor C64, crystal oscillator JT2, resistor R39, capacitor C68, variable capacitor C48, capacitor C44, capacitor C61, and capacitor C62. The same-name end of the primary coil of transformer T1 is connected to the fourth pin of chip U1, and the different-name end of the primary coil of transformer T1 is connected to the third pin of chip U1. The same-name end of the secondary coil of transformer T1, one end of resistor R38, one end of capacitor C43, one end of resistor R39, and one end of capacitor C44 are connected. The other end of capacitor C44 is grounded, and the other end of capacitor C43 is connected to the different-name end of the secondary coil of transformer T1. The collector of triode VT8 is connected to the neutral point of the secondary coil of transformer T1. The emitter of triode VT8, one end of capacitor C46, one end of resistor R63, and one end of capacitor C64 are connected. The other end of capacitor C64, the base of triode VT8, one end of crystal oscillator JT2, and the other end of resistor R39 are connected; the other end of crystal oscillator JT2, one end of capacitor C68, and one end of variable capacitor C48 are connected. The other end of capacitor C46, the other end of resistor R63, the other end of capacitor C68, and the other end of variable capacitor C48 are connected and grounded; the other end of resistor R38, the seventh pin of chip U1, the positive electrode of capacitor C61, and one end of capacitor C62 are all connected to the neutral point of the primary coil of transformer T2. The negative electrode of capacitor C61 and the other end of capacitor C62 are connected and grounded.

9. A dual-channel simultaneous interpretation wireless transceiver system according to claim 8, characterized in that, The power amplifier circuit includes a chip U2 and capacitors C55 to C58 numbered in sequence. The sixth pin of the chip U2 is connected to the twenty-third pin of the chip U1, and the eighth pin of the chip U2 is grounded; the third pin of the chip U2, one end of the capacitor C62, the positive electrode of the capacitor C57, and one end of the capacitor C58 are connected and connected to the power supply +6V. The negative electrode of the capacitor C57 and the other end of the capacitor C58 are connected and grounded. The positive electrode of the capacitor C55 is connected to the fourth pin of the chip U2, the negative electrode of the capacitor C55 is grounded, and both ends of the capacitor C56 are connected to two filters. The output ends of the two filters are respectively connected to a speaker, and the two speakers respectively output a voice signal.

10. A dual-channel simultaneous interpretation wireless transceiver system according to claim 9, characterized in that, The model of the chip U2 is LM386.

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