Chip, data processing method and device, electronic equipment and medium

Abstract

The invention provides a chip and a data processing method, and relates to the technical field of communication. The chip comprises a reading module, a processing module and a sending module, the reading module is respectively connected with the processing module, a media access control (MAC) sub-layer of a data link layer and a transmission processing unit of a physical layer, and the sending module is respectively connected with the processing module and the transmission processing unit of the physical layer; the reading module is used for acquiring a target transmission request from a transmission processing unit of a physical layer and acquiring a TB descriptor chain table from an MAC sub-layer, and the processing module is used for sequentially performing encryption and integrity protection processing on a target data packet according to the TB descriptor chain table and a target transmission quantity to obtain an encrypted data packet; and the sending module is used for sending the encrypted data packet to a transmission processing unit of a physical layer. According to the chip provided by the invention, encryption and integrity protection are delayed to the last sub-layer of the data link layer, so that the access times of the memory are reduced, and meanwhile, the bandwidth requirement of the memory and the power consumption of the system are reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technologies, and in particular, to a chip, a data processing method, a device, an electronic device, and a medium. Background Art

[0002] In the uplink data packet processing flow of the data link layer, with the increase in rate, using the CPU to complete the encryption of PDCP and the packet assembly of MAC will bring a large consumption of MIPS (Million Instructions Per Second). The access of the network layer data packet to the memory is "two reads and two writes", which will bring a high demand for the system DDR (Double Data Rate) bandwidth and generate a large power consumption at the same time. Summary of the Invention

[0003] The present disclosure provides a chip, a data processing method, a device, an electronic device, and a medium.

[0004] In a first aspect embodiment of the present disclosure, a chip is provided, including: a reading module, a processing module, and a sending module. The reading module is respectively connected to the processing module, the media access control (MAC) sublayer of the data link layer, and the transmission processing unit of the physical layer. The sending module is respectively connected to the processing module and the transmission processing unit of the physical layer. The reading module is configured to obtain a target transmission request from the transmission processing unit of the physical layer and obtain a transmission block (TB) descriptor linked list from the MAC sublayer. The processing module is configured to perform encryption and integrity protection processing on the target data packet in sequence according to the TB descriptor linked list according to the target transmission amount to obtain an encrypted data packet. The target transmission request includes the target transmission amount. The sending module is configured to send the encrypted data packet to the transmission processing unit of the physical layer.

[0005] In some embodiments of the present disclosure, the reading module is further configured to read the target data packet from the packet data convergence protocol (PDCP) sublayer of the data link layer based on the TB descriptor linked list and the target transmission request.

[0006] In some embodiments of the present disclosure, the TB descriptor linked list includes at least one of the following: COUNT value; data transmission direction; identifier of the radio bearer; key; start address; data packet length; address of the PDCP SDU.

[0007] In some embodiments of the present disclosure, the reading module is further configured to read a target data packet from the PDCP SDUs stored in the PDCP sublayer based on the start address, the data packet length, the identifier of the radio bearer, and the target transmission volume; the processing module is further configured to perform encryption and integrity protection processing on the target data packet according to the COUNT value and the key to obtain an encrypted data packet; the reading module is further configured to store the encryption information, where the encryption information includes the end position of the currently transmitted encrypted data packet corresponding to the target data packet.

[0008] In some embodiments of the present disclosure, the reading module is further configured to delete the encryption information after receiving the feedback information indicating that the encrypted data packet has been successfully sent.

[0009] The second aspect of the embodiments of the present disclosure provides a data processing method, which includes: obtaining a radio link control sublayer protocol data unit (RLC PDU) according to the logical channel priority and the authorization information, and adding a media access control (MAC) sublayer header to the RLC PDU to generate a transmission block (TB) descriptor linked list, where the TB descriptor linked list includes encryption parameters; performing encryption and integrity protection processing on the target data packet in sequence according to the target transmission request and the TB descriptor linked list.

[0010] In some embodiments of the present disclosure, the TB descriptor linked list includes at least one of the following: COUNT value; data transmission direction; identifier of the radio bearer; key; start address; data packet length; address of the packet data convergence protocol (PDCP) sublayer data transmission unit (PDCP SDU).

[0011] In some embodiments of the present disclosure, performing encryption and integrity protection processing on the target data packet in sequence according to the target transmission request and the TB descriptor linked list includes: reading the target data packet from the data transmission units (PDCP SDUs) stored in the packet data convergence protocol sublayer based on the start address, the data packet length, the identifier of the radio bearer, and the target transmission volume, where the target transmission request includes the target transmission volume; performing encryption and integrity protection processing on the target data packet according to the COUNT value and the key to obtain an encrypted data packet; storing the encryption information, where the encryption information includes the end position of the currently transmitted encrypted data packet corresponding to the target data packet.

[0012] In some embodiments of the present disclosure, the method further includes: deleting the encryption information after receiving the feedback information indicating that the encrypted data packet has been successfully sent.

[0013] A third - aspect embodiment of the present disclosure provides a data - processing device, including: a generating unit, configured to obtain a Radio Link Control (RLC) protocol data unit (PDU) of the radio link control sub - layer according to the logical channel priority and authorization information, and add a Medium Access Control (MAC) sub - layer header to the RLC PDU to generate a linked list of transport - block (TB) descriptors, where the linked list of TB descriptors includes encrypted parameters; a processing unit, configured to perform encryption and integrity - protection processing on the target data packet in sequence according to the target transmission request and the linked list of TB descriptors.

[0014] A fourth - aspect embodiment of the present disclosure provides an electronic device, including: a processor and a memory for storing a computer program that can run on the processor, where the processor is configured to execute the method described in any one of the embodiments of the second aspect of the present disclosure when running the computer program.

[0015] A fifth - aspect embodiment of the present disclosure provides an electronic device, including: a main board and a chip as described in any one of the embodiments of the first aspect of the present disclosure.

[0016] A sixth - aspect embodiment of the present disclosure provides a non - transitory computer - readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method described in any one of the embodiments of the second aspect of the present disclosure.

[0017] A seventh - aspect embodiment of the present disclosure provides a chip, including at least one processor and a communication interface; the communication interface is configured to receive a signal input to the chip or a signal output from the chip, and the processor communicates with the communication interface and implements the method described in any one of the embodiments of the second aspect of the present disclosure through logic circuits or by executing code instructions.

[0018] In summary, the chip, data processing method, device, electronic device, and medium proposed in the present disclosure include: a reading module, a processing module, and a sending module. The reading module is respectively connected to the processing module, the media access control (MAC) sublayer of the data link layer, and the transmission processing unit of the physical layer. The sending module is respectively connected to the processing module and the transmission processing unit of the physical layer. The reading module is configured to obtain a target transmission request from the transmission processing unit of the physical layer and obtain a linked list of TB descriptors from the MAC sublayer. The processing module is configured to perform encryption and integrity protection processing on the target data packet in sequence according to the target transmission amount based on the linked list of TB descriptors to obtain an encrypted data packet. The sending module is configured to send the encrypted data packet to the transmission processing unit of the physical layer. It can perform the encryption and integrity protection of PDCP in the MAC sublayer, reducing the memory access volume, and simultaneously reducing the DDR bandwidth requirement and system power consumption. At the same time, the chip of the present disclosure supports the transmission at the code block or symbol level with the physical layer, which can avoid the instantaneous impact on the memory bandwidth caused by the data packet generated for transmission at one time, improving the system stability, and also reducing the size of the on-chip memory required for caching data in the transmission processing unit of the physical layer.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an improper limitation to the present disclosure.

[0021] Figure 1 It is the architecture diagram of the communication system provided by the embodiment of the present disclosure;

[0022] Figure 2 It is the architecture diagram of a chip proposed by the embodiment of the present disclosure;

[0023] Figure 3 It is the schematic flowchart of a data processing method proposed by the embodiment of the present disclosure;

[0024] Figure 4 It is the method flowchart of the data processing method proposed by the embodiment of the present disclosure;

[0025] Figure 5 It is the method flowchart of the encryption and integrity protection processing proposed by the embodiment of the present disclosure;

[0026] Figure 6A It is a UL L2 data processing flowchart;

[0027] Figure 6B It is the system architecture diagram of UL 2A;

[0028] Figure 6C Schematic diagram for the processing of UL 2A;

[0029] Figure 7 Schematic diagram of the structure of the data processing device proposed in the embodiment of the present disclosure;

[0030] Figure 8 Schematic diagram of the structure of the electronic device provided in the embodiment of the present disclosure;

[0031] Figure 9 Schematic diagram of the structure of the chip provided in the embodiment of the present disclosure. Detailed implementation manners

[0032] The embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, but should not be construed as limiting the present disclosure.

[0033] The following are the explanations of professional terms in the embodiments of the present disclosure:

[0034] The data link layer includes a PDCP sublayer, an RLC sublayer, and a MAC sublayer.

[0035] 1. PDCP sublayer: Packet Data Convergence Protocol, the packet data convergence layer protocol. The PDCPSDU is the data transmission unit of the PDCP layer, which contains the data to be transmitted and some related control information. The PDCP PDU contains information from the upper layer and additional information of the entity of the current layer;

[0036] 2. RLC sublayer: Radio Link Control, the radio link control protocol. The RLC layer is located above the MAC layer and provides segmentation and retransmission services for user and control data. Each RLC entity is configured by the RRC and has three modes according to the service type: transparent mode (TM), unacknowledged mode (UM), and acknowledged mode (AM).

[0037] 3. MAC sublayer: Medium Access Control, the medium access control / media access control. The MAC sublayer is mainly responsible for controlling and connecting to the physical layer. When sending data, the MAC protocol determines whether it can be sent. If it can be sent, after adding control information, the data and control information are sent to the physical layer; when receiving data, the MAC protocol first determines whether there is a transmission error in the input information. If there is no error, the control information is removed and sent to the logical link control layer.

[0038] 4. SDU: Service Data Unit, the service data unit. In a hierarchical network structure, the information received by each layer from the upper layer is the SDU of this layer, and the information transmitted to the lower layer after adding the entity additional information of the current layer to the SDU is the PDU of this layer.

[0039] 5. PDU: Protocol Data Unit, the protocol data unit.

[0040] 6. UL: Up Link, the uplink. In the field of mobile communication technology, the uplink is the signal or information transmitted from the terminal to the base station.

[0041] 7. DL: Data Layer, the data layer.

[0042] 8. BEARER: Bearer, which can be understood as bearing and loading. It is a logical path from the core network to the UE. Nodes between two network elements, or three or more, can form various bearers. The path for data transmission is the bearer. The RB (Radio Bearer) ID is the identifier of the radio bearer.

[0043] 9. Payload: Payload, the effective data part carried in the transmission protocol, which is the basis for realizing information transmission and exchange.

[0044] 10. DDR: Double Data Rate, double data rate memory.

[0045] The uplink packet transmission process of the data link layer includes: The UL layer writes the data packet payload into the PDCP SDU Buffer (PDCP SDU cache), and notifies the PDCP of the PDCP SDU packet descriptor to inform the PDCP to send; The PDCP assigns an SN (Serial Number) packet to the PDCP SDU, and delivers the packet descriptor to the Cipher accelerator. The Cipher accelerator reads the payload of the data packet from the PDCP SDU buffer, completes encryption and integrity protection, and writes the result into the RLC SDU Buffer. The PDCP adds a Header to the PDCP SDU to generate a PDCP PDU, and notifies the RLC of the PDCP PDU descriptor. After receiving the Grant (authorization / request) delivered by the PHY (physical layer), the MAC provides data packets to be sent of a given size from different RLC entities according to the Grant size and logical channel priority. Each RLC entity performs operations such as segmentation, re-segmentation, and recombination of the RLC SDU according to the size of the data packet requested by the MAC, and adds an RLC Header to form an RLC PDU. The RLC sends the descriptor of the RLC PDU to the MAC. The MAC adds a MAC Header to the RLC PDU to form a TB block, and the MAC delivers a TB description node to the Link DMA. The Link DMA reads the RLC SDU Payload from the RLC SDU Buffer according to the information, and then delivers it to the CB Buffer of the PHY TX processing unit for transmission. In the above process, the access of the data packet of the UL Layer to the DDR is "two reads and two writes", that is, one write by the UL Layer to the DDR, one read and one write by the Cipher accelerator to the DDR, and one read by the MAC packet assembly DMA (Direct Memory Access), which will bring a high system DDR bandwidth requirement and generate a large power consumption.

[0046] Therefore, in order to reduce the number of memory accesses in the uplink packet transmission process of the data link layer, reduce the memory bandwidth requirement, and at the same time reduce the system power consumption, the embodiments of the present disclosure provide a chip and a data processing method, which move the process of encryption and integrity protection of the PDCP to the MAC sublayer for execution to reduce the memory access to "one read and one write", thereby achieving the purpose of reducing the system power consumption, improving the data processing speed and transmission efficiency.

[0047] The chip and the data processing method provided by the present application will be introduced in detail below with reference to the accompanying drawings.

[0048] Figure 1It is a schematic diagram of the architecture of a communication system shown according to an embodiment of the present disclosure. As Figure 1 shown, the communication system 100 may include a terminal 101 and a network device 102. The network device 102 may include at least one of an access network device and a core network device.

[0049] In some embodiments, the terminal 101 includes, for example, at least one of a mobile phone, a wearable device, an Internet of Things device, a vehicle with communication function, a smart vehicle, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, and a wireless terminal in smart home, but is not limited thereto.

[0050] In some embodiments, the access network device is, for example, a node or device that connects a terminal to a wireless network. The access network device may include at least one of an evolved NodeB (eNB) in a 5G communication system, a next-generation evolved NodeB (ng-eNB), a next-generation NodeB (gNB), a NodeB (NB), a home NodeB (HNB), a home evolved NodeB (HeNB), a wireless backhaul device, a radio network controller (RNC), a base station controller (BSC), a base transceiver station (BTS), a baseband unit (BBU), a mobile switching center, a base station in a 6G communication system, an Open RAN, a Cloud RAN, a base station in other communication systems, and an access node in a WiFi system, but is not limited thereto.

[0051] In some embodiments, the technical solutions of the present disclosure can be applied to the Open RAN architecture. At this time, the interfaces between access network devices or within access network devices involved in the embodiments of the present disclosure can become the internal interfaces of Open RAN, and the processes and information interactions between these internal interfaces can be implemented through software or programs.

[0052] In some embodiments, the access network device can be composed of a central unit (CU) and a distributed unit (DU). Among them, the CU can also be referred to as a control unit. Adopting the CU-DU structure can split the protocol layer of the access network device. The functions of some protocol layers are centrally controlled by the CU, and the functions of the remaining part or all protocol layers are distributed in the DU. The CU centrally controls the DU, but it is not limited to this.

[0053] In some embodiments, the core network device can be a single device including one or more network elements, or multiple devices or device groups, each including all or part of one or more network elements. The network elements can be virtual or physical. The core network includes, for example, at least one of the Evolved Packet Core (EPC), 5G Core Network (5GCN), and Next Generation Core (NGC).

[0054] It can be understood that the communication system described in the embodiments of the present disclosure is to more clearly illustrate the technical solutions of the embodiments of the present disclosure, and does not constitute a limitation on the technical solutions proposed in the embodiments of the present disclosure. Those of ordinary skill in the art know that with the evolution of the system architecture and the emergence of new service scenarios, the technical solutions proposed in the embodiments of the present disclosure are equally applicable to similar technical problems.

[0055] The following embodiments of the present disclosure can be applied to Figure 1 the communication system 100 shown, or a part of the main body, but it is not limited to this. Figure 1 The main bodies shown are examples. The communication system can include Figure 1 all or part of the main bodies, or can include Figure 1 other main bodies outside. The number and form of each main body are arbitrary. The connection relationships between the main bodies are examples. The main bodies can be not connected or connected. Their connection can be in any way, either directly connected or indirectly connected, either wired or wirelessly connected.

[0056] Embodiments of the present disclosure can be applied to Long Term Evolution (LTE), LTE-Advanced (LTE-A), LTE-Beyond (LTE-B), SUPER 3G, IMT-Advanced, 4th generation mobile communication system (4G), 5th generation mobile communication system (5G), 5G New Radio (NR), 6th generation mobile communication system (6G), Future Radio Access (FRA), New Radio Access Technology (RAT), New Radio (NR), New radio access (NX), Future generation radio access (FX), Global System for Mobile communications (GSM (registered trademark)), CDMA2000, Ultra Mobile Broadband (UMB), IEEE 802.11 (Wi-Fi (registered trademark)), IEEE 802.16 (WiMAX (registered trademark)), IEEE 802.20, Ultra-WideBand (UWB), Bluetooth (registered trademark), Public Land Mobile Network (PLMN) network, Device-to-Device (D2D) system, Machine to Machine (M2M) system, Internet of Things (IoT) system, Vehicle-to-Everything (V2X), systems using other communication methods, next-generation systems extended based on them, etc. In addition, multiple systems can be combined (for example, a combination of LTE or LTE-A and 5G, etc.) and applied.

[0057] Figure 2 The architecture diagram of a chip 200 proposed for the embodiments of the present disclosure. As Figure 2 shown, it includes:

[0058] A reading module 201, a processing module 202, and a sending module 203. The reading module is respectively connected to the processing module, the media access control (MAC) sublayer of the data link layer, and the transmission processing unit of the physical layer. The sending module is respectively connected to the processing module and the transmission processing unit of the physical layer.

[0059] The reading module is used to obtain a target transmission request from the transmission processing unit of the physical layer and obtain a transmission block (TB) descriptor linked list from the MAC sublayer. The processing module is used to encrypt and perform integrity protection processing on the target data packets in sequence according to the TB descriptor linked list according to the target transmission amount to obtain encrypted data packets. The target transmission request includes the target transmission amount. The sending module is used to send the encrypted data packets to the transmission processing unit of the physical layer.

[0060] The reading module is further used to read the target data packets based on the TB descriptor linked list, the target transmission request, from the packet data convergence protocol (PDCP) sublayer of the data link layer.

[0061] In some embodiments, the TB descriptor linked list includes at least one of the following: COUNT value; data transmission direction; identifier of the radio bearer; key; starting address; packet length; address of the PDCP SDU.

[0062] In some embodiments, the reading module is further used to read the target data packets from the PDCP SDUs stored in the PDCP sublayer based on the starting address, the packet length, the identifier of the radio bearer, and the target transmission amount. The processing module is further used to encrypt and perform integrity protection processing on the target data packets according to the COUNT value and the key to obtain encrypted data packets. The reading module is further used to store the encryption information, where the encryption information includes the ending position of the currently transmitted encrypted data packet corresponding to the target data packet.

[0063] In some embodiments, the reading module reads the target data packets from the cache by accessing the memory based on the starting address, the packet length, the identifier of the radio bearer, the target transmission amount, and the stored PDCP SDUs. The total amount of the target data packets obtained each time is equal to the size of the target transmission amount. The target data packets are the stored PDCP SDUs, that is, the PDCP SDUs read from the PDCP SDU Buffer according to the TB descriptor nodes in the TB descriptor linked list corresponding to the target transmission amount.

[0064] In some embodiments, the MAC sublayer sends a linked list of TB descriptors to the reading module of the data processing chip via TB Transmit Req (transmission block request). Some of the descriptor nodes point to the PDCP SDU Payload and carry information such as the COUNT value required for encryption and integrity protection, the data transmission direction, the identifier of the radio bearer, the key, the starting address, the packet length, and the address of the PDCP SDU.

[0065] In some embodiments, the reading module selects the corresponding descriptor node from the linked list of TB descriptors according to the size of the packet generated in the target transmission request sent by the transmission processing unit of the physical layer, and generates the corresponding payload according to the starting address.

[0066] In some embodiments, the target transmission request is a request sent by the transmission processing unit of the physical layer to the data link layer. Each target transmission request corresponds to a target transmission amount, which can be at the CB (code block) level or the symbol level, or can be a fixed size value between the CB level and the symbol level. The present disclosure does not limit this.

[0067] Exemplarily, UL2A supports pipelining at the CB level or the symbol level with the transmission processing unit of the physical layer, and generates multiple corresponding transmission Payloads according to the transmission size of the CB Req request sent by the transmission processing unit of the physical layer. As Figure 6C shown, each CB Req corresponds to a TB Payload, and each TB Payload corresponds to one or more TB descriptor nodes.

[0068] In the above embodiments, the chip of the present disclosure decomposes the one-time generation of the TB Payload into multiple CB Payloads or symbol Payloads according to the target transmission amount to smooth the amount of data transmitted, thereby avoiding the instantaneous impact on the DDR bandwidth caused by the one-time generation of the transmitted Payload, improving the stability of the system, and also reducing the size of the on-chip Memory required for caching data in the transmission processing unit of the physical layer.

[0069] In some embodiments, the processing module performs encryption and integrity protection processing according to the obtained target packet and the encryption information contained in the descriptor node corresponding to it in the linked list of TB descriptors, that is, the COUNT value and the key. Among them, COUNT is related to the corresponding sublayer, that is, the COUNT value in the packet descriptor of the PDCP sublayer is the COUNT value generated in the PDCP sublayer processing process, and the COUNT value in the packet descriptor of the MAC sublayer is the COUNT value generated in the MAC sublayer processing process.

[0070] In some embodiments, the encryption algorithm adopted for encryption may be a symmetric encryption algorithm (such as AES) or an asymmetric encryption algorithm (such as RSA).

[0071] In some embodiments, the encryption process may adopt encryption of 128 bits or 192 bits or 256 bits, and the present disclosure is not limited thereto.

[0072] In some embodiments, integrity protection may be to generate an integrity check code for the data in the target data packet, for example, a CRC check code.

[0073] In some embodiments, the reading module reads the target data packet according to the target transmission amount requested by each target transmission request, and the processing module performs encryption and integrity protection processing based on the COUNT value and the key included in the descriptor node of the TB descriptor linked list corresponding to the target data packet to obtain the corresponding encrypted data packet.

[0074] Exemplarily, UL2A generates a data packet size according to the CB Req request sent by the transmission processing unit of the physical layer. Packet Info handling selects the corresponding descriptor from the TB descriptor link and obtains the corresponding Payload according to the starting position. If the payload is part of an RLC SDU, encryption and integrity protection processing are performed according to the encryption parameters carried therein. The integrity protection of a complete RLC SDU can be calculated from the integrity protection results of multiple executions of this RLC SDU according to CB Req.

[0075] In some embodiments, the encryption information includes the end position in the target data packet corresponding to the currently transmitted encrypted data packet.

[0076] In some embodiments, the reading module stores the encryption information corresponding to each encryption and integrity protection process in the memory for subsequent retransmission and other processes.

[0077] In some embodiments, storing the encryption information can determine the start position of encryption when performing encryption and integrity protection processing for the next target transmission request, avoiding repeated encryption of the same data packet.

[0078] In some embodiments, the chip of the present disclosure may be a hardware accelerator, and its name may be UL2A, or a processing chip, etc., and the present disclosure is not limited thereto.

[0079] Exemplarily, such as Figure 6BSchematic diagram of the architecture of the hardware accelerator shown. To avoid encrypting and integrity-protecting the parts starting from the TB block for each CB Req, Packet Info Handling needs to store context information related to the encryption of each logical channel, including the end position of the encryption for the Payload generated each time corresponding to the target data packet.

[0080] In some embodiments, after receiving the feedback information indicating the successful transmission of the encrypted data packet, the reading module deletes the encryption information.

[0081] In some embodiments, the reading module sends the encrypted data packet obtained after the encryption and integrity protection processing to the transmission processing unit of the physical layer. After ensuring that the physical layer receives the encrypted data packet and then receives the feedback information indicating successful transmission, the encryption information is deleted.

[0082] In some embodiments, when the physical layer does not receive the encrypted data packet sent for the first time, an automatic retransmission request is triggered. The data processing chip needs to generate the encrypted data packet again and send it to the transmission processing unit of the physical layer until the feedback information indicating successful transmission is received, and then the encryption information is deleted.

[0083] In the above embodiments, the chip of the present disclosure sequentially reads the PDCPSDU in the memory according to the request of the physical layer to obtain the target data packet, and after performing encryption and integrity protection processing, sends it to the physical layer. Thus, the data packet can be read, processed, and sent according to each demand, reducing the traffic volume and improving the data processing efficiency. In the existing related technologies, preparing all at once according to all the demands of the physical layer will generate a large traffic volume and cause congestion in the data transmission path.

[0084] In the above embodiments, the chip supports the transmission at the code block or symbol level with the physical layer, which can avoid the instantaneous impact on the DDR bandwidth caused by generating the TB Payload all at once, improve the stability of the system, and also reduce the size of the on-chip memory required for caching data in the transmission processing unit of the physical layer.

[0085] Figure 3 Flowchart of a data processing method proposed in an embodiment of the present disclosure. As Figure 3 shown, the method includes the following steps.

[0086] Step 301, obtain the RLC PDU according to the logical channel priority and authorization information, and add a MAC sublayer header to the RLC PDU to generate a linked list of transport block (TB) descriptors.

[0087] In some embodiments, the linked list of TB descriptors includes encryption parameters.

[0088] In some embodiments, the MAC sublayer obtains RLC PDUs from different entities of the RLC sublayer according to the logical channel priority and the grant information sent by the physical layer, and adds a MAC sublayer header to the RLC PDUs to generate a linked list of transport block (TB) descriptors.

[0089] In some embodiments, the logical channel priority is the priority corresponding to the identifier of the radio bearer. The size of the data packets that each logical channel can transmit is limited. The logical channel includes multiple data packets. The logical channel with a higher priority transmits data packets first, and the logical channel with a lower priority transmits later. For example, if the current TB descriptor linked list includes the identifiers of the radio bearers of RB1, RB2, and RB3, the corresponding priorities are RB1 > RB2 > RB3. The order in which the MAC sublayer obtains the data packets from different RLC entities will also obtain the data packets in the RB in the order of priority.

[0090] In some embodiments, the order of the logical channel priorities can be sorted according to the serial number of the identifier of the radio bearer, or the order of the priorities can be customized. The present disclosure does not limit this.

[0091] In some embodiments, the TB descriptor linked list includes multiple TB descriptor nodes, and each descriptor node includes the relevant information of the data packet obtained from the RLC entity according to the grant of the physical layer.

[0092] In some embodiments, the TB descriptor linked list includes at least one of the following: COUNT value; data transmission direction; identifier of the radio bearer; key; start address; data packet length; address of the packet data convergence protocol (PDCP) sublayer's data transmission unit (PDCP PDU).

[0093] In some embodiments, the COUNT value and the key are the encryption parameters originally required for the encryption and integrity protection processing by the PDCP layer. In this method, the encryption and integrity protection are postponed to the MAC sublayer for processing. Therefore, the PDCP sublayer stores the encrypted information in the data packet descriptor to pass it backward to the MAC sublayer, and the MAC sublayer generates the corresponding TB descriptor node. Among them, COUNT is related to the corresponding sublayer, that is, the COUNT value in the data packet descriptor of the PDCP sublayer is the COUNT value generated during the PDCP sublayer's processing, and the COUNT value in the data packet descriptor of the MAC sublayer is the COUNT value generated during the MAC sublayer's processing.

[0094] In some embodiments, the data transmission direction is the transmission direction of the current data in the data link layer. In this method, the data transmission direction is uplink transmission.

[0095] In some embodiments, the identifier of the radio bearer is the identifier corresponding to the original data packet, i.e., the identifier of the RB ID or BEARER, which is the identifier of the bearer where the data packet transmitted from the network layer to the data link layer is located.

[0096] In some embodiments, the starting address is the offset of the address of each corresponding data packet relative to the address of the original data packet, that is, there is an offset starting address for the address of the PDCP SDU.

[0097] In some embodiments, the data packet length is the length of each data packet in the PDCP SDU.

[0098] Exemplarily, after the MAC receives the Grant submitted by the PHY (Physical Layer), according to the size of the Grant and the logical channel priority, it provides data packets to be transmitted of a given size from different RLC entities, adds a MAC Header (MAC sub-layer header) to the obtained RLC PDU to form a TB (Transport Block), and the TB is represented by a TB descriptor link list. Some of the descriptor nodes point to the PDCP SDU Payload and carry information such as COUNT, DIRECTION, BEARER / RB ID, KEY required for encryption and integrity protection, as well as the starting address, length, and address of the PDCP SDU. The addresses stored on the DDR of the PDCP SDU Payload (payload) are not consecutive.

[0099] Step 302: According to the target transmission request and the TB descriptor link list, perform encryption and integrity protection processing on the target data packets in sequence.

[0100] In some embodiments, the MAC sub-layer sends the TB descriptor link list to the data processing chip, and the data processing chip performs encryption and integrity protection processing on the target data packets in sequence according to the target transmission request and the TB descriptor link list.

[0101] In some embodiments, the data processing chip sequentially reads the PDCP SDU Payload from the PDCP SDU buffer according to the TB descriptor link list and the size of the request data packet sent by the transmission processing unit of the physical layer, and performs encryption and integrity protection processing on the target data packets one by one.

[0102] In some embodiments, the target transmission request is a packet transmission request sent by the physical layer to the MAC sublayer of the data link layer. The data processing chip connected to the MAC sublayer will read the original packet in the memory according to the target transmission request and the address of the PDCP SDU indicated by the TB descriptor list, so as to perform encryption and integrity protection processing on the read target packet.

[0103] In some embodiments, the name of the data processing chip can be set arbitrarily, and the present disclosure does not limit this. In the embodiments of the present disclosure, the data processing chip can be the hardware accelerator UL2A.

[0104] Exemplarily, the MAC sublayer delivers the TB descriptor link that composes a TB to the UL2A. The UL2A reads the PDCP SDU Payload from the PDCP SDU buffer according to this information, and after completing encryption and integrity protection, delivers it to the physical layer for transmission.

[0105] In the above embodiments, the access amount to the memory is reduced to one write operation and one read operation, and the encryption and integrity protection processing are moved to the MAC sublayer to complete, improving the system efficiency and reducing the system power consumption.

[0106] Figure 4 This is the method flowchart of the data processing method proposed in the embodiments of the present disclosure. Based on Figure 3 the embodiments shown, as Figure 4 shown, the following steps are further included:

[0107] Step 401, store the PDCP SDU, and add a PDCP sublayer header to the PDCP SDU to obtain a packet descriptor of the PDCP PDU.

[0108] In some embodiments, the packet descriptor of the PDCP PDU includes a COUNT value, a data transmission direction, an identifier of a radio bearer, a key, a packet length, and an address of the PDCP SDU.

[0109] In some embodiments, the PDCP sublayer stores the PDCP SDU delivered by the network layer in the PDCP SDU buffer in the memory, and after adding a PDCP sublayer header to the PDCP SDU, obtains a packet descriptor of the PDCP PDU. The packet descriptor includes information such as COUNT, DIRECTION, BEARER / RBID, KAY, etc. required for encryption and integrity protection, as well as a packet length, a packet address, etc.

[0110] In some embodiments, the data packets delivered by the network layer may be IP packets of the DRB or signaling packets of the control plane, etc., and the present disclosure is not limited thereto.

[0111] In some embodiments, the data packet descriptor of the PDCP SDU includes information such as the original address of the data packet, the length of the data packet, and the RBID.

[0112] In some embodiments, the PDCP sublayer does not perform encryption and integrity protection on the PDCP SDU, but directly adds a PDCP Header to generate a PDCP PDU, and delivers the data packet descriptor of the PDCP PDU to the RLC sublayer.

[0113] Exemplarily, the network layer UL Layer writes the data packet payload into the PDCP SDU Buffer, which is generally a storage area allocated on the memory DDR. PDCP notifies PDCP of the data packet descriptor of the PDCP SDU, notifies PDCP to send, PDCP does not perform encryption and integrity protection on the PDCP SDU, but directly adds a PDCP Header to generate a PDCP PDU, and delivers the data packet descriptor of the PDCP PDU to the RLC sublayer.

[0114] Step 402: Perform RLC SDU processing on the RLC SDU in sequence, and add an RLC sublayer header to obtain the data packet descriptor of the RLC PDU.

[0115] In some embodiments, the RLC SDU processing includes segmentation processing, re-segmentation processing, recombination processing, etc., and may also include numbering processing, duplicate detection processing, ARQ (Automatic Repeat reQuest) error correction processing, RLC SDU discard processing, RLC reconstruction and other operations, and the present disclosure is not limited thereto.

[0116] In some embodiments, the RLC sublayer performs segmentation processing, re-segmentation processing, and recombination processing on the RLC SDU in sequence, and after adding an RLC sublayer header, obtains the data packet descriptor of the RLC PDU. The data packet descriptor of the RLC PDU includes information such as the data packet length, the address of the PDCP SDU, and the RBID.

[0117] In some embodiments, the entity of the RLC sublayer performs operations such as segmentation, re-segmentation, and recombination of the RLC SDU according to the data packet size requested by the MAC sublayer, and at the same time adds an RLC Header (header) to form an RLC PDU. The RLC sublayer delivers the data packet descriptor of the RLC PDU to the MAC sublayer.

[0118] In some embodiments, the RLC sublayer supports three transmission modes, including TM (Transparent Mode), UM (Unacknowledged Mode), and AM (Acknowledged Mode). Different RLC entities perform operations such as Segmentation (for AM and UM) and re-segmentation (for AM) of RLC SDUs, as well as Reassembly (for AM and UM) based on the size of the data packet requested by the MAC sublayer according to the authorization information from the physical layer.

[0119] Exemplarily, each RLC entity performs operations such as segmentation, re-segmentation, and reassembly of the RLC SDU according to the size of the data packet requested by the MAC, and at the same time adds an RLC Header to form an RLC PDU. The RLC delivers the descriptor of the RLC PDU (carrying information such as length, address, RBID, etc.) to the MAC sublayer.

[0120] In the above embodiments, before the MAC sublayer requests a data packet from the RLC sublayer according to the authorization information from the physical layer, the data process of the data packet further includes the processing of the PDCP sublayer and the processing operations performed by different entities of the RLC sublayer. The PDCP sublayer does not perform encryption and integrity protection on the data packet, but directly adds a PDCP sublayer header and then delivers it to the RLC sublayer, thereby reducing one read operation and one write operation to the memory, further reducing the system power consumption, and improving the system efficiency.

[0121] Figure 5 This is a flowchart of the method for encryption and integrity protection processing proposed in the embodiments of the present disclosure. Based on Figure 3 - Figure 4 the embodiments shown, Figure 5 for Figure 3 step 302 in Figure 5 a further description is provided as

[0122] Step 501: Read the target data packet from the PDCP SDUs stored in the PDCP sublayer based on the start address, data packet length, identifier of the radio bearer, and target transmission volume.

[0123] In some embodiments, the target transmission request includes the target transmission volume.

[0124] In some embodiments, the hardware accelerator connected to the MAC sublayer reads the target data packet from the cache by accessing the memory based on the start address, data packet length, identifier of the radio bearer, target transmission amount, and stored PDCP SDU. The total amount of the target data packet obtained each time is equal to the size of the target transmission amount. The target data packet is the stored PDCP SDU, that is, the PDCP SDU read from the PDCP SDU Buffer corresponding to the TB descriptor node in the TB descriptor linked list according to the target transmission amount.

[0125] In some embodiments, the MAC sublayer sends the TB descriptor linked list to the hardware accelerator through a TB Transmit Req (transmission block request). Some of the descriptor nodes point to the PDCP SDU Payload and carry information such as the COUNT value required for encryption and integrity protection, data transmission direction, identifier of the radio bearer, key, start address, data packet length, and address of the PDCP SDU.

[0126] In some embodiments, the hardware accelerator selects the corresponding descriptor node from the TB descriptor linked list according to the size of the data packet requested to be generated in the target transmission request sent by the transmission processing unit of the physical layer, and performs the corresponding payload according to the start address.

[0127] In some embodiments, the hardware accelerator sequentially reads data packets from the PDCP SDU Buffer in the memory according to the target transmission amount to obtain the target data packet. The size of the target data packet corresponds to the target transmission amount in the current target transmission request.

[0128] In some embodiments, the target transmission request is a request sent by the transmission processing unit of the physical layer to the data link layer. Each target transmission request corresponds to a target transmission amount. The target transmission amount can be at the CB (code block) level or the symbol level, or can be a fixed size value between the CB level and the symbol level. The present disclosure does not limit this.

[0129] Exemplarily, UL2A supports pipelining at the CB level or the symbol level with the transmission processing unit of the physical layer, and generates multiple corresponding transmission Payloads according to the transmission size of the CB Req request sent by the transmission processing unit of the physical layer. As Figure 6C shown, each CB Req corresponds to a TB Payload, and each TB Payload corresponds to one or more TB descriptor nodes.

[0130] In the above embodiments, the hardware accelerator of the MAC sublayer decomposes the one-time generation of the TB Payload into multiple CB Payloads or symbol Payloads according to the target transmission volume, so as to smooth the amount of data to be transmitted, thereby avoiding the instantaneous impact on the DDR bandwidth caused by the one-time generation of the transmitted Payload, improving the stability of the system, and also reducing the size of the on-chip Memory required for caching data in the transmission processing unit of the physical layer.

[0131] Step 502: Encrypt and perform integrity protection processing on the target data packet according to the COUNT value and the key to obtain an encrypted data packet.

[0132] In some embodiments, the hardware accelerator connected to the MAC sublayer performs encryption and integrity protection processing according to the obtained target data packet and the encryption information (i.e., the COUNT value and the key) contained in the descriptor node corresponding to the target data packet in the TB descriptor linked list.

[0133] In some embodiments, the encryption algorithm adopted for encryption can be a symmetric encryption algorithm (such as AES) or an asymmetric encryption algorithm (such as RSA).

[0134] In some embodiments, the encryption process can be encrypted with 128 bits or 192 bits or 256 bits, and the present disclosure is not limited thereto.

[0135] In some embodiments, integrity protection can be to generate an integrity check code for the data in the target data packet, for example, a CRC check code.

[0136] In some embodiments, the hardware accelerator obtains the target data packet according to the target transmission volume requested by each target transmission request, and performs encryption and integrity protection processing according to the COUNT value and the key contained in the descriptor node corresponding to the target data packet in the TB descriptor linked list to obtain the corresponding encrypted data packet.

[0137] Exemplarily, UL2A generates a data packet according to the packet size generated by the CB Req request sent by the transmission processing unit of the physical layer. Packet Info handling selects the corresponding descriptor from the TB descriptor link according to the starting position and obtains the corresponding Payload. If the payload is a part of the RLC SDU, it performs encryption and integrity protection processing according to the carried encryption parameters. The integrity protection of a complete RLC SDU can be calculated from the results of multiple integrity protections performed by this RLC SDU according to the CB Req.

[0138] Step 503: Store the encryption information.

[0139] In some embodiments, the encrypted information includes the end position corresponding to the target data packet for the currently transmitted encrypted data packet.

[0140] In some embodiments, the hardware accelerator stores the encrypted information corresponding to each encryption and integrity protection process in memory for subsequent retransmission and other processes.

[0141] In some embodiments, storing the encrypted information can determine the start position of encryption when performing encryption and integrity protection processing for the next target transmission request, avoiding repeated encryption of the same data packet.

[0142] Exemplarily, as Figure 6B shown in the schematic architecture diagram of the hardware accelerator, in order to avoid performing encryption and integrity protection processing on the part starting from the TB block for each CB Req, Packet Info Handling needs to store the context information related to encryption of each logical channel, including the end position of encryption for the Payload generated each time corresponding to the target data packet.

[0143] In some embodiments, after receiving the feedback information indicating successful transmission of the encrypted data packet, the encrypted information is deleted.

[0144] In some embodiments, the hardware accelerator sends the encrypted data packet obtained after completing the encryption and integrity protection processing to the transmission processing unit of the physical layer. After ensuring that the physical layer receives the encrypted data packet and then receives the feedback information indicating successful transmission, the encrypted information is deleted.

[0145] In some embodiments, when the physical layer does not receive the encrypted data packet sent for the first time, an automatic retransmission request is triggered. The hardware accelerator needs to send the encrypted data packet to the transmission processing unit of the physical layer again until the feedback information indicating successful transmission is received, and then the encrypted information is deleted.

[0146] In the above embodiments, the hardware accelerator sequentially reads the PDCP SDU in the memory according to the request of the physical layer to obtain the target data packet, and after performing encryption and integrity protection processing, sends it to the physical layer. Thus, the hardware accelerator can read, process, and send the data packet according to each demand, reducing the traffic volume and improving the data processing efficiency. In the existing related technologies, preparing all the demands of the physical layer at one time will generate a large traffic volume and cause congestion in the data transmission path.

[0147] In summary, the data processing method proposed in this disclosure can process the encryption and integrity protection of PDCP at the MAC sublayer, thereby reducing the memory access volume of the data packets delivered by the network layer in the uplink data link layer data processing flow, while reducing the DDR bandwidth requirement and system power consumption. At the same time, the data processing chip supports the transmission at the code block or symbol level between the physical layer, which can avoid the instantaneous impact on the DDR bandwidth caused by the one-time generation of the TB Payload, improve the stability of the system, and also reduce the size of the on-chip memory required for caching data in the physical layer transmission processing unit.

[0148] Figure 6A It is a UL L2 data processing flow chart. As Figure 6A shown, the data processing flow includes:

[0149] 1. The UL Layer writes the Payload of the data packet (which can be an IP packet of the DRB or a signaling packet of the control plane, that is, the PDCP SDU)

[0150] into the PDCP SDU Buffer. The PDCP SDU Buffer is generally a storage area allocated on the DDR. The PDCP SDU packet descriptor (including information such as address, length, RB ID, etc.) is informed to PDCP, and then PDCP is notified to send.

[0151] 2. PDCP does not perform encryption and integrity protection on the PDCP SDU, but directly adds the PDCP Header to generate the PDCP PDU. Then PDCP delivers the packet descriptor (PDCP PDU) (carrying information such as COUNT, DIRECTION, BEARER, KEY, etc. required for encryption and integrity protection, as well as length, address, RBID, etc.) to RLC.

[0152] 3. After the MAC receives the Grant (request / authorization) delivered by the PHY (physical layer), according to the Grant size and logical channel priority, it provides data packets to be sent of a given size from different RLC entities. Each RLC entity will perform operations such as Segmentation (AM and UM), re-segmentation (AM), and Reassembly (AM and UM) of the RLC SDU according to the size of the data packet requested by the MAC, and at the same time add the RLC Header to form the RLC PDU. RLC delivers the descriptor of the RLC PDU (carrying information such as length, address, RBID, etc.) to the MAC.

[0153] 4. The MAC adds a MAC Header to the RLC PDU to form a transport block (TB). The TB is represented by a TB descriptor link. Obviously, some of these descriptor links point to the PDCP SDU Payload and carry information such as COUNT, DIRECTION, BEARER, KEY, as well as the start address, length, address, RBID, etc., which are required for encryption and integrity protection. The addresses where the PDCP SDU Payload is stored on the DDR are not consecutive.

[0154] 5. The MAC hands over a TB descriptor link (TB descriptor linked list) to UL 2A. UL 2A reads the PDCP SDU Payload from the PDCP SDU Buffer based on this information, and after completing encryption and integrity protection, it hands it over to the transmission Buffer of the PHY TX processing unit for transmission. The transmission Buffer is generally on-chip Memory.

[0155] Figure 6B The system architecture diagram of UL 2A is as follows:

[0156] 1. The MAC sends the TB descriptor link to UL 2A through the "TB Transmit Req" command. Some of these descriptor links point to the PDCP SDU Payload and carry information such as COUNT, DIRECTION, BEARER, KEY, as well as the start address, length, address, RBID, etc., which are required for encryption and integrity protection.

[0157] 2. As Figure 6C shown in the processing schematic diagram of UL 2A, UL 2A will select the corresponding descriptor from the TB descriptor link (TB descriptor linked list) by the packet Info handling according to the size of the data packet generated by the "CBReq" (CB request) sent by the PHY TX processing unit, and perform the corresponding payload according to the start position. If the payload is part of the RLC SDU, the Cipher and Integrity will perform encryption and integrity protection processing according to the encryption parameters it carries. The integrity protection of a complete RLC SDU can be calculated from the results of multiple integrity protections performed by this RLC SDU according to the CB Req.

[0158] 3. To avoid decrypting and integrity protecting each CB Req starting from the beginning of the TB block, PacketInfo Handling needs to store the context information related to the encryption of each logical channel.

[0159] 4. The information of the TB descriptor link is released only after HARQ retransmission to support HARQ retransmission and CBG retransmission.

[0160] In summary, the above-mentioned UL 2A hardware accelerator architecture and the mechanism of placing the encryption and integrity protection of PDCP in the MAC execution reduce the access to the DDR for the data packets delivered by the UL Layer in the UL data processing flow, reducing the DDR bandwidth requirement and system power consumption. At the same time, UL2A supports pipelining at the CB level or symbol level with the TX processing unit of the physical layer, which can avoid the instantaneous impact on the DDR bandwidth caused by generating the TB Payload at one time, improve the system stability, and also reduce the on-chip memory size required for caching data in the PHY TX processing unit.

[0161] Figure 7 It is a schematic structural diagram of the data processing device according to the embodiment of the present disclosure. As Figure 7 shown, the data processing device includes:

[0162] A generating unit 701, configured to obtain a radio link control sublayer protocol data unit RLC PDU according to a logical channel priority and authorization information, add a media access control MAC sublayer header to the RLC PDU, and generate a transmission block TB descriptor linked list, where the TB descriptor linked list includes encryption parameters;

[0163] A processing unit 702, configured to sequentially perform encryption and integrity protection processing on a target data packet according to a target transmission request and the TB descriptor linked list.

[0164] In some embodiments, the TB descriptor linked list includes at least one of the following: COUNT value; data transmission direction; identifier of a radio bearer; key; start address; data packet length; address of a packet data convergence protocol sublayer data transmission unit PDCPSDU.

[0165] In some embodiments, the processing unit is further configured to read a target data packet from a packet data convergence protocol sublayer stored data transmission unit PDCP SDU based on a start address, a data packet length, an identifier of a radio bearer, and a target transmission amount, where the target transmission request includes the target transmission amount; perform encryption and integrity protection processing on the target data packet according to the COUNT value and the key to obtain an encrypted data packet; and store encryption information, where the encryption information includes an end position in the target data packet corresponding to the currently transmitted encrypted data packet.

[0166] In some embodiments, the processing unit is further configured to delete the encryption information after receiving the feedback information indicating successful transmission of the encrypted data packet.

[0167] In summary, the data processing apparatus proposed in the present disclosure can move the processes of PDCP encryption and integrity protection processing to the last sublayer of the data link layer, so that in the uplink data link layer data processing flow, the memory access volume of the data packet delivered by the network layer is reduced, and at the same time, the DDR bandwidth requirement and system power consumption are reduced; at the same time, the last sublayer supports the transmission at the code block or symbol level between the physical layer, which can avoid the instantaneous impact on the DDR bandwidth caused by the data packet generated for transmission at one time, improve the stability of the system, and also reduce the size of the on-chip memory required for the physical layer to cache data.

[0168] Figure 8 FIG. 800 is a schematic structural diagram of an electronic device for implementing the above data processing method according to an exemplary embodiment.

[0169] Referring to Figure 8 , the electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0170] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, telephone call, data communication, camera operation, and recording operation. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0171] The memory 804 is configured to store various types of data to support the operation of the electronic device 800. Examples of these data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disc.

[0172] The power supply component 806 provides power for various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0173] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0174] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 further includes a speaker for outputting audio signals.

[0175] The I / O interface 812 provides an interface between the processing component 802 and a peripheral interface module, and the peripheral interface module can be a keyboard, a click wheel, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a power-on button, and a lock button.

[0176] The sensor assembly 814 includes one or more sensors for providing status assessments of various aspects for the electronic device 800. For example, the sensor assembly 814 can detect the on / off state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800. The sensor assembly 814 can also detect changes in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and temperature changes of the electronic device 800. The sensor assembly 814 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0177] The communication component 816 is configured to facilitate communication between the electronic device 800 and other devices in a wired or wireless manner. The electronic device 800 can access a wireless network based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (New Radio), or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0178] In an exemplary embodiment, the electronic device 800 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described methods.

[0179] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as the memory 804 including instructions that can be executed by the processor 820 of the electronic device 800 to complete the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0180] Embodiments of the present disclosure also propose an electronic device, including: a main board and a chip as described in the above embodiments of the present disclosure.

[0181] Embodiments of the present disclosure also propose a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the data processing method described in the above embodiments of the present disclosure.

[0182] Embodiments of the present disclosure also propose a computer program product, including a computer program, where the computer program, when executed by a processor, implements the data processing method described in the above embodiments of the present disclosure.

[0183] Figure 9 is a schematic structural diagram of a chip 900 for implementing the above data processing method shown according to an exemplary embodiment. Refer to Figure 9 , the chip 900 includes at least one communication interface 901 and a processor 902. The communication interface 901 is used to receive signals input to the chip 900 or signals output from the above chip 900. The processor 902 communicates with the communication interface 901 and implements the data processing method described in the above embodiments of the present disclosure through logic circuits or by executing code instructions.

[0184] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described here can be implemented in an order different from those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0185] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0186] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present disclosure includes additional implementations, where functions may be performed in an order not shown or discussed, including in a substantially simultaneous manner or in a reverse order according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0187] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing a logical function, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. As used in this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of the computer-readable medium include the following: an electrical connection (control method) having one or more wirings, a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or other suitable processing as necessary, and then stored in a computer memory.

[0188] It should be understood that various parts of the embodiments of the present disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following techniques known in the art or a combination thereof can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), and the like.

[0189] Those of ordinary skill in the art can understand that all or part of the steps carried out in implementing the above-described embodiment methods can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0190] In addition, in each of the various embodiments of the present disclosure, the functional units can be integrated in a processing module, or each unit can exist physically alone, or two or more units can be integrated in a module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disk, etc.

[0191] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A chip, characterized in that, It includes: A reading module, a processing module, and a sending module. The reading module is respectively connected to the processing module, the media access control (MAC) sublayer of the data link layer, and the transmission processing unit of the physical layer. The sending module is respectively connected to the processing module and the transmission processing unit of the physical layer; The reading module is used to obtain a target transmission request from the transmission processing unit of the physical layer and obtain a transmission block (TB) descriptor linked list from the MAC sublayer. The processing module is used to encrypt and perform integrity protection processing on target data packets in sequence according to the TB descriptor linked list according to the target transmission amount to obtain encrypted data packets. The target transmission request includes the target transmission amount; The sending module is used to send the encrypted data packets to the transmission processing unit of the physical layer.

2. The chip according to claim 1, wherein the reading module is further used to read target data packets from the packet data convergence protocol (PDCP) sublayer of the data link layer based on the TB descriptor linked list and the target transmission request.

3. The chip according to claim 2, wherein the TB descriptor linked list includes at least one of the following: COUNT value; Data transmission direction; Identifier of the radio bearer; Key; Starting address; Packet length; Address of the PDCP service data unit (SDU).

4. The chip according to claim 3, wherein the reading module is further used to read the target data packets from the PDCP SDUs stored in the PDCP sublayer based on the starting address, the packet length, the identifier of the radio bearer, and the target transmission amount; the processing module is further used to perform the encryption and integrity protection processing on the target data packets according to the COUNT value and the key to obtain the encrypted data packets; the reading module is further used to store encryption information, and the encryption information includes the end position of the currently transmitted encrypted data packet corresponding to the target data packet.

5. The chip according to claim 4, wherein, the reading module is further used to delete the encryption information after receiving the feedback information indicating successful transmission of the encrypted data packet.

6. A data processing method, characterized in that The method includes: Obtaining a radio link control (RLC) protocol data unit (PDU) of the sublayer according to the logical channel priority and authorization information, and adding a media access control (MAC) sublayer header to the RLC PDU to generate a transmission block (TB) descriptor linked list, where the TB descriptor linked list includes encryption parameters; Performing encryption and integrity protection processing on target data packets in sequence according to the target transmission request and the TB descriptor linked list.

7. The method according to claim 6, wherein The TB descriptor linked list includes at least one of the following: COUNT value; Data transmission direction; Identifier of the radio bearer; Key; Starting address; Packet length; Address of the packet data convergence protocol sublayer data transmission unit (PDCP SDU).

8. The method according to claim 7, wherein The performing encryption and integrity protection processing on target data packets in sequence according to the target transmission request and the TB descriptor linked list includes: Read the target data packet from the packet data convergence protocol (PDCP) sub-layer stored data transmission unit (PDCP SDU) based on the starting address, the data packet length, the identifier of the radio bearer, and the target transmission amount, where the target transmission request includes the target transmission amount; Perform the encryption and integrity protection processing on the target data packet according to the COUNT value and the key to obtain an encrypted data packet; Store the encryption information, where the encryption information includes the ending position in the target data packet corresponding to the currently transmitted encrypted data packet.

9. The method according to claim 8, characterized in that, The method further includes: After receiving the feedback information indicating successful transmission of the encrypted data packet, delete the encryption information.

10. A data processing device, characterized in that, Includes: A generating unit, configured to obtain a radio link control (RLC) sub-layer protocol data unit (RLC PDU) according to the logical channel priority and the authorization information, and add a media access control (MAC) sub-layer header to the RLC PDU to generate a transmission block (TB) descriptor linked list, where the TB descriptor linked list includes encryption parameters; A processing unit, configured to perform the encryption and integrity protection processing on the target data packet sequentially according to the target transmission request and the TB descriptor linked list.

11. An electronic device, characterized in that, Includes: A processor and a memory for storing a computer program capable of running on the processor, wherein, when the processor is used to run the computer program, it executes the method according to any one of claims 6-9.

12. An electronic device, characterized in that, Includes: A main board and a chip as described in claims 1-5.

13. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 6-9.

14. A chip, characterized in that, Includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method according to any one of claims 6-9 through logic circuits or by executing code instructions.

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