BGP (Border Gateway Protocol) network flow migration verification method based on FPGA (Field Programmable Gate Array) acceleration

Abstract

The invention provides a BGP (Border Gateway Protocol) network traffic migration verification method based on FPGA (Field Programmable Gate Array) acceleration, which comprises the following steps: collecting traffic characteristic data and topological information before and after network configuration change, and extracting traffic equivalence classes including a source IP (Internet Protocol) address, a destination IP address and a service quality parameter; dynamically analyzing the data of the traffic equivalence class by a CPU (Central Processing Unit), and converting network topology into graph model representation of a node set and an edge set; uniquely converting the graph model representation by an FPGA (Field Programmable Gate Array) to generate a deterministic state machine model; and comparing the standardized data sequences of the state machine before and after migration in real time by using the parallel computing capability of the FPGA, and if the serialization results of the node set and the edge set are completely consistent, judging that the traffic migration behavior is equivalent.

Description

Technical Field

[0001] The present invention belongs to the technical field of BGP traffic migration verification in the field of computer networks, and particularly relates to a method for verifying BGP network traffic migration based on FPGA acceleration, which is used to efficiently verify the equivalence of large-scale network configuration changes and ensure the consistency of network behavior during the traffic migration process. Background Art

[0002] In modern computer networks, the verification of traffic migration in BGP (Border Gateway Protocol) networks is crucial for ensuring the stability, reliability, and correctness of the network. With the continuous expansion of the network scale and the increasing complexity of business requirements, network administrators need to frequently adjust and optimize network configurations. These configuration changes may introduce various errors, such as traffic loss, routing loops, network congestion, etc., resulting in a decline in network performance and even service interruption. Therefore, verifying the traffic migration in BGP networks to ensure that configuration changes do not introduce errors has become a key issue in network management.

[0003] Traditional traffic migration verification methods mainly rely on manual verification, that is, network administrators check whether there are differences in traffic behavior by comparing the network states before and after configuration changes. However, manual verification is not only time-consuming and laborious but also error-prone. Especially in a large-scale network environment, the efficiency of manual verification is extremely low and it is difficult to meet the actual needs. In recent years, automated verification methods have gradually received attention. These methods represent the forwarding behavior of the network by constructing state machines and verify the correctness of traffic migration by comparing the state machines before and after configuration changes. However, existing automated verification methods are mainly implemented based on CPUs in software, facing problems such as poor scalability and large computational overhead. In a large-scale network environment, the verification time of these methods will increase significantly with the increase of the network scale, resulting in low verification efficiency and being unable to detect and correct configuration errors in a timely manner.

[0004] Existing automated verification methods also have certain limitations when dealing with dynamic network environments. The traffic patterns and topological structures in the network may change over time, and existing methods often have difficulty quickly adapting to these changes, affecting the accuracy and timeliness of verification results. Summary of the Invention

[0005] Aiming at the defects and deficiencies existing in the prior art, the present invention provides a method for verifying BGP network traffic migration based on FPGA acceleration, which solves the problem of low efficiency in verifying configuration changes in large-scale dynamic networks through a software-hardware co-design architecture and pipeline optimization design. The core innovations of this solution include:

[0006] Domain-specialized software-hardware co-architecture: Separate the dynamic data preprocessing (TEC parsing, topology standardization) of the CPU from the parallel state machine construction and equivalence verification of the FPGA, and achieve a significant improvement in verification efficiency through hardware offloading.

[0007] Unique deterministic state machine generation technology: Based on the pipelined operations of node sorting, index remapping, and edge sorting, transform the dynamic network topology into a uniquely determined state machine model, eliminate redundant calculations in traditional methods, and greatly reduce storage overhead.

[0008] FPGA parallel serialization comparison algorithm: Use the pipelined architecture to process multiple groups of traffic equivalence class (TEC) data simultaneously, and match the node and edge sets item by item through the standardized sequence format (text / binary) to achieve high-throughput and low-latency real-time verification.

[0009] Dynamic network adaptability optimization: Support large-scale network environments with dynamic adjustment of BGP routing policies (such as route aggregation, path policy change). Through compact index mapping and resource allocation strategies, ensure service continuity and verification real-time under complex topology changes.

[0010] The present invention is applicable to carrier-grade BGP networks, significantly improving the verification efficiency and reliability of configuration changes, and filling the gap in the combination of hardware acceleration and dynamic network scenarios in the prior art.

[0011] The technical solution specifically adopted by the present invention to solve its technical problems is:

[0012] A method for verifying BGP network traffic migration based on FPGA acceleration, comprising the following steps:

[0013] Collect traffic characteristic data and topology information before and after network configuration changes, and extract traffic equivalence classes, including source IP address, destination IP address, and quality of service parameters;

[0014] Dynamically parse the data of the traffic equivalence classes by the CPU, and transform the network topology into a graph model representation of a node set and an edge set;

[0015] Perform a uniquification transformation on the graph model representation by the FPGA to generate a deterministic state machine model;

[0016] Utilize the parallel computing power of the FPGA to compare the standardized data sequences of the state machines before and after migration in real time. If the serialization results of the node set and the edge set are exactly the same, it is determined that the traffic migration behavior is equivalent.

[0017] Furthermore, the traffic characteristic data is collected by snapshot, covering the complete network state before and after configuration changes, and the network topology is represented by a directed graph, where the nodes are network devices and the edges are the forwarding paths between devices.

[0018] Furthermore, the graph model representation includes a node set and an edge set, and is converted by the CPU into a standardized format that can be processed by the FPGA.

[0019] Furthermore, the unique transformation includes:

[0020] Sort the nodes in lexicographic order of their device unique identifiers;

[0021] Assign consecutive indices to the sorted nodes;

[0022] Sort the edge set by source and target nodes based on the index.

[0023] Furthermore, the standardized data sequence is generated by a serialization algorithm, the serialization format is text or binary data, and the serialization result includes an ordered arrangement of a node set and an edge set.

[0024] Furthermore, the FPGA uses a pipeline architecture to perform the following operations in parallel:

[0025] Simultaneously build state machine models corresponding to multiple traffic equivalence classes;

[0026] While building the state machine, perform equivalence verification on the generated state machine.

[0027] Furthermore, the storage resource usage is optimized by index remapping, and the original device identifier is mapped into a compact continuous index to reduce the memory usage of the state machine data.

[0028] Furthermore, it supports BGP configuration changes in dynamic network environments, including routing policy adjustments, device additions and reductions, and real-time verification of the equivalence of traffic migration after the changes.

[0029] Furthermore, during the FPGA parallel comparison process, high-throughput equivalence verification is achieved by matching the serialized data of nodes and edges one by one.

[0030] And, an FPGA, used to execute the above method.

[0031] And, an electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the program.

[0032] A non-transitory computer-readable storage medium stores a computer program, which implements the steps of the method described above when executed by a processor.

[0033] Compared with the prior art, the present invention and its preferred embodiments include at least the following beneficial effects:

[0034] Significantly improve the verification efficiency of large-scale BGP networks: Through a software-hardware collaborative architecture, separate the preprocessing of dynamic data from computationally intensive tasks, and use FPGA parallel acceleration to construct state machines and perform equivalence verification, overcoming the performance bottleneck of traditional pure CPU solutions and achieving high-performance verification.

[0035] Ensure the accuracy of network behavior consistency verification: Based on the unique transformation of network topologies (node sorting, index remapping, and edge sorting), generate a deterministic state machine model, eliminating the risk of misjudgment caused by differences in topology representation in traditional methods and ensuring the strict equivalence of verification results.

[0036] Adapt to high-throughput verification in dynamic network environments: Through a pipeline architecture, parallel process multiple groups of traffic equivalence class data, support real-time verification requirements for scenarios such as routing policy adjustment and device addition or removal, and avoid the problem of lag in response to dynamic topology changes in existing technologies.

[0037] Optimize storage and computing resource occupancy: Adopt a compact index mapping and a standardized sequence format to reduce the memory overhead of state machine data. At the same time, improve the utilization rate of hardware resources through a task parallelization strategy to meet the deployment requirements of ultra-large-scale networks. Brief Description of the Drawings

[0038] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:

[0039] Figure 1 It is a schematic diagram and flowchart of the overall architecture of the embodiment solution of the present invention.

[0040] Figure 2 It is an example diagram of the software-hardware function boundary division of the embodiment of the present invention.

[0041] Figure 3 It is an example diagram of the state machine pipeline construction of the embodiment of the present invention.

[0042] Figure 4 It is an example diagram of the state machine equivalence verification of the embodiment of the present invention.

[0043] Figure 5 It is a flowchart of the core steps of the embodiment of the present invention. Detailed Description of the Invention

[0044] To make the features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail as follows:

[0045] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used in this specification have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0046] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0047] In order to ensure the efficiency and stability of traffic migration verification in a large-scale network environment, an embodiment of the present invention provides a BGP network traffic migration verification method based on FPGA acceleration. By constructing a software and hardware collaborative computing architecture, combining the parallel computing ability of FPGA and the state machine serialization technology, the efficient verification of BGP traffic migration is realized. Four main steps, namely TEC data collection, software and hardware boundary division, state machine construction, and equivalence judgment, are adopted to achieve the efficient verification of BGP network traffic migration. Among them, the CPU is responsible for data preprocessing and task scheduling, while the FPGA executes the computationally intensive state machine comparison to make full use of the hardware parallel ability. By optimizing the state machine construction process through device sorting, re-numbering, and edge sorting, the consistency of network behavior before and after traffic migration is ensured. At the same time, a pipeline architecture is adopted to optimize computing resources and improve the throughput rate. It can provide high-speed traffic migration verification in a large-scale network environment while ensuring low storage overhead, and is applicable to the real-time verification requirements of complex BGP network configuration changes. Utilizing the parallel computing ability of FPGA, the state machine construction and equivalence verification processes are accelerated, thereby improving the verification speed, reducing the computing overhead, and ensuring the stability and reliability of network configuration changes.

[0048] The implementation of the solution generally includes the following steps:

[0049] 1) TEC data collection: By capturing data snapshots before and after network configuration changes, traffic equivalence classes (TECs) are extracted to obtain traffic characteristic data, including source IP, destination IP, and QoS parameters, and network topology information is constructed; by taking snapshots of the network at different time points or before and after different configuration changes, key fields such as source IP, destination IP, and QoS are extracted to form complete traffic equivalence classes;

[0050] 2) Software and hardware boundary division: During the verification process, the CPU is responsible for dynamic data preprocessing and TEC data organization, while the FPGA executes the computationally intensive state machine equivalence verification to make full use of the hardware parallel ability; sequential processing operations such as parsing large-scale and dynamic TEC data are assigned to the CPU side, and the computationally intensive state machine construction and equivalence verification operations are offloaded to the FPGA for execution;

[0051] 3) State machine construction: Based on the TEC data, state machines before and after traffic migration are constructed respectively. Among them, network devices are mapped to states, and the connection relationships between devices are mapped to state transitions. The pipeline calculation is used to optimize the state machine construction process; for each TEC, state machines before and after migration are constructed respectively. By sorting and remapping the nodes and ordering the edges, unique and comparable state machine data are obtained;

[0052] 4) Equivalence judgment: Utilize the parallel processing ability of FPGA, and based on the serialization matching algorithm, compare the state machines to ensure the equivalence before and after traffic migration, and optimize the calculation resource allocation to improve the throughput. On the FPGA side, the state machines before and after migration constructed above are compared one by one. If the two are exactly the same in the serialization results of nodes and edges, it is determined that the BGP traffic behavior corresponding to this TEC is equivalent before and after migration.

[0053] Among them, the TEC data collection process includes parsing the data snapshots before and after network configuration changes, extracting traffic equivalence classes, and constructing network topology information based on traffic characteristics. The network topology is represented by a graph model, where nodes correspond to network devices and edges represent the forwarding relationships between devices for subsequent state machine construction and equivalence judgment.

[0054] In an embodiment of the present invention, the TEC data collection step specifically includes the following process: First, network snapshot data are collected at two different times before and after configuration migration of the network. Each snapshot contains traffic characteristic data ipTrafficKeys, and network topology structure data graphBefore and graphAfter. Among them, ipTrafficKeys are used to define the specific traffic characteristics of traffic equivalence classes (TECs). Each record consists of a source IP address (srcIp), a destination IP address (dstIp), and a quality of service parameter (qos), and is represented as a set:

[0055]

[0056] where n represents the total number of traffic entries. At the same time, graphBefore and graphAFter describe the network topology before and after migration in the form of a directed graph, which is specifically composed of a network device set (node set) V and a device - to - device connection relationship set (edge set) E, and is represented as:

[0057] graphBefore=(V before ,E before ), graphAfter=(V after ,E after )

[0058] Among them, each edge in the edge set E represents the forwarding path relationship between device nodes in the network, and each node in the node set V represents an actual network device, such as a router, etc.

[0059] The software and hardware boundary division adopts a task division strategy. Among them, the CPU is responsible for TEC data parsing, traffic feature extraction, and state machine data preprocessing, while the FPGA executes state machine construction and equivalence verification. By reasonably allocating computing tasks, the computing burden of the CPU is reduced, and the overall verification efficiency is improved.

[0060] In an embodiment of the present invention, the software and hardware boundary division steps include the clear definition and allocation of tasks to efficiently utilize the respective advantages of the CPU and the FPGA. Specifically, since the network snapshot data is large in scale and complex in structure, it is more suitable for serial parsing and preprocessing by the CPU; while the state machine construction and equivalence verification have obvious parallelism and are more suitable for being completed by FPGA hardware acceleration. Therefore, the CPU side is first responsible for parsing the TEC data, including the extraction of traffic feature fields, the sorting of the topological structure, and the conversion of the data into a standardized format required for state machine construction; then, the preprocessed data is transmitted to the FPGA side. After obtaining the preprocessed data, the FPGA uses its parallel computing ability to quickly perform subsequent state machine construction and state machine equivalence judgment, thereby greatly improving the verification efficiency.

[0061] During the state machine construction process, the FPGA adopts a pipeline architecture to optimize the state construction process, including device sorting, re-numbering, and state transition storage optimization, to ensure the efficient construction of the state machine, reduce the computing overhead, and improve the data throughput rate.

[0062] In an embodiment of the present invention, the state machine construction steps include using a serialization algorithm to convert network topology data into a state machine representation form. The specific process is as follows: First, sort the device nodes (V) in the network topology data according to the unique identifier of the nodes to obtain an ordered sequence of devices; then re-number the sorted nodes to obtain the remapped node set V'. The re-numbering process is based on the node positions in the ordered sequence to ensure that the representation of the state machine nodes is compact and unique; finally, perform a sorting operation on the edge set E in the network, that is, order the edge set according to the node indexes after re-numbering to obtain the serialized edge set E'. Through the combined processing of the above sorting and re-numbering, the finally obtained state machine data is represented as:

[0063] SM=(S,T), S = V', T = E'

[0064] Among them, S is the state set, T is the state transition set, and the definition of the state transition is from the source node s i to the target node s jThe mapping relationship is an edge in the state machine:

[0065] t ij =(s i ,s j ),s i ,s j ∈S

[0066] During the equivalence judgment process, FPGA uses parallel computing capabilities to compare multiple state machines simultaneously, and uses a serialized matching algorithm to convert the state machine into a standard format for high-speed matching. This method uses pipeline processing to gradually parse and compare state machine data, and ultimately determines whether traffic remains equivalent before and after migration.

[0067] The equivalence judgment uses an FPGA pipeline architecture to enable the state machine construction and verification process to be executed in parallel, improve throughput, optimize computing resource allocation, reduce storage resource usage, and ensure efficient verification in a large-scale network environment. The pipeline architecture can process multiple TEC data sets at the same time, support data parallelism and task parallelism, and improve the throughput of equivalence verification.

[0068] In one embodiment of the present invention, the state machine equivalence determination step is executed in parallel by the FPGA, and the serialization results of the state machines before and after the migration are efficiently compared to quickly determine whether the two state machines are completely consistent. Specifically, the state machine SM before migration obtained in the aforementioned state machine construction step is used. pre =(S pre ,T pre ) and the post-migration state machine SM post =(S post ,T post ), the FPGA compares the serialized data of the two state machines one by one in parallel in hardware and That is, compare whether the ordered sequences of the node sets and edge sets of the two state machines are consistent item by item:

[0069]

[0070] The solution is applicable to large-scale BGP networks and can realize rapid verification of traffic migration in a dynamic network environment, adapt to complex network topology change requirements, and improve network security and stability. The method supports multiple BGP protocol configurations, including route aggregation, route filtering, and path policy adjustment, to meet the needs of different operator networks and ensure business continuity and consistency during traffic migration.

[0071] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings.

[0072] like Figure 5As shown in the figure, the present invention provides a method for verifying the traffic migration of the Border Gateway Protocol (BGP) accelerated by a Field-Programmable Gate Array (FPGA). By constructing an efficient state machine model and utilizing the parallel computing ability of the FPGA, the verification process of traffic equivalence classes is optimized, and the equivalence verification efficiency of BGP configuration changes is improved. The method includes the following steps:

[0073] 1) Divide the software and hardware function boundaries, and extract the traffic equivalence class data before and after migration;

[0074] 2) Construct a state machine model in a pipeline. Based on device node sorting, index remapping, and edge sorting, generate a standardized state machine representation;

[0075] 3) Perform parallel computing for state machine equivalence verification. Execute pipeline parallel computing on the FPGA, compare multiple traffic equivalence classes, and determine whether they are equivalent before and after network migration.

[0076] The following is the specific implementation process of an application example of the present invention.

[0077] Please refer to Figure 1 , the present invention includes three main parts: software and hardware function boundary division, state machine construction, and parallel equivalence verification.

[0078] (1) Software and hardware function boundary division

[0079] In the present invention, the division of software and hardware function boundaries is a key link for realizing efficient network traffic migration verification. Specifically, the function boundary division strategy reasonably allocates tasks to the Central Processing Unit (CPU) and the Field-Programmable Gate Array (FPGA) according to the processing characteristics of network traffic data, so as to give full play to the respective advantages of software and hardware, as Figure 2 shown. The CPU is mainly responsible for the acquisition and preprocessing of traffic equivalence class (TEC) data, including extracting and parsing IP traffic keywords (ipTrafficKeys), and the topological maps before and after network migration, denoted as graph Before and graph After respectively. The preprocessing process involves a large amount of dynamic and sequentially executed data operations, which is suitable for the serial processing mode of the CPU.

[0080] The FPGA is responsible for processing computationally intensive tasks, namely state machine construction and equivalence verification. In the state machine construction stage, the FPGA first transforms the network topology into a deterministic state machine model through pipeline operations such as node sorting, reindexing, and edge sorting. Specifically, the set of device nodes in the network is denoted as D = {d1, d2,..., d n}, and after sorting, an ordered set D is obtainedsorted = {d'1, d'2, …, d' n}, satisfying d'1 < d'2 < … < d' n ; After remapping, the device index is denoted as the set D' = {d'1, d'2, …, d' n}, ensuring that each device has a unique and optimized identifier. In the equivalence verification stage, the FPGA parallelly compares the serialized data of the state machines constructed before and after migration, greatly improving the network migration verification speed.

[0081]

[0082]

[0083] (2) Pipeline construction state machine model

[0084] The pipeline construction state machine model method of the present invention includes three consecutive steps: node sorting, index remapping, and edge sorting, aiming to quickly and accurately map the network topology structure to the state machine representation, as Figure 3 shown. First, the node sorting step sorts the node set based on the unique identifiers of the network device nodes. Assume the device node set is: D = {d1, d2, …, d n}, after sorting, the device nodes obtain the following ordered set:

[0085] D sorted = {d′1, d′2, …, d′ n}.

[0086] Secondly, the index remapping step reassigns new indexes to each device according to the sorted node set to achieve an optimized and efficient representation of the state machine in hardware. The new index set is represented as follows:

[0087] E{e ij |e ij represents the connection from device d i to device d j}.

[0088] Convert this connection relationship into the transfer set in the state machine:

[0089] T = {t ij |t ij represents the transfer from state s i to state s j}

[0090] The index of each device node is unique and ordered, which simplifies the data structure in hardware implementation. Finally, in the edge sorting stage, the connection relationship between devices in the network is mapped to the transition relationship in the state machine. Through the above-mentioned clear and continuous pipeline operations, the present invention ensures the efficiency and unique determinacy of state machine construction, avoiding repeated calculations and resource waste.

[0091] (3) Parallel computing for state machine equivalence verification

[0092] The present invention uses a parallel computing method to efficiently perform state machine equivalence verification on an FPGA. State machine equivalence verification quickly determines whether network migration maintains the consistency of traffic forwarding behavior by comparing the serialized representations of the state machines before and after migration, as Figure 4 shown. Assume that the state machines before and after migration are respectively represented as: SM pre =(S pre , T pre ), SM post =(S post , T post ) where S pre and S post respectively represent the state sets in the state machines before and after migration, and T pre and T post respectively represent the transition sets in the state machines before and after migration. On the FPGA, the state machine data is serialized into a unified and determined text or binary format, represented by the function $S(\cdot)$. The state machines before and after migration are serialized as:

[0093]

[0094] The FPGA hardware performs parallel comparison of the serialized data of multiple state machines to determine whether the following equation holds:

[0095]

[0096] If the serialized data is exactly the same, it is determined that the state machines before and after network migration are equivalent; otherwise, it is determined to be non-equivalent. This method makes full use of the parallel processing ability of the FPGA, significantly reducing the complexity and time overhead of equivalence verification, and achieving fast and efficient verification of large-scale network migration tasks.

[0097] Based on the same inventive concept, the present invention further provides a computer device, which includes: one or more processors, and a memory for storing one or more computer programs; the program includes program instructions, and the processor is configured to execute the program instructions stored in the memory. The processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and is used to implement one or more instructions, specifically for loading and executing one or more instructions in the computer storage medium to implement the above method.

[0098] It should be further noted that, based on the same inventive concept, the present invention further provides a computer storage medium, on which a computer program is stored, and the computer program, when run by a processor, executes the above method. The storage medium may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may, for example, but not be limited to, an electrical, magnetic, optical, electrical, magnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection having one or more wires, a portable computer disk, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or combined with an instruction execution system, apparatus, or device.

[0099] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the ordinary meanings understood by those with ordinary skills in the field to which the present invention pertains. The "first", "second" and similar terms used in the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0100] As described above, it is only the preferred embodiment of the present invention, and it is not a limitation to the present invention in other forms. Any person skilled in the art may use the technical content disclosed above to make changes or modifications into equivalent embodiments with equivalent changes. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solution content of the present invention still fall within the protection scope of the technical solution of the present invention.

[0101] The present invention is not limited to the above best mode. Anyone inspired by the present invention can obtain various other forms of a method for verifying BGP network traffic migration based on FPGA acceleration. All equal changes and modifications made according to the scope of the patent application of the present invention shall fall within the coverage scope of the present invention.

Claims

1. A method for verifying BGP network traffic migration based on FPGA acceleration, characterized in that The following steps are involved: Collect traffic characteristic data and topology information before and after network configuration changes, and extract traffic equivalence classes, including source IP address, destination IP address, and service quality parameters; The CPU dynamically analyzes the data of the traffic equivalence class and converts the network topology into a graph model representation of a node set and an edge set; The FPGA performs unique conversion on the graphical model representation to generate a deterministic state machine model; By utilizing the parallel computing capability of FPGA, the standardized data sequences of the state machines before and after migration are compared in real time. If the serialization results of the node set and the edge set are exactly the same, the traffic migration behavior is determined to be equivalent.

2. The method for verifying BGP network traffic migration based on FPGA acceleration according to claim 1, wherein: The traffic characteristic data is collected in a snapshot manner, covering the complete network status before and after the configuration change, and the network topology is represented by a directed graph, with nodes being network devices and edges being forwarding paths between devices.

3. A method for verifying BGP network traffic migration based on FPGA acceleration according to claim 1, characterized in that: The graph model representation includes a node set and an edge set, and is converted by the CPU into a standardized format that can be processed by the FPGA.

4. According to the method for verifying BGP network traffic migration based on FPGA acceleration according to claim 1, it is characterized in that: The unique transformation includes: Sort the nodes in lexicographic order of their device unique identifiers; Assign consecutive indices to the sorted nodes; Sort the edge set by source and target nodes based on the index.

5. A method for verifying BGP network traffic migration based on FPGA acceleration according to claim 1, characterized in that: The standardized data sequence is generated by a serialization algorithm, the serialization format is text or binary data, and the serialization result includes an ordered arrangement of a node set and an edge set.

6. The BGP network traffic migration verification method based on FPGA acceleration according to claim 1 is characterized in that: The FPGA uses a pipeline architecture to perform the following operations in parallel: Simultaneously build state machine models corresponding to multiple traffic equivalence classes; While building the state machine, perform equivalence verification on the generated state machine.

7. A method for verifying BGP network traffic migration based on FPGA acceleration according to claim 1, characterized in that: The storage resource usage is optimized by index remapping, mapping the original device identifier to a compact continuous index to reduce the memory usage of the state machine data.

8. A method for verifying BGP network traffic migration based on FPGA acceleration according to claim 1, characterized in that: Supports BGP configuration changes in dynamic network environments, including routing policy adjustments, device additions and deletions, and real-time verification of traffic migration equivalence after changes.

9. A method for verifying BGP network traffic migration based on FPGA acceleration according to claim 1, characterized in that: During the FPGA parallel comparison process, high-throughput equivalence verification is achieved by matching the serialized data of nodes and edges one by one.

10. An FPGA, characterized in that: Used to execute the method according to any one of claims 1 to 9.

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