TBC battery and preparation method thereof

Abstract

The invention relates to a TBC battery and a preparation method thereof. The preparation method comprises the following steps: S1, depositing a tunneling oxide layer and a polycrystalline silicon layer; S2, depositing a dopant source layer of first conductive type impurities and a mask layer; S3, opening a film and cleaning; according to the invention, the process flow is simplified, the series resistance is obviously reduced, the current density is improved, the passivation performance and the UV attenuation resistance of the TBC battery are improved, and the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and particularly relates to a TBC cell and a preparation method thereof. Background Art

[0002] A solar cell is a device that directly converts solar energy into electrical energy, and its working principle is based on the photovoltaic effect. An IBC (Interdigitated Back Contact) cell and a TOPcon (Tunnel Oxide Passivated Contact) cell can be stacked to form a TBC cell. The TBC cell absorbs the tunneling oxide passivated contact technology of the TOPCon cell and the technology of preparing P regions and N regions arranged in an interdigitated and spaced manner on the back surface of the IBC cell. In the existing process route, in order to prepare the N+ region, the local P+ region, and the isolation region therebetween (the structure formed by the combination of these three is usually called the P-I-N structure), two high-temperature doping processes, two amorphous silicon formation processes, two laser processes, and multiple mask processes are required. The process is cumbersome and the process time is long, which seriously affects the production capacity, causes additional manufacturing costs, and there are too many high-temperature processes in the existing process route. Two high-temperature dopings (phosphorus doping temperature is 700 - 1000 °C, boron doping temperature is 900 - 1200 °C), which greatly affect the minority carrier lifetime of the substrate silicon wafer and thus have an adverse effect on the cell efficiency.

[0003] Currently, in the related art, two high-temperature doping processes, two amorphous silicon formation processes, two laser processes, and multiple mask processes are required. The process is cumbersome and the process time is long, which seriously affects the production capacity, causes additional manufacturing costs, and there are too many high-temperature processes in the existing process route, two high-temperature dopings; at the same time, because some TBC cell processes need to add high-temperature and wet processes again for manufacturing FSF, the process of manufacturing FSF will be directly omitted.

[0004] The existing crystalline silicon solar cell technology has the following problems: 1. In order to reduce high-temperature and wet processes, the preparation of FSF is not carried out, resulting in efficiency loss; 2. The BSG thickness is relatively thick, the thickness > 100 nm and the oxygen content of the silicon wafer is relatively high, the B-O recombination is serious and the boron diffusion or phosphorus diffusion temperature is relatively high; 3. It needs to go through multiple high-temperature, film opening, masking, and wet processes. The process is cumbersome, the pollution is large, and the process time is long, which is not conducive to the introduction of mass production processes and reduces the cell efficiency. Summary of the Invention

[0005] CVD as mentioned in the present application refers to Chemical Vapor Doping.

[0006] BSG as mentioned in the present application refers to Borosilicate Glass.

[0007] The PSG described in this application refers to Phosphosilicate glass.

[0008] The FSF described in this application refers to Front Surface Field.

[0009] The BSF described in this application refers to Back Surface Field.

[0010] In order to simplify the process flow, precisely adjust the phosphorus and boron doping levels of the front surface field and the back surface field, significantly reduce the series resistance, increase the current density, improve the passivation performance and anti-UV attenuation performance of the TBC cell, and improve the cell conversion efficiency, this application provides a TBC cell and its manufacturing method.

[0011] In the first aspect, this application provides a manufacturing method of a TBC cell, adopting the following technical solution:

[0012] A manufacturing method of a TBC cell includes the following steps:

[0013] S1. Deposit a tunneling oxide layer and a polysilicon layer: sequentially deposit a tunneling oxide layer and a polysilicon layer on the surface of the substrate silicon wafer.

[0014] S2. Deposit a dopant source layer and a mask layer of impurities of the first conductivity type: sequentially deposit a dopant source layer and a mask layer of impurities of the first conductivity type outside the polysilicon layer on the back of the substrate silicon wafer, and sequentially deposit a dopant source layer and a mask layer of impurities of the first conductivity type outside the single-crystalline silicon layer on the front of the substrate silicon wafer.

[0015] S3. Open the film and clean: Remove the dopant source layer and the mask layer of impurities of the first conductivity type on the back part of the substrate silicon wafer to form a reserved area.

[0016] S4. One-step co-doping: Co-dope the dopant source layers of impurities of different conductivity types in one step to form a back P region, an N region, and a front surface field on the front.

[0017] S5. Texturing: Form a textured pyramid structure with a doping concentration gradually decreasing from the side away from the substrate silicon wafer to the side close to the substrate silicon wafer, that is, the doping concentration at the tip of the pyramid structure is higher than that at the bottom of the pyramid structure, the height of the pyramid structure is 0.1 μm - 3 μm, and the doping concentration decreases by 10 - 10 4 times.

[0018] Optionally, the height of the pyramid structure can be 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0019] Optionally, the substrate silicon wafer is an N-type silicon wafer or a P-type silicon wafer.

[0020] By adopting the above technical solution, by sequentially depositing a tunneling oxide layer and a polysilicon layer on the back surface of the substrate silicon wafer first, and then sequentially depositing a dopant source layer and a mask layer of impurities of the first conduction type, the dopant source layer and the mask layer of impurities of the first conduction type on the back surface of the substrate silicon wafer are located outside the polysilicon layer. By performing the steps of opening the film and cleaning, part of the dopant source layer and the mask layer of impurities of the first conduction type are removed to form a reserved space. During the one-step co-doping process, dopant source layers of impurities of the first conduction type with two different electricities can be simultaneously formed on the back surface of the silicon wafer, that is, the P region and the N region on the back surface, and the front surface field on the front surface of the substrate silicon wafer is simultaneously formed. Moreover, without multiple masking and mask removal processes, the phosphorus and boron doping levels of the front surface field and the back surface field can be precisely adjusted; after texturing, the FSF of the original surface pyramids is retained, enhancing the pyramid tips or surface passivation of the texture, and at the same time promoting the carriers on the front surface to move towards the back field, which can significantly reduce the series resistance of the TBC cell, increase the current density, and improve the anti-UV attenuation performance of the TBC cell; therefore, the process flow of the TBC cell is simplified, the process time is shortened, the high temperature is reduced, and the cell conversion efficiency is improved.

[0021] Optionally, before the S5 texturing, an etching step for the front surface of the substrate silicon wafer is further included, and a mixed acid solution containing HNO3 is used to etch the front surface, and the acid concentration is 1%-30%; during the S5 texturing, a texturing mixed solution with a concentration of 1%-30% is used for etching to form a texture pyramid structure on the surface of the substrate silicon wafer, and the doping substance is located at the tip of the pyramid structure or the entire pyramid structure.

[0022] By adopting the above technical solution, the front surface of the substrate silicon wafer is etched first, that is, the phosphosilicate glass layer or borosilicate glass layer and the polysilicon layer on the front surface are removed by using an acid solution, and then texturing is performed, that is, an alkali solution and a texturing additive are used to react with the single crystal silicon to form a pyramid structure anisotropically, thereby ensuring the formation of the pyramid structure.

[0023] Optionally, in the S1 deposition of the tunneling oxide layer and the polysilicon layer, the thickness of the tunneling oxide layer deposited on the surface of the substrate silicon wafer is 0.5 nm - 20 nm, and the deposition thickness of the polysilicon layer is 50 nm - 400 nm.

[0024] By adopting the above technical solution, the surface of the substrate silicon wafer includes a front surface and a back surface. When depositing the tunneling oxide layer and the polysilicon layer on the back surface of the substrate silicon wafer, some equipment will inevitably deposit the tunneling oxide layer and the polysilicon layer with the same thickness on the front surface. The polysilicon layer on the front surface can block the diffusion of impurities on the front surface, thereby better forming a pyramid doping concentration gradient.

[0025] Optionally, the thickness of the tunneling oxide layer can be 0.5 nm, 1 nm, 3 nm, 5 nm, 7 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, etc., and the deposition thickness of the polysilicon layer can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, etc.

[0026] Optionally, in S2, the doped dopant source layer and the mask layer of the first conductive type impurity, the thickness of the doped dopant source layer of the first conductive type impurity deposited by CVD outside the polysilicon layer on the back of the substrate silicon wafer is 10 nm - 100 nm, and the thickness of the mask layer is 2 nm - 200 nm.

[0027] Optionally, the thickness of the doped dopant source layer of the first conductive type impurity deposited on the polysilicon layer on the back of the substrate silicon wafer can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.; the thickness of the mask layer can be 2 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, etc.

[0028] Optionally, in S2, the doped dopant source layer and the mask layer of the first conductive type impurity further include: sequentially depositing a doped dopant source layer of 5 nm - 60 nm and a mask layer of 2 nm - 200 nm outside the single crystal silicon layer on the front of the substrate silicon wafer.

[0029] Optionally, the deposition thickness of the doped dopant source layer of the first conductive type impurity deposited on the front of the substrate silicon wafer can be 5 nm, 10 nm, 15 nm, 20 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, etc., and the deposition thickness of the mask layer can be 2 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, etc.

[0030] Optionally, the doping concentration of the doped dopant source layer of the first conductive type impurity is 1*10 17 -9*10 21 cm -3 , and the diffusion depth is 0.005 μm - 3 μm. The doping concentration can be 1*10 16 cm -3 、1*10 17 cm-3 、 1×10 18 cm -3 、 1×10 19 cm -3 、 1×10 20 cm -3 、 1×10 21 cm -3 、 9×10 21 cm -3 , the diffusion depths are 0.005 μm, 0.01 μm, 0.1 μm, 1 μm, 2 μm, and 3 μm.

[0031] Optionally, the dopant source layer of the first conductivity type impurity is a phosphorus-containing silicon oxide layer or a boron-containing silicon oxide layer, and the mask layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0032] Optionally, in the S3, film opening and cleaning, a part of the dopant source layer and the mask layer of the first conductivity type impurity on the back of the substrate silicon wafer are removed by means of laser, etching slurry, photolithography, or plasma etching.

[0033] Optionally, the S4, one-step co-doping is a phosphorus diffusion or boron diffusion process. When the dopant source layer of the first conductivity type impurity is a phosphorus-containing silicon oxide layer, the one-step co-doping is a boron diffusion process, the boron diffusion temperature is 600°C - 1000°C, and the boron diffusion time is 5 min - 180 min; when the dopant source layer of the first conductivity type impurity is a boron-containing silicon oxide layer, the one-step co-doping is a phosphorus diffusion process, the phosphorus diffusion temperature is 600°C - 1000°C, and the phosphorus diffusion time is 5 min - 180 min.

[0034] Optionally, the boron diffusion temperature can be 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, etc., and the boron diffusion time can be 5 min, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, 120 min, 130 min, 140 min, 150 min, 160 min, 170 min, 180 min, etc.; the phosphorus diffusion temperature can be 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, etc., and the phosphorus diffusion time can be 5 min, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, 120 min, 130 min, 140 min, 150 min, 160 min, 170 min, 180 min, etc.

[0035] By adopting the above technical solution, within the time and temperature range of boron diffusion or phosphorus diffusion in the present application, it is possible to simultaneously achieve the simultaneous doping of the FSF on the front side of the substrate silicon wafer, the P region and the N region on the back side, without the need for multiple masking processes, simplifying the process steps and shortening the overall process time, and ensuring an increase in the conversion efficiency of the battery.

[0036] Optionally, in the S2, the dopant source layer and the mask layer for depositing the impurity of the first conductive type, the thickness of the dopant source layer for depositing the impurity of the first conductive type deposited on the outside of the polysilicon layer on the back side of the substrate silicon wafer by CVD is 10 nm - 100 nm, and the thickness of the mask layer is 2 nm - 200 nm.

[0037] Optionally, in the S2, the dopant source layer and the mask layer for depositing the impurity of the first conductive type further include: depositing a dopant source layer of 5 nm - 60 nm for the impurity of the first conductive type and a mask layer of 2 nm - 200 nm in sequence on the outside of the single crystal silicon layer on the front side of the substrate silicon wafer.

[0038] Optionally, the doping concentration after high-temperature diffusion of the dopant source layer of the impurity of the first conductive type on the front side of the substrate silicon wafer is 1*10 16 -1*10 21 cm -3 , the diffusion depth is 0.005 μm - 3 μm, the tip size of the pyramid structure accounts for 1 / 50 - 1 / 10 of the entire pyramid structure size, and the tip concentration is 10 2 ~105 times

[0039] Optionally, the deposition temperature of CVD is 150 - 800 °C.

[0040] Optionally, the tunneling oxide layer is a phosphorus-silicon oxide compound layer or a boron-silicon oxide compound layer, and the mask layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0041] Optionally, in the steps of S3, film opening and cleaning, a part of the dopant source layer and the mask layer of the first conductive type impurities on the back of the substrate silicon wafer are removed by means of laser, etching slurry, photolithography, or plasma etching.

[0042] Optionally, the back surface is opened with a laser, with a wavelength of 200 nm - 1064 nm and a power ≥ 1 W, and then pickled, washed with water, and dried in a cleaning machine; or in a screen printing machine, the etching slurry is coated according to the back N-region pattern, left standing after screen printing for a standing time ≥ 0.5 min, and then washed with water and dried in a cleaning machine.

[0043] In a second aspect, the present application provides a TBC battery, adopting the following technical solution:

[0044] A TBC battery includes a substrate silicon wafer, the substrate silicon wafer having a front surface facing the sun during normal operation and a back surface opposite to the front surface, a tunneling oxide layer, a first conductive type impurity polysilicon region, a second conductive type impurity polysilicon region, a gap region, a first dielectric layer, and a metal electrode being provided on the back surface of the substrate silicon wafer, the first conductive type impurity polysilicon region and the second conductive type impurity polysilicon region having opposite electricities, and the metal electrode forming an ohmic contact with the first conductive type impurity polysilicon region or the second conductive type impurity polysilicon region; a front surface field and a second dielectric layer are sequentially provided on the front surface of the substrate silicon wafer from the inside out;

[0045] The doping concentration after high-temperature diffusion of the dopant source layer in the front surface field is 1×10 16 -1×10 21 cm -3 , and the diffusion depth is 0.005 μm - 3 μm; the doping concentration of the second conductive type impurity polysilicon region is 1×10 19 -1×10 22 cm -3 ; the doping concentration of the region where the metal electrode contacts the first conductive type impurity polysilicon region or the second conductive type impurity polysilicon region is 5×10 18 -1×10 21 cm -3 ; the doping concentration of the gap region is 1×10 15 -1×10 20 cm-3 。

[0046] In summary, the present application has the following beneficial effects:

[0047] 1. By using the CVD method to deposit the dopant source layer of the first-conductivity-type impurities on the front and back of the battery, and using one-step high temperature to simultaneously dope to form the FSF, back N region, and P region of the TBC battery, the high-temperature temperature is reduced; after texturing, the tips of the pyramids on the textured surface or the entire pyramid retain the original FSF, enhancing the passivation of the textured surface tips or the textured surface, and at the same time promoting the movement of carriers on the front surface to the back field; at the same time, this process is compatible with single-insertion and double-insertion throughout the process, and the post-texturing does not require a relatively thick BSG thickness, reducing the oxygen content of the silicon wafer, flexibly adjusting the doping concentration, shortening the process and time of the TBC battery, without more thermal processes, heating / cooling processes, wet processes, and film-opening processes, which is beneficial to reducing the series resistance of the solar cell, improving the conversion efficiency of the solar cell, improving the UV resistance of the TBC battery, simplifying the process steps and time of the solar cell, thereby saving production costs and being conducive to large-scale production.

[0048] 2. After depositing the dopant source layer of the first-conductivity-type impurities by CVD, the high-temperature temperature can be reduced; the post-texturing does not require a relatively thick BSG thickness, reducing the oxygen content of the silicon wafer, reducing the B-O recombination of the battery, and improving the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic structural diagram of a TBC battery.

[0050] Figure 2 It is a schematic flow diagram of the preparation method of the TBC battery in Example 1.1.

[0051] Figure 3 It is a schematic flow diagram of the preparation method of the TBC battery in Example 2.1.

[0052] Figure 4 It is a schematic diagram of the textured surface doping structure of a TBC battery.

[0053] Description of the reference numerals: 1. Second dielectric layer; 2. Front surface field; 3. Substrate silicon wafer; 4. Tunneling oxide layer; 5. Second-conductivity-type impurity polysilicon region; 6. First dielectric layer; 7. Electrode; 8. Gap region; 9. First-conductivity-type impurity polysilicon region. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] In the following embodiments of the present invention, the experimental methods without specific conditions are usually carried out according to conventional conditions or according to the conditions recommended by the manufacturer. All kinds of commonly used chemical reagents used in the embodiments are commercially available products.

[0055] Examples 1.1 - 1.3 (N-type back deposition)

[0056] Example 1.1

[0057] As Figure 1 shown, a TBC cell includes a substrate silicon wafer 3. The substrate silicon wafer is an N-type silicon wafer, and the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side. A tunneling oxide layer 4, a second-conductivity-type impurity polysilicon region 5, a first dielectric layer 6, a metal electrode 7, a gap region 8, and a first-conductivity-type impurity polysilicon region 9 are provided on the back side of the substrate silicon wafer. The first-conductivity-type impurity polysilicon region 9 and the second-conductivity-type impurity polysilicon region 5 have opposite electricities, and the metal electrode 7 forms an ohmic contact with the first-conductivity-type impurity polysilicon region 9 or the second-conductivity-type impurity polysilicon region 5; on the front side of the substrate silicon wafer 3, a front surface field 2 and a second dielectric layer 1 are sequentially provided from the inside to the outside.

[0058] The doping concentration after high-temperature diffusion of the dopant source layer in the front surface field is 1×10 16 -1×10 21 cm -3 , and the diffusion depth is 0.005 μm - 3 μm; the doping concentration of the second-conductivity-type impurity polysilicon region is 1×10 19 -1×10 22 cm -3 ; the doping concentration of the region where the metal electrode contacts the first-conductivity-type impurity polysilicon region or the second-conductivity-type impurity polysilicon region is 5×10 18 -1×10 21 cm -3 ; the doping concentration of the gap region is 1×10 15 -1×10 20 cm -3 .

[0059] As Figure 2 shown, a preparation method of a TBC cell includes the following steps:

[0060] 1. Cleaning and polishing: Clean and polish the substrate silicon wafer 3. The resistivity of the substrate silicon wafer 3 is 0.1 Ωcm, and the thickness is 100 μm;

[0061] 2. CVD depositing tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, deposit a 3-nm tunneling oxide layer 4 and a 60-nm polysilicon layer in sequence in an LPCVD furnace tube;

[0062] 3. Doping source layer and mask layer for depositing the first conductive type impurities on the back surface by CVD: In a PECVD furnace tube, using PH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 300 °C and a time of 5 min, deposit a silicon oxide layer containing phosphorus with a thickness of 20 nm on the polysilicon layer; with a deposition temperature of 300 °C, deposit a silicon oxide mask layer with a thickness of 10 nm on the silicon oxide layer containing phosphorus;

[0063] 4. Film opening and cleaning: Open the back surface of the device obtained in step 3 using a laser, with a wavelength of 500 nm and a power of 1 W, and then pickle, wash with water, and dry in a cleaning machine to reserve space for the doping source diffusion of the second conductive type impurity polysilicon region 5;

[0064] 5. Boron diffusion: Place the device obtained in step 4 into a boron diffusion tube for boron diffusion, with a boron diffusion temperature of 700 °C and a boron diffusion time of 10 min, so that the back surface PSG becomes a blocking layer and an N-region diffusion layer, a second conductive type impurity polysilicon region 5 and a first conductive type impurity polysilicon region 9 with opposite electrical properties are formed on the back surface of the substrate silicon wafer 3, and a front surface field 2 is formed on the front surface of the substrate silicon wafer 3;

[0065] 6. Preparation of the Gap region: Open the back surface of the device obtained in step 5 using a laser, with a wavelength of 500 nm and a power of 1 W, and then pickle, wash with water, and dry in a cleaning machine; to obtain the Gap region 8.

[0066] 7. Acid etching, texturing, and removal of PSG and BSG: Perform acid etching and front surface texturing on the device obtained in step 6 in sequence. Use a mixed acid solution containing HNO3 to etch the front surface, with an acid solution concentration of 20%, and then etch using an alkaline solution with a concentration of 20% and a texturing mixed solution to form a pyramidal texture structure on the surface of the substrate silicon wafer 3 (as shown in Figure 4 ), the height of the pyramidal structure is 2 μm, and the doping concentration decreases by 100 times every 0.01 μm from the tip to the bottom of the pyramid. Then place it in an acid solution to remove the BSG and PSG on the front, side, and back surfaces; then perform RCA standard cleaning on the device to remove surface contaminants;

[0067] 8. Passivation and antireflection: Deposit a passivation and antireflection dielectric layer on the surface of the device obtained in step 7 to form a second dielectric layer 1 and a first dielectric layer 6;

[0068] 9. Metallization: Set a metal electrode 7 on the back surface of the device obtained in step 8 to obtain a TBC cell structure.

[0069] Example 1.2

[0070] Refer to Figure 2 , a method for preparing a TBC cell, which is different from Example 1.1 in that the process parameters are different.

[0071] Specifically, it includes the following steps:

[0072] 1. Cleaning and polishing: Clean and polish the substrate silicon wafer 3 with a resistivity of 0.1 Ωcm and a thickness of 100 μm;

[0073] 2. CVD deposition of tunneling SiOx and Poly layers: Deposit a 3-nm tunneling oxide layer 4 and a 50-nm polysilicon layer in sequence on the device obtained after cleaning and polishing in an LPCVD furnace tube;

[0074] 3. CVD deposition of dopant source layer and mask layer for the first conductive type impurity on the back side: In a PECVD furnace tube, using PH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 200 °C and a time of 90 min, deposit a 10-nm phosphorus-containing silicon oxide layer on the polysilicon layer; with a deposition temperature of 800 °C, deposit a 2-nm silicon oxide mask layer on the phosphorus-containing silicon oxide layer;

[0075] 4. Film opening and cleaning: Open the back side of the device obtained in step 3 using a laser with a wavelength of 200 nm and a power ≥1W, and then pickle, wash with water, and dry in a cleaning machine to reserve a deposition space for the second conductive type impurity polysilicon region 5;

[0076] 5. Boron diffusion: Place the device obtained in step 4 into a boron diffusion tube for boron diffusion at a temperature of 600 °C and a time of 180 min, so that the back side PSG becomes a blocking layer and an N-region diffusion layer, forming a second conductive type impurity polysilicon region 5 and a first conductive type impurity polysilicon region 9 with opposite electrical properties on the back side of the substrate silicon wafer 3, and forming a front surface field 2 on the front side of the substrate silicon wafer 3;

[0077] 6. Preparation of Gap region: Open the back side of the device obtained in step 5 using a laser with a wavelength of 200 nm and a power ≥1W, and then pickle, wash with water, and dry in a cleaning machine; to obtain the Gap region 8.

[0078] 7. Acid etching, texturing, and removal of PSG and BSG: Perform acid etching and front side texturing on the device obtained in step 6, etch the front side with a mixed acid solution containing HNO3 with an acid concentration of 20%, and then etch with a texturing mixed solution with a concentration of 1% to form a velvet pyramid structure on the surface of the substrate silicon wafer 3. The height of the pyramid structure is 0.1 μm, and the doping concentration decreases by 10 times every 0.01 μm from the top to the bottom of the pyramid, and then place it in an acid solution to remove the BSG and PSG on the front side, side, and back side; then perform RCA standard cleaning on the device to remove surface contaminants;

[0079] 8. Passivation and antireflection: Deposit a passivation and antireflection dielectric layer on the surface of the device obtained in step 7 to form the second dielectric layer 1 and the first dielectric layer 6;

[0080] 9. Metallization: A metal electrode 7 is provided on the back surface of the device obtained in step 8 to obtain a TBC cell structure.

[0081] Example 1.3

[0082] Refer to Figure 2 , a method for preparing a TBC cell, which is different from Example 1.1 in that the process parameters are different.

[0083] Specifically, it includes the following steps:

[0084] 1. Cleaning and polishing: The substrate silicon wafer 3 is cleaned and polished. The resistivity of the substrate silicon wafer 3 is 0.1 Ω·cm and the thickness is 100 μm.

[0085] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, a 3-nm tunneling oxide layer 4 and a 400-nm polysilicon layer are sequentially deposited in an LPCVD furnace tube.

[0086] 3. CVD deposition of dopant source layer and mask layer for the first conductive type impurity on the back surface: In a PECVD furnace tube, using PH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 800 °C and a time of 5 min, a phosphorus-containing silicon oxide layer with a thickness of 100 nm is deposited on the polysilicon layer; with a deposition temperature of 200 °C, a silicon oxide mask layer with a thickness of 200 nm is deposited on the phosphorus-containing silicon oxide layer to form a first conductive type impurity polysilicon region 9.

[0087] 4. Film opening and cleaning: The back surface of the device obtained in step 3 is opened with a laser, with a wavelength of 1064 nm and a power ≥ 1 W, and then pickled, washed with water, and dried in a cleaning machine to reserve a deposition space for the second conductive type impurity polysilicon region 5.

[0088] 5. Boron diffusion: The device obtained in step 4 is placed in a boron diffusion tube for boron diffusion. The boron diffusion temperature is 1000 °C and the boron diffusion time is 5 min, so that the back surface PSG becomes a blocking layer and an N-region diffusion layer. A second conductive type impurity polysilicon region 5 and a first conductive type impurity polysilicon region 9 with opposite electric properties are formed on the back surface of the substrate silicon wafer 3, and a front surface field 2 is formed on the front surface of the substrate silicon wafer 3.

[0089] 6. Film opening and cleaning: The back surface of the device obtained in step 5 is opened with a laser, with a wavelength of 1064 nm and a power ≥ 1 W, and then pickled, washed with water, and dried in a cleaning machine; to obtain a Gap region 8.

[0090] 7. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 6 is subjected to acid etching and front texturing. A mixed acid solution containing HNO3 is used to etch the front surface, with the acid concentration being 30%. Then, a texturing mixed solution with a concentration of 10% is used for etching to form a pyramidal texture structure on the surface of the substrate silicon wafer 3. The height of the pyramidal structure is 3 μm, and the doping concentration decreases by 10 4 times every 0.01 μm from the tip to the bottom of the pyramid. Then, it is placed in the acid solution to remove BSG and PSG on the front, side, and back surfaces. Subsequently, the device is subjected to RCA standard cleaning to remove surface contaminants;

[0091] 8. Passivation and antireflection: A passivation and antireflection dielectric layer is deposited on the surface of the device obtained in step 7 to form the second dielectric layer 1 and the first dielectric layer 6;

[0092] 9. Metallization: A metal electrode 7 is provided on the back surface of the device obtained in step 8 to obtain a TBC cell structure.

[0093] Example 1.4

[0094] As Figure 1 shown, a TBC cell includes a substrate silicon wafer 3, which is a P-type silicon wafer. The substrate silicon wafer has a front surface facing the sun during normal operation and a back surface opposite to the front surface. A tunneling oxide layer 4, a second-conductivity-type impurity polysilicon region 5, a first dielectric layer 6, a metal electrode 7, a gap region 8, and a first-conductivity-type impurity polysilicon region 9 are provided on the back surface of the substrate silicon wafer. The first-conductivity-type impurity polysilicon region 9 and the second-conductivity-type impurity polysilicon region 5 have opposite electrical properties, and the metal electrode 7 forms an ohmic contact with the first-conductivity-type impurity polysilicon region 9 or the second-conductivity-type impurity polysilicon region 5. On the front surface of the substrate silicon wafer 3, a front surface field 2 and a second dielectric layer 1 are sequentially provided from the inside out.

[0095] As Figure 2 shown, a method for manufacturing a TBC cell includes the following steps:

[0096] 1. Cleaning and polishing: The substrate silicon wafer 3 is cleaned and polished. The resistivity of the substrate silicon wafer 3 is 0.1 Ω·cm, and the thickness is 100 μm;

[0097] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, a 3-nm tunneling oxide layer 4 and a 60-nm polysilicon layer are sequentially deposited in an LPCVD furnace tube;

[0098] 3. CVD deposition of the dopant source layer and mask layer for the first conductive type impurity on the back surface: In a PECVD furnace tube, using BH3, SiH4, and N2O as deposition raw materials, the deposition temperature is 300 °C, and the time is 5 min. A silicon oxide layer containing boron with a thickness of 20 nm is deposited on the polysilicon layer; the deposition temperature is 300 °C, and a silicon oxide mask layer with a thickness of 10 nm is deposited on the silicon oxide layer containing boron;

[0099] 4. Opening the film and cleaning: The back surface of the device obtained in step 3 is opened with a laser, the wavelength is 500 nm, and the power is 1 W. Then, it is pickled, washed with water, and dried in a cleaning machine to reserve space for the doping source diffusion of the second conductive type impurity polysilicon region 5;

[0100] 5. Phosphorus diffusion: The device obtained in step 4 is placed in a phosphorus diffusion tube for phosphorus diffusion. The phosphorus diffusion temperature is 700 °C, and the phosphorus diffusion time is 10 min, so that the back surface BSG becomes the blocking layer and the N-region diffusion layer. On the back surface of the substrate silicon wafer 3, a second conductive type impurity polysilicon region 5 and a first conductive type impurity polysilicon region 9 with opposite electrical properties are formed, and a front surface field 2 is formed on the front surface of the substrate silicon wafer 3;

[0101] 6. Preparation of the Gap region: The back surface of the device obtained in step 5 is opened with a laser, the wavelength is 500 nm, and the power is 1 W. Then, it is pickled, washed with water, and dried in a cleaning machine to obtain the Gap region 8.

[0102] 7. Acid etching, texturing, and removal of PSG and BSG: The device obtained in step 6 is acid etched and textured on the front surface. The front surface is etched with a mixed acid solution containing HNO3, and the acid concentration is 20%. Then, it is etched with a texturing mixed solution with a concentration of 20%. A pyramidal structure with a velvet surface is formed on the surface of the substrate silicon wafer 3 (as shown in Figure 4 shown). The height of the pyramidal structure is 2 μm, and the doping concentration decreases by 100 times every 0.01 μm from the top to the bottom of the pyramid. Then, it is placed in an acid solution to remove the BSG and PSG on the front, side, and back surfaces; the device is then subjected to RCA standard cleaning to remove surface contaminants;

[0103] 8. Passivation and antireflection: A passivation and antireflection dielectric layer is deposited on the surface of the device obtained in step 7 to form the second dielectric layer 1 and the first dielectric layer 6;

[0104] 9. Metallization: A metal electrode 7 is provided on the back surface of the device obtained in step 8 to obtain the TBC cell structure.

[0105] That is, the difference between Example 1.4 and Example 1.1 is that the substrate silicon wafer 3 is a P-type substrate silicon wafer; in step 3, the dopant source layer for CVD deposition of the first conductive type impurity on the back surface is a silicon oxide layer containing boron; step 5 is the phosphorus diffusion process.

[0106] Example 1.5

[0107] A method for preparing a TBC cell, which is different from that of Example 1.1 in that step 6 for preparing the Gap region is not carried out, and the remaining steps are the same.

[0108] Example 1.6

[0109] A method for preparing a TBC cell, which is different from that of Example 1.1 in that

[0110] 2. CVD deposit the tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, deposit a 3-nm tunneling oxide layer 4 and a 300-nm polysilicon layer in sequence in an LPCVD furnace tube;

[0111] 3. CVD deposit the dopant source layer and the mask layer of the first conductive type impurity on the back side: In a PECVD furnace tube, using PH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 450 °C and a time of 30 min, deposit a phosphorus-containing silicon oxide layer with a thickness of 40 nm on the polysilicon layer; with a deposition temperature of 450 °C, deposit a 10-nm silicon oxide mask layer on the phosphorus-containing silicon oxide layer. The remaining steps are the same.

[0112] Examples 2.1 - 2.3 (using a P-type substrate, depositing the dopant source layer and the mask layer of the first conductive type impurity on both the front and back sides of the substrate silicon wafer)

[0113] Example 2.1

[0114] Refer to Figure 1 , a TBC cell, including a substrate silicon wafer, the substrate silicon wafer is a P-type silicon wafer, the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, a tunneling oxide layer, a first conductive type impurity polysilicon region, a second conductive type impurity polysilicon region, a gap region, a first dielectric layer, and a metal electrode are provided on the back side of the substrate silicon wafer, the electrical properties of the first conductive type impurity polysilicon region and the second conductive type impurity polysilicon region are opposite, and the metal electrode forms an ohmic contact with the first conductive type impurity polysilicon region or the second conductive type impurity polysilicon region; a front surface field and a second dielectric layer are sequentially provided from the inside to the outside on the front side of the substrate silicon wafer.

[0115] The doping concentration after high-temperature diffusion of the dopant source layer in the front surface field is 1*10 16 -1*10 21 cm -3 , and the diffusion depth is 0.005 μm - 3 μm; the doping concentration of the second conductive type impurity polysilicon region is 1*10 19 -1*10 22 cm -3; The doping concentration of the region where the metal electrode contacts the first-conductivity-type impurity polysilicon region or the second-conductivity-type impurity polysilicon region is 5*10 18 -1*10 21 cm -3 ; The doping concentration of the gap region is 1*10 15 -1*10 20 cm -3 。

[0116] As Figure 3 shown, a preparation method of a TBC battery includes the following steps:

[0117] 1. Cleaning and polishing: Cleaning and polishing the substrate silicon wafer;

[0118] 2. CVD depositing a tunneling SiOx and Poly layer: Sequentially depositing a 5-nm tunneling SiOx layer and a 60-nm Poly layer on the device obtained in step 1 in an LPCVD furnace tube;

[0119] 3. CVD depositing a dopant source layer and a mask layer of the first-conductivity-type impurity on the back side: Using BH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 400°C and a time of 20 min, depositing a 50-nm boron-containing silicon oxide layer on the polysilicon layer; with a deposition temperature of 400°C, depositing a 30-nm silicon oxide mask layer on the boron-containing silicon oxide layer;

[0120] 4. CVD depositing a dopant source layer and a mask layer of the first-conductivity-type impurity on the front side: Using BH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 400°C and a time of 20 min, depositing a 30-nm boron-containing silicon oxide layer on the front side of the substrate silicon wafer; with a deposition temperature of 200°C, depositing a 5-nm silicon oxide mask layer on the boron-containing silicon oxide layer;

[0121] 5. Opening the film and cleaning: Using a laser to open the film on the back side of the device obtained in step 3, with a wavelength of 500 nm and a power of 1 W, and then pickling, washing with water, and drying in a cleaning machine to provide a reserved space for the diffusion of the dopant source of the second-conductivity-type impurity;

[0122] 6. Phosphorus diffusion: Placing the device obtained in step 5 into a phosphorus diffusion tube for phosphorus diffusion, with a phosphorus diffusion temperature of 800°C and a phosphorus diffusion time of 20 min. The back-side silicon oxide mask layer serves as a P-region blocking layer, and the back-side BSG forms a P-region diffusion layer. At the same time, the front side diffuses to form an N-doped FSF and the back-side N region;

[0123] 7. Preparing the gap region: Using a laser to open the film on the back side of the device obtained in step 5, with a wavelength of 800 nm and a power ≥1 W, and then pickling, washing with water, and drying in a cleaning machine to obtain the gap region.

[0124] 8. Acid etching, texturing, and removing PSG and BSG: The device obtained in step 7 is subjected to acid etching and front texturing. A mixed acid solution containing HNO3 is used to etch the front surface, with the acid concentration being 20%. Then, etching is carried out using a texturing mixed solution with a concentration of 20% to form a textured pyramid structure on the surface of the substrate silicon wafer 3 (as Figure 4 shown). The height of the pyramid structure is 2 μm, and the doping concentration decreases by 100 times every 0.01 μm from the tip to the bottom of the pyramid. Then, it is placed in an acid solution to remove BSG and PSG on the front, side, and back surfaces; the device is then subjected to RCA standard cleaning to remove surface contaminants;

[0125] 9. Passivation and antireflection: A passivation and antireflection dielectric layer, including a second dielectric layer and a first dielectric layer, is deposited on the surface of the device obtained in step 8;

[0126] 10. Metallization: A back metal electrode is set on the device obtained in step 9 to obtain the TBC cell structure.

[0127] Example 2.2

[0128] Referring to Figure 3 , a preparation method of a TBC cell, which is different from that of Example 2.1 in that the preparation process parameters are different, and specifically includes the following steps:

[0129] 1. Cleaning and polishing: The substrate silicon wafer is cleaned and polished;

[0130] 2. CVD depositing tunneling SiOx and Poly layers: On the device obtained in step 1, a tunneling SiOx layer with a thickness of 0.5 nm and a Poly layer with a thickness of 400 nm are sequentially deposited in an LPCVD furnace tube;

[0131] 3. CVD depositing a dopant source layer and a mask layer of the first conductive type impurity on the back: Using BH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 200 °C and a time of 30 min, a boron-containing silicon oxide layer with a thickness of 10 nm is deposited on the polysilicon layer; with a deposition temperature of 600 °C, a silicon oxide mask layer with a thickness of 200 nm is deposited on the boron-containing silicon oxide layer;

[0132] 4. CVD depositing a dopant source layer and a mask layer of the first conductive type impurity on the front: Using BH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 200 °C and a time of 20 min, a boron-containing silicon oxide layer with a thickness of 5 nm is deposited on the front surface of the substrate silicon wafer; with a deposition temperature of 400 °C, a silicon oxide mask layer with a thickness of 200 nm is deposited on the boron-containing silicon oxide layer;

[0133] 5. Film opening and cleaning: Open the back of the device obtained in step 3 using a laser with a wavelength of 500 nm and a power of 1 W. Then, pickle, wash with water, and dry in a cleaning machine to provide a reserved space for the diffusion of the dopant source of the second conductive type impurities;

[0134] 6. Phosphorus diffusion: Place the device obtained in step 5 into a phosphorus diffusion tube for phosphorus diffusion. The phosphorus diffusion temperature is 600 °C, and the phosphorus diffusion time is 120 min. The silicon oxide mask layer on the back is the P-region blocking layer, and the back BSG forms the P-region diffusion layer. At the same time, N-doped FSF is formed by diffusion on the front, together with the N-region on the back;

[0135] 7. Preparation of the gap region: Open the back of the device obtained in step 5 using a laser with a wavelength of 800 nm and a power ≥ 1 W. Then, pickle, wash with water, and dry in a cleaning machine to obtain the gap region.

[0136] 8. Acid etching, texturing, and removal of PSG and BSG: Acid etch and texture the front of the device obtained in step 7. Use a mixed acid solution containing HNO3 to etch the front. The acid concentration is 20%. Then, etch with a texturing mixed solution with a concentration of 20% to form a textured pyramid structure on the surface of the substrate silicon wafer 3 (as shown in Figure 4 ), the height of the pyramid structure is 0.2 μm, and the doping concentration decreases by 100 times every 0.01 μm from the top to the bottom of the pyramid. Then, place it in an acid solution to remove the BSG and PSG on the front, side, and back; then perform RCA standard cleaning on the device to remove surface contaminants;

[0137] 9. Passivation and antireflection: Deposit a passivation and antireflection dielectric layer on the surface of the device obtained in step 8, including a second dielectric layer and a first dielectric layer;

[0138] 10. Metallization: Set a back metal electrode on the device obtained in step 9 to obtain the TBC cell structure.

[0139] Example 2.3

[0140] Refer to Figure 3 , a TBC cell and its preparation method. The difference from Example 2.1 lies in different preparation process parameters, which specifically include the following steps:

[0141] 1. Cleaning and polishing: Clean and polish the substrate silicon wafer;

[0142] 2. CVD deposition of tunneling SiOx and Poly layers: Sequentially deposit a 20 nm tunneling SiOx layer and a 50 nm Poly layer on the device obtained in step 1 in an LPCVD furnace tube;

[0143] 3. CVD Deposition of Dopant Source Layer and Mask Layer for the First Conductivity Type Impurity on the Back Side: Using BH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 600 °C and a time of 30 min, deposit a boron-containing silicon oxide layer with a thickness of 100 nm on the polysilicon layer; with a deposition temperature of 200 °C, deposit a silicon oxide mask layer with a thickness of 2 nm on the boron-containing silicon oxide layer;

[0144] 4. CVD Deposition of Dopant Source Layer and Mask Layer for the First Conductivity Type Impurity on the Front Side: Using BH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 400 °C and a time of 40 min, deposit a boron-containing silicon oxide layer with a thickness of 60 nm on the front side of the substrate silicon wafer; with a deposition temperature of 200 °C, deposit a silicon oxide mask layer with a thickness of 2 nm on the boron-containing silicon oxide layer;

[0145] 5. Film Opening and Cleaning: Open the film on the back side of the device obtained in step 3 using a laser, with a wavelength of 500 nm and a power of 1 W, and then perform pickling, water washing, and drying in a cleaning machine to provide a reserved space for the diffusion of the dopant source of the second conductivity type impurity;

[0146] 6. Phosphorus Diffusion: Place the device obtained in step 5 into a phosphorus diffusion tube for phosphorus diffusion. The phosphorus diffusion temperature is 1000 °C, and the phosphorus diffusion time is 5 min. The back side silicon oxide mask layer is the P-region blocking layer, and the back side BSG forms the P-region diffusion layer. At the same time, the front side diffuses to form the N-doped FSF and the back side N-region;

[0147] 7. Preparation of the gap Region: Open the film on the back side of the device obtained in step 5 using a laser, with a wavelength of 800 nm and a power of 1 W, and then perform pickling, water washing, and drying in a cleaning machine to obtain the gap region.

[0148] 8. Acid Etching, Texturing, and Removal of PSG and BSG: Perform acid etching and front side texturing on the device obtained in step 7. Use a mixed acid solution containing HNO3 to etch the front side. The acid solution concentration is 20%. Then, etch using a texturing mixed solution with a concentration of 20% to form a pyramidal texture structure on the surface of the substrate silicon wafer 3 (as shown in Figure 4 shown). The height of the pyramidal structure is 3 μm, and the doping concentration decreases by 10 times every 0.01 μm from the tip to the bottom of the pyramid. Then, place it in an acid solution to remove the BSG and PSG on the front side, side, and back side; then perform RCA standard cleaning on the device to remove surface contaminants; 4 9. Passivation and Antireflection: Deposit a passivation and antireflection dielectric layer on the surface of the device obtained in step 8, including a second dielectric layer and a first dielectric layer;

[0149] 10. Metallization: Set a back side metal electrode on the device obtained in step 9 to obtain the TBC cell structure.

[0150] 10. Metallization: Set a back side metal electrode on the device obtained in step 9 to obtain the TBC cell structure.

[0151] Example 2.4

[0152] Reference Figure 1 , a TBC cell, comprising a substrate silicon wafer, the substrate silicon wafer being an N-type silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, a tunneling oxide layer, a first-conductivity-type impurity polysilicon region, a second-conductivity-type impurity polysilicon region, a gap region, a first dielectric layer and a metal electrode are provided on the back side of the substrate silicon wafer, the first-conductivity-type impurity polysilicon region and the second-conductivity-type impurity polysilicon region have opposite electricities, and the metal electrode forms an ohmic contact with the first-conductivity-type impurity polysilicon region or the second-conductivity-type impurity polysilicon region; a front surface field and a second dielectric layer are sequentially provided on the front side of the substrate silicon wafer from inside to outside.

[0153] As Figure 3 shown, a method for manufacturing a TBC cell includes the following steps:

[0154] 1. Cleaning and polishing: cleaning and polishing the substrate silicon wafer;

[0155] 2. CVD depositing a tunneling SiOx and Poly layer: sequentially depositing a 5-nm tunneling SiOx layer and a 60-nm Poly layer on the device obtained in step 1 in an LPCVD furnace tube;

[0156] 3. CVD depositing a dopant source layer and a mask layer of the first-conductivity-type impurity on the back side: using PH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 400°C and a time of 20 min, depositing a 50-nm phosphorus-containing silicon oxide layer on the polysilicon layer; with a deposition temperature of 400°C, depositing a 30-nm silicon oxide mask layer on the phosphorus-containing silicon oxide layer;

[0157] 4. CVD depositing a dopant source layer and a mask layer of the first-conductivity-type impurity on the front side: using PH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 400°C and a time of 20 min, depositing a 30-nm phosphorus-containing silicon oxide layer on the front side of the substrate silicon wafer; with a deposition temperature of 200°C, depositing a 5-nm silicon oxide mask layer on the phosphorus-containing silicon oxide layer;

[0158] 5. Opening the film and cleaning: opening the film on the back side of the device obtained in step 3 using a laser, with a wavelength of 500 nm and a power of 1 W, and then pickling, water washing, and drying in a cleaning machine to provide a reserved space for the diffusion of the dopant source of the second-conductivity-type impurity;

[0159] 6. Boron diffusion: Put the device obtained in step 5 into a phosphorus diffusion tube for boron diffusion. The boron diffusion temperature is 800 °C and the boron diffusion time is 20 min. The backside silicon oxide mask layer serves as the P-region blocking layer, and the backside BSG forms the P-region diffusion layer. Meanwhile, N-doped FSF is formed on the front side by diffusion, together with the backside N-region;

[0160] 7. Preparation of the gap region: For the device obtained in step 5, use a laser to open the film on the backside with a wavelength of 800 nm and a power ≥1 W, and then pickle, wash with water, and dry in a cleaning machine to obtain the gap region.

[0161] 8. Acid etching, texturing, and removal of PSG and BSG: Acid etch and texture the front side of the device obtained in step 7. Use a mixed acid solution containing HNO3 to etch the front side. The acid concentration is 20%. Then use a texturing mixed solution with a concentration of 20% for etching to form a pyramidal texture structure on the surface of the substrate silicon wafer 3 (as shown in Figure 4 shown). The height of the pyramidal structure is 2 μm, and the doping concentration decreases by 100 times every 0.01 μm from the tip to the bottom of the pyramid. Then put it into the acid solution to remove the BSG and PSG on the front, side, and back; then perform RCA standard cleaning on the device to remove surface contaminants;

[0162] 9. Passivation and antireflection: Deposit a passivation and antireflection dielectric layer on the surface of the device obtained in step 8, including the second dielectric layer and the first dielectric layer;

[0163] 10. Metallization: Set a backside metal electrode on the device obtained in step 9 to obtain the TBC cell structure.

[0164] That is, the difference between Example 2.4 and Example 2.1 is that the substrate silicon wafer is an N-type silicon wafer, the layers deposited in steps 3 and 4 are both phosphorus-containing silicon oxide layers, and step 6 is a boron diffusion process.

[0165] Example 2.5

[0166] A method for preparing a TBC cell, which is different from Example 2.1 in that step 7 for preparing the gap region is not carried out.

[0167] Example 2.6

[0168] A method for preparing a TBC cell, based on Example 2.1, and different from Example 2.1 in that

[0169] 2. CVD deposition of tunneling SiOx and Poly layers: On the device obtained after cleaning and polishing, sequentially deposit a 3-nm tunneling oxide layer 4 and a 300-nm polysilicon layer in an LPCVD furnace tube;

[0170] 3. CVD Deposition of Dopant Source Layer and Mask Layer for the First Conductive-Type Impurities on the Back Side: In a PECVD furnace tube, using PH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 450 °C and a time of 30 min, a silicon oxide layer containing phosphorus with a thickness of 40 nm is deposited on the polysilicon layer; with a deposition temperature of 450 °C, a silicon oxide mask layer with a thickness of 10 nm is deposited on the silicon oxide layer containing phosphorus;

[0171] 4. CVD Deposition of Dopant Source Layer and Mask Layer for the First Conductive-Type Impurities on the Front Side: Using PH3, SiH4, and N2O as deposition raw materials, with a deposition temperature of 400 °C and a time of 20 min, a boron-containing silicon oxide layer with a thickness of 10 nm is deposited on the front side of the substrate silicon wafer; with a deposition temperature of 400 °C, a silicon oxide mask layer with a thickness of 40 nm is deposited on the silicon oxide layer containing phosphorus; the remaining steps are the same.

[0172] Comparative Example 1

[0173] A preparation method of a TBC cell containing FSF, comprising the following steps:

[0174] Cleaning → LPCVD to form a tunneling oxide layer and an intrinsic amorphous silicon layer → High-temperature boron doping to complete doping and crystallization (Emitter) → Masking → Laser opening of BSG (N region) and cleaning → Reverse etching → LPCVD to form an intrinsic amorphous silicon layer → High-temperature phosphorus doping to complete doping (BSF) → Masking → Front-side cleaning → FSF → Annealing → Laser opening of the gap region → Texturing → Removal of silicon oxide and RCA standard cleaning → Passivation antireflection layer formation → Metallization.

[0175] Comparative Example 2

[0176] A preparation method of a TBC cell, different from Example 1.1 in that the height of the pyramid structure is 5 μm.

[0177] Comparative Example 3

[0178] A preparation method of a TBC cell, different from Example 1.1 in that the height of the pyramid structure is 0.01 μm.

[0179] Comparative Example 4

[0180] A preparation method of a TBC cell, different from Example 1.1 in that texturing is not performed.

[0181] Comparative Example 5

[0182] A preparation method of a TBC cell, different from Example 2.1 in that texturing is not performed.

[0183] Comparative Example 6

[0184] A TBC cell, which is different from that of Example 1.1 in that the doping concentrations at the tips and bottoms of the pyramid structures formed by texturing are the same.

[0185] Comparative Example 7

[0186] A TBC cell, which is different from that of Example 1.1 in that the pyramid has no doping or no structure with a gradually decreasing concentration from the tip to the silicon substrate.

[0187] Comparative Example 8

[0188] A method for preparing a TBC cell, which is different from that of Example 1.1 in that a tunneling oxide layer and a polysilicon layer are not deposited on the front side of the substrate silicon wafer, so that during the subsequent boron diffusion process, the front side of the substrate silicon wafer is not doped.

[0189] Comparative Example 9

[0190] A method for preparing a TBC cell, which is different from that of Example 2.1 in that a tunneling oxide layer and a polysilicon layer are not deposited on the front side of the substrate silicon wafer, so that during the subsequent boron diffusion process, the front side of the substrate silicon wafer is not doped.

[0191] Performance detection test

[0192] The cells of Examples 1.1 - 1.3, Examples 2.1 - 2.3 and Comparative Example 1 were tested under the same conditions respectively, and the test results are shown in Table 1.

[0193] Table 1 Test results of examples and comparative examples

[0194]

[0195] Combining Examples 2.1 - 2.3 and Examples 1.1 - 1.3 and combining with the appendix Figure 2-3It can be seen that when depositing the dopant source layer and the mask layer of impurities of the first conductivity type on the front side of the silicon wafer substrate (i.e., Examples 2.1 - 2.3), after high-temperature one-step co-doping and forming the pyramid structure through texturing, the mask layer plays a role in blocking the doping of impurities of the second conductivity type to the front side of the silicon wafer substrate during high-temperature diffusion. Moreover, the concentration at the tip of the formed pyramid is higher than that at the bottom of the pyramid, and it has the same doping source as the polysilicon region of impurities of the first conductivity type on the back side of the silicon wafer substrate, enabling the textured pyramid to retain the original FSF, enhancing the textured tip or textured passivation, while promoting the movement of carriers on the front surface towards the back field, which can significantly reduce the side base resistance loss and the total series resistance of the BC cell, improve the current density, and improve the UV attenuation resistance performance of the BC cell; when not depositing the dopant source layer and the mask layer of impurities of the first conductivity type on the front side of the silicon wafer substrate (i.e., Examples 1.1 - 1.3), after high-temperature one-step co-doping, the front side of the silicon wafer substrate has the same doping source as the polysilicon region of impurities of the second conductivity type on the back side of the silicon wafer substrate. After texturing, the formed pyramid structure can enhance the textured tip or textured passivation, while promoting the movement of carriers on the front surface towards the back field, improve the current density, and improve the UV attenuation resistance performance of the BC cell.

[0196] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. A method for preparing a TBC battery, characterized in that: It includes the following steps: S1. Depositing a tunneling oxide layer and a polysilicon layer: Sequentially deposit a tunneling oxide layer and a polysilicon layer on the surface of the substrate silicon wafer; S2. Depositing a dopant source layer and a mask layer of the first conductive type impurity: Sequentially deposit a dopant source layer and a mask layer of the first conductive type impurity outside the polysilicon layer on the back side of the substrate silicon wafer; S3. Opening the film and cleaning: Remove the dopant source layer and the mask layer of the first conductive type impurity on the back side of the substrate silicon wafer to form a reserved area; S4. One-step co-doping: Co-dope the dopant source layers of different conductive type impurities in one step to form a back P region, an N region, and a front surface field on the front side; S5, Texturing: Form a textured pyramid structure with a doping concentration gradually decreasing from the side far from the substrate wafer to the side close to the substrate wafer, that is, the doping concentration at the tip of the pyramid structure is higher than that at the bottom of the pyramid structure. The height of the pyramid structure is 0.1 μm - 3 μm, and the doping concentration decreases by 10 - 10 4 times per 0.01 micrometer from the tip to the bottom of the pyramid structure.

2. The preparation method of a TBC battery according to claim 1, wherein: Before the S5. Texturing, it also includes an etching step on the front side of the substrate silicon wafer, etching the front side with a mixed acid solution containing HNO3, and the acid concentration is 1%-30%; during the S5. Texturing, etch with a texturing mixed solution with a concentration of 1%-30% to form a textured pyramid structure on the surface of the substrate silicon wafer, and the doping substance is located at the tip of the pyramid structure or the entire pyramid structure.

3. The preparation method of a TBC battery according to claim 1, characterized in that: In the S1. Depositing a tunneling oxide layer and a polysilicon layer, the thickness of the tunneling oxide layer deposited on the surface of the substrate silicon wafer is 0.5 nm - 20 nm, and the deposition thickness of the polysilicon layer is 50 nm - 400 nm.

4. The preparation method of a TBC battery according to claim 1, characterized in that: In the S2. Depositing a dopant source layer and a mask layer of the first conductive type impurity, the thickness of the dopant source layer of the first conductive type impurity deposited outside the polysilicon layer on the back side of the substrate silicon wafer by CVD is 10 nm - 100 nm, and the thickness of the mask layer is 2 nm - 200 nm.

5. The preparation method of a TBC battery according to claim 1, characterized in that: In the S2. Depositing a dopant source layer and a mask layer of the first conductive type impurity, it also includes: Sequentially deposit a dopant source layer of 5 nm - 60 nm of the first conductive type impurity and a mask layer of 2 nm - 200 nm outside the single-crystalline silicon layer on the front side of the substrate silicon wafer.

6. The preparation method of a TBC battery according to claim 5, characterized in that: The doping concentration of the dopant source layer of the first conductive type impurity on the front side of the substrate silicon wafer after high-temperature diffusion is 1×10 16 -1×10 21 cm -3 , the diffusion depth is 0.005 μm - 3 μm, the tip size of the pyramid structure accounts for 1 / 50 - 1 / 10 of the size of the entire pyramid structure, and the tip concentration is 10 2 ~10 5 times that of the bottom.

7. A method for preparing a TBC battery according to any one of claims 4-5, characterized in that: The dopant source layer of the first conductive type impurity is a silicon oxide layer containing phosphorus or a silicon oxide layer containing boron, and the mask layer is composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

8. A method for preparing a TBC battery according to claim 1, characterized in that: In the S3. Opening the film and cleaning, use laser, etching slurry, photolithography, or plasma etching to remove part of the dopant source layer and the mask layer of the first conductive type impurity on the back side of the substrate silicon wafer.

9. The preparation method of a TBC battery according to claim 7, characterized in that: The S4. One-step co-doping is a phosphorus diffusion or boron diffusion process. When the dopant source layer of the first conductive type impurity is a silicon oxide layer containing phosphorus, the one-step co-doping is a boron diffusion process, the boron diffusion temperature is 600°C - 1000°C, and the boron diffusion time is 5 min - 180 min; when the dopant source layer of the first conductive type impurity is a silicon oxide layer containing boron, the one-step co-doping is a phosphorus diffusion process, the phosphorus diffusion temperature is 600°C - 1000°C, and the phosphorus diffusion time is 5 min - 180 min.

10. A TBC battery prepared by the method for preparing a TBC battery according to any one of claims 1-9, characterized in that: It includes a substrate silicon wafer (3), the substrate silicon wafer (3) having a front side facing the sun during normal operation and a back side opposite to the front side. A tunneling oxide layer (4), a first-conductivity-type impurity polysilicon region (9), a second-conductivity-type impurity polysilicon region (5), a gap region (8), a first dielectric layer (6), and a metal electrode (7) are provided on the back side of the substrate silicon wafer (3). The first-conductivity-type impurity polysilicon region (9) and the second-conductivity-type impurity polysilicon region (5) have opposite electricities, and the metal electrode (7) forms an ohmic contact with the first-conductivity-type impurity polysilicon region (9) or the second-conductivity-type impurity polysilicon region (5); a front surface field (2) and a second dielectric layer (1) are sequentially provided on the front side of the substrate silicon wafer (3) from inside to outside; The doping concentration after high-temperature diffusion of the dopant source layer in the front surface field (2) is 1×10 16 -1×10 21 cm -3 , and the diffusion depth is 0.005 μm - 3 μm; the doping concentration of the second conductivity type impurity polysilicon region (5) is 1×10 19 -1×10 22 cm -3 ; the doping concentration of the region where the metal electrode (7) contacts the first conductivity type impurity polysilicon region (9) or the second conductivity type impurity polysilicon region (5) is 5×10 18 -1×10 21 cm -3 ; the doping concentration of the gap region (8) is 1×10 15 -1×10 20 cm -3 .

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