Heterojunction contact layer for solar cell, solar cell and preparation method thereof

Abstract

The invention discloses a heterojunction contact layer for a solar cell, the solar cell and a preparation method thereof, and the heterojunction contact layer comprises an n +-GaAs matching contact layer, an n +-In (x) Ga (1-x) As transition contact layer formed on the n +-GaAs matching contact layer, and an n +-In (y) Ga (1-y) As surface contact layer formed on the n +-In (x) Ga (1-x) As transition contact layer, the solar cell comprises the heterojunction contact layer, a substrate, a first sub-cell, a tunnel junction and a second sub-cell, the first sub-cell, the tunnel junction and the second sub-cell are sequentially formed on the first face of the substrate from bottom to top, and a back electrode is formed on the second face, opposite to the first face of the substrate, of the substrate. And the heterojunction contact layer is formed on the second sub-cell, and a gate electrode is formed on the heterojunction contact layer. According to the heterojunction contact layer provided by the invention, the contact resistance formed between an electrode material on the solar cell and the heterojunction contact layer can be reduced, and the efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar photovoltaics, and particularly relates to a heterojunction contact layer for a solar cell, a solar cell, and a preparation method thereof. Background Art

[0002] III-V compound semiconductor multi-junction solar cells can achieve higher conversion efficiency by fully absorbing sunlight through a reasonable bandgap combination. The six-junction AlGaInP / AlGaAs / GaAs / GaInAs(3) solar cell achieves a photoelectric conversion efficiency of 39.2% under AM1.5G, and the efficiency reaches 47.1% under concentration.

[0003] The GaInP / GaAs(mqw) / GaInAs solar cell prepared by optimizing the GaAs bandgap using GaInAs / GaAsP strain-balanced quantum wells (QW) achieves efficiencies of 39.5% and 34.2% under the AM1.5G spectrum and the space spectrum respectively, exceeding the non-concentrating efficiency of the previously recorded six-junction cell devices. III-V solar cells have very stable performance and excellent radiation resistance, and have been widely used in space power supplies.

[0004] At present, the front grid electrodes of III-V multi-junction cells are all formed of Au alloy on the contact layer through photolithography and electron beam evaporation. Although this process method can precisely control the thickness and width of the electrodes, the patterning electrode operation process is very complex and costly.

[0005] If the AuGe / Ni / Au electrode in the traditional III-V multi-junction cell is replaced with a silver paste electrode, the electrode manufacturing cost can be greatly reduced, and at the same time, the complex process of photolithography and the costly photolithography equipment and material costs can be saved. The key to the application of the silver paste electrode lies in whether it can form a good ohmic contact with the contact layer of the cell. A low contact resistance is beneficial to the improvement of the cell efficiency.

[0006] III-V multi-junction cells use a GaAs contact layer. Although GaAs can form an ohmic contact with the silver paste, due to the work function of the GaAs contact layer not being able to match better with the work function of the annealed silver metal, the ohmic contact resistance between the silver paste and the GaAs contact layer is slightly higher than that of the traditional electrode. Summary of the Invention

[0007] In view of the deficiencies of the prior art, the present invention provides a heterojunction contact layer for a solar cell, a solar cell, and a preparation method thereof, so as to solve the problem of high ohmic contact resistance between the electrode and the contact layer in the existing solar cell.

[0008] To solve the above problems, the present invention first provides a heterojunction contact layer for a solar cell, and the heterojunction contact layer includes an n+-GaAs matching contact layer, an n+-In (x) Ga (1-x) As transition contact layer formed on the n+-GaAs matching contact layer, and an n+-In (x) Ga (1-x) As surface contact layer formed on the n+-In (y) Ga (1-y) As transition contact layer.

[0009] Among them, the thickness of the n+-GaAs matching contact layer is 100 nm to 200 nm, and the thickness of the n+-In (x) Ga (1-x) As transition contact layer is 50 nm to 100 nm, and the thickness of the n+-In (y) Ga (1-y) As surface contact layer is 50 nm to 100 nm.

[0010] In the n+-In (x) Ga (1-x) As transition contact layer and the n+-In (y) Ga (1-y) As surface contact layer, the relationship between the x value and the y value is: x ≤ y.

[0011] Further, in the n+-In (x) Ga (1-x) As transition contact layer, the x value is 0 to 0.5, and in the n+-In (y) Ga (1-y) As surface contact layer, the y value is 0.3 to 0.6.

[0012] Further, the doping concentration of the n+-GaAs matching contact layer is 1e18 to 6e18, the doping concentration of the n+-In (x) Ga (1-x) As transition contact layer is greater than 1e18, and the doping concentration of the n+-In (y) Ga (1-y) As surface contact layer is greater than 4e18.

[0013] Further, the n+-In (x) Ga (1-x) As transition contact layer is formed by sequentially laminating a plurality of n+-In (x) (i)Ga (1-x) As transition layers, and the thickness of each n+-In (x) (i)Ga (1-x) As transition layer does not exceed 20 nm, and the n+-In(x) (i) Ga (1-x) In the GaAs transition layer, 0 < x(i) ≤ 0.5.

[0014] The present invention also provides a solar cell, which includes the heterojunction contact layer described above. Among them, the solar cell further includes a substrate, a first sub-cell, a tunnel junction, and a second sub-cell that are sequentially formed on the first surface of the substrate from bottom to top. A back electrode is formed on the second surface of the substrate opposite to the first surface of the substrate. The heterojunction contact layer is formed on the second sub-cell, and a grid electrode is formed on the heterojunction contact layer.

[0015] Furthermore, an anti-reflection film is provided on the surface of the grid electrode.

[0016] Furthermore, the grid electrode is a silver paste electrode, the substrate is a P-type GaAs substrate, the first sub-cell is a GaAs sub-cell, and the second sub-cell is a GaInP sub-cell.

[0017] Furthermore, the GaAs sub-cell includes a p+-GaInP back surface field layer, a p-GaAs base, an n+-GaAs emitter, and an n+-GaInP window layer that are stacked from bottom to top. The p+-GaInP back surface field layer is provided on the P-type GaAs substrate, and the tunnel junction is provided on the n+-GaInP window layer.

[0018] The GaInP sub-cell includes a p-AlGaInP back surface field layer, a p-GaInP base, an n+-GaInP emitter, and an n-AlInP window layer that are stacked from bottom to top. The p-AlGaInP back surface field layer is provided on the tunnel junction, and the heterojunction contact layer is formed on the n-AlInP window layer.

[0019] The present invention also provides a preparation method of the above-mentioned solar cell. The preparation method includes the following steps:

[0020] S10. Grow a first sub-cell on the substrate by molecular beam epitaxy.

[0021] S20. Grow a tunnel junction on the first sub-cell.

[0022] S30. Grow a second sub-cell on the tunnel junction.

[0023] S40. Grow an n+-GaAs matching contact layer on the second sub-cell.

[0024] S50. Grow an n+-In (x) Ga (1-x) As transition contact layer.

[0025] S60. Grow an n+-In (x) Ga (1-x) As surface contact layer on the n+-In (y) Ga (1-y) As transition contact layer.

[0026] S70. Print a grid electrode on the n+-In (y) Ga (1-y) As surface contact layer.

[0027] S80. Form the substrate on the back electrode.

[0028] Furthermore, the growth temperature of the n+-GaAs matching contact layer in step S40 is 530°C to 620°C, and the growth temperature of the n+-In (x) Ga (1-x) As transition contact layer in step S50 is 470°C to 520°C, and the growth temperature of the n+-In (y) Ga (1-y) As surface contact layer in step S60 is 470°C to 520°C.

[0029] The heterojunction contact layer for a solar cell provided by the present invention includes an n+-GaAs matching contact layer, an n+-In (x) Ga (1-x) As transition contact layer formed on the n+-GaAs matching contact layer, and an n+-In (x) Ga (1-x) As surface contact layer formed on the n+-In (y) Ga (1-y) As transition contact layer, thereby forming an n+-GaAs / n+-In (x) Ga (1-x) As / n+-In (y) Ga (1-y) As graded heterojunction structure as the contact layer. Applying the contact layer with such a graded heterojunction structure to a solar cell can better match the work function of the contact layer material and the electrode material in the solar cell, reduce the contact resistance, effectively simplify the preparation process of the solar cell, and improve the photoelectric conversion efficiency at the same time. Among them, the preparation method of the solar cell with the heterojunction contact layer has simple equipment technology and low cost. Description of the Drawings

[0030] Figure 1 is a schematic structural diagram of the solar cell provided by the embodiment of the present invention;

[0031] Figure 2 is a schematic structural diagram of the heterojunction contact layer provided by the embodiment of the present invention;

[0032] Figure 3 This is a schematic structural diagram of the n+-In (x) Ga (1-x) As transition contact layer provided by an embodiment of the present invention. Specific embodiments

[0033] To make the objectives, technical solutions and advantages of the present invention clearer, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the drawings. The embodiments of the present invention shown in the drawings and described according to the drawings are merely exemplary, and the present invention is not limited to these embodiments.

[0034] Here, it should also be noted that in order to avoid obscuring the present invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the present invention are shown in the drawings, while other details less related to the present invention are omitted.

[0035] Figure 2 This is a schematic structural diagram of the heterojunction contact layer provided by an embodiment of the present invention. Refer to Figure 2 , the heterojunction contact layer for a solar cell provided by the present invention includes an n+-GaAs matching contact layer, an n+-In (x) Ga (1-x) As transition contact layer formed on the n+-GaAs matching contact layer, and an n+-In (x) Ga (1-x) As surface contact layer formed on the n+-In (y) Ga (1-y) As transition contact layer.

[0036] Specifically, the thickness of the n+-GaAs matching contact layer is 100 nm to 200 nm, and the thickness of the n+-In (x) Ga (1-x) As transition contact layer is 50 nm to 100 nm, and the thickness of the n+-In (y) Ga (1-y) As surface contact layer is 50 nm to 100 nm.

[0037] Specifically, the relationship between the x value and the y value in the n+-In (x) Ga (1-x) As transition contact layer and the n+-In (y) Ga (1-y) As surface contact layer is: x ≤ y.

[0038] More specifically, the n+-In (x) Ga (1-x)In the n+-InGaAs transition contact layer, the value of x ranges from 0 to 0.5, and the n+- (y) Ga (1-y) In the As surface contact layer, the value of y ranges from 0.3 to 0.6.

[0039] Specifically, the doping concentration of the n+-GaAs matching contact layer is 1e18 to 6e18, and the doping concentration of the n+-In (x) Ga (1-x) As transition contact layer is greater than 1e18, and the doping concentration of the n+-In (y) Ga (1-y) As surface contact layer is greater than 4e18. Refer to Figure 2 , for example, the doping concentration of the n+-GaAs matching contact layer is 1e18 to 6e18, and the doping concentration of the n+-In (x) Ga (1-x) As transition contact layer is 1e18 to 6e18, and the doping concentration of the n+-In (y) Ga (1-y) As surface contact layer is greater than 4e18 to 6e18.

[0040] Specifically, the n+-In (x) Ga (1-x) As transition contact layer is formed by laminating multiple n+-In (x) (i)Ga (1-x) As transition layers in sequence. The thickness of each n+-In (x) (i)Ga (1-x) As transition layer does not exceed 20 nm, and in the n+-In (x) (i)Ga (1-x) As transition layer, 0 < x(i) ≤ 0.5.

[0041] In the n+-In (x) Ga (1-x) As transition contact layer, the value of x transitions from 0 to the value of y. The n+-In (x) Ga (1-x) As transition contact layer includes several transition layers laminated in sequence with the material being n+-In (x) (i)Ga (1-x) As. The value range of the indium content is 0 < x(i) ≤ 0.5. That is, the n+-In (x) Ga (1-x) As transition contact layer represents a series of In (x) (i)Ga (1-x)As a combination of transition layers, wherein the change in indium content x(i) is achieved by controlling the flow rate of the indium source or the gallium source, thereby forming a series of transition layer groups with gradually changing compositions. The change mode of the indium content x(i) can be selected from any one of the linear increase or stepwise increase in the direction away from the n+-GaAs matching contact layer.

[0042] Figure 3 is the n+-In provided by the embodiment of the present invention (x) Ga (1-x) Schematic structural diagram of the As transition contact layer. Refer to Figure 3 , for example, in this embodiment, n+-In (x) Ga (1-x) The As transition contact layer includes N+-In grown by laminating from bottom to top in sequence (0.1) Ga (0.9) As, N+-In (0.2) Ga (0.8) As, N+-In (0.3) Ga (0.7) As, N+-In (0.4) Ga (0.6) As, N+-In (0.5) Ga (0.5) As, and the thickness of each transition layer does not exceed 20 nm. Among them, the transition layer where N+-In (0.1) Ga (0.9) As is formed on the n+-GaAs matching contact layer.

[0043] The heterojunction contact layer provided by the above embodiment is formed by laminating the n+-GaAs matching contact layer, the n+-In (x) Ga (1-x) As transition contact layer, and the n+-In (y) Ga (1-y) As surface contact layer in sequence, thereby forming an n+-GaAs / n+-In (x) Ga (1-x) As / n+-In (y) Ga (1-y) As gradually varying heterojunction structure contact layer. Applying this gradually varying heterojunction structure contact layer to a solar cell can better match the work function of the contact layer material and the electrode material in the solar cell, and reduce the contact resistance.

[0044] An embodiment of the present invention further provides a solar cell, which includes the above-mentioned heterojunction contact layer. Specifically, the solar cell further includes a substrate, a first sub-cell, a tunnel junction, and a second sub-cell that are sequentially formed on the first surface of the substrate from bottom to top. A back electrode is formed on the second surface of the substrate opposite to the first surface. The heterojunction contact layer is formed on the second sub-cell, and a grid electrode is formed on the heterojunction contact layer.

[0045] Figure 1 is a schematic structural diagram of the solar cell provided by the embodiment of the present invention. Refer to Figure 1 , specifically, the grid electrode is a silver paste electrode, the substrate is a P-type GaAs substrate, the first sub-cell is a GaAs sub-cell, the second sub-cell is a GaInP sub-cell, and an anti-reflection film is provided on the surface of the grid electrode.

[0046] Specifically, the tunnel junction is p+GaAs / n+GaAs or p+AlGaAs / n+GaInP or p-GaAs / n-GaAs.

[0047] Specifically, the GaAs sub-cell includes a p+-GaInP back surface field layer, a p-GaAs base, an n+-GaAs emitter, and an n+-GaInP window layer that are stacked in sequence from bottom to top. The p+-GaInP back surface field layer is disposed on the P-type GaAs substrate, and the tunnel junction is disposed on the n+-GaInP window layer.

[0048] More specifically, refer to Figure 1 , in this embodiment, the GaAs sub-cell (GaAs Bottom cell) includes a p-GaInP back surface field layer, a p-GaAs base, an n-GaAs emitter, and an n-GaInP window layer that are stacked in sequence from bottom to top, and the tunnel junction is disposed on the n-GaInP window layer.

[0049] Refer to Figure 1 , the tunnel junction (GaAs Tunneljunction) p-GaAsTJ / n-GaAsTJ is disposed on the n-GaInP window layer in the GaAs sub-cell.

[0050] Refer to Figure 1 , the p-GaInP back surface field layer in the GaAs sub-cell is disposed on the P-type GaAs substrate, and the P-type GaAs substrate is disposed on the back electrode.

[0051] Specifically, the GaInP sub-cell includes a p-AlGaInP back surface field layer, a p-GaInP base, an n+-GaInP emitter, and an n-AlInP window layer, which are stacked from bottom to top. The p-AlGaInP back surface field layer is disposed on the tunnel junction, and the heterojunction contact layer is formed on the n-AlInP window layer.

[0052] More specifically, referring to Figure 1 , in this embodiment, the GaInP sub-cell (GaInP Bottom cell) includes a p-AlGaInP back surface field layer, a p-GaInP base, an n-GaInP emitter, and an n-AlInP window layer, which are stacked from bottom to top. The heterojunction contact layer is disposed on the n-AlInP window layer, and the p-AlGaInP back surface field layer is disposed on the tunnel junction.

[0053] Referring to Figure 1 , specifically, the grid electrode is disposed on the heterojunction contact layer (n+-GaAs / n+-In (x) Ga (1-x) As / n+-In (y) Ga (1-y) As). The grid electrode adopts a traditional comb-shaped electrode, and the shielding area of the electrode is 2-5%. The grid electrode material uses silver paste, and through thermal annealing, a good ohmic contact is formed between the grid electrode and the n+-In (y) Ga (1-y) As layer.

[0054] In an embodiment of the present invention, the heterojunction contact layer is applied to a double-junction GaInP / GaAs solar cell formed by a GaAs sub-cell and a GaInP sub-cell. Based on the lower work function of the n+-In (y) Ga (1-y) As material on the uppermost surface in the GaAs / InGaA heterojunction structure, the work function of the contact layer material and the annealed silver metal is better matched, the contact resistance is reduced, the preparation process of the double-junction solar cell is effectively simplified, and the photoelectric conversion efficiency is improved.

[0055] The heterojunction contact layer for a solar cell provided by the present invention is not limited to a double-junction GaInP / GaAs solar cell, and can also be applied to an AlGaInP / GaInP / GaAs triple-junction solar cell, a GaInP / GaAs / Ge triple-junction solar cell, an AlGaInP / GaInP / GaAs / Ge quadruple-junction solar cell, as well as a GaInP single-junction cell and a GaAs single-junction cell, so as to simplify the electrode preparation process thereof.

[0056] An embodiment of the present invention further provides a preparation method for the above-mentioned solar cell, and the preparation method includes the following steps:

[0057] S10. Grow the first sub-cell on the substrate by molecular beam epitaxy growth method.

[0058] Specifically, in this embodiment, the first sub-cell is a single-junction GaAs sub-cell. In the molecular beam epitaxy growth system, the P-type GaAs substrate is heated to deoxidize, and then a p+-GaInP back surface field layer, a p-GaAs base, an n+-GaAs emitter, and an n+-GaInP window layer are sequentially grown on the substrate.

[0059] Specifically, the growth temperature of the GaAs sub-cell is 580 °C to 650 °C, and the growth rate is 0.5 ml / s to 1.5 ml / s.

[0060] S20. Grow a tunnel junction on the first sub-cell.

[0061] Specifically, in this embodiment, a tunnel junction is grown on the single-junction GaAs sub-cell, and the tunnel junction is grown on the n+-GaInP window layer in the single-junction GaAs sub-cell.

[0062] S30. Grow a second sub-cell on the tunnel junction.

[0063] Specifically, in this embodiment, a single-junction GaInP sub-cell is grown on the tunnel junction. When growing the single-junction GaInP sub-cell, a p+-AlGaInP back surface field layer is first grown on the tunnel junction, and then a p-GaInP base, an n+-GaInP emitter, and an n-AlInP window layer are sequentially grown.

[0064] S40. Grow an n+-GaAs matching contact layer on the second sub-cell.

[0065] Specifically, in this embodiment, an n+-GaAs matching contact layer is grown on the single-junction GaInP sub-cell. The growth temperature of the n+-GaAs matching contact layer is between 530 and 620 °C, the thickness of the n+-GaAs matching contact layer is 100 nm to 200 nm, and the doping concentration is 1e18 to 6e18. Synchronously adjust the In source furnace temperature according to the In component in n+-In (x) Ga (1-x) As.

[0066] More specifically, the growth temperature of the n+-GaAs matching contact layer adopts a step-by-step transition.

[0067] S50. Grow an n+-In (x) Ga (1-x) As transition contact layer on the n+-GaAs matching contact layer.

[0068] Specifically, in this embodiment, after the growth of the n+-GaAs matching contact layer, the substrate temperature is lowered, and n+-In (x) Ga (1-x) As transition contact layer is grown on the n+-GaAs matching contact layer. The temperature is between 470 °C and 520 °C, the thickness is 50 nm to 150 nm, and the x value is between 0 and 0.5.

[0069] The n+-In (x) Ga (1-x) The material growth mode of the As transition contact layer is as follows: the x value is in a gradient mode, a step mode, or linearly increasing.

[0070] More specifically, the x value of n+-In (x) Ga (1-x) As gradually transitions from 0 to between 0.3 and 0.5.

[0071] S60. Grow an n+-In (x) Ga (1-x) As surface contact layer on the n+-In (y) Ga (1-y) As surface contact layer.

[0072] Specifically, grow an n+-In (x) Ga (1-x) As surface contact layer on the n+-In (y) Ga (1-y) As surface contact layer. The temperature is between 470 °C and 520 °C, the thickness is 50 nm to 100 nm, and the y value is between 0.3 and 0.6.

[0073] S70. Print a gate electrode on the n+-In (y) Ga (1-y) As surface contact layer.

[0074] Specifically, in this embodiment, a gate electrode is prepared on the surface of the n+-In (y) Ga (1-y) As surface contact layer. The gate electrode uses a traditional comb-shaped electrode. The shielding area of the electrode is 2% to 5%. The gate electrode material uses silver paste. After evaporating the electrode, the unnecessary contact layer is etched off. Finally, an antireflection film is grown in the window layer area in the middle of the gate electrode.

[0075] S80. Form the substrate on the back electrode.

[0076] Specifically, in this embodiment, a back electrode is prepared on the entire bottom surface of the GaAs sub-cell on the substrate.

[0077] In the above preparation method, in the heterojunction contact layer growth method, Si or Te is selected as the n-type doping source.

[0078] In III-V solar cells, the contact layer is used to fabricate the upper surface electrode thereon, so as to collect the current generated by light irradiation within the P-N junction and output it to an external load. Conventional GaAs-based multi-junction solar cells use a GaAs contact layer. The front grid electrode forms an Au alloy on the contact layer through photolithography and electron beam evaporation. The patterning electrode operation process is very complex and costly. Using a silver paste electrode can greatly reduce the electrode manufacturing cost and simplify the process flow at the same time.

[0079] In the conventional GaAs contact layer, the silver paste needs high-temperature annealing when contacting with GaAs. After the silver paste is annealed at high temperature, the resistivity between the silver paste and the GaAs contact layer reaches 6.67×10 -4 Ω·cm 2 .

[0080] In the present invention, an n+-GaAs / n+-In (x) Ga (1-x) As / n+-In (y) Ga (1-y) As heterojunction structure is used as the contact layer to replace the conventional n+-GaAs contact layer. It can better match the work function of the annealed silver metal, thereby reducing the contact resistance between the upper surface n-type contact layer and the new silver paste electrode, realizing the reduction of the overall series resistance of the battery, effectively simplifying the electrode preparation process and cost of the battery structure in the later stage, and improving the efficiency of multi-junction solar cells at the same time.

[0081] In the present invention, through specific experiments, using an n+-GaAs / n+-In (x) Ga (1-x) As / n+-In (y) Ga (1-y) As heterojunction structure contact layer, the resistivity between this contact layer and the silver paste can reach 5.79×10 -5 Ω·cm 2 , and the contact current between the contact layer and the silver paste is also more stable.

[0082] In summary, the heterojunction contact layer for solar cells provided by the embodiments of the present invention can enable the solar cell to omit the photolithography electrode and electron beam evaporation processes during preparation, and at the same time reduce the contact resistance formed between the electrode material on the solar cell and the heterojunction contact layer, realizing the reduction of the overall series resistance of the battery, effectively simplifying the electrode preparation process and cost, and improving the efficiency of multi-junction solar cells at the same time.

[0083] The above are only specific embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A heterojunction contact layer for a solar cell, characterized in that, The heterojunction contact layer includes an n+-GaAs matching contact layer, an n+-In (x) Ga (1-x) As transition contact layer formed on the n+-GaAs matching contact layer, and an n+-In (x) Ga (1-x) As transition contact layer formed on the n+-In (y) Ga (1-y) As surface contact layer; Among them, the thickness of the n+-GaAs matching contact layer is 100 nm to 200 nm, and the n+-In (x) Ga (1-x) As transition contact layer has a thickness of 50 nm to 100 nm, and the n+-In (y) Ga (1-y) As surface contact layer has a thickness of 50 nm to 100 nm; The n+-In (x) Ga (1-x) As transition contact layer and the n+-In (y) Ga (1-y) The relationship between the x value and the y value in the As surface contact layer is: x ≤ y.

2. The heterojunction contact layer for a solar cell according to claim 1, wherein The n+-In (x) Ga (1-x) value of x in the As transition contact layer is 0 to 0.5, and the n+-In (y) Ga (1-y) value of y in the As surface contact layer is 0.3 to 0.

6.

3. The heterojunction contact layer for a solar cell according to claim 1, wherein The doping concentration of the n+-GaAs matching contact layer is 1e18 to 6e18, and the n+-In (x) Ga (1-x) As transition contact layer has a doping concentration greater than 1e18, and the n+-In (y) Ga (1-y) As surface contact layer has a doping concentration greater than 4e18.

4. The heterojunction contact layer for a solar cell according to claim 1, characterized in that, The n+-In (x) Ga (1-x) As transition contact layer is formed by stacking multiple n+-In (x) (i)Ga (1-x) As transition layers in sequence, and each of the n+-In (x) (i)Ga (1-x) As transition layer has a thickness not exceeding 20 nm, and in the n+-In (x) (i)Ga (1-x) As transition layer, 0 < x(i) ≤ 0.

5.

5. A solar cell, characterized in that, The solar cell includes a heterojunction contact layer as described in any one of claims 1-4. Wherein, the solar cell further includes a substrate, a first sub-cell, a tunnel junction, and a second sub-cell that are sequentially formed on the first surface of the substrate from bottom to top. A back electrode is formed on the second surface of the substrate opposite to the first surface of the substrate. The heterojunction contact layer is formed on the second sub-cell, and a grid electrode is formed on the heterojunction contact layer.

6. The solar cell according to claim 5, wherein, An anti-reflection film is provided on the surface of the grid electrode.

7. The solar cell according to claim 6, characterized in that, The grid electrode is a silver paste electrode, the substrate is a P-type GaAs substrate, the first sub-cell is a GaAs sub-cell, and the second sub-cell is a GaInP sub-cell.

8. The solar cell according to claim 7, wherein, The GaAs sub-cell includes a p+-GaInP back surface field layer, a p-GaAs base, an n+-GaAs emitter, and an n+-GaInP window layer that are stacked from bottom to top. The p+-GaInP back surface field layer is disposed on the P-type GaAs substrate, and the tunnel junction is disposed on the n+-GaInP window layer. The GaInP sub-cell includes a p-AlGaInP back surface field layer, a p-GaInP base, an n+-GaInP emitter, and an n-AlInP window layer that are stacked from bottom to top. The p-AlGaInP back surface field layer is disposed on the tunnel junction, and the heterojunction contact layer is formed on the n-AlInP window layer.

9. A method for preparing a solar cell according to any one of claims 5-8, characterized in that, The preparation method includes the following steps: S10: Grow a first sub-cell on the substrate by molecular beam epitaxy growth method. S20: Grow a tunnel junction on the first sub-cell. S30: Grow a second sub-cell on the tunnel junction. S40: Grow an n+-GaAs matching contact layer on the second sub-cell. S50. Grow an n+-In (x) Ga (1-x) As transition contact layer on the n+-GaAs matching contact layer; (x) Ga (1-x) As transition contact layer; S60. Growing an n+-In (x) Ga (1-x) As transition contact layer on the n+-In (y) Ga (1-y) As surface contact layer; S70. Printing a gate electrode on the n+-In (y) Ga (1-y) As surface contact layer; S80: Form the substrate on the back electrode.

10. The manufacturing method of the solar cell according to claim 9, characterized in that, In the step S40, the growth temperature of the n+-GaAs matching contact layer is 530°C to 620°C. In the step S50, the growth temperature of the n+-In (x) Ga (1-x) As transition contact layer is 470°C to 520°C. In the step S60, the growth temperature of the n+-In (y) Ga (1-y) As surface contact layer is 470°C to 520°C.

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