Back contact battery capable of resisting hot spot effect and preparation method of back contact battery

Abstract

The invention discloses a hot spot effect-resistant back contact cell and a preparation method thereof, and belongs to the field of solar cells, the hot spot effect-resistant back contact cell comprises a silicon substrate, a plurality of first areas and a plurality of second areas with opposite polarities are alternately arranged on the back surface of the silicon substrate, and fourth areas are arranged on the side edges, close to the second areas, of the first areas; the fourth region comprises a gradually-changed lightly-doped region which is in composite contact with the first doped layer, and a heavily-doped region which is in composite contact with the second passivation layer is arranged on the back surface, far away from the silicon substrate, of the gradually-changed lightly-doped region. The method has the beneficial effects that the electric leakage channel formed in the fourth region is adjusted into the heavily-doped region and the gradually-changed lightly-doped region by utilizing laser beams and improving the process, so that the electric leakage capability of a single electric leakage channel is remarkably enhanced, and the electric leakage capacity of the single electric leakage channel is greatly improved while the number of the required electric leakage channels is reduced; and carrier recombination during normal working of a single electric leakage channel is reduced, and the targets of high-efficiency hot spot prevention and high photoelectric conversion efficiency are achieved.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and more particularly, to a back-contact cell with anti-hot spot effect and a method for preparing the same. Background Art

[0002] The hot spot effect refers to the situation where when some cells in a solar cell module are shaded, the voltage increases due to the inability to output current, and then local hot spots are generated on the cell, thus triggering the hot spot effect. Since the front side of a back-contact solar cell has no electrode obstruction, it can minimize optical losses and increase the short-circuit current density to the greatest extent, so it has a relatively high photoelectric conversion efficiency. However, there is a technical problem with existing back-contact solar cells, that is, how to effectively prevent the occurrence of the hot spot effect while improving the photoelectric conversion efficiency. To prevent the hot spot effect, existing back-contact solar cells usually adopt the Zener breakdown principle, overlapping part of the first doping layer and the second doping layer to form a leakage channel to release heat. However, this method requires a large number of leakage channels to achieve an effective anti-hot spot effect, and a large number of leakage channels will increase carrier recombination during normal operation, reducing the photoelectric conversion efficiency.

[0003] Moreover, during the preparation process of TBC cells, there are relatively high requirements for the concentration of the doping layer. When the doping concentration is too high, serious Auger recombination will occur, reducing the minority carrier lifetime, which in turn affects the cell efficiency. And the concentration threshold limits the leakage ability of a single leakage channel. Therefore, when in the reverse bias state, the leakage ability of a single leakage channel is weak. To make the cell have a leakage ability that meets the requirements, a relatively large number of leakage channels are needed. And the doping concentration threshold limits the barrier height of the PN junction of the leakage channel. When in the forward bias state, carriers are prone to directly cross the barrier of the leakage channel and recombine, thereby reducing the cell efficiency. The more the number, the greater the efficiency loss. For example, the invention patent with the publication number CN117976743A discloses a solar cell, a cell module and a photovoltaic system. The solar cell includes a silicon wafer, a first doping layer and a second doping layer. The second doping layer is in compound contact with the first doping layer at a preset position to form a leakage recombination contact structure, which can reduce the hot spot risk without causing too much loss of the conversion efficiency of the solar cell. However, under the premise of effectively controlling the hot spot, a 0.3% efficiency loss is still a relatively large value for the cell. Therefore, how to achieve efficient anti-hot spot effect in back-contact solar cells while avoiding the efficiency loss caused by excessive leakage channels has become an urgent technical problem to be solved.

[0004] In view of this, the inventor of the present invention has conducted in-depth research on this need, and thus this case has been created. Summary of the Invention

[0005] To improve the generation of hot spot effects in back-contact solar cells in the prior art, and to address the problem that while improving the generation of hot spot effects, it leads to an increase in carrier recombination and a decrease in photoelectric conversion efficiency, this application provides an anti-hot spot effect back-contact cell and its preparation method, and the technical solution is as follows:

[0006] An anti-hot spot effect back-contact cell includes a silicon substrate. On the back of the silicon substrate, there are several first regions and several second regions. The first regions and the second regions have opposite polarities and are arranged alternately along a first direction. At the connection of the first region and the second region, a third region is provided. The first region, the second region, and the third region all extend along a second direction, and the second direction intersects the first direction perpendicularly; the first region includes a first passivation layer and a first doping layer stacked in sequence on the back of the silicon substrate, the second region includes a second passivation layer and a second doping layer stacked in sequence on the back of the silicon substrate, a fourth region is provided on the side of the first region close to the second region, and the fourth region is evenly distributed on the side of the first region along the second direction. The fourth region includes a graded lightly doped region in compound contact with the first doping layer, and a heavily doped region in compound contact with the second passivation layer is provided away from the back of the silicon substrate on the graded lightly doped region.

[0007] By setting the fourth region as a heavily doped region in compound contact with the first doping region and a graded lightly doped region in compound contact with the second doping region, wherein the heavily doped region and the second doping layer form a high-barrier vertical junction, and the graded lightly doped region and the second doping layer form an auxiliary lateral junction, both having a strong Zener breakdown effect. In addition, the heavily doped region and the graded lightly doped region are designed in a stacked manner, thereby forming a dual-channel conductivity of lateral lightly doped conduction / longitudinal heavily doped conduction, and the ratio range of lateral lightly doped conduction / longitudinal heavily doped conduction is 0.5:1 to 2:1.

[0008] Preferably, the doping element of the heavily doped region is boron, and the doping concentration is 1×10 21 ~1×10 23 cm -3 , and the longitudinal doping depth is 10 - 20 nm; the doping element of the graded lightly doped region is boron, and the graded doping concentration is from 1×10 21 cm -3 to 1×10 17 cm -3 .

[0009] Preferably, the barrier height formed by the heavily doped region and the second doping layer is 0.1 - 0.5 eV higher than the barrier height formed by the graded lightly doped region and the second doping layer.

[0010] By forming a barrier height difference of 0.1 - 0.5 eV, it is ensured that in a single leakage channel, carriers in the leakage channel under forward bias during normal operation are not likely to cross the barrier, further reducing carrier recombination in the battery cell within a single leakage channel during normal operation, thereby achieving efficient thermal hotspot prevention and high photovoltaic conversion efficiency. Moreover, when the longitudinal junction barrier height is higher than that of the lateral junction, the carrier recombination probability under its normal operating state is less than that of the lateral junction, and its reverse leakage ability is also higher than that of the lateral junction. While further improving the leakage ability of a single leakage channel, the efficiency loss is further reduced.

[0011] Preferably, the first passivation layer is a tunneling oxide layer with a thickness of 3 - 10 nm, and the first doping layer is a doped polysilicon layer doped with boron element, with a doping thickness of 150 - 350 nm and a doping concentration of 5×10 19 ~1×10 20 cm -3 ; the second passivation layer is a tunneling oxide layer with a thickness of 3 - 10 nm, and the second doping layer is a doped polysilicon layer doped with phosphorus element, with a doping thickness of 150 - 300 nm and a doping concentration of 1×10 20 ~1×10 22 cm -3 .

[0012] Preferably, the front side of the silicon substrate sequentially includes a front passivation layer and a front antireflection layer from inside to outside; the back side of the silicon substrate sequentially includes the first region / the second region, a back passivation layer, a back antireflection layer, and an electrode from inside to outside; the first region and the second region have opposite polarities and are alternately arranged along the first direction, and a third region is provided at the connection of the first region and the second region. The first region, the second region, and the third region all extend along the second direction, and the second direction is perpendicular to and intersects with the first direction; a fourth region is provided on the side of the first region close to the second region, and the fourth region is evenly distributed on the side of the first region along the second direction. The fourth region includes a gradually graded lightly doped region in composite contact with the first doping layer, and a heavily doped region in composite contact with the second passivation layer is provided away from the back side of the silicon substrate in the gradually graded lightly doped region; the electrode includes a first electrode and a second electrode. The first electrode penetrates the back antireflection layer and the back passivation layer to form an ohmic contact with the first doping layer, and the second electrode penetrates the back antireflection layer and the back passivation layer to form an ohmic contact with the second doping layer.

[0013] This application also provides a preparation method for the above back contact battery, including the following steps:

[0014] Step 1, select a silicon substrate and put it into a tank-type alkaline solution for polishing;

[0015] Step 2: Deposit a first passivation layer and a first doping layer successively on the entire back surface of the silicon substrate;

[0016] Step 3: Deposit a layer of BSG layer on the back surface of the silicon substrate;

[0017] Step 4: Use a laser beam to perform spaced ablation on the back surface of the silicon substrate, and use an alkali solution to etch the silicon substrate to respectively form a first unablated region, a second region exposing the silicon substrate, and a third region exposing the silicon substrate;

[0018] Step 5: Use a laser beam to irradiate the side part of the BSG layer of the first region close to the second region to form a fourth region. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doping layer to form a heavily doped region;

[0019] Step 6: Anneal the heavily doped region to redistribute the boron element in the first doping layer to form a graded lightly doped region;

[0020] Step 7: Deposit a second passivation layer, a second doping layer, and a PSG layer successively on the entire back surface of the silicon substrate;

[0021] Step 8: Use a laser beam to ablate the PSG layer of the first region and the third region on the back surface of the silicon substrate, and use a strong acid to etch the front and side surfaces of the silicon substrate to respectively expose the silicon substrate on the front and side surfaces;

[0022] Step 9: Use an alkali solution and a strong acid to respectively clean the surfaces of the first region and the third region, and simultaneously texture the front surface and the third region of the silicon substrate to expose the silicon substrate in the third region, and clean the PSG in the second region;

[0023] Step 10: Deposit a front passivation layer and a back passivation layer on the front and back surfaces of the silicon substrate;

[0024] Step 11: Deposit a front antireflection layer and a back antireflection layer on the front and back surfaces of the silicon substrate;

[0025] Step 12: Perform paste printing and metal sintering on the silicon substrate.

[0026] Preferably, the thickness of the BSG layer deposited on the back surface of the silicon substrate in Step 3 is 50 - 100 nm; the thickness of the PSG layer deposited on the back surface of the silicon substrate in Step 7 is 50 - 100 nm.

[0027] Preferably, Step 4 specifically includes: using the laser beam to ablate the BSG layer of the second region and the third region. The laser beam uses pulsed laser, the pulse width is 5 - 30 ps, the wavelength is 355 nm or 532 nm, the spot size is 150 - 300 μm, and the energy density is 4×103 J / m 2 ~9×10 3 J / m 2 , with an overlap rate of 10 - 80%; after the lye is etched with NaOH, there is still a BSG layer with a thickness of 10 - 40 nm on the surface of the first region, and the surface height of the first region is 1 - 5 μm higher than that of the second region.

[0028] Preferably, the fifth step specifically includes: irradiating the BSG layer in the fourth region with the laser beam, and the BSG layer serves as a boron source for longitudinal diffusion into the first doping layer. The laser beam is a pulsed laser with a pulse width of 5 - 30 ps, a wavelength of 355 nm or 532 nm, a spot size of 150 - 300 μm, and an energy density of 3.55×10 3 J / m 2 ~6.5×10 3 J / m 2 , with an overlap rate of 10 - 80%.

[0029] The BSG layer acts as an isolation layer to block the longitudinal conductivity, making the heavily doped region non-conductive. Therefore, by irradiating the BSG layer with a laser in the fifth step, not only can the remaining BSG isolation layer be modified into an active layer, enabling the heavily doped region in the fourth region to have conductivity, but also the ability of a single leakage channel is significantly improved while controlling the doping concentration to be 1×10 21 ~1×10 23 cm -3 and a doping depth of 10 - 20 nm are easily achievable in industrial scale production, and the Zener breakdown effect of the heavily doped region is better.

[0030] Preferably, the sixth step specifically includes: annealing the heavily doped region to redistribute boron elements in the first doping layer, with an annealing temperature of 800 - 1000 °C and an annealing time of 30 - 90 min.

[0031] The gradient effect of the graded lightly doped region can be achieved by annealing the longitudinal doping region. However, in the seventh step, the second passivation layer, the second doping layer, and the PSG layer are deposited in sequence, which also requires deposition in a high-temperature environment. Therefore, the sixth step can be omitted. However, since the main purpose of the seventh step is to deposit other substances and the process parameters mainly focus on depositing other substances, the annealing effect is not as good as that of separate annealing, and the conductivity of the leakage channel is not as good as that of separate annealing. However, the conductivity of the leakage channel is still significantly improved compared to the heavily doped state. Considering the cost, it can be cancelled.

[0032] Preferably, the step eight specifically includes: using the laser beam to ablate the PSG layer in the first region and the third region, the laser beam is a pulsed laser with a pulse width of 5 to 30 ps, a wavelength of 355 nm or 532 nm, a spot size of 150 to 300 μm, and an energy density of 2×10 3 j / m 2 ~4×10 3 j / m 2 , the overlap rate is 10~50%; the strong acid is HF and HNO3 for etching.

[0033] Preferably, in step nine, alkaline solution and strong acid are used to clean the second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region respectively, and the front side of the silicon substrate and the third region are textured simultaneously to expose the silicon substrate in the third region and clean the PSG in the second region; after textured, the texture reflectivity of the front side of the silicon substrate is 5~10%, and the surface height of the second region is 1~3μm higher than the surface height of the third region.

[0034] Preferably, in the step ten, the front passivation layer and the back passivation layer with a thickness of 4-10 nm are deposited on the front and back sides of the silicon substrate respectively by an ALD process; and in the step eleven, the front anti-reflection layer and the back anti-reflection layer with a thickness of 50-100 nm are deposited on the front and back sides of the silicon substrate respectively by a PECVD process.

[0035] The beneficial effects produced by the technical solution of the present invention are as follows:

[0036] (1) By using a laser beam and improving the process, the leakage channel formed in the fourth region is adjusted to a heavily doped region and a gradually lightly doped region, so that the leakage capacity of a single leakage channel is significantly enhanced, thereby reducing the number of required leakage channels while also reducing the carrier recombination when a single leakage channel works normally, achieving the goals of efficient hot spot prevention and high photoelectric conversion efficiency.

[0037] (2) The potential barrier height formed by the heavily doped region and the second doped layer is 0.1-0.5 eV higher than the potential barrier height formed by the gradually lightly doped region and the second doped layer, so that in a single leakage channel, the leakage channel carriers in a forward biased state during normal operation are not easy to cross the potential barrier, further reducing the carrier recombination in the single leakage channel during normal operation of the battery cell, thereby achieving efficient hot spot prevention and high photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0039] Figure 1 Schematic structural diagram of the side of the single-crystalline silicon wafer for Embodiment 2;

[0040] Figure 2 Schematic structural diagram of the back of the single-crystalline silicon wafer for Embodiment 2;

[0041] Figure 3 Process flow chart of the preparation method of the back-contact battery for Embodiment 2.

[0042] Explanation of reference numerals: 1, silicon substrate; 2, front passivation layer; 3, front antireflection layer; 4, first region; 41, first passivation layer; 42, first doping layer; 5, second region; 51, second passivation layer; 52, second doping layer; 6, third region; 7, fourth region; 71, heavily doped region; 72, gradually-varying lightly doped region; 8, back passivation layer; 9, back antireflection layer; 10, first electrode; 11, second electrode. Detailed implementation manners

[0043] To make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. Therefore, the detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0044] In this embodiment, by using a laser beam and process improvement, the leakage channels formed in the fourth region are adjusted into a heavily doped region and a gradually-varying lightly doped region, significantly enhancing the leakage ability of a single leakage channel. Thus, while reducing the required number of leakage channels, the carrier recombination during the normal operation of a single leakage channel is also reduced, achieving the goals of efficient thermal spot prevention and high photoelectric conversion efficiency. The detailed implementation manners are as follows:

[0045] A back-contact cell for resisting hot-spot effect, comprising a silicon substrate, wherein a plurality of first regions and a plurality of second regions are provided on the back surface of the silicon substrate, the first regions and the second regions have opposite polarities and are arranged alternately along a first direction, a third region is provided at the connection of each of the first regions and the second regions, the first regions, the second regions and the third regions all extend along a second direction, and the second direction intersects the first direction perpendicularly; the first region includes a first passivation layer and a first doping layer stacked on the back surface of the silicon substrate in sequence, the second region includes a second passivation layer and a second doping layer stacked on the back surface of the silicon substrate in sequence, a fourth region is provided on the side of the first region close to the second region, and the fourth region is uniformly distributed on the side of the first region along the second direction, the fourth region includes a gradually-varying lightly-doped region in composite contact with the first doping layer, and a heavily-doped region in composite contact with the second passivation layer is provided on the side of the gradually-varying lightly-doped region away from the back surface of the silicon substrate.

[0046] By setting the fourth region as a heavily-doped region in composite contact with the first doping region and a gradually-varying lightly-doped region in composite contact with the second doping region, wherein, the heavily-doped region and the second doping layer form a high-barrier vertical junction, and the gradually-varying lightly-doped region and the second doping layer form an auxiliary lateral junction, both having a strong Zener breakdown effect. In addition, the heavily-doped region and the gradually-varying lightly-doped region are stacked, so as to form a dual-channel conductivity of lateral lightly-doped conductivity / vertical heavily-doped conductivity, and the ratio range of lateral lightly-doped conductivity / vertical heavily-doped conductivity is 0.5:1 to 2:1.

[0047] As a preferred embodiment, the doping element of the heavily-doped region is boron element, and the doping concentration is 1×10 21 ~1×10 23 cm -3 , and the longitudinal doping depth is 10 to 20 nm; the doping element of the gradually-varying lightly-doped region is boron element, and the gradually-varying doping concentration is 1×10 21 cm -3 to 1×10 17 cm -3 .

[0048] As a preferred embodiment, the barrier height formed by the heavily-doped region and the second doping layer is 0.1 to 0.5 eV higher than the barrier height formed by the gradually-varying lightly-doped region and the second doping layer.

[0049] By forming a barrier height difference of 0.1 - 0.5 eV, such that in a single leakage channel, carriers in the leakage channel in the forward bias state during normal operation are not easily able to cross the barrier, further reducing carrier recombination in the battery cell within a single leakage channel during normal operation, thereby achieving efficient thermal hotspot prevention and high photoelectric conversion efficiency. Moreover, when the longitudinal junction barrier height is higher than that of the lateral junction, the carrier recombination probability in its normal operating state is less than that of the lateral junction while its reverse leakage ability is also higher than that of the lateral junction, enabling further improvement in the leakage ability of a single leakage channel while further reducing efficiency loss.

[0050] As a preferred embodiment, the first passivation layer is a tunneling oxide layer with a thickness of 3 - 10 nm, the first doping layer is a doped polysilicon layer doped with boron element, the doping thickness is 150 - 350 nm, and the doping concentration is 5×10 19 ~1×10 20 cm -3 ; the second passivation layer is a tunneling oxide layer with a thickness of 3 - 10 nm, the second doping layer is a doped polysilicon layer doped with phosphorus element, the doping thickness is 150 - 300 nm, and the doping concentration is 1×10 20 ~1×10 22 cm -3 。

[0051] As a preferred embodiment, the front surface of the silicon substrate sequentially includes a front passivation layer and a front antireflection layer from the inside to the outside; the back surface of the silicon substrate sequentially includes the first region / the second region, a back passivation layer, a back antireflection layer, and an electrode from the inside to the outside; the first region and the second region have opposite polarities and are alternately arranged along the first direction, a third region is provided at the connection of the first region and the second region, the first region, the second region, and the third region all extend along the second direction, and the second direction is perpendicular and intersects with the first direction; a fourth region is provided on the side of the first region close to the second region, and the fourth region is evenly distributed on the side of the first region along the second direction. The fourth region includes a graded lightly doped region in composite contact with the first doping layer, and a heavily doped region in composite contact with the second passivation layer is provided away from the back surface of the silicon substrate in the graded lightly doped region; the electrode includes a first electrode and a second electrode, the first electrode penetrates through the back antireflection layer and the back passivation layer to form an ohmic contact with the first doping layer, and the second electrode penetrates through the back antireflection layer and the back passivation layer to form an ohmic contact with the second doping layer.

[0052] The present application also provides a method for manufacturing the above-mentioned back contact battery, including the following steps:

[0053] Step 1: Select a silicon substrate and place it in a trough-type alkaline solution for polishing;

[0054] Step 2: Deposit a first passivation layer and a first doping layer successively on the entire back surface of the silicon substrate;

[0055] Step 3: Deposit a layer of BSG layer on the back surface of the silicon substrate;

[0056] Step 4: Use a laser beam to perform spaced ablation on the back surface of the silicon substrate, and use an alkaline solution to etch the silicon substrate to form a first non-ablated region, a second region exposing the silicon substrate, and a third region exposing the silicon substrate respectively;

[0057] Step 5: Use a laser beam to irradiate the side part of the BSG layer of the first region close to the second region to form a fourth region. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doping layer to form a heavily doped region;

[0058] Step 6: Anneal the heavily doped region to redistribute the boron element in the first doping layer to form a graded lightly doped region;

[0059] Step 7: Deposit a second passivation layer, a second doping layer, and a PSG layer successively on the entire back surface of the silicon substrate;

[0060] Step 8: Use a laser beam to ablate the PSG layer of the first region and the third region on the back surface of the silicon substrate, and use a strong acid to etch the front and side surfaces of the silicon substrate to expose the silicon substrate on the front and side surfaces respectively;

[0061] Step 9: Use an alkaline solution and a strong acid to clean the surfaces of the first region and the third region respectively, and simultaneously texture the front surface and the third region of the silicon substrate to expose the silicon substrate in the third region, and clean the PSG in the second region;

[0062] Step 10: Deposit a front passivation layer and a back passivation layer on the front and back surfaces of the silicon substrate;

[0063] Step 11: Deposit a front antireflection layer and a back antireflection layer on the front and back surfaces of the silicon substrate;

[0064] Step 12: Perform paste printing and metal sintering on the silicon substrate.

[0065] As a preferred embodiment, the thickness of the BSG layer deposited on the back surface of the silicon substrate in Step 3 is 50 - 100 nm; the thickness of the PSG layer deposited on the back surface of the silicon substrate in Step 7 is 50 - 100 nm.

[0066] As a preferred embodiment, step four specifically includes: using the laser beam to ablate the BSG layers in the second region and the third region, the laser beam being pulsed laser with a pulse width of 5 - 30 ps, a wavelength of 355 nm or 532 nm, a spot size of 150 - 300 μm, and an energy density of 4×10 3 j / m 2 ~9×10 3 j / m 2 , with an overlap rate of 10 - 80%; after etching with NaOH for the lye, there is still a 10 - 40 nm BSG layer on the surface of the first region, and the surface height of the first region is 1 - 5 μm higher than the surface height of the second region.

[0067] As a preferred embodiment, step five specifically includes: irradiating the BSG layer in the fourth region with a laser beam, the BSG layer serving as a boron source for longitudinal diffusion into the first doped layer, the laser beam being pulsed laser with a pulse width of 5 - 30 ps, a wavelength of 355 nm or 532 nm, a spot size of 150 - 300 μm, and an energy density of 3.55×10 3 j / m 2 ~6.5×10 3 j / m 2 , with an overlap rate of 10 - 80%.

[0068] The BSG layer acts as an isolation layer to block the longitudinal conductivity, making the heavily doped region non - conductive. Therefore, by laser irradiating the BSG layer in step five, not only can the remaining BSG isolation layer be modified into an active layer, enabling the heavily doped region in the fourth region to have conductivity, but also the ability of a single leakage channel is significantly improved while controlling the doping concentration to be 1×10 21 ~1×10 23 cm -3 and the doping depth to be 10 - 20 nm are easily achievable in industrial scale production, and the Zener breakdown effect of the heavily doped region is better.

[0069] As a preferred embodiment, step six specifically includes: annealing the heavily doped region to redistribute the boron element within the first doped layer, with an annealing temperature of 800 - 1000 °C and an annealing time of 30 - 90 min.

[0070] The graded effect of the graded lightly doped region can be achieved by annealing the longitudinal doped region. However, in step seven, depositing the second passivation layer, the second doped layer, and the PSG layer in sequence also needs to be deposited in a high-temperature environment, so step six can be omitted. However, since the main purpose of step seven is to deposit other substances and the process parameters mainly focus on depositing other substances, the annealing effect is not as good as that of separate annealing, and the conductivity of the leakage channel is not as good as that of separate annealing either. However, the conductivity of the leakage channel is still significantly improved compared to the heavily doped state. Considering the cost, it can be cancelled.

[0071] As a preferred embodiment, step eight specifically includes: ablating the PSG layer in the first region and the third region using the laser beam. The laser beam is a pulsed laser with a pulse width of 5 - 30 ps, a wavelength of 355 nm or 532 nm, a spot size of 150 - 300 μm, and an energy density of 2×10 3 j / m 2 ~4×10 3 j / m 2 , and the overlap rate is 10 - 50%; the strong acid is etched using HF and HNO3.

[0072] As a preferred embodiment, in step nine, the second doped layer on the surface of the first region, the remaining BSG layer, and the second doped layer in the third region are cleaned using an alkaline solution and a strong acid respectively, and the front surface of the silicon substrate and the third region are textured simultaneously to expose the silicon substrate in the third region and clean the PSG in the second region; after texturing, the surface reflectivity of the front surface of the silicon substrate is 5 - 10%, and the surface height of the second region is 1 - 3 μm higher than the surface height of the third region.

[0073] As a preferred embodiment, in step ten, a front passivation layer and a back passivation layer with a thickness of 4 - 10 nm are deposited on the front and back surfaces of the silicon substrate respectively using the ALD process; in step eleven, a front antireflection layer and a back antireflection layer with a thickness of 50 - 100 nm are deposited on the front and back surfaces of the silicon substrate respectively using the PECVD process.

[0074] Next, the beneficial effects of a back-contact battery with anti-thermal-spot effect and its manufacturing method in the present invention are further evaluated through several sets of examples.

[0075] Example 1:

[0076] This Example 1 provides a back-contact battery with anti - thermal - spot effect, and its manufacturing method includes the following steps:

[0077] Step one, select a single - crystal silicon wafer with a resistivity of 30 Ω·cm and put it into a tank - type alkaline solution for polishing;

[0078] Step 2: Deposit a 3-nm first passivation layer and a 150-nm first doping layer on the entire back surface of the single-crystalline silicon wafer in sequence, with a doping concentration of 5E19 cm -3 ;

[0079] Step 3: Deposit another BSG layer with a thickness of 50 nm on the back surface of the single-crystalline silicon wafer;

[0080] Step 4: Ablate the BSG layer in the second area and the third area on the back surface of the single-crystalline silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 355 nm, a spot size of 150 μm, and an energy density of 4×10 3 j / m 2 , and an overlap rate of 10%; Etch the single-crystalline silicon wafer with NaOH. There is still a 10-nm BSG layer on the surface of the first area, and the surface height of the first area is 1 μm higher than the surface height of the second area;

[0081] Step 5: Irradiate the BSG layer in the fourth area on the back surface of the single-crystalline silicon wafer with a laser beam. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doping layer to form a heavily doped area. The laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 355 nm, a spot size of 150 μm, and an energy density of 3.55×10 3 j / m 2 , and an overlap rate of 10%;

[0082] Step 6: Anneal the heavily doped area to redistribute the boron element in the first doping layer. The annealing temperature is 800 °C and the annealing time is 30 min to form a graded lightly doped area;

[0083] Step 7: Deposit a 3-nm second passivation layer, a 150-nm second doping layer with a doping concentration of 1E20 cm -3 , and a PSG layer with a thickness of 50 nm on the entire back surface of the single-crystalline silicon wafer in sequence;

[0084] Step 8: Ablate the PSG layer in the first area and the third area on the back surface of the single-crystalline silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 355 nm, a spot size of 150 μm, and an energy density of 2×10 3 j / m 2 , and an overlap rate of 10%; Etch the front surface and the side surface of the single-crystalline silicon wafer with HF and HNO3 to expose the single-crystalline silicon wafer on the front surface and the side surface respectively;

[0085] Step Nine: Clean the second doped layer and the remaining BSG layer on the surface of the first region, and the second doped layer in the third region with lye and strong acid respectively, and simultaneously texture the front side of the silicon substrate and the third region to expose the silicon substrate in the third region, clean the PSG in the second region. After texturing, the surface reflectivity of the front side of the silicon substrate is 5%, and the surface height of the second region is 1 μm higher than that of the third region;

[0086] Step Ten: Deposit a front passivation layer and a back passivation layer with a thickness of 4 nm each on the front and back sides of the single-crystalline silicon wafer by ALD process;

[0087] Step Eleven: Deposit a front antireflection layer and a back antireflection layer with a thickness of 50 nm each on the front and back sides of the single-crystalline silicon wafer by PECVD process;

[0088] Step Twelve: Perform paste printing and metal sintering on the single-crystalline silicon wafer.

[0089] Example 2:

[0090] This Example 2 provides a back-contact battery with anti-thermal-spot effect, and its preparation method includes the following steps:

[0091] Step One: Select a single-crystalline silicon wafer with a resistivity of 30 Ω·cm and put it into a trough-type alkaline solution for polishing;

[0092] Step Two: Deposit a first passivation layer with a thickness of 5 nm and a first doped layer with a thickness of 200 nm on the entire back side of the single-crystalline silicon wafer in sequence, and the doping concentration is 7E19 cm -3 ;

[0093] Step Three: Deposit another BSG layer with a thickness of 80 nm on the back side of the single-crystalline silicon wafer;

[0094] Step Four: Ablate the BSG layer in the second region and the third region on the back side of the single-crystalline silicon wafer with a laser beam. The laser beam is a pulsed laser with a pulse width of 10 ps, a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 6×10 3 j / m 2 , and the overlap rate is 30%; Etch the single-crystalline silicon wafer with NaOH. There is still a 30-nm BSG layer on the surface of the first region, and the surface height of the first region is 2 μm higher than that of the second region;

[0095] Step Five: Irradiate the BSG layer in the fourth region on the back side of the single-crystalline silicon wafer with a laser beam. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doped layer to form a heavily doped region. The laser beam is a pulsed laser with a pulse width of 10 ps, a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 4.5×103 J / m 2 with an overlap rate of 30%;

[0096] Step Six: Anneal the heavily doped region to redistribute boron in the first doped layer. The annealing temperature is 900 °C and the annealing time is 60 min to form a gradually-varying lightly doped region;

[0097] Step Seven: Sequentially deposit a 5-nm second passivation layer, a 200-nm second doped layer with a doping concentration of 1E21 cm -3 on the entire back surface of the single-crystalline silicon wafer, and a PSG layer with a thickness of 80 nm;

[0098] Step Eight: Ablate the PSG layer in the first region and the third region on the back surface of the single-crystalline silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 10 ps, a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 3×10 3 J / m 2 with an overlap rate of 30%; and etch the front and side surfaces of the single-crystalline silicon wafer using HF and HNO3 to expose the single-crystalline silicon wafer on the front and side surfaces respectively;

[0099] Step Nine: Clean the second doped layer and the remaining BSG layer on the surface of the first region, and the second doped layer in the third region using an alkaline solution and a strong acid respectively, and simultaneously texture the front surface of the silicon substrate and the third region to expose the silicon substrate in the third region, clean the PSG in the second region. After texturing, the surface reflectivity of the front surface of the silicon substrate is 8%, and the surface height of the second region is 2 μm higher than the surface height of the third region;

[0100] Step Ten: Deposit a front passivation layer and a back passivation layer with a thickness of 5 nm each on the front and back surfaces of the single-crystalline silicon wafer using the ALD process;

[0101] Step Eleven: Deposit a front antireflection layer and a back antireflection layer with a thickness of 70 nm each on the front and back surfaces of the single-crystalline silicon wafer using the PECVD process;

[0102] Step Twelve: Perform paste printing and metal sintering on the single-crystalline silicon wafer.

[0103] Example 3:

[0104] This Example 3 provides a back-contact battery with anti-thermal-spot effect, and its preparation method includes the following steps:

[0105] Step One: Select a single-crystalline silicon wafer with a resistivity of 30 Ω·cm and place it in a trough-type alkaline solution for polishing;

[0106] Step 2: Deposit a first passivation layer with a thickness of 8 nm and a first doping layer with a thickness of 250 nm on the entire back surface of the single-crystalline silicon wafer in sequence, and the doping concentration is 9E19 cm -3 ;

[0107] Step 3: Deposit another BSG layer with a thickness of 90 nm on the back surface of the single-crystalline silicon wafer;

[0108] Step 4: Ablate the BSG layer in the second area and the third area on the back surface of the single-crystalline silicon wafer by using a laser beam. The laser beam is a pulsed laser with a pulse width of 20 ps, a wavelength of 532 nm, a spot size of 250 μm, and an energy density of 8×10 3 j / m 2 , and the overlap rate is 50%; Etch the single-crystalline silicon wafer with NaOH. There is still a 40-nm BSG layer on the surface of the first area, and the surface height of the first area is 4 μm higher than the surface height of the second area;

[0109] Step 5: Irradiate the BSG layer in the fourth area on the back surface of the single-crystalline silicon wafer by using a laser beam. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doping layer to form a heavily doped area. The laser beam is a pulsed laser with a pulse width of 20 ps, a wavelength of 532 nm, a spot size of 250 μm, and an energy density of 5.5×10 3 j / m 2 , and the overlap rate is 60%;

[0110] Step 6: Perform an annealing treatment on the heavily doped area to redistribute the boron element in the first doping layer. The annealing temperature is 900 °C and the annealing time is 80 min to form a gradually-varying lightly doped area;

[0111] Step 7: Deposit a second passivation layer with a thickness of 8 nm, a second doping layer with a thickness of 250 nm, and a doping concentration of 1E21 cm -3 , and a PSG layer with a thickness of 90 nm on the entire back surface of the single-crystalline silicon wafer in sequence;

[0112] Step 8: Ablate the PSG layer in the first area and the third area on the back surface of the single-crystalline silicon wafer by using a laser beam. The laser beam is a pulsed laser with a pulse width of 20 ps, a wavelength of 532 nm, a spot size of 250 μm, and an energy density of 3×10 3 j / m 2 , and the overlap rate is 40%; Etch the front surface and the side surface of the single-crystalline silicon wafer with HF and HNO3 to expose the single-crystalline silicon wafer on the front surface and the side surface respectively;

[0113] Step 9: Clean the second doped layer and the remaining BSG layer on the surface of the first region, and the second doped layer in the third region with lye and strong acid respectively, and simultaneously texture the front side of the silicon substrate and the third region to expose the silicon substrate in the third region, clean the PSG in the second region. After texturing, the surface texture reflectivity of the front side of the silicon substrate is 9%, and the surface height of the second region is 2 μm higher than that of the third region;

[0114] Step 10: Deposit a front passivation layer and a back passivation layer with a thickness of 8 nm each on the front and back sides of the monocrystalline silicon wafer by ALD process;

[0115] Step 11: Deposit a front antireflection layer and a back antireflection layer with a thickness of 80 nm each on the front and back sides of the monocrystalline silicon wafer by PECVD process;

[0116] Step 12: Perform paste printing and metal sintering on the monocrystalline silicon wafer.

[0117] Example 4:

[0118] This Example 4 provides a back contact battery with anti - hot - spot effect, and its preparation method includes the following steps:

[0119] Step 1: Select a monocrystalline silicon wafer with a resistivity of 30 Ω·cm and put it into a trough - type alkaline solution for polishing;

[0120] Step 2: Deposit a first passivation layer with a thickness of 10 nm and a first doped layer with a thickness of 350 nm in sequence on the entire back side of the monocrystalline silicon wafer, and the doping concentration is 1E20 cm -3 ;

[0121] Step 3: Deposit another BSG layer with a thickness of 100 nm on the back side of the monocrystalline silicon wafer;

[0122] Step 4: Ablate the BSG layer in the second region and the third region on the back side of the monocrystalline silicon wafer with a laser beam. The laser beam is a pulsed laser with a pulse width of 30 ps, a wavelength of 532 nm, a spot size of 300 μm, and an energy density of 9×10 3 j / m 2 , and the overlap rate is 80%; Etch the monocrystalline silicon wafer with NaOH. There is still a 40 - nm BSG layer on the surface of the first region, and the surface height of the first region is 5 μm higher than that of the second region;

[0123] Step 5: Irradiate the BSG layer in the fourth region on the back side of the monocrystalline silicon wafer with a laser beam. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doped layer to form a heavily doped region. The laser beam is a pulsed laser with a pulse width of 30 ps, a wavelength of 532 nm, a spot size of 300 μm, and an energy density of 6.5×103 J / m 2 , with an overlap rate of 80%;

[0124] Step Six: Anneal the heavily doped region to redistribute boron in the first doped layer. The annealing temperature is 1000 °C and the annealing time is 90 min to form a graded lightly doped region;

[0125] Step Seven: Deposit a 10-nm second passivation layer and a 300-nm second doped layer on the entire back surface of the single-crystalline silicon wafer in sequence. The doping concentration is 1E22 cm -3 , and a PSG layer with a thickness of 100 nm;

[0126] Step Eight: Ablate the PSG layer in the first and third regions on the back surface of the single-crystalline silicon wafer using a laser beam. The laser beam is a pulsed laser with a pulse width of 30 ps, a wavelength of 532 nm, a spot size of 300 μm, and an energy density of 4×10 3 J / m 2 , with an overlap rate of 50%; and etch the front and side surfaces of the single-crystalline silicon wafer using HF and HNO3 to expose the single-crystalline silicon wafer on the front and side surfaces respectively;

[0127] Step Nine: Clean the second doped layer and the remaining BSG layer on the surface of the first region and the second doped layer in the third region using an alkaline solution and a strong acid respectively, and simultaneously texture the front surface and the third region of the silicon substrate to expose the silicon substrate in the third region, clean the PSG in the second region. After texturing, the surface reflectivity of the front surface of the silicon substrate is 10%, and the surface height of the second region is 3 μm higher than the surface height of the third region;

[0128] Step Ten: Deposit a front passivation layer and a back passivation layer with a thickness of 10 nm each on the front and back surfaces of the single-crystalline silicon wafer using the ALD process;

[0129] Step Eleven: Deposit a front antireflection layer and a back antireflection layer with a thickness of 100 nm each on the front and back surfaces of the single-crystalline silicon wafer using the PECVD process;

[0130] Step Twelve: Perform paste printing and metal sintering on the single-crystalline silicon wafer.

[0131] Comparative Example 1:

[0132] Comparative Example 1 provides a back-contact cell with anti-hot-spot effect, including a silicon substrate. The front side of the silicon substrate sequentially includes a front passivation layer and a front antireflection layer from inside to outside; the back side of the silicon substrate sequentially includes a first region / second region, a back passivation layer, a back antireflection layer, and electrodes from inside to outside; the first region and the second region have opposite polarities and are arranged alternately along a first direction. A third region is provided at the connection of the first region and the second region. The first region, the second region, and the third region all extend along a second direction, and the second direction is perpendicular to and intersects the first direction; the electrodes include a first electrode and a second electrode. The first electrode penetrates the back antireflection layer to form an ohmic contact with the second doping layer, and the second electrode penetrates the back antireflection layer to form an ohmic contact with the first doping layer. Its preparation method includes the following steps:

[0133] Step 1: Select a single-crystalline silicon wafer with a resistivity of 30 Ω·cm and put it into a tank-type alkaline solution for polishing;

[0134] Step 2: Deposit a 5-nm first passivation layer and a 200-nm first doping layer with a doping concentration of 7E19 cm -3 ;

[0135] Step 3: Deposit another BSG layer with a thickness of 80 nm on the back side of the single-crystalline silicon wafer;

[0136] Step 4: Use a laser beam to ablate the BSG layer in the second region and the third region on the back side of the single-crystalline silicon wafer. The laser beam uses pulsed laser with a pulse width of 10 ps, a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 6×10 3 j / m 2 , and the overlap rate is 30%; Use NaOH to etch the single-crystalline silicon wafer. There is still a 30-nm BSG layer on the surface of the first region, and the second region and the third region expose the single-crystalline silicon wafer, and the surface height of the first region is 2 μm higher than the surface height of the second region;

[0137] Step 5: Deposit a 5-nm second passivation layer, a 200-nm second doping layer with a doping concentration of 1E21 cm -3 , and a PSG layer with a thickness of 80 nm on the entire back side of the single-crystalline silicon wafer;

[0138] Step 6: Use a laser beam to ablate the PSG layer in the first region and the third region on the back side of the single-crystalline silicon wafer. The laser beam uses pulsed laser with a pulse width of 10 ps, a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 3×10 3 j / m 2, the overlap rate is 30%; and HF and HNO3 are used to etch the front and side surfaces of the single-crystalline silicon wafer, respectively exposing the single-crystalline silicon wafers on the front and side surfaces;

[0139] Step 7, use an alkaline solution and a strong acid to clean the second doped layer and the remaining BSG layer on the surface of the first region, and the second doped layer in the third region, respectively, and simultaneously texture the front surface of the single-crystalline silicon wafer and the third region to expose the silicon substrate in the third region, clean the PSG in the second region, and the surface height of the front surface of the single-crystalline silicon wafer after texturing is 8%, and the surface height of the second region is 2 μm higher than the surface height of the third region;

[0140] Step 8, use the ALD process to deposit a front passivation layer and a back passivation layer with a thickness of 5 nm on the front and back surfaces of the single-crystalline silicon wafer, respectively;

[0141] Step 9, use the PECVD process to deposit a front antireflection layer and a back antireflection layer with a thickness of 70 nm on the front and back surfaces of the single-crystalline silicon wafer, respectively;

[0142] Step 10, perform paste printing and metal sintering on the single-crystalline silicon wafer.

[0143] Comparative Example 2:

[0144] This Comparative Example 2 provides a back-contact battery with anti-thermal-spot effect, including a silicon substrate. The front surface of the silicon substrate sequentially includes a front passivation layer and a front antireflection layer from inside to outside; the back surface of the silicon substrate sequentially includes a first region / second region, a back passivation layer, a back antireflection layer, and an electrode from inside to outside; the first region and the second region have opposite polarities and are arranged alternately along the first direction, and a third region is provided at the connection of the first region and the second region. The first region, the second region, and the third region all extend along the second direction, and the second direction is perpendicular and intersects with the first direction; a fourth region is provided on the side of the first region close to the second region, and the fourth region is evenly distributed on the side of the first region along the second direction. The fourth region includes the first doped region and the second doped region arranged in a stacked manner; the electrode includes a first electrode and a second electrode. The first electrode penetrates the back antireflection layer to form an ohmic contact with the second doped layer, and the second electrode penetrates the back antireflection layer to form an ohmic contact with the first doped layer. Its preparation method includes the following steps:

[0145] Step 1, select a single-crystalline silicon wafer with a resistivity of 30 Ω·cm and put it into a trough-type alkaline solution for polishing;

[0146] Step 2, deposit a 5-nm first passivation layer and a 200-nm first doped layer on the entire back surface of the single-crystalline silicon wafer in sequence, and the doping concentration is 7E19 cm -3 ;

[0147] Step 3: Deposit another BSG layer with a thickness of 80 nm on the back of the single-crystalline silicon wafer;

[0148] Step 4: Ablate the BSG layer in the second and third regions on the back of the single-crystalline silicon wafer using a laser beam. The laser beam is pulsed laser with a pulse width of 10 ps, a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 6×10 3 j / m 2 , and the overlap rate is 30%; Etch the single-crystalline silicon wafer with NaOH. There is still a 30-nm BSG layer on the surface of the first region, the second and third regions expose the single-crystalline silicon wafer, and the surface height of the first region is 2 μm higher than the surface height of the second region;

[0149] Step 5: Deposit a 5-nm second passivation layer and a 200-nm second doping layer on the entire back of the single-crystalline silicon wafer in sequence. The doping concentration is 1E21 cm -3 , and a PSG layer with a thickness of 80 nm;

[0150] Step 6: Ablate the PSG layer in the first and third regions on the back of the single-crystalline silicon wafer using a laser beam. The laser beam is pulsed laser with a pulse width of 10 ps, a wavelength of 532 nm, a spot size of 200 μm, and an energy density of 3×10 3 j / m 2 , and the overlap rate is 30%; Etch the front and side surfaces of the single-crystalline silicon wafer with HF and HNO3 to expose the single-crystalline silicon wafers on the front and side respectively;

[0151] Step 7: Clean the second doping layer and the remaining BSG layer on the surface of the first region, and the second doping layer in the third region using an alkali solution and a strong acid respectively, and simultaneously texture the front surface of the silicon substrate and the third region to expose the silicon substrate in the third region, clean the PSG in the second region. After texturing, the surface reflectivity of the front surface of the silicon substrate is 8%, and the surface height of the second region is 2 μm higher than the surface height of the third region;

[0152] Step 8: Deposit a front passivation layer and a back passivation layer with a thickness of 5 nm on the front and back of the single-crystalline silicon wafer respectively using the ALD process;

[0153] Step 9: Deposit a front antireflection layer and a back antireflection layer with a thickness of 70 nm on the front and back of the single-crystalline silicon wafer respectively using the PECVD process;

[0154] Step 10: Perform paste printing and metal sintering on the single-crystalline silicon wafer.

[0155] Next, the solar cells obtained in the above examples and comparative examples are subjected to performance tests, and the results are as follows:

[0156] Table 1 Electrical performance test results of the solar cells prepared in the examples and comparative examples

[0157] Example EFF(%) Isc(A) Voc(mV) FF(%) Rs(mohm) Rsh(ohm) URev2 = -7V: IRev2(A) Example 1 26.58 16.049 745.3 85.25 2.1 1208 26.5 Example 2 26.63 16.059 745.8 85.29 2.1 1352 28.4 Example 3 26.61 16.052 746.1 85.25 2.1 1314 27.9 Example 4 26.60 16.048 745.6 85.27 2.1 1197 26.9 Comparative Example 1 26.67 16.065 746.5 85.32 2.1 1513 0.1 Comparative Example 2 26.44 16.045 743.5 85.02 2.1 1405 19.1

[0158] Table 2 Thermal spot temperature test results of the solar cells prepared in the examples and comparative examples

[0159] Example Under the condition of completely blocking 1 piece Example 1 113℃ Example 2 102℃ Example 3 105℃ Example 4 111℃ Comparative Example 1 158℃ Comparative Example 2 115℃

[0160] Examples 1 to 4 are back-contact cells of the present application that adjust the leakage current channels formed in the fourth region into heavily doped regions and gradually-varying lightly doped regions by using a laser beam and process improvement. Comparative example 1 is a back-contact cell without a leakage current channel, and comparative example 2 is a back-contact cell with only a leakage current channel but without using a laser beam and process improvement. As can be seen from Tables 1 and 2, the electrical performance data of the cells obtained in the examples of the present application are significantly better than those of comparative example 2. Therefore, the leakage current ability is significantly enhanced. Thus, while reducing the number of required leakage current channels, the carrier recombination during the normal operation of a single leakage current channel is also reduced, achieving the goal of high photoelectric conversion efficiency. Since comparative example 1 does not have a leakage current path, IRev2 is very small, but the thermal spot temperature is significantly higher than that of each example of the present application. In addition, the thermal spot effect temperature of the examples of the present application is also lower than that of comparative examples 1 and 2, achieving the goal of efficiently preventing the thermal spot effect.

[0161] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A back-contact battery with anti-hot spot effect, characterized in that It includes a silicon substrate, on the back surface of which there are a number of first regions and a number of second regions. The first regions and the second regions have opposite polarities and are arranged alternately along a first direction. A third region is provided at the connection of each of the first regions and the second regions. The first regions, the second regions and the third regions all extend along a second direction, and the second direction intersects the first direction perpendicularly. The first region includes a first passivation layer and a first doping layer stacked in sequence on the back surface of the silicon substrate. The second region includes a second passivation layer and a second doping layer stacked in sequence on the back surface of the silicon substrate. A fourth region is provided on the side of the first region close to the second region, and the fourth region is evenly distributed along the second direction on the side of the first region. The fourth region includes a graded lightly doped region in composite contact with the first doping layer, and a heavily doped region in composite contact with the second passivation layer is provided away from the back surface of the silicon substrate in the graded lightly doped region.

2. The back-contact cell with anti-hot spot effect according to claim 1, characterized in that, The doping element of the heavily doped region is boron, and the doping concentration is 1×10 21 ~1×10 23 cm -3 , and the doping depth is 10 - 20 nm; the doping element of the graded lightly doped region is boron, and the graded doping concentration is 1×10 21 cm -3 to 1×10 17 cm -3 .

3. The back contact cell with anti - hot spot effect according to claim 2, characterized in that, The barrier height formed by the heavily doped region and the second doping layer is 0.1 - 0.5 eV higher than the barrier height formed by the graded lightly doped region and the second doping layer.

4. The back-contact battery with anti-hot spot effect according to claim 1, characterized in that, The first passivation layer is a tunneling oxide layer with a thickness of 3 to 10 nm. The first doped layer is a doped polysilicon layer doped with boron element, with a doping thickness of 150 to 350 nm and a doping concentration of 5×10 19 ~1×10 20 cm -3 ; The second passivation layer is a tunneling oxide layer with a thickness of 3 to 10 nm. The second doped layer is a doped polysilicon layer doped with phosphorus element, with a doping thickness of 150 to 300 nm and a doping concentration of 1×10 20 ~1×10 22 cm -3 .

5. The back contact battery for resisting hot spot effect according to claim 1, characterized in that, The front surface of the silicon substrate includes a front passivation layer and a front antireflection layer from the inside to the outside in sequence; the back surface of the silicon substrate includes the first region / the second region, a back passivation layer, a back antireflection layer and an electrode from the inside to the outside in sequence. The first regions and the second regions have opposite polarities and are arranged alternately along the first direction. A third region is provided at the connection of each of the first regions and the second regions. The first regions, the second regions and the third regions all extend along the second direction, and the second direction intersects the first direction perpendicularly. A fourth region is provided on the side of the first region close to the second region, and the fourth region is evenly distributed along the second direction on the side of the first region. The fourth region includes a graded lightly doped region in composite contact with the first doping layer, and a heavily doped region in composite contact with the second passivation layer is provided away from the back surface of the silicon substrate in the graded lightly doped region. The electrode includes a first electrode and a second electrode. The first electrode penetrates through the back antireflection layer and the back passivation layer to form an ohmic contact with the first doping layer, and the second electrode penetrates through the back antireflection layer and the back passivation layer to form an ohmic contact with the second doping layer.

6. A method for preparing a back-contact battery according to any one of claims 1 to 5, characterized in that, It includes the following steps: Step 1: Select a silicon substrate and put it into a trough-type alkaline solution for polishing. Step 2: Deposit a first passivation layer and a first doping layer in sequence on the entire back surface of the silicon substrate. Step 3: Deposit a BSG layer on the back surface of the silicon substrate. Step 4: Use a laser beam to ablate the back surface of the silicon substrate at intervals, and use an alkaline solution to etch the silicon substrate to respectively form unablated first regions, second regions exposing the silicon substrate, and third regions exposing the silicon substrate. Step 5: Use a laser beam to irradiate a part of the BSG layer on the side of the first region close to the second region to form a fourth region. After being irradiated by the laser beam, the boron element in the BSG layer diffuses longitudinally into the first doping layer inward to form a heavily doped region. Step six: Anneal the heavily doped region to redistribute boron elements within the first doped layer, forming a gradually-varying lightly doped region; Step seven: Sequentially deposit a second passivation layer, a second doped layer, and a PSG layer on the entire back surface of the silicon substrate; Step eight: Ablate the PSG layer in the first region and the third region on the back surface of the silicon substrate using a laser beam, and etch the front surface and the side surfaces of the silicon substrate using a strong acid to expose the silicon substrate on the front surface and the side surfaces respectively; Step nine: Clean the surfaces of the first region and the third region using an alkaline solution and a strong acid respectively, and simultaneously texture the front surface of the silicon substrate and the third region to expose the silicon substrate in the third region, and clean the PSG in the second region; Step ten: Deposit a front passivation layer and a back passivation layer on the front and back surfaces of the silicon substrate; Step eleven: Deposit a front antireflection layer and a back antireflection layer on the front and back surfaces of the silicon substrate; Step twelve: Perform paste printing and metal sintering on the silicon substrate.

7. The manufacturing method of the back-contact battery according to claim 6, characterized in that, The specific steps of step four include: ablating the BSG layer in the second region and the third region by using the laser beam, where the laser beam is a pulsed laser with a pulse width of 5 - 30 ps, a wavelength of 355 nm or 532 nm, a spot size of 150 - 300 μm, and an energy density of 4×10 3 j / m 2 ~9×10 3 j / m 2 , with an overlap rate of 10 - 80%; after the alkaline etching, there is still a 10 - 40 nm BSG layer on the surface of the first region, and the surface height of the first region is 1 - 5 μm higher than the surface height of the second region.

8. The manufacturing method of the back contact battery according to claim 6, characterized in that, Step five specifically includes: irradiating the BSG layer in the fourth region with the laser beam, and the BSG layer serves as a boron source for longitudinal diffusion into the first doped layer. The laser beam is a pulsed laser with a pulse width of 5 - 30 ps, a wavelength of 355 nm or 532 nm, a spot size of 150 - 300 μm, and an energy density of 3.55×10 3 j / m 2 ~6.5×10 3 j / m 2 , and the overlap rate is 10 - 80%.

9. The preparation method of the back-contact battery according to claim 6, wherein The specific content of step six includes: Anneal the heavily doped region to redistribute boron elements within the first doped layer. The annealing temperature is 800~1000°C, and the annealing time is 30~90 min.

10. The method for preparing a back contact battery according to claim 6, wherein, Step eight specifically includes: using the laser beam to ablate the PSG layers in the first region and the third region, where the laser beam is pulsed laser with a pulse width of 5 - 30 ps, a wavelength of 355 nm or 532 nm, a spot size of 150 - 300 μm, and an energy density of 2×10 3 j / m 2 ~4×10 3 j / m 2 , and the overlap rate is 10 - 50%.

Images