Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprises a pixel driving circuit and a plurality of scanning signal lines connected with the pixel driving circuit, and the pixel driving circuit at least comprises a plurality of transistors; in the direction perpendicular to the display substrate, the display substrate at least comprises a first gate metal layer (GATE1) arranged on a substrate (101) and a first source-drain metal layer (SD1) arranged on the side, away from the substrate (101), of the first gate metal layer (GATE1), a gate electrode of the at least one transistor is arranged in the first gate metal layer (GATE1), at least one scanning signal line is arranged on the first source-drain metal layer (SD1), and a gate electrode of the at least one transistor is arranged on the first source-drain metal layer (SD1). The scanning signal line is connected with the gate electrode through the via hole.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and a plurality of scanning signal lines connected to the pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; in a direction perpendicular to the display substrate, the display substrate comprises at least a first gate metal layer arranged on a substrate and a first source-drain metal layer arranged on a side of the first gate metal layer away from the substrate, the gate electrode of at least one transistor being arranged in the first gate metal layer, at least one scanning signal line being arranged in the first source-drain metal layer, and the scanning signal line being connected to the gate electrode through a via.

[0006] In an exemplary embodiment, the multiple transistors include at least a first transistor serving as a first initialization transistor, the first transistor including at least a first gate electrode, the first gate electrode being connected to a fourth scan signal line, and the first electrode of the first transistor being connected to the first initial signal line; the first gate electrode being arranged in the first gate metal layer, the fourth scan signal line being arranged in the first source-drain metal layer, and the fourth scan signal line being connected to the first gate electrode through a first gate via.

[0007] In an exemplary embodiment, in a cell row direction, the first gate electrodes in at least two adjacent circuit cells are connected to each other in an integrated structure.

[0008] In an exemplary embodiment, in the cell row direction, at least two adjacent circuit cells share the same first gate via.

[0009] In an exemplary embodiment, the shape of the first initial signal line is a straight line or a broken line extending along the unit row direction; at least one circuit unit also includes a first initial connection line, the shape of the first initial connection line is a straight line or a broken line extending along the unit column direction, and the first initial connection line is connected to the first initial signal line to form a network connectivity structure for transmitting the first initial signal.

[0010] In an exemplary embodiment, the first preliminary connection line is disposed in the first gate metal layer, and the first preliminary signal line is disposed in the first source / drain metal layer.

[0011] In an exemplary embodiment, the display substrate further includes a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate, the first initial signal line is in the shape of a straight line or a broken line extending along the unit column direction, and the first initial signal line is disposed in the second source-drain metal layer.

[0012] In an exemplary embodiment, the multiple transistors include at least a seventh transistor serving as a second initialization transistor, the seventh transistor including at least a seventh gate electrode, the seventh gate electrode being connected to the first scan signal line, and the first electrode of the seventh transistor being connected to the second initial signal line; the seventh gate electrode being arranged in the first gate metal layer, the first scan signal line being arranged in the first source-drain metal layer, and the first scan signal line being connected to the seventh gate electrode through a seventh gate via.

[0013] In an exemplary embodiment, in a cell row direction, the seventh gate electrodes in at least two adjacent circuit cells are connected to each other in an integrated structure.

[0014] In an exemplary embodiment, the second initial signal line is in the shape of a straight line or a broken line extending along the unit row direction, and at least one circuit unit further includes a second initial connection line, the shape of the second initial connection line is in the shape of a straight line or a broken line extending along the unit column direction, and the second initial connection line is connected to the second initial signal line to form a network connectivity structure for transmitting the second initial signal.

[0015] In an exemplary embodiment, the second preliminary connection line is disposed in the first gate metal layer, and the second preliminary signal line is disposed in the first source / drain metal layer.

[0016] In an exemplary embodiment, the multiple transistors include at least a third transistor serving as a driving transistor, a fifth transistor serving as a first light-emitting control transistor, and a sixth transistor serving as a second light-emitting control transistor, the fifth transistor including at least a fifth gate electrode, the sixth transistor including at least a sixth gate electrode, the fifth gate electrode being connected to a first light-emitting signal line, a first electrode of the fifth transistor being connected to a first power line, a second electrode of the fifth transistor being connected to a first electrode of the third transistor, the sixth gate electrode being connected to a second light-emitting signal line, and a first electrode of the sixth transistor being connected to a second electrode of the third transistor; the fifth gate electrode and the sixth gate electrode being arranged in the first gate metal layer, the first light-emitting signal line and the second light-emitting signal line being arranged in the first source-drain metal layer, the first light-emitting signal line being connected to the fifth gate electrode through a via, and the second light-emitting signal line being connected to the sixth gate electrode through a via.

[0017] In an exemplary embodiment, the multiple transistors include at least a third transistor serving as a driving transistor, a fifth transistor serving as a first light-emitting control transistor, and a sixth transistor serving as a second light-emitting control transistor, the fifth transistor including at least a fifth gate electrode, the sixth transistor including at least a sixth gate electrode, the fifth gate electrode being connected to a light-emitting signal line, a first electrode of the fifth transistor being connected to a first power line, a second electrode of the fifth transistor being connected to a first electrode of the third transistor, the sixth gate electrode being connected to a light-emitting signal line, and a first electrode of the sixth transistor being connected to a second electrode of the third transistor; the fifth gate electrode and the sixth gate electrode being arranged in the first gate metal layer, the light-emitting signal line being arranged in the first source-drain metal layer, and the light-emitting signal line being connected to the fifth gate electrode and the sixth gate electrode through the same via.

[0018] In an exemplary embodiment, in at least one circuit unit, the fifth gate electrode and the sixth gate electrode are connected to each other as an integral structure.

[0019] In an exemplary embodiment, in a cell row direction, the sixth gate electrodes in at least two adjacent circuit cells are connected to each other in an integrated structure.

[0020] In an exemplary embodiment, the pixel driving circuit further includes a first capacitor and a second capacitor, the first capacitor includes at least a first plate and a third plate, the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate, and the second capacitor includes at least a second plate and a fourth plate, the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate; the first plate and the second plate are arranged in the first gate metal layer, and the third plate and the fourth plate are arranged in the first source and drain metal layer, and are an integrated structure connected to each other.

[0021] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, which includes at least a fifth plate and a sixth plate, and the orthographic projection of the fifth plate on the substrate at least partially overlaps with the orthographic projection of the sixth plate on the substrate; the fifth plate is arranged in the first gate metal layer, and the sixth plate is arranged in the first source and drain metal layer.

[0022] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0023] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and a plurality of scanning signal lines connected to the pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; the manufacturing method comprising:

[0024] forming a first gate metal layer on a substrate, wherein a gate electrode of at least one transistor is disposed in the first gate metal layer;

[0025] A first source-drain metal layer is formed on the first gate metal layer. At least one scan signal line is provided on the first source-drain metal layer. The scan signal line is connected to the gate electrode through a via hole.

[0026] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0028] FIG1 is a schematic structural diagram of a display device;

[0029] FIG2 is a schematic structural diagram of a display substrate;

[0030] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate;

[0031] FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0032] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0033] FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] FIG7 is a cross-sectional view taken along line AA in FIG6 ;

[0035] FIG8 is a schematic diagram of a display substrate after forming a shielding metal layer pattern according to the present disclosure;

[0036] 9A and 9B are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0037] 10A and 10B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0038] FIG11 is a schematic diagram of a display substrate after a third insulating layer pattern is formed according to the present disclosure;

[0039] 12A and 12B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0040] FIG13 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure;

[0041] 14A and 14B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0042] FIG15 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0043] FIG16 is a cross-sectional view taken along line AA in FIG15 ;

[0044] FIG17 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0045] FIG18 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0046] FIG19 is a cross-sectional view taken along line BB in FIG18 ;

[0047] FIG20 is a schematic diagram of another display substrate after forming a shielding metal layer pattern according to the present disclosure;

[0048] 21A and 21B are schematic diagrams of another display substrate after semiconductor layer patterns are formed according to the present disclosure;

[0049] 22A and 22B are schematic diagrams of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0050] FIG23 is a schematic diagram of another display substrate after forming a third insulating layer pattern according to the present disclosure;

[0051] 24A and 24B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0052] FIG25 is a schematic diagram of another display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0053] 26A and 26B are schematic diagrams of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0054] FIG27 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0055] FIG28 is a cross-sectional view taken along line BB in FIG27 .

[0056] DESCRIPTION OF NUMERALS: 10—first capacitor; 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 19—ninth active layer; 20—second capacitor; 21—first gate electrode; 22—second gate electrode; 24—fourth gate electrode; 25—fifth gate electrode; 26—sixth gate electrode; 27—seventh gate electrode; 29—ninth gate electrode; 30—storage capacitor; 31—first plate; 32—second plate; 33—third plate; 34—fourth plate; 35—fifth plate; 36—sixth plate; 37—groove; 41—first connecting electrode; 42—second connecting electrode; 43—third connecting electrode; 44—fourth connecting electrode; 45—fifth connecting electrode; 46—sixth connecting electrode; 47—seventh connecting electrode; 51—first power line; 52—data signal line; 53—first reference connecting line; 54—anode connecting electrode; 61—first scanning signal line; 62—second scanning signal line; 63—third scanning signal line; 64—fourth scanning signal line; 65—fifth scanning signal line; 66—first light-emitting signal line; 67—second light-emitting signal line; 68—light-emitting signal line; 71—first initial signal line; 72—second initial signal line; 73—first initial connecting line; 74—second initial connecting line; 81—first reference signal line; 82—second reference signal line; 91—shielding electrode; 92—shielding connecting bar; 100—display area; 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer;104 — packaging structure layer; 110 — first insulating layer; 120 — second insulating layer; 130 — third insulating layer; 140 — fourth insulating layer; 200 — bonding area; 300 — frame area. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0058] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0059] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0060] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0061] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0062] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0063] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0064] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0065] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0066] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0067] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0068] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0069] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0070] Figure 2 is a schematic diagram of the structure of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels forming a pixel array. The plurality of sub-pixels are configured to display dynamic or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled.

[0071] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area 100. The fan-out area is connected to the display area 100 and may include at least a plurality of data lead-out lines parallel to each other. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the binding area to the back of the display area. The driver chip area may include at least an integrated circuit (IC) configured to be connected to a plurality of data fan-out lines. The binding pin area may include at least a plurality of bonding pads configured to be bound and connected to an external flexible printed circuit (FPC).

[0072] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line of the pixel drive circuit in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove respectively.

[0073] In an exemplary embodiment, the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with at least one isolation dam, and the isolation dam may extend in a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the display area close to the binding area or the border area.

[0074] Figure 3 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 3, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may include at least a light-emitting device. The light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0075] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0076] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0077] Figure 4 is a schematic cross-sectional view of the display region of a display substrate, illustrating the structure of three sub-pixels within the display substrate. As shown in Figure 4, in a plane perpendicular to the display substrate, the display region of the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0078] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least a light-emitting device, and the light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0079] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises a pixel driving circuit and a plurality of scanning signal lines connected to the pixel driving circuit, wherein the pixel driving circuit comprises at least a plurality of transistors; in a direction perpendicular to the display substrate, the display substrate comprises at least a first gate metal layer disposed on a base and a first source-drain metal layer disposed on a side of the first gate metal layer away from the base, the gate electrode of at least one transistor being disposed in the first gate metal layer, and at least one scanning signal line being disposed in the first source-drain metal layer, wherein the scanning signal line is connected to the gate electrode through a via.

[0080] In an exemplary embodiment, the multiple transistors include at least a first transistor serving as a first initialization transistor, the first transistor including at least a first gate electrode, the first gate electrode being connected to a fourth scan signal line, and the first electrode of the first transistor being connected to the first initial signal line; the first gate electrode being arranged in the first gate metal layer, the fourth scan signal line being arranged in the first source-drain metal layer, and the fourth scan signal line being connected to the first gate electrode through a first gate via.

[0081] In an exemplary embodiment, the multiple transistors include at least a seventh transistor serving as a second initialization transistor, the seventh transistor including at least a seventh gate electrode, the seventh gate electrode being connected to the first scan signal line, and the first electrode of the seventh transistor being connected to the second initial signal line; the seventh gate electrode being arranged in the first gate metal layer, the first scan signal line being arranged in the first source-drain metal layer, and the first scan signal line being connected to the seventh gate electrode through a seventh gate via.

[0082] In an exemplary embodiment, the multiple transistors include at least a third transistor serving as a driving transistor, a fifth transistor serving as a first light-emitting control transistor, and a sixth transistor serving as a second light-emitting control transistor, the fifth transistor including at least a fifth gate electrode, the sixth transistor including at least a sixth gate electrode, the fifth gate electrode being connected to a first light-emitting signal line, a first electrode of the fifth transistor being connected to a first power line, a second electrode of the fifth transistor being connected to a first electrode of the third transistor, the sixth gate electrode being connected to a second light-emitting signal line, and a first electrode of the sixth transistor being connected to a second electrode of the third transistor; the fifth gate electrode and the sixth gate electrode being arranged in the first gate metal layer, the first light-emitting signal line and the second light-emitting signal line being arranged in the first source-drain metal layer, the first light-emitting signal line being connected to the fifth gate electrode through a via, and the second light-emitting signal line being connected to the sixth gate electrode through a via.

[0083] In an exemplary embodiment, the multiple transistors include at least a third transistor serving as a driving transistor, a fifth transistor serving as a first light-emitting control transistor, and a sixth transistor serving as a second light-emitting control transistor, the fifth transistor including at least a fifth gate electrode, the sixth transistor including at least a sixth gate electrode, the fifth gate electrode being connected to a light-emitting signal line, a first electrode of the fifth transistor being connected to a first power line, a second electrode of the fifth transistor being connected to a first electrode of the third transistor, the sixth gate electrode being connected to a light-emitting signal line, and a first electrode of the sixth transistor being connected to a second electrode of the third transistor; the fifth gate electrode and the sixth gate electrode being arranged in the first gate metal layer, the light-emitting signal line being arranged in the first source-drain metal layer, and the light-emitting signal line being connected to the fifth gate electrode and the sixth gate electrode through the same via.

[0084] In an exemplary embodiment, the pixel driving circuit further includes a first capacitor and a second capacitor, the first capacitor includes at least a first plate and a third plate, the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate, and the second capacitor includes at least a second plate and a fourth plate, the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate; the first plate and the second plate are arranged in the first gate metal layer, and the third plate and the fourth plate are arranged in the first source and drain metal layer, and are an integrated structure connected to each other.

[0085] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, which includes at least a fifth plate and a sixth plate, and the orthographic projection of the fifth plate on the substrate at least partially overlaps with the orthographic projection of the sixth plate on the substrate; the fifth plate is arranged in the first gate metal layer, and the sixth plate is arranged in the first source and drain metal layer.

[0086] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0087] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG5 , the pixel driving circuit according to the exemplary embodiment of the present disclosure may have a 9T2C structure, which may include nine transistors (first transistor T1 to ninth transistor T9) and two capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is connected to 12 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light-emitting signal line EM1, second light-emitting signal line EM2, first initial signal line INIT1, second initial signal line INIT2, first reference signal line REF1, second reference signal line REF2, data signal line DATA, and first power line VDD).

[0088] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the eighth transistor T8, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively; and the fifth node N5 is connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the second end of the first capacitor C1, and the second end of the second capacitor C2, respectively.

[0089] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 is connected to the fifth node N5, a first end of the second capacitor C2 is connected to the first power line VDD, and a second end of the second capacitor C2 is connected to the fifth node N5.

[0090] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor. A gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor is connected to the first node N1. When a turn-on signal is applied to the fourth scan signal line S4, the first transistor T1 transmits a first initialization voltage to the gate electrode of the third transistor T3 and the first terminal of the first capacitor C1, thereby releasing the charge accumulated in the first capacitor C1 and achieving initialization.

[0091] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor. A gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. When a turn-on signal is applied to the second scan signal line S2, the second transistor T2 connects the first node N1 and the third node N3.

[0092] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor. The third transistor T3 determines the magnitude of a driving current based on a potential difference between its gate electrode and the first electrode.

[0093] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data write transistor. A gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the fifth node N5. When a turn-on signal is applied to the third scan signal line S3, the fourth transistor T4 inputs a data voltage of the data signal line DATA to the second end of the first capacitor C1 and the second end of the second capacitor C2.

[0094] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor. A gate electrode of the fifth transistor T5 is connected to the first light emission signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. The sixth transistor T6 may be referred to as a second light emission control transistor. A gate electrode of the sixth transistor T6 is connected to the second light emission signal line EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. When a turn-on signal is applied to the first light emission signal line EM1 and the second light emission signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power supply line VDD and the second power supply line VSS, thereby causing the light emitting device EL to emit light.

[0095] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor. A gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When a turn-on signal is applied to the first scan signal line S1, the seventh transistor T7 transmits a second initialization voltage to the first electrode of the light-emitting device EL, thereby releasing charge accumulated in the first electrode of the light-emitting device EL and achieving initialization.

[0096] In an exemplary embodiment, the eighth transistor T8 may be referred to as a first reference transistor. A gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, a first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and a second electrode of the eighth transistor T8 is connected to the second node N2. When a turn-on signal is applied to the first scan signal line S1, the eighth transistor T8 transmits the second reference signal to the second node N2.

[0097] In an exemplary embodiment, the ninth transistor T9 may be referred to as a second reference transistor. A gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, a first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and a second electrode of the ninth transistor T9 is connected to the fifth node N5. When a turn-on signal is applied to the second scan signal line S2, the ninth transistor T9 transmits the first reference signal to the fifth node N5.

[0098] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0099] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0100] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include P-type transistors and N-type transistors.

[0101] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0102] Figure 6 is a schematic planar structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of pixel driving circuits in three circuit units (a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3) in the display substrate. Figure 7 is a cross-sectional view taken along line AA in Figure 6. In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate. The driving circuit layer may include at least a plurality of circuit units, the light-emitting structure layer may include at least a plurality of light-emitting units, at least one circuit unit may include a pixel driving circuit, and at least one light-emitting unit may include a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit.

[0103] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0104] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects the second direction Y.

[0105] As shown in Figures 6 and 7, the pixel driving circuit in at least one circuit unit may include at least a first capacitor 10, a second capacitor 20, and multiple transistors. The multiple transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emission control transistor, a sixth transistor T6 as a second light emission control transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a first reference transistor, and a ninth transistor T9 as a second reference transistor. The first capacitor 10 may include a first plate 31 and a third plate 33, and the second capacitor 20 may include a second plate 32 and a fourth plate 34.

[0106] In this exemplary embodiment, the first gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, the first electrode of the first transistor T1 is connected to the first initial signal line 71, and the second electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the first electrode plate 31 via the second connection electrode 42. The second gate electrode of the second transistor T2 is connected to the second scan signal line 62, and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, respectively. The gate electrode of the third transistor T3 can serve as the first electrode plate 31, and the first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8, respectively. The fourth gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first electrode of the fourth transistor T4 is connected to the data signal line 52, and the second electrode of the fourth transistor T4 and the second electrode of the ninth transistor T9 are connected to the fourth electrode plate 34 via the sixth connection electrode 46. The fifth gate electrode of the fifth transistor T5 is connected to the first light emitting signal line 66, and the first electrode of the fifth transistor T5 is connected to the first power line 51. A sixth gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 67, and a second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. A gate electrode of the seventh transistor T7 is connected to the first scanning signal line 61, and a first electrode of the seventh transistor T7 is connected to the second initial signal line 72. A gate electrode of the eighth transistor T8 is connected to the first scanning signal line 61, and a first electrode of the eighth transistor T8 is connected to the second reference signal line 82. A ninth gate electrode of the ninth transistor T9 is connected to the fifth scanning signal line 65, and a first electrode of the ninth transistor T9 is connected to the first reference signal line 81.

[0107] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 may transmit the same scan signal.

[0108] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first light-emitting signal line 66, the second light-emitting signal line 67, the second initial signal line 72, the first reference signal line 81 and the second reference signal line 82 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the first power line 51, the data signal line 52 and the first initial signal line 71 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0109] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.

[0110] In an exemplary embodiment, at least one circuit unit may further include a first reference connection line 53. The first reference connection line 53 may be in the shape of a straight line or a broken line, with the main portion extending along the second direction Y, and is connected to the first reference signal line 81. Thus, the first reference signal line 81 extending along the first direction X and the first reference connection line 53 extending along the second direction Y are interconnected, so that the first reference signal line 81 and the first reference connection line 53 form a mesh-like network connection structure on the display substrate for transmitting the first reference signal.

[0111] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include: a blocking metal layer (BSM) disposed on a substrate 101, a first insulating layer 110 disposed on a side of the blocking metal layer away from the substrate 101, a semiconductor layer disposed on a side of the first insulating layer 110 away from the substrate 101, a second insulating layer 120 disposed on a side of the semiconductor layer away from the substrate 101, a first gate metal layer (GATE1) disposed on a side of the second insulating layer 120 away from the substrate 101, a third insulating layer 130 disposed on a side of the first gate metal layer away from the substrate 101, a first source-drain metal layer (SD1) disposed on a side of the third insulating layer 130 away from the substrate 101, a fourth insulating layer 140 disposed on a side of the first source-drain metal layer away from the substrate 101, and a second source-drain metal layer (SD2) disposed on a side of the fourth insulating layer 140 away from the substrate 101.

[0112] In an exemplary embodiment, the first plate 31 of the first capacitor 10 and the second plate 32 of the second capacitor 20 can be arranged in the first gate metal layer, the third plate 33 of the first capacitor 10 and the fourth plate 34 of the second capacitor 20 can be arranged in the first source-drain metal layer, the orthographic projection of the first plate 31 on the substrate and the orthographic projection of the third plate 33 on the substrate at least partially overlap, the orthographic projection of the second plate 32 on the substrate and the orthographic projection of the fourth plate 34 on the substrate at least partially overlap, and the third plate 33 and the fourth plate 34 can be an integrated structure connected to each other.

[0113] In an exemplary embodiment, the first gate electrode of the first transistor T1 may be disposed in the first gate metal layer, the fourth scan signal line 64 may be disposed in the first source-drain metal layer, and the fourth scan signal line 64 may be connected to the first gate electrode of the first transistor T1 through a via.

[0114] In an exemplary embodiment, the second gate electrode of the second transistor T2 may be disposed in the first gate metal layer, the second scan signal line 62 may be disposed in the first source / drain metal layer, and the second scan signal line 62 may be connected to the second gate electrode of the second transistor T2 through a via.

[0115] In an exemplary embodiment, the fourth gate electrode of the fourth transistor T4 may be disposed in the first gate metal layer, the third scan signal line 63 may be disposed in the first source-drain metal layer, and the third scan signal line 63 may be connected to the fourth gate electrode of the fourth transistor T4 through a via.

[0116] In an exemplary embodiment, the fifth gate electrode of the fifth transistor T5 may be disposed in the first gate metal layer, the first light emitting signal line 66 may be disposed in the first source-drain metal layer, and the first light emitting signal line 66 may be connected to the fifth gate electrode of the fifth transistor T5 through a via.

[0117] In an exemplary embodiment, the sixth gate electrode of the sixth transistor T6 may be disposed in the first gate metal layer, the second light emitting signal line 67 may be disposed in the first source-drain metal layer, and the second light emitting signal line 67 may be connected to the sixth gate electrode of the sixth transistor T6 through a via.

[0118] In an exemplary embodiment, the ninth gate electrode of the ninth transistor T9 may be disposed in the first gate metal layer, the fifth scan signal line 65 may be disposed in the first source-drain metal layer, and the fifth scan signal line 65 may be connected to the ninth gate electrode of the ninth transistor T9 through a via.

[0119] In an exemplary embodiment, the first preliminary signal line 71 may be disposed in the second source-drain metal layer, and the second preliminary signal line 72 may be disposed in the first source-drain metal layer.

[0120] In an exemplary embodiment, the first reference signal line 81 and the second reference signal line 82 may be disposed in a first source-drain metal layer, and the first reference connection line 53 may be disposed in a second source-drain metal layer.

[0121] As shown in FIG7 , in an exemplary embodiment, the blocking metal layer may include at least a blocking electrode 91, the semiconductor layer may include at least a first active layer 11, a second active layer 12, a third active layer 13, a fourth active layer 14, and a ninth active layer 19, and the first gate metal layer (first conductive layer) may include at least a first electrode plate 31 and a second electrode plate 32. The first source-drain metal layer (third conductive layer) may include at least a third electrode plate 33, a fourth electrode plate 34, a second connection electrode 42, a sixth connection electrode 46, and a seventh connection electrode 47. The second connection electrode 42 is connected to the first electrode plate 31 through a via, the sixth connection electrode 46 is connected to the fourth active layer 14 and the ninth active layer 19 through a via, and the seventh connection electrode 47 is connected to the second electrode plate 32 through a via. The second source-drain metal layer (fourth conductive layer) may include at least a first power line 51, which is connected to the seventh connection electrode 47 through a via.

[0122] In an exemplary embodiment, the first gate metal layer (first conductive layer) may further include a first scan signal line 61 , the first source / drain metal layer (third conductive layer) may further include a plurality of connecting electrodes, and the second source / drain metal layer (fourth conductive layer) may further include a data signal line 52 .

[0123] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0124] In an exemplary embodiment, taking three circuit units (a first circuit unit Q1 , a second circuit unit Q2 , and a third circuit unit Q3 ) as an example, the manufacturing process of the display substrate of this embodiment may include the following operations.

[0125] (11) Forming a blocking metal layer pattern. In an exemplary embodiment, forming the blocking metal layer pattern may include: depositing a blocking metal film on a substrate, patterning the blocking metal film through a patterning process, and forming a blocking metal layer (BSM) disposed on the substrate, as shown in FIG8 .

[0126] In an exemplary embodiment, the blocking metal layer of each circuit unit in the display substrate may include at least a blocking electrode 91 and a blocking connection bar 92 .

[0127] In an exemplary embodiment, the shielding electrode 91 may be in the shape of a block (such as a rectangle) and may be disposed in the middle region of the circuit unit in the first direction X and the second direction Y. The shielding electrode 91 is configured to serve as a shielding layer for the third transistor T3, shielding the third transistor T3 from light, reducing the intensity of light incident on the third transistor T3, and reducing the leakage current of the third transistor T3, thereby reducing the influence of light on the characteristics of the third transistor T3.

[0128] In an exemplary embodiment, the shielding connection strip 92 may be in the shape of a strip extending along the first direction X, and may be arranged on one side of the shielding electrode 91 in the first direction X or on the side opposite to the first direction X. The first end of the shielding connection strip 92 is connected to the shielding electrode 91 in the current circuit unit, and the second end of the shielding connection strip 92 extends to the adjacent circuit unit and is connected to the shielding electrode 91 of the adjacent circuit unit.

[0129] In an exemplary embodiment, the shielding electrodes 91 and the shielding connection bars 92 may be an integral structure connected to each other.

[0130] In an exemplary embodiment, positions and shapes of the blocking metal layers in the plurality of circuit units in the first direction X may be substantially the same.

[0131] (12) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding metal layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a schematic diagram of the semiconductor layer in FIG9A .

[0132] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display substrate may include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9. The first to third active layers 11 to 13 and the fifth to eighth active layers 15 to 18 may be interconnected as an integral structure, and the fourth active layer 14 and the ninth active layer 19 may be interconnected as an integral structure.

[0133] In an exemplary embodiment, in the first direction X, the eighth active layer 18 may be located on a side of the third active layer 13 of the present circuit unit opposite to the first direction X, and the sixth active layer 16 and the seventh active layer 17 may be located on one side of the third active layer 13 of the present circuit unit in the first direction X. In the second direction Y, the fourth active layer 14 and the ninth active layer 19 may be located on a side of the third active layer 13 of the present circuit unit opposite to the second direction Y, and the first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 may be located on one side of the third active layer 13 in the second direction Y.

[0134] In an exemplary embodiment, the first active layer 11 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the fifth active layer 15 may be located on one side of the first active layer 11 of the present circuit unit in the second direction Y, and the eighth active layer 18 may be located on one side of the fifth active layer 15 of the present circuit unit in the second direction Y. The second active layer 12 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the sixth active layer 16 may be located on one side of the second active layer 12 of the present circuit unit in the second direction Y, and the seventh active layer 17 may be located on one side of the sixth active layer 16 of the present circuit unit in the second direction Y.

[0135] In an exemplary embodiment, the first active layer 11, the second active layer 12, the fourth active layer 14, and the ninth active layer 19 may have an "L" shape, the third active layer 13 may have an "Ω" shape, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may have an "I" shape.

[0136] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 91 on the substrate, so that the shielding electrode 91 can shield the third transistor T3, reduce the intensity of light irradiated on the third transistor T3, reduce the leakage current of the third transistor T3, and thus reduce the impact of light on the characteristics of the third transistor T3.

[0137] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0138] In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, and the second region 18-2 of the eighth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as both the second region 15-2 of the fifth active layer and the second region 18-2 of the eighth active layer, thereby forming a second node N2 of the pixel driving circuit. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 13-2 of the third active layer may serve as both the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, thereby forming a third node N3 of the pixel driving circuit. The second region 14-2 of the fourth active layer and the second region 19-2 of the ninth active layer can be connected to each other, and the second region 14-2 of the fourth active layer can serve as the second region 19-2 of the ninth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer, forming a fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the first region 19-1 of the ninth active layer can be provided separately.

[0139] In example embodiments, positions and shapes of semiconductor layers in a plurality of circuit units in the first direction X may be substantially the same.

[0140] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a schematic diagram of the first conductive layer in FIG10A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0141] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first plate 31 of a first capacitor, and a second plate 32 of a second capacitor.

[0142] In an exemplary embodiment, the shape of the first plate 31 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the first plate 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. The first plate 31 can simultaneously serve as a plate of the first capacitor and a gate electrode of the third transistor T3.

[0143] In an exemplary embodiment, the first electrode plate 31 may be provided with a first electrode plate connecting block 31-1. The first electrode plate connecting block 31-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the first electrode plate 31 away from the second electrode plate 32. A first end of the first electrode plate connecting block 31-1 is connected to the first electrode plate 31, and a second end of the first electrode plate connecting block 31-1 extends away from the second electrode plate 32. The first electrode plate connecting block 31-1 is configured to be connected to the second region of the first active layer (also the first region of the second active layer) via a subsequently formed second connecting electrode.

[0144] In an exemplary embodiment, the first electrode plate 31 and the first electrode plate connection block 31 - 1 may be an integral structure connected to each other.

[0145] In an exemplary embodiment, the shape of the second electrode plate 32 of the second capacitor can be rectangular, the corners of the rectangle can be chamfered or grooved, and can be located on the side opposite to the second direction Y of the first electrode plate 31. The second electrode plate 32 can serve as a plate of the second capacitor.

[0146] In an exemplary embodiment, in at least one circuit unit, an orthographic projection of the second electrode plate 32 on the substrate does not overlap with an orthographic projection of the semiconductor layer on the substrate.

[0147] In an exemplary embodiment, the second electrode plate 32 may be provided with a plate connecting bar 32-1. The plate connecting bar 32-1 may be in the shape of a bar extending along the first direction X and may be provided on one side of the second electrode plate 32 in the first direction X or on a side opposite to the first direction X. The first end of the plate connecting bar 32-1 is connected to the second electrode plate 32 in the current circuit unit, and the second end of the plate connecting bar 32-1 extends to the adjacent circuit unit and connects to the second electrode plate 32 of the adjacent circuit unit, thereby interconnecting the second electrode plates 32 of adjacent circuit units in a unit row.

[0148] In an exemplary embodiment, the plurality of second plates 32 and the plurality of plate connecting bars 32-1 spaced apart along the first direction X may be interconnected and integrally formed. Because the second plates 32 are connected to subsequently formed first power lines, the second plates 32 of the integrated structure of the plurality of circuit units can be reused as transverse power lines extending along the first direction X. This not only ensures that the plurality of second plates 32 in a unit row have the same potential, but also reduces the voltage drop of the first power signal, thereby improving the uniformity of the panel, preventing display defects on the display substrate, and ensuring the display quality of the display substrate.

[0149] In an exemplary embodiment, the second electrode plate 32 may be provided with a second electrode plate connecting block 32-2. The second electrode plate connecting block 32-2 may be block-shaped (e.g., rectangular) and may be provided on a side of the second electrode plate 32 close to the first electrode plate 31. A first end of the second electrode plate connecting block 32-2 is connected to the second electrode plate 32, and a second end of the second electrode plate connecting block 32-2 extends toward the first electrode plate 31. The second electrode plate connecting block 32-2 is configured to be connected to the first power line via a seventh connecting electrode formed later.

[0150] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 32 , the electrode plate connecting bar 32 - 1 , and the second electrode plate connecting block 32 - 2 may be an integral structure connected to each other.

[0151] In an exemplary embodiment, the shape of the first scanning signal line 61 can be a straight line or a broken line with the main portion extending along the first direction X, and can be located on one side of the first electrode plate 31 in the second direction Y. The area where the first scanning signal line 61 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the first scanning signal line 61 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0152] In an exemplary embodiment, the first gate electrode 21 may be in an L-shape and may be located between the first electrode plate 31 and the first scanning signal line 61 . The region where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0153] In an exemplary embodiment, the second gate electrode 22 may be in an "L" shape and may be located between the first electrode plate 31 and the first scanning signal line 61. The region where the second gate electrode 22 overlaps with the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0154] In an exemplary embodiment, the fourth gate electrode 24 can be in a "U" shape and can be located on the side of the second electrode 32 away from the first electrode 31. The area where the fourth gate electrode 24 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4 of the dual-gate structure.

[0155] In an exemplary embodiment, the fifth gate electrode 25 can be in the shape of a strip extending along the second direction Y, and can be located on the side of the first gate electrode 21 away from the first electrode plate 31. The area where the fifth gate electrode 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5.

[0156] In an exemplary embodiment, the sixth gate electrode 26 may be in the shape of a strip extending along the first direction X, and may be located on a side of the second gate electrode 22 away from the first electrode plate 31 . The area where the sixth gate electrode 26 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6 .

[0157] In an exemplary embodiment, the ninth gate electrode 29 may be in a "U" shape and may be located on the side of the second electrode 32 away from the first electrode 31. The area where the ninth gate electrode 29 overlaps with the ninth active layer may serve as the gate electrode of the ninth transistor T9 of the dual-gate structure.

[0158] In an exemplary embodiment, positions and shapes of the first conductive layers in the plurality of circuit units in the first direction X may be substantially the same.

[0159] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield. The semiconductor layer shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9, and the semiconductor layer not shielded by the first conductive layer is conductorized. The first and second regions of the first to ninth active layers are all conductorized.

[0160] (14) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film using a patterning process to form a third insulating layer covering the first conductive layer, and providing a plurality of vias in each circuit unit, as shown in FIG. 11 .

[0161] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.

[0162] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the first region of the first active layer through the via hole.

[0163] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0164] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first region of the fourth active layer through the via hole.

[0165] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the fourth active layer (also the second region of the ninth active layer) on the substrate, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the fourth active layer (also the second region of the ninth active layer), and the fourth via hole V4 is configured to connect the subsequently formed sixth connecting electrode to the second region of the fourth active layer (also the second region of the ninth active layer) through the via hole.

[0166] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first region of the fifth active layer, and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via hole.

[0167] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the sixth via hole V6 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0168] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the third insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first region of the seventh active layer, and the seventh via V7 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.

[0169] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the third insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the first region of the eighth active layer, and the eighth via V8 is configured to connect a subsequently formed second reference signal line to the first region of the eighth active layer through the via.

[0170] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the third insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first region of the ninth active layer, and the ninth via V9 is configured to connect a subsequently formed first reference signal line to the first region of the ninth active layer through the via.

[0171] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the first electrode plate connecting block 31-1 of the first electrode plate 31 on the substrate. The third insulating layer in the tenth via V10 is etched away to expose the surface of the first electrode plate connecting block 31-1. The tenth via V10 is configured to connect a subsequently formed second connecting electrode to the first electrode plate connecting block 31-1 through the via.

[0172] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second electrode plate connecting block 32-2 of the second electrode plate 32 on the substrate. The third insulating layer in the eleventh via hole V11 is etched away to expose the surface of the second electrode plate connecting block 32-2. The eleventh via hole V11 is configured to connect the subsequently formed seventh connecting electrode to the second electrode plate connecting block 32-2 through the via hole.

[0173] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the third insulating layer in the twelfth via hole V12 is etched away to expose the surface of the first gate electrode 21, and the twelfth via hole V12 is configured to connect the subsequently formed fourth scanning signal line to the first gate electrode 21 through the via hole.

[0174] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second gate electrode 22 on the substrate, the third insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the second gate electrode 22, and the thirteenth via hole V13 is configured to connect a subsequently formed second scanning signal line to the second gate electrode 22 through the via hole.

[0175] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the fourth gate electrode 24 on the substrate, the third insulating layer in the fourteenth via hole V14 is etched away to expose the surface of the fourth gate electrode 24, and the fourteenth via hole V14 is configured to connect the subsequently formed third scan signal line to the fourth gate electrode 24 through the via hole.

[0176] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the third insulating layer in the fifteenth via hole V15 is etched away to expose the surface of the fifth gate electrode 25, and the fifteenth via hole V15 is configured to connect the subsequently formed first light-emitting signal line to the fifth gate electrode 25 through the via hole.

[0177] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the third insulating layer in the sixteenth via hole V16 is etched away to expose the surface of the sixth gate electrode 26, and the sixteenth via hole V16 is configured to connect the subsequently formed second light-emitting signal line to the sixth gate electrode 26 through the via hole.

[0178] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the ninth gate electrode 29 on the substrate, the third insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the ninth gate electrode 29, and the seventeenth via hole V17 is configured to connect the subsequently formed fifth scanning signal line to the ninth gate electrode 29 through the via hole.

[0179] In an exemplary embodiment, positions and shapes of the via holes in the plurality of circuit units in the first direction X may be substantially the same.

[0180] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0181] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate may include: a third plate 33 of a first capacitor, a fourth plate 34 of a second capacitor, a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a fifth scanning signal line 65, a first light-emitting signal line 66, a second light-emitting signal line 67, a second initial signal line 72, a first reference signal line 81, and a second reference signal line 82.

[0182] In an exemplary embodiment, the shape of the third plate 33 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the third plate 33 on the substrate at least partially overlaps with the orthographic projection of the first plate 31 on the substrate. The third plate 33 can serve as another plate of the first capacitor, and the first plate 31 and the third plate 33 constitute the first capacitor of the pixel driving circuit.

[0183] In an exemplary embodiment, the shape of the fourth plate 34 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the fourth plate 34 on the substrate at least partially overlaps with the orthographic projection of the second plate 32 on the substrate. The fourth plate 34 can serve as another plate of the second capacitor, and the second plate 32 and the fourth plate 34 constitute the second capacitor of the pixel driving circuit.

[0184] In an exemplary embodiment, in at least one circuit unit, the third electrode plate 33 and the fourth electrode plate 34 may be an integral structure connected to each other.

[0185] In an exemplary embodiment, a groove 37 may be provided on the third electrode plate 33 and the fourth electrode plate 34 of the integrated structure, and the orthographic projection of the groove 37 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate connecting block 32-2 on the substrate. The groove 37 is configured to accommodate the subsequently formed seventh connecting electrode, so that the seventh connecting electrode is connected to the second electrode plate connecting block 32-2.

[0186] In an exemplary embodiment, the shape of the second scanning signal line 62 can be a straight line or a broken line with the main part extending along the first direction X, and can be located on the side of the third electrode 33 away from the fourth electrode 34. The second scanning signal line 62 is connected to the second gate electrode 22 through the thirteenth via V13, thereby realizing that the second scanning signal line 62 is connected to the gate electrode of the second transistor T2, and the second scanning signal line 62 can control the conduction and disconnection of the second transistor T2.

[0187] In an exemplary embodiment, the shape of the third scan signal line 63 can be a straight line or a broken line with the main portion extending along the first direction X, and can be located on the side of the fourth electrode 34 away from the third electrode 33. The third scan signal line 63 is connected to the fourth gate electrode 24 through the fourteenth via V14, thereby realizing that the third scan signal line 63 is connected to the gate electrode of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0188] In an exemplary embodiment, the shape of the fourth scan signal line 64 can be a straight line or a broken line with the main part extending along the first direction X, and can be located on the side of the second scan signal line 62 away from the third electrode 33. The fourth scan signal line 64 is connected to the first gate electrode 21 through the twelfth via V12, thereby realizing that the fourth scan signal line 64 is connected to the gate electrode of the first transistor T1, and the fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0189] In an exemplary embodiment, the shape of the fifth scan signal line 65 can be a straight line or a broken line with the main portion extending along the first direction X, and can be located on the side of the third scan signal line 63 away from the fourth substrate 74. The fifth scan signal line 65 is connected to the ninth gate electrode 29 through the seventeenth via V17, thereby realizing that the fifth scan signal line 65 is connected to the gate electrode of the ninth transistor T9. The fifth scan signal line 65 can control the conduction and disconnection of the ninth transistor T9.

[0190] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 may be extended to the frame area and connected to the same gate driving circuit to output the same scan signal.

[0191] In an exemplary embodiment, the shape of the first light-emitting signal line 66 can be a straight line or a broken line with the main part extending along the first direction X. The first light-emitting signal line 66 can be located on the side of the first scanning signal line 61 close to the third electrode 33. The first light-emitting signal line 66 is connected to the fifth gate electrode 25 through the fifteenth via V15, thereby realizing that the first light-emitting signal line 66 is connected to the gate electrode of the fifth transistor T5. The first light-emitting signal line 66 can control the conduction and disconnection of the fifth transistor T5.

[0192] In an exemplary embodiment, the shape of the second light-emitting signal line 67 can be a straight line or a broken line with the main portion extending along the first direction X. The second light-emitting signal line 67 can be located between the fourth scanning signal line 64 and the first light-emitting signal line 66. The second light-emitting signal line 67 is connected to the sixth gate electrode 26 through the sixteenth via hole V16, thereby realizing that the second light-emitting signal line 67 is connected to the gate electrode of the sixth transistor T6. The second light-emitting signal line 67 can control the conduction and disconnection of the sixth transistor T6.

[0193] In an exemplary embodiment, the shape of the second initial signal line 72 can be a straight line or a broken line with the main portion extending along the first direction X. The second initial signal line 72 can be located on the side of the first scanning signal line 61 away from the third electrode plate 33. The second initial signal line 72 is connected to the first area of ​​the seventh active layer through the seventh via V7, thereby realizing that the second initial signal line 72 is connected to the first electrode of the seventh transistor T7. The second initial signal line 72 can write the second initial signal into the first electrode of the seventh transistor T7.

[0194] In an exemplary embodiment, the shape of the first reference signal line 81 can be a straight line or a broken line with the main portion extending along the first direction X. The first reference signal line 81 can be located between the third scanning signal line 63 and the fourth electrode plate 34. The first reference signal line 81 is connected to the first region of the ninth active layer through the ninth via V9, thereby realizing that the first reference signal line 81 is connected to the first electrode of the ninth transistor T9. The first reference signal line 81 can write the first reference signal into the first electrode of the ninth transistor T9.

[0195] In an exemplary embodiment, the shape of the second reference signal line 82 can be a straight line or a broken line with the main portion extending along the first direction X. The second reference signal line 82 can be located between the first light-emitting signal line 66 and the second initial signal line 72. The second reference signal line 82 is connected to the first region of the eighth active layer through the eighth via V8, thereby realizing that the second reference signal line 82 is connected to the first electrode of the eighth transistor T8. The second reference signal line 82 can write the second reference signal into the first electrode of the eighth transistor T8.

[0196] In an exemplary embodiment, the third scan signal line 63, the fifth scan signal line 65, and the first reference signal line 81 may be located on a side of the fourth plate 34 away from the third plate 33. Specifically, the first reference signal line 81 may be located on a side of the fourth plate 34 away from the third plate 33, the third scan signal line 63 may be located on a side of the first reference signal line 81 away from the fourth plate 34, and the fifth scan signal line 65 may be located on a side of the third scan signal line 63 away from the fourth plate 34.

[0197] In an exemplary embodiment, the second scan signal line 62, the fourth scan signal line 64, the first light-emitting signal line 66, the second light-emitting signal line 67, the second initial signal line 72, and the second reference signal line 82 may be located on a side of the third plate 33 away from the fourth plate 34. Specifically, the second scan signal line 62 may be located on a side of the third plate 33 away from the fourth plate 34, the fourth scan signal line 64 may be located on a side of the second scan signal line 62 away from the third plate 33, the second light-emitting signal line 67 may be located on a side of the fourth scan signal line 64 away from the third plate 33, the first light-emitting signal line 66 may be located on a side of the second light-emitting signal line 67 away from the third plate 33, the second reference signal line 82 may be located on a side of the first light-emitting signal line 66 away from the third plate 33, and the second initial signal line 72 may be located on a side of the second reference signal line 82 away from the third plate 33.

[0198] In an exemplary embodiment, the first connection electrode 41 may be in a block shape (e.g., a rectangular shape) and may be disposed between the first light emitting signal line 66 and the second light emitting signal line 67. The first connection electrode 41 is connected to the first region of the first active layer through a first via hole V1. In an exemplary embodiment, the first connection electrode 41 is configured to be connected to a first initial signal line formed subsequently.

[0199] In an exemplary embodiment, the second connection electrode 42 may be block-shaped (e.g., rectangular) and may be disposed between the third plate 33 and the second scan signal line 62. A first end of the second connection electrode 42 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via V2, and a second end of the second connection electrode 42 is connected to the first plate connection block 31-1 via a tenth via V10. Because the first plate connection block 31-1 is connected to the first plate 31, and the first plate 31 serves as the gate electrode of the third transistor T3, the second connection electrode 42 ensures that the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the first capacitor have the same potential, forming a first node N1 of the pixel driving circuit.

[0200] In an exemplary embodiment, the third connection electrode 43 may be block-shaped (e.g., rectangular) and may be disposed between the third scan signal line 63 and the fifth scan signal line 65. The third connection electrode 43 is connected to the first region of the fourth active layer through a third via hole V3. In an exemplary embodiment, the third connection electrode 43 is configured to be connected to a subsequently formed data signal line.

[0201] In an exemplary embodiment, the fourth connection electrode 44 may be block-shaped (e.g., rectangular) and may be disposed between the first light emitting signal line 66 and the second light emitting signal line 67. The fourth connection electrode 44 is connected to the first region of the fifth active layer through a fifth via hole V5. In an exemplary embodiment, the fourth connection electrode 44 is configured to be connected to a first power supply line formed subsequently.

[0202] In an exemplary embodiment, the fifth connection electrode 45 may be in a block shape (e.g., a rectangle) and may be disposed between the first light emitting signal line 66 and the second light emitting signal line 67. The fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a sixth via hole V6. In an exemplary embodiment, the fifth connection electrode 45 is configured to be connected to a subsequently formed anode connection electrode.

[0203] In an exemplary embodiment, in at least one circuit unit, the first connection electrode 41 may be disposed on one side of the fourth connection electrode 44 in the first direction X, and the fifth connection electrode 45 may be disposed on one side of the first connection electrode 41 in the first direction X.

[0204] In an exemplary embodiment, the sixth connecting electrode 46 may be in the shape of a block (such as a rectangle), may be disposed on a side of the fourth electrode plate 34 away from the third electrode plate 33, and may be connected to the fourth electrode plate 34. The sixth connecting electrode 46 may be connected to the second region of the fourth active layer (also the second region of the ninth active layer) through a fourth via hole V4.

[0205] In an exemplary embodiment, the sixth connection electrode 46 and the fourth plate 34 may be an integral structure connected to each other. Since the third plate 33 and the fourth plate 34 are an integral structure connected to each other, the sixth connection electrode 46 enables the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third plate 33 of the first capacitor, and the fourth plate 34 of the second capacitor to have the same potential, forming a fifth node N5 of the pixel driving circuit.

[0206] In an exemplary embodiment, the seventh connection electrode 47 may be block-shaped (e.g., rectangular) and may be disposed within the recess 37. The seventh connection electrode 47 is connected to the second electrode plate connection block 32-2 via the eleventh via hole V11. In an exemplary embodiment, the seventh connection electrode 47 is configured to be connected to a first power line formed subsequently.

[0207] In an exemplary embodiment, positions and shapes of the third conductive layers in the plurality of circuit units in the first direction X may be substantially the same.

[0208] (16) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 13 .

[0209] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display substrate includes at least a twenty-first via hole V21 , a twenty-second via hole V22 , a twenty-third via hole V23 , a twenty-fourth via hole V24 , a twenty-fifth via hole V25 , and a twenty-sixth via hole V26 .

[0210] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the third connecting electrode 43 on the substrate, the fourth insulating layer in the twenty-first via hole V21 is removed, exposing the surface of the third connecting electrode 43, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the third connecting electrode 43 through the via hole.

[0211] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the fourth insulating layer in the twenty-second via hole V22 is removed, exposing the surface of the fourth connecting electrode 44, and the twenty-second via hole V22 is configured to connect the subsequently formed first power line to the fourth connecting electrode 44 through the via hole.

[0212] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fourth insulating layer in the twenty-third via hole V23 is removed, exposing the surface of the fifth connecting electrode 45, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the fifth connecting electrode 45 through the via hole.

[0213] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the seventh connecting electrode 47 on the substrate, the fourth insulating layer in the twenty-fourth via V24 is removed, exposing the surface of the seventh connecting electrode 47, and the twenty-fourth via V24 is configured to connect the subsequently formed first power line to the seventh connecting electrode 47 through the via.

[0214] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the first connecting electrode 41 on the substrate, the fourth insulating layer in the twenty-fifth via hole V25 is removed, exposing the surface of the first connecting electrode 41, and the twenty-fifth via hole V25 is configured to connect the subsequently formed first initial signal line to the first connecting electrode 41 through the via hole.

[0215] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the first reference signal line 81 on the substrate, the fourth insulating layer in the twenty-sixth via V26 is removed, exposing the surface of the first reference signal line 81, and the twenty-sixth via V26 is configured to connect the subsequently formed first reference connection line to the first reference signal line 81 through the via.

[0216] In an exemplary embodiment, positions and shapes of the via holes in the plurality of circuit units in the first direction X may be substantially the same.

[0217] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in Figures 14A and 14B , with Figure 14B being a schematic diagram of the fourth conductive layer in Figure 14A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0218] In an exemplary embodiment, the fourth conductive layer patterns of the plurality of circuit units in the display substrate may each include a first power line 51 , a data signal line 52 , a first reference connection line 53 , an anode connection electrode 54 , and a first initial signal line 71 .

[0219] In an exemplary embodiment, the shapes of the first power line 51, the data signal line 52, the first reference connection line 53 and the first initial signal line 71 can be straight lines or broken lines with the main body extending along the second direction Y. The first power line 51 can be located on one side of the first reference connection line 53 in the first direction X, the first initial signal line 71 can be located on one side of the first power line 51 in the first direction X, and the data signal line 52 can be located on one side of the first initial signal line 71 in the first direction X.

[0220] In an exemplary embodiment, the first power line 51 may be shaped as a straight line or a zigzag line, with its main portion extending along the second direction Y. The first power line 51 is connected to the fourth connection electrode 44 via the twenty-second via hole V22, and to the seventh connection electrode 47 via the twenty-fourth via hole V24. Since the fourth connection electrode 44 is connected to the first region of the fifth active layer via the via hole, the seventh connection electrode 47 is connected to the second plate connection block 32-2 via the via hole, and the second plate connection block 32-2 is connected to the second plate 32, the first power line 51 is connected to the first electrode of the fifth transistor T5 and the second plate 32 of the second capacitor. The first power line 51 can write a first power signal to the first electrode of the fifth transistor T5 and the first end of the second capacitor.

[0221] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps the orthographic projection of the second connection electrode 42 on the substrate. Because the second connection electrode 42 serves as the first node N1 in the pixel driving circuit, the constant voltage first power line 51 can effectively shield the first node N1 from the effects of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0222] In an exemplary embodiment, the data signal line 52 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 52 is connected to the third connection electrode 43 through the twenty-first via hole V21. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via hole, the data signal line 52 writes the data signal to the first electrode of the fourth transistor T4.

[0223] In an exemplary embodiment, the shape of the first reference connection line 53 can be a straight line or a broken line extending along the second direction Y of the main part. The first reference connection line 53 is connected to the first reference signal line 81 through the twenty-sixth via V26, thereby realizing the mutual connection between the first reference signal line 81 extending along the first direction X of the main part and the first reference connection line 53 extending along the second direction Y of the main part, so that the first reference signal line 81 and the first reference connection line 53 form a meshed network connection structure for transmitting the first reference signal on the display substrate, which can not only effectively reduce the resistance of the first reference signal line and reduce the voltage drop of the first reference signal, but also effectively improve the uniformity of the first reference signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0224] In an exemplary embodiment, the anode connection electrode 54 may be in a block shape (e.g., a rectangular shape) and is connected to the fifth connection electrode 45 via a twenty-third via hole V23. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via the via hole, the anode connection electrode 54 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connection electrode 54 is configured to be connected to a subsequently formed anode, thereby enabling the pixel driving circuit to drive the light-emitting device.

[0225] In an exemplary embodiment, the shape of the first initial signal line 71 can be a straight line or a broken line with the main part extending along the second direction Y. The first initial signal line 71 is connected to the first connection electrode 41 through the twenty-fifth via V25, thereby enabling the first initial signal line 71 to write the first initial signal into the first electrode of the first transistor T1.

[0226] In an exemplary embodiment, the first power line 51, the data signal line 52, the first reference connection line 53 and the first initial signal line 71 can be designed with equal width or unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0227] In an exemplary embodiment, since the first plate 31 of the first capacitor (the first end of the first capacitor) has a potential of the first node N1 and the third plate 33 of the first capacitor (the second end of the first capacitor) has a potential of the fifth node N5, the first plate 31 and the third plate 33 form a first capacitor.

[0228] In an exemplary embodiment, since the second plate 32 of the second capacitor (the first end of the second capacitor) has the potential of the first power line 51 and the fourth plate 34 of the second capacitor (the second end of the second capacitor) has the potential of the fifth node N5, the second plate 32 and the fourth plate 34 form a second capacitor.

[0229] The present disclosure utilizes the first conductive layer and the third conductive layer to form the first capacitor and the second capacitor, and the third plate and the fourth plate are an interconnected integral structure, which effectively increases the capacitance value of the first capacitor and the second capacitor and reduces the occupied area.

[0230] In an exemplary embodiment, positions and shapes of the fourth conductive layers in the plurality of circuit units in the first direction X may be substantially the same.

[0231] In an exemplary embodiment, the subsequent preparation process may include forming a flat layer pattern, an anode via is provided on the flat layer, the orthographic projection of the anode via on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, the flat layer in the anode via is removed to expose the surface of the anode connecting electrode, and the anode via is configured to connect a subsequently formed anode to the anode connecting electrode through the via.

[0232] At this point, the driving circuit layer is prepared on the substrate. In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer and an encapsulation structure layer can be sequentially prepared on the driving circuit layer, which will not be described in detail here.

[0233] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0234] In an exemplary embodiment, the first conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene. In other words, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0235] In an exemplary embodiment, during the above preparation process, while forming the pixel driving circuit in the display area, the gate driving circuit can be simultaneously formed in the frame area and the data transmission line can be simultaneously formed in the bonding area.

[0236] In an exemplary embodiment, the scan output lines of the gate driver circuit in the frame region are connected to the scan signal lines in the display region. The multiple scan output lines in the frame region may all be located on the first conductive layer and connected to the multiple scan signal lines in the display region on the third conductive layer via jumper wires. Alternatively, the multiple scan output lines in the frame region may alternately be located on the first and fourth conductive layers and connected to the multiple scan signal lines in the display region on the third conductive layer via jumper wires.

[0237] In an exemplary embodiment, the data transmission lines in the binding area are connected to the data signal lines in the display area. The multiple data transmission lines in the binding area can all be located in the first conductive layer, and connected to the multiple data signal lines located in the fourth conductive layer in the display area by means of jumpers. Alternatively, the multiple data transmission lines in the binding area can be alternately located in the shielding metal layer and the first conductive layer, and connected to the multiple data signal lines located in the fourth conductive layer in the display area by means of jumpers. Alternatively, the multiple data transmission lines in the binding area can be alternately located in the first conductive layer and the third conductive layer, or the multiple data transmission lines in the binding area can be alternately located in the first conductive layer and the fourth conductive layer, and the present disclosure is not limited thereto.

[0238] Figure 15 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure, and Figure 16 is a cross-sectional view taken along line AA in Figure 15. The main structure of the display substrate in this embodiment is substantially the same as that of the display substrates shown in Figures 6 and 7, except that the display substrate in this embodiment does not include a shielding metal layer.

[0239] As shown in Figures 15 and 16, in an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include: a first insulating layer 110 arranged on a substrate 101, a semiconductor layer arranged on a side of the first insulating layer 110 away from the substrate 101, a second insulating layer 120 arranged on a side of the semiconductor layer away from the substrate 101, a first conductive layer (GATE1) arranged on a side of the second insulating layer 120 away from the substrate 101, a third insulating layer 130 arranged on a side of the first conductive layer away from the substrate 101, a third conductive layer (SD1) arranged on a side of the third insulating layer 130 away from the substrate 101, a fourth insulating layer 140 arranged on a side of the third conductive layer away from the substrate 101, and a fourth conductive layer (SD2) arranged on a side of the fourth insulating layer 140 away from the substrate 101.

[0240] In an exemplary embodiment, the semiconductor layer may include at least a first active layer 11, a second active layer 12, a third active layer 13, a fourth active layer 14, and a ninth active layer 19. The first conductive layer may include at least a first electrode plate 31 and a second electrode plate 32. The third conductive layer may include at least a third electrode plate 33, a fourth electrode plate 34, a second connecting electrode 42, a sixth connecting electrode 46, and a seventh connecting electrode 47. The orthographic projection of the third electrode plate 33 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate, and the orthographic projection of the fourth electrode plate 34 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 32 on the substrate. The second connecting electrode 42 is connected to the first electrode plate 31 through a via hole, the sixth connecting electrode 46 is connected to the fourth active layer 14 and the ninth active layer 19 through a via hole, and the seventh connecting electrode 47 is connected to the second electrode plate 32 through a via hole. The fourth conductive layer may include at least a first power line 51, which is connected to the seventh connecting electrode 47 through a via hole.

[0241] In an exemplary embodiment, the first conductive layer may further include a first scan signal line 61 and gate electrodes of multiple transistors, the third conductive layer may further include a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a fifth scan signal line 65, a first light-emitting signal line 66, a second light-emitting signal line 67, a second initial signal line 72, a first reference signal line 81, a second reference signal line 82 and a plurality of connecting electrodes, and the fourth conductive layer may further include a data signal line 52, a first reference connecting line 53 and a first initial signal line 71.

[0242] In an exemplary embodiment, the preparation process of the substrate in this embodiment is substantially the same as that in the previous embodiment, except that the operation of forming the shielding metal layer is omitted.

[0243] Figure 17 is an equivalent circuit diagram of another pixel driving circuit of an exemplary embodiment of the present disclosure. As shown in Figure 17, the pixel driving circuit of the exemplary embodiment of the present disclosure can be a 7T1C structure, which can include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is respectively connected to nine signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power line VDD).

[0244] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the first transistor, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; and the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0245] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0246] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor is connected to the first node N1 .

[0247] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0248] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0249] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0250] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0251] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0252] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1 , a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0253] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0254] FIG18 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of the pixel driving circuit in two circuit units (a first circuit unit Q1 and a second circuit unit Q2) in the display substrate. FIG19 is a cross-sectional view taken along the BB line of FIG18 . As shown in FIG18 and FIG19 , the pixel driving circuit in at least one circuit unit may include at least a storage capacitor and multiple transistors. The multiple transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, and a seventh transistor T7 as a second initialization transistor. The storage capacitor may include a fifth plate 35 and a sixth plate 36, wherein the orthographic projection of the sixth plate 36 on the substrate at least partially overlaps the orthographic projection of the fifth plate 35 on the substrate.

[0255] In this exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, the first electrode of the first transistor T1 is connected to the first initial signal line 71, and the second electrode of the first transistor T1 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The gate electrode of the second transistor T2 is connected to the second scan signal line 62, and the first electrode of the second transistor T2 is connected to the fifth electrode plate 35 via the second connection electrode 42. The gate electrode of the third transistor T3 can serve as the fifth electrode plate 35, and the first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, and the first electrode of the fourth transistor T4 is connected to the data signal line 52. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 68, and the first electrode of the fifth transistor T5 is connected to the first power supply line 51. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 68, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. A gate electrode of the seventh transistor T7 is connected to the first scanning signal line 61 , and a first electrode of the seventh transistor T7 is connected to the second initial signal line 72 .

[0256] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the light-emitting signal line 68, the first initial signal line 71 and the second initial signal line 72 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the first power line 51 and the data signal line 52 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0257] In an exemplary embodiment, at least one circuit unit may further include a first initial connection line 73. The first initial connection line 73 may be in the shape of a straight line or a broken line, with the main portion extending along the second direction Y, and is connected to the first initial signal line 71. This achieves mutual connection between the first initial signal line 71 extending along the first direction X and the first initial connection line 73 extending along the second direction Y, so that the first initial signal line 71 and the first initial connection line 73 form a mesh-like network connection structure on the display substrate for transmitting the first initial signal.

[0258] In an exemplary embodiment, at least one circuit unit may further include a second initial connection line 74. The second initial connection line 74 may be in the shape of a straight line or a broken line, with the main portion extending along the second direction Y, and is connected to the second initial signal line 72. This achieves mutual connection between the second initial signal line 72 extending along the first direction X and the second initial connection line 74 extending along the second direction Y, so that the second initial signal line 72 and the second initial connection line 74 form a mesh-like network connection structure on the display substrate for transmitting the second initial signal.

[0259] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include: a blocking metal layer (BSM) disposed on a substrate 101, a first insulating layer 110 disposed on a side of the blocking metal layer away from the substrate 101, a semiconductor layer disposed on a side of the first insulating layer 110 away from the substrate 101, a second insulating layer 120 disposed on a side of the semiconductor layer away from the substrate 101, a first gate metal layer (GATE1) disposed on a side of the second insulating layer 120 away from the substrate 101, a third insulating layer 130 disposed on a side of the first conductive layer away from the substrate 101, a first source-drain metal layer (SD1) disposed on a side of the third insulating layer 130 away from the substrate 101, a fourth insulating layer 140 disposed on a side of the third conductive layer away from the substrate 101, and a second source-drain metal (SD2) disposed on a side of the fourth insulating layer 140 away from the substrate 101.

[0260] In an exemplary embodiment, the fifth plate 35 of the storage capacitor 30 can be set in the first gate metal layer, and the sixth plate 36 of the storage capacitor 30 can be set in the first source and drain metal layer, and the orthographic projection of the fifth plate 35 on the substrate at least partially overlaps with the orthographic projection of the sixth plate 36 on the substrate.

[0261] In an exemplary embodiment, the first gate electrode of the first transistor T1 may be disposed in the first gate metal layer, the fourth scan signal line 64 may be disposed in the first source-drain metal layer, and the fourth scan signal line 64 may be connected to the first gate electrode of the first transistor T1 through a first gate via.

[0262] In an exemplary embodiment, in the first direction X, the first gate electrodes in two partially adjacent circuit units may be connected to each other in an integrated structure.

[0263] In an exemplary embodiment, in the first direction X, two adjacent circuit units partially share a first gate via hole connecting the same fourth scan signal line 64 to the first gate electrode.

[0264] In an exemplary embodiment, the second gate electrode of the second transistor T2 may be disposed in the first gate metal layer, the second scan signal line 62 may be disposed in the first source / drain metal layer, and the second scan signal line 62 may be connected to the second gate electrode of the second transistor T2 through a via.

[0265] In an exemplary embodiment, the fourth gate electrode of the fourth transistor T4 may be disposed in the first gate metal layer, the third scan signal line 63 may be disposed in the first source-drain metal layer, and the third scan signal line 63 may be connected to the fourth gate electrode of the fourth transistor T4 through a via.

[0266] In an exemplary embodiment, the fifth gate electrode of the fifth transistor T5 may be disposed in the first gate metal layer, the light emitting signal line 68 may be disposed in the first source-drain metal layer, and the light emitting signal line 68 may be connected to the fifth gate electrode of the fifth transistor T5 through a via.

[0267] In an exemplary embodiment, the sixth gate electrode of the sixth transistor T6 may be disposed in the first gate metal layer, the light emitting signal line 68 may be disposed in the first source-drain metal layer, and the light emitting signal line 68 may be connected to the sixth gate electrode of the sixth transistor T6 through a via.

[0268] In an exemplary embodiment, in at least one circuit unit, the fifth gate electrode and the sixth gate electrode may be an integral structure connected to each other.

[0269] In an exemplary embodiment, in at least one circuit unit, the fifth gate electrode and the sixth gate electrode may share the same via hole connected to the light emitting signal line 68 , that is, the light emitting signal line 68 is simultaneously connected to the fifth gate electrode of the fifth transistor T5 through the same via hole.

[0270] In an exemplary embodiment, in the first direction X, the sixth gate electrodes in two partially adjacent circuit units may be connected to each other in an integrated structure.

[0271] In an exemplary embodiment, in the first direction X, the fifth gate electrode and the sixth gate electrode in two partially adjacent circuit units may be an integrated structure connected to each other.

[0272] In an exemplary embodiment, the seventh gate electrode of the seventh transistor T7 may be disposed in the first gate metal layer, the first scan signal line 61 may be disposed in the first source-drain metal layer, and the first scan signal line 61 may be connected to the seventh gate electrode of the seventh transistor T7 through a via.

[0273] In an exemplary embodiment, in the first direction X, the seventh gate electrodes in two partially adjacent circuit units may be connected to each other in an integrated structure.

[0274] In an exemplary embodiment, the first and second preliminary connection lines 73 and 74 may be disposed in a first gate metal layer, and the first and second preliminary signal lines 71 and 72 may be disposed in a first source / drain metal layer.

[0275] As shown in FIG19 , in an exemplary embodiment, the shielding metal layer may include at least a shielding electrode 91, the semiconductor layer may include at least a third active layer 13, and the first gate metal layer (first conductive layer) may include at least a fifth electrode 35. The first source-drain metal layer (third conductive layer) may include at least a sixth electrode 36 and a second connection electrode 42, the second connection electrode 42 being connected to the fifth electrode 35 via a via. The second source-drain metal layer (fourth conductive layer) may include at least a first power line 51, the first power line 51 being connected to the sixth electrode 36 via a via.

[0276] In an exemplary embodiment, taking two circuit units (a first circuit unit Q1 and a second circuit unit Q2) as an example, the manufacturing process of the display substrate of this embodiment may include the following operations.

[0277] (21) Forming a blocking metal layer pattern. In an exemplary embodiment, forming the blocking metal layer pattern may include: depositing a blocking metal film on a substrate, patterning the blocking metal film through a patterning process, and forming a blocking metal layer (BSM) disposed on the substrate, as shown in FIG. 20 .

[0278] In an exemplary embodiment, the blocking metal layer of each circuit unit in the display substrate may include at least a blocking electrode 91 .

[0279] In an exemplary embodiment, the shape of the blocking electrode 91 can be block-shaped (such as rectangular), and the blocking electrode 91 is configured to serve as a blocking layer for the third transistor T3, shielding the third transistor T3 from light, reducing the intensity of light irradiated on the third transistor T3, reducing the leakage current of the third transistor T3, and thereby reducing the impact of light on the characteristics of the third transistor T3.

[0280] In an exemplary embodiment, the shielding electrode 91 in the present circuit unit and the shielding electrode 91 in the adjacent circuit unit in the first direction X may be an integrated structure connected to each other to form a shielding line extending along the first direction X.

[0281] In an exemplary embodiment, the blocking metal layers of adjacent circuit units in the first direction X may be substantially mirror-symmetrical with respect to a unit reference line, which is a straight line located between adjacent circuit units and extending along the second direction Y.

[0282] (22) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding metal layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG21A and FIG21B , where FIG21B is a schematic diagram of the semiconductor layer in FIG21A .

[0283] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display substrate may include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, and a seventh active layer 17 of a seventh transistor T7, and the first active layer 11 to the seventh active layer 17 may be an integrated structure connected to each other.

[0284] In an exemplary embodiment, in the second direction Y, the first active layer 11 and the second active layer 12 can be located on the side of the third active layer 13 of the present circuit unit in the opposite direction of the second direction Y, and the fourth active layer 14, the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 can be located on the side of the third active layer 13 in the second direction Y.

[0285] In an exemplary embodiment, the first to seventh active layers 11, 12, 14, 16, and 17 may have an I shape, and the third to fifth active layers 13 and 15 may have an L shape.

[0286] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 91 on the substrate, so that the shielding electrode 91 can shield the third transistor T3, reduce the intensity of light irradiated on the third transistor T3, reduce the leakage current of the third transistor T3, and thus reduce the impact of light on the characteristics of the third transistor T3.

[0287] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer, the second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected. The second region 13-2 of the third active layer may simultaneously serve as the second region 11-2 of the first active layer, the second region 12-2 of the second active layer, and the first region 16-1 of the sixth active layer, forming a third node N3 of the pixel driving circuit. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected. The first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer, forming a second node N2 of the pixel driving circuit. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer, constituting a fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer, the first region 12-1 of the second active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer can be provided separately.

[0288] In an exemplary embodiment, semiconductor layers of adjacent circuit cells in the first direction X may be substantially mirror-symmetrical with respect to a cell reference line.

[0289] (23) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG. 22A and FIG. 22B , where FIG. 22B is a schematic diagram of the first conductive layer in FIG. 22A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0290] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a seventh gate electrode 27 and a fifth plate 35 of the storage capacitor.

[0291] In an exemplary embodiment, the shape of the fifth plate 35 of the storage capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the fifth plate 35 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. The fifth plate 35 can serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0292] In an exemplary embodiment, the fifth electrode plate 35 may be provided with a fifth electrode plate connecting block 35-1. The fifth electrode plate connecting block 35-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the fifth electrode plate 35 opposite to the second direction Y. A first end of the fifth electrode plate connecting block 35-1 is connected to the fifth electrode plate 35, and a second end of the fifth electrode plate connecting block 35-1 extends away from the fifth electrode plate 35. The fifth electrode plate connecting block 35-1 is configured to be connected to the first region of the second active layer via a second connecting electrode formed subsequently.

[0293] In an exemplary embodiment, the first gate electrode 21 may be in the shape of a strip extending along the first direction X, and may be located on the side of the fifth electrode 35 in the opposite direction of the second direction Y. The region where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1.

[0294] In an exemplary embodiment, in the first direction X, the first gate electrodes 21 in two partially adjacent circuit units may be an integrated structure connected to each other. For example,

[0295] In an exemplary embodiment, the first gate electrode 21 in the first circuit unit Q1 and the first gate electrode 21 in the second circuit unit Q2 adjacent in the first direction X may be an integral structure connected to each other.

[0296] In an exemplary embodiment, the second gate electrode 22 may be U-shaped and may be located between the fifth plate 35 and the first gate electrode 21 . The region where the second gate electrode 22 overlaps with the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0297] In an exemplary embodiment, the fourth gate electrode 24 may be in the shape of a strip extending along the first direction X and may be located on one side of the fifth electrode 35 in the second direction Y. The region where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4.

[0298] In an exemplary embodiment, the fifth gate electrode 25 may be in the shape of a strip extending along the first direction X and may be located on one side of the fifth electrode plate 35 in the second direction Y. The area where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5.

[0299] In an exemplary embodiment, the sixth gate electrode 26 may be in the shape of a strip extending along the first direction X and may be located on one side of the fifth electrode 35 in the second direction Y. The area where the sixth gate electrode 26 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0300] In example embodiments, the sixth gate electrode 26 may be located on one side of the fifth gate electrode 25 in the first direction X or on a side in the opposite direction of the first direction X, and connected to the fifth gate electrode 25 .

[0301] In an exemplary embodiment, in at least one circuit unit, the fifth gate electrode 25 and the sixth gate electrode 26 may be an integral structure connected to each other.

[0302] In an exemplary embodiment, the sixth gate electrodes in two partially adjacent circuit units in the first direction X may be connected to each other as an integral structure. For example, the sixth gate electrode 26 in the first circuit unit Q1 and the sixth gate electrode 26 in the second circuit unit Q2 adjacent to each other in the first direction X may be connected to each other as an integral structure.

[0303] In an exemplary embodiment, in the first direction X, the fifth gate electrode 25 and the sixth gate electrode 26 in two partially adjacent circuit units may be an integrated structure connected to each other.

[0304] In an exemplary embodiment, the seventh gate electrode 27 may be in the shape of a strip extending along the first direction X, and may be located on a side of the sixth gate electrode 26 away from the fifth electrode plate 35 . The area where the seventh gate electrode 27 overlaps with the seventh active layer may serve as the gate electrode of the seventh transistor T7 .

[0305] In an exemplary embodiment, the seventh gate electrodes in two partially adjacent circuit units in the first direction X may be connected to each other as an integral structure. For example, the seventh gate electrode 27 in the first circuit unit Q1 and the seventh gate electrode 27 in the second circuit unit Q2 adjacent to each other in the first direction X may be connected to each other as an integral structure.

[0306] In an exemplary embodiment, the above-described patterns of the first conductive layers of adjacent circuit cells in the first direction X may be substantially mirror-symmetrical with respect to the cell reference line.

[0307] In exemplary embodiments, the first conductive layer may further include a first preliminary connection line 73 and a second preliminary connection line 74 .

[0308] In an exemplary embodiment, the first preliminary connection line 73 may be in the shape of a straight line or a broken line, with the main portion extending along the second direction Y. The line may be located on a side of the first circuit unit Q1 opposite to the first direction X. A first preliminary connection block 73-1 may be provided on the first preliminary connection line 73. The first preliminary connection block 73-1 may be in the shape of a block (e.g., a rectangle) and connected to the first preliminary connection line 73. The first preliminary connection block 73-1 is configured to connect to a subsequently formed first preliminary signal line.

[0309] In an exemplary embodiment, in at least one circuit unit, the first preliminary connection line 73 and the first preliminary connection block 73 - 1 may be an integral structure connected to each other.

[0310] In an exemplary embodiment, the second preliminary connection line 74 may be in the shape of a straight line or a zigzag line, with a main portion extending along the second direction Y. The second preliminary connection line 74 may be located on one side of the second circuit unit Q2 in the first direction X. A second preliminary connection block 74-1 may be provided on the second preliminary connection line 74. The second preliminary connection block 74-1 may be in the shape of a block (e.g., a rectangle) and connected to the second preliminary connection line 74. The second preliminary connection block 74-1 is configured to connect to a subsequently formed second preliminary signal line.

[0311] In an exemplary embodiment, in at least one circuit unit, the second preliminary connection line 74 and the second preliminary connection block 74 - 1 may be an integral structure connected to each other.

[0312] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield. The semiconductor layer shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer not shielded by the first conductive layer is conductorized. The first region and the second region of the first active layer to the seventh active layer are all conductorized.

[0313] (24) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film using a patterning process to form a third insulating layer covering the first conductive layer, and providing a plurality of vias in each circuit unit, as shown in FIG. 23 .

[0314] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fifth via V5, a sixth via V6, a seventh via V7, a tenth via V10, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and an eighteenth via V18.

[0315] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first initial signal line to the first region of the first active layer through the via hole.

[0316] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first region of the second active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the first region of the second active layer through the via hole.

[0317] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first region of the fourth active layer through the via hole.

[0318] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first region of the fifth active layer, and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via hole.

[0319] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the sixth via hole V6 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0320] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the third insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first region of the seventh active layer, and the seventh via V7 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.

[0321] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the fifth plate connecting block 35-1 of the fifth plate 35 on the substrate, the third insulating layer in the tenth via hole V10 is etched away, exposing the surface of the fifth plate connecting block 35-1, and the tenth via hole V10 is configured to connect a subsequently formed second connecting electrode to the fifth plate connecting block 35-1 through the via hole.

[0322] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the third insulating layer in the twelfth via hole V12 is etched away to expose the surface of the first gate electrode 21, and the twelfth via hole V12 is configured to connect the subsequently formed fourth scanning signal line to the first gate electrode 21 through the via hole. The twelfth via hole V12 can serve as the first gate via hole of the present disclosure.

[0323] In an exemplary embodiment, since the first gate electrodes 21 in the adjacent circuit units in the first direction X are connected to each other as an integral structure, the twelfth via hole V12 can be provided between the adjacent circuit units, and the adjacent circuit units can share the same twelfth via hole V12.

[0324] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second gate electrode 22 on the substrate, the third insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the second gate electrode 22, and the thirteenth via hole V13 is configured to connect a subsequently formed second scanning signal line to the second gate electrode 22 through the via hole.

[0325] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the fourth gate electrode 24 on the substrate, the third insulating layer in the fourteenth via hole V14 is etched away to expose the surface of the fourth gate electrode 24, and the fourteenth via hole V14 is configured to connect the subsequently formed third scan signal line to the fourth gate electrode 24 through the via hole.

[0326] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the third insulating layer in the fifteenth via hole V15 is etched away to expose the surface of the fifth gate electrode 25, and the fifteenth via hole V15 is configured to connect a subsequently formed light-emitting signal line to the fifth gate electrode 25 through the via hole.

[0327] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the third insulating layer in the sixteenth via hole V16 is etched away to expose the surface of the sixth gate electrode 26, and the sixteenth via hole V16 is configured to connect a subsequently formed light-emitting signal line to the sixth gate electrode 26 through the via hole.

[0328] In an exemplary embodiment, since the fifth gate electrode 25 and the sixth gate electrode 26 in one circuit unit are an integrated structure connected to each other, the fifteenth via hole V15 and the sixteenth via hole V16 may be the same via hole.

[0329] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the seventh gate electrode 27 on the substrate, the third insulating layer in the eighteenth via hole V18 is etched away to expose the surface of the seventh gate electrode 27, and the eighteenth via hole V18 is configured to connect the subsequently formed first scanning signal line to the seventh gate electrode 27 through the via hole.

[0330] In an exemplary embodiment, a plurality of via holes of adjacent circuit cells in the first direction X may be substantially mirror-symmetrical with respect to the cell reference line.

[0331] In exemplary embodiments, the third insulating layer may further include first and second preliminary via holes V31 and V32 .

[0332] In an exemplary embodiment, the orthographic projection of the first initial via V31 on the substrate is located within the range of the orthographic projection of the first initial connection block 73-1 of the first initial connection line 73 on the substrate, the third insulating layer in the first initial via V31 is etched away, exposing the surface of the first initial connection block 73-1, and the first initial via V31 is configured to connect the subsequently formed first initial signal line to the first initial connection block 73-1 through the via.

[0333] In an exemplary embodiment, the orthographic projection of the second initial via V32 on the substrate is located within the range of the orthographic projection of the second initial connection block 74-1 of the second initial connection line 74 on the substrate, the third insulating layer in the second initial via V32 is etched away to expose the surface of the second initial connection block 74-1, and the second initial via V32 is configured to connect the subsequently formed second initial signal line to the second initial connection block 74-1 through the via.

[0334] (25) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in FIG. 24A and FIG. 24B , where FIG. 24B is a schematic diagram of the third conductive layer in FIG. 24A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0335] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate may include: a sixth plate 36 of a storage capacitor, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a first scanning signal line 61, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a light-emitting signal line 68, a first initial signal line 71, and a second initial signal line 72.

[0336] In an exemplary embodiment, the shape of the sixth plate 36 of the storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the sixth plate 36 on the substrate at least partially overlaps with the orthographic projection of the fifth plate 35 on the substrate. The sixth plate 36 can serve as another plate of the storage capacitor, and the fifth plate 35 and the sixth plate 36 constitute the storage capacitor of the pixel driving circuit.

[0337] In an exemplary embodiment, the sixth electrode plate 36 may be provided with a sixth electrode plate connecting block 36-1. The sixth electrode plate connecting block 36-1 may be in the shape of a strip extending along the first direction X and may be provided on one side of the sixth electrode plate 36 in the first direction X or on a side opposite to the first direction X. A first end of the sixth electrode plate connecting block 36-1 is connected to the sixth electrode plate 36, and a second end of the sixth electrode plate connecting block 36-1 extends to an adjacent circuit unit and is connected to the sixth electrode plate 36 of the adjacent circuit unit.

[0338] In an exemplary embodiment, the sixth electrode plate 36 and the sixth electrode plate connecting block 36 - 1 in one circuit unit may be an integral structure connected to each other.

[0339] In an exemplary embodiment, the plurality of sixth plates 36 and the plurality of sixth plate connecting blocks 36-1 spaced apart in a cell row may be interconnected and integrally formed. Since the sixth plates 36 are connected to a subsequently formed first power line, the sixth plates 36 of the integrated structure of the multiple circuit units can be reused as a transverse power line extending along the first direction X. This not only ensures that the plurality of sixth plates 36 in a cell row have the same potential, but also reduces the voltage drop of the first power signal, thereby improving the uniformity of the panel, preventing display defects on the display substrate, and ensuring the display quality of the display substrate.

[0340] In an exemplary embodiment, the shape of the first scanning signal line 61 can be a straight line or a broken line with the main part extending along the first direction X, and can be located on one side of the sixth electrode 36 in the second direction Y. The first scanning signal line 61 is connected to the seventh gate electrode 27 through the eighteenth via V18, thereby realizing that the first scanning signal line 61 is connected to the gate electrode of the seventh transistor T7, and the first scanning signal line 61 is used to control the conduction and disconnection of the seventh transistor T7.

[0341] In an exemplary embodiment, the shape of the second scanning signal line 62 can be a straight line or a broken line with the main part extending along the first direction X, and can be located on the side of the sixth electrode 36 in the opposite direction of the second direction Y. The second scanning signal line 62 is connected to the second gate electrode 22 through the thirteenth via V13, thereby realizing that the second scanning signal line 62 is connected to the gate electrode of the second transistor T2, and the second scanning signal line 62 can control the conduction and disconnection of the second transistor T2.

[0342] In an exemplary embodiment, the shape of the third scan signal line 63 can be a straight line or a broken line with the main part extending along the first direction X, and can be located between the sixth electrode 36 and the first scan signal line 61. The third scan signal line 63 is connected to the fourth gate electrode 24 through the fourteenth via V14, thereby realizing that the third scan signal line 63 is connected to the gate electrode of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0343] In an exemplary embodiment, the shape of the fourth scan signal line 64 can be a straight line or a broken line with the main part extending along the first direction X, and can be located on the side of the second scan signal line 62 away from the sixth electrode 36. The fourth scan signal line 64 is connected to the first gate electrode 21 through the twelfth via V12, thereby realizing that the fourth scan signal line 64 is connected to the gate electrode of the first transistor T1, and the fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0344] In an exemplary embodiment, the shape of the light-emitting signal line 68 can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting signal line 68 can be located between the sixth electrode 36 and the third scanning signal line 63. The light-emitting signal line 68 is connected to the fifth gate electrode 25 (also the sixth gate electrode 26) through the fifteenth via hole V15 (also the sixteenth via hole V16), thereby realizing that the light-emitting signal line 68 is connected to the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6. The light-emitting signal line 68 can simultaneously control the conduction and disconnection of the fifth transistor T5 and the sixth transistor T6.

[0345] In an exemplary embodiment, the shape of the first initial signal line 71 can be a straight line or a broken line with the main portion extending along the first direction X. The first initial signal line 71 can be located on the side of the fourth scanning signal line 64 away from the sixth electrode plate 36. The first initial signal line 71 is connected to the first area of ​​the first active layer through the first via V1, thereby realizing that the first initial signal line 71 is connected to the first electrode of the first transistor T1. The first initial signal line 71 can write the first initial signal into the first electrode of the first transistor T1.

[0346] In the exemplary embodiment, the first initial signal line 71 is further connected to the first initial connection block 73-1 via the first initial via V31. Since the first initial connection block 73-1 is connected to the first initial connection line 73, the first initial signal line 71, whose main portion extends along the first direction X, is interconnected with the first initial connection line 73, whose main portion extends along the second direction Y. This allows the first initial signal line 71 and the first initial connection line 73 to form a mesh-like network connection structure on the display substrate for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial signal line and the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal across the display substrate, effectively improving display uniformity and enhancing display quality.

[0347] In an exemplary embodiment, the shape of the second initial signal line 72 can be a straight line or a broken line with the main part extending along the first direction X. The second initial signal line 72 can be located on the side of the first scanning signal line 61 away from the sixth electrode plate 36. The second initial signal line 72 is connected to the first area of ​​the seventh active layer through the seventh via V7, thereby realizing that the second initial signal line 72 is connected to the first electrode of the seventh transistor T7. The second initial signal line 72 can write the second initial signal into the first electrode of the seventh transistor T7.

[0348] In the exemplary embodiment, the second initial signal line 72 is further connected to the second initial connection block 74-1 via the second initial via V32. Since the second initial connection block 74-1 is connected to the second initial connection line 74, the second initial signal line 72, whose main portion extends along the first direction X, is interconnected with the second initial connection line 74, whose main portion extends along the second direction Y. This allows the second initial signal line 72 and the second initial connection line 74 to form a mesh-like network connection structure on the display substrate for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial signal line and the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal across the display substrate, effectively improving display uniformity and enhancing display quality.

[0349] In an exemplary embodiment, only one of the first initial connection line 73 and the second initial connection line 74 may be provided in one cell column, and the first initial connection line 73 and the second initial connection line 74 are alternately provided in the first direction X. For example, the first initial connection line 73 may be provided in the cell column where the first circuit unit and the third circuit unit are located, and the second initial connection line 74 may be provided in the cell column where the second circuit unit and the fourth circuit unit are located.

[0350] In an exemplary embodiment, the first initial connection lines 73 of adjacent cell columns may be interconnected integrally, or adjacent cell columns may share the same first initial connection line 73. For example, the cell column where the first circuit unit Q1 is located and the adjacent cell column in the opposite direction to the first direction X may share the same first initial connection line 73.

[0351] In an exemplary embodiment, the second initial connection lines 74 of adjacent cell columns may be interconnected as an integral structure, or adjacent cell columns may share the same second initial connection line 74. For example, the cell column where the second circuit unit Q2 is located and the cell column adjacent in the first direction X may share the same second initial connection line 74.

[0352] In an exemplary embodiment, the first scan signal line 61, the third scan signal line 63, the light emitting signal line 68, and the second initial signal line 72 may be located on one side of the sixth electrode plate 36 in the second direction Y. Specifically, the light emitting signal line 68 may be located on one side of the sixth electrode plate 36 in the second direction Y, the third scan signal line 63 may be located on a side of the light emitting signal line 68 away from the sixth electrode plate 36, the first scan signal line 61 may be located on a side of the third scan signal line 63 away from the sixth electrode plate 36, and the second initial signal line 72 may be located on a side of the first scan signal line 61 away from the sixth electrode plate 36.

[0353] In an exemplary embodiment, the second scan signal line 62, the fourth scan signal line 64, and the first initial signal line 71 may be located on a side of the sixth electrode plate 36 opposite to the second direction Y. The second scan signal line 62 may be located on a side of the sixth electrode plate 36 opposite to the second direction Y, the fourth scan signal line 64 may be located on a side of the second scan signal line 62 away from the sixth electrode plate 36, and the first initial signal line 71 may be located on a side of the fourth scan signal line 64 away from the sixth electrode plate 36.

[0354] In an exemplary embodiment, the second connection electrode 42 may be block-shaped (e.g., rectangular) and may be disposed between the sixth plate 36 and the second scan signal line 62. A first end of the second connection electrode 42 is connected to the first region of the second active layer via a second via V2, and a second end of the second connection electrode 42 is connected to the fifth plate connection block 35-1 via a tenth via V10. Because the fifth plate connection block 35-1 is connected to the fifth plate 35, which serves as the gate electrode of the third transistor T3, the second connection electrode 42 ensures that the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the fifth plate 35 of the storage capacitor have the same potential, forming a first node N1 of the pixel driving circuit.

[0355] In an exemplary embodiment, the third connection electrode 43 may be block-shaped (e.g., rectangular) and may be disposed between the first scan signal line 61 and the third scan signal line 63. The third connection electrode 43 is connected to the first region of the fourth active layer through a third via hole V3. In an exemplary embodiment, the third connection electrode 43 is configured to be connected to a subsequently formed data signal line.

[0356] In an exemplary embodiment, the fourth connection electrode 44 may be block-shaped (e.g., rectangular) and may be disposed between the first scan signal line 61 and the third scan signal line 63. The fourth connection electrode 44 is connected to the first region of the fifth active layer through a fifth via hole V5. In an exemplary embodiment, the fourth connection electrode 44 is configured to be connected to a first power line formed subsequently.

[0357] In an exemplary embodiment, the fifth connection electrode 45 may be in a block shape (e.g., a rectangle) and may be disposed between the first scan signal line 61 and the third scan signal line 63. The fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a sixth via hole V6. In an exemplary embodiment, the fifth connection electrode 45 is configured to be connected to a subsequently formed anode connection electrode.

[0358] In an exemplary embodiment, the third conductive layers of adjacent circuit cells in the first direction X may be substantially mirror-symmetrical with respect to the cell reference line.

[0359] (26) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 25 .

[0360] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display substrate includes at least a twenty-first via hole V21 , a twenty-second via hole V22 , a twenty-third via hole V23 , and a twenty-seventh via hole V27 .

[0361] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the third connecting electrode 43 on the substrate, the fourth insulating layer in the twenty-first via hole V21 is removed, exposing the surface of the third connecting electrode 43, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the third connecting electrode 43 through the via hole.

[0362] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the fourth insulating layer in the twenty-second via hole V22 is removed, exposing the surface of the fourth connecting electrode 44, and the twenty-second via hole V22 is configured to connect the subsequently formed first power line to the fourth connecting electrode 44 through the via hole.

[0363] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fourth insulating layer in the twenty-third via hole V23 is removed, exposing the surface of the fifth connecting electrode 45, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the fifth connecting electrode 45 through the via hole.

[0364] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the sixth electrode plate 36 on the substrate, the fourth insulating layer in the twenty-seventh via V27 is removed, exposing the surface of the sixth electrode plate 36, and the twenty-seventh via V27 is configured to connect the subsequently formed first power line to the sixth electrode plate 36 through the via.

[0365] In an exemplary embodiment, a plurality of via holes of adjacent circuit cells in the first direction X may be substantially mirror-symmetrical with respect to the cell reference line.

[0366] (27) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in Figures 26A and 26B, where Figure 26B is a schematic diagram of the fourth conductive layer in Figure 26A. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0367] In an exemplary embodiment, each of the fourth conductive layer patterns of the plurality of circuit units in the display substrate may include a first power line 51 , a data signal line 52 , and an anode connection electrode 54 .

[0368] In an exemplary embodiment, the first power line 51 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 51 is connected to the fourth connection electrode 44 via the twenty-second via hole V22, and is connected to the sixth electrode plate 36 via the twenty-seventh via hole V27. Because the fourth connection electrode 44 is connected to the first region of the fifth active layer via the via hole, the first power line 51 is connected to the first electrode of the fifth transistor T5 and the sixth electrode plate 36 of the storage capacitor. The first power line 51 can write the first power signal to the first electrode of the fifth transistor T5 and the sixth electrode plate 36 of the storage capacitor.

[0369] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps the orthographic projection of the second connection electrode 42 on the substrate. Because the second connection electrode 42 serves as the first node N1 in the pixel driving circuit, the constant voltage first power line 51 can effectively shield the first node N1 from the effects of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0370] In an exemplary embodiment, the data signal line 52 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 52 is connected to the third connection electrode 43 through the twenty-first via hole V21. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via hole, the data signal line 52 writes the data signal to the first electrode of the fourth transistor T4.

[0371] In an exemplary embodiment, the anode connection electrode 54 may be in a block shape (e.g., a rectangular shape) and is connected to the fifth connection electrode 45 via a twenty-third via hole V23. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via the via hole, the anode connection electrode 54 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connection electrode 54 is configured to be connected to a subsequently formed anode, thereby enabling the pixel driving circuit to drive the light-emitting device.

[0372] In an exemplary embodiment, the first power supply line 51 and the data signal line 52 may be designed with equal width or unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0373] In the exemplary embodiment, the fifth plate 35 of the storage capacitor has the potential of the first node N1, and the sixth plate 36 of the storage capacitor has the potential of the first power line 51. Therefore, the fifth plate 35 and the sixth plate 36 form a storage capacitor. In the exemplary embodiment, the size of the storage capacitor can be increased by reducing the thickness of the insulating layer between the first conductive layer and the third conductive layer, changing the dielectric constant of the insulating layer, etc.

[0374] In an exemplary embodiment, the fourth conductive layers of adjacent circuit cells in the first direction X may be substantially mirror-symmetrical with respect to the cell reference line.

[0375] Figure 27 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure, and Figure 28 is a cross-sectional view taken along line BB in Figure 27. The main structure of the display substrate of this embodiment is substantially the same as that of the display substrates shown in Figures 18 and 19, except that the display substrate of this embodiment does not have a shielding metal layer.

[0376] As shown in Figures 27 and 28, in an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include: a first insulating layer 110 arranged on a substrate 101, a semiconductor layer arranged on a side of the first insulating layer 110 away from the substrate 101, a second insulating layer 120 arranged on a side of the semiconductor layer away from the substrate 101, a first conductive layer (GATE1) arranged on a side of the second insulating layer 120 away from the substrate 101, a third insulating layer 130 arranged on a side of the first conductive layer away from the substrate 101, a third conductive layer (SD1) arranged on a side of the third insulating layer 130 away from the substrate 101, a fourth insulating layer 140 arranged on a side of the third conductive layer away from the substrate 101, and a fourth conductive layer (SD2) arranged on a side of the fourth insulating layer 140 away from the substrate 101.

[0377] In an exemplary embodiment, the semiconductor layer may include at least a third active layer 13, and the first conductive layer may include at least a fifth electrode plate 35. The third conductive layer may include at least a sixth electrode plate 36 and a second connecting electrode 42, wherein the orthographic projection of the sixth electrode plate 36 on the substrate at least partially overlaps with the orthographic projection of the fifth electrode plate 35 on the substrate, and the second connecting electrode 42 is connected to the fifth electrode plate 35 through a via. The fourth conductive layer may include at least a first power line 51, which is connected to the sixth electrode plate 36 through a via.

[0378] In an exemplary embodiment, the first conductive layer may further include a first initial connection line 73, a second initial connection line 74 and gate electrodes of multiple transistors, the third conductive layer may further include a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a light-emitting signal line 68, a first initial signal line 71, a second initial signal line 72 and multiple connection electrodes, and the fourth conductive layer may further include a data signal line 52.

[0379] In an exemplary embodiment, the preparation process of the substrate in this embodiment is substantially the same as that in the previous embodiment, except that the operation of forming the shielding metal layer is omitted.

[0380] A display substrate adopts a dual-GATE dual-SD structure, including a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer arranged in sequence on a substrate. It usually requires 12 to 14 patterning (masking) processes. Not only is the process time long and the production cost high, but the intermediate film layer is complex and the finished product yield is low.

[0381] An exemplary embodiment of the present disclosure provides a display substrate that adopts a single-GATE dual-SD structure, including a semiconductor layer, a first gate metal layer, a first source-drain metal layer, and a second source-drain metal layer sequentially arranged on a substrate. By reducing the second gate metal layer, not only the number of patterning processes is effectively reduced, the process time is shortened, the production capacity is improved, and the production cost is reduced, but also the intermediate film layer is simplified, the layout space is optimized, and the yield of the finished product is effectively improved.

[0382] The present disclosure shows that a substrate uses a first gate metal layer and a first source / drain metal layer to form the plates of a storage capacitor. Compared to existing structures that use a first gate metal layer and a second gate metal layer to form the capacitor plates, the present disclosure not only reduces the patterning process of the second gate metal layer, but also reduces the number of connecting vias and connecting electrodes, reducing process complexity, improving process quality, and reducing the area occupied by the connecting vias and connecting electrodes, which is conducive to improving resolution.

[0383] The disclosed display substrate uses a first source / drain metal layer to form scanning signal lines and light-emitting signal lines. Compared to existing structures that use a second gate metal layer (typically Mo) to form signal lines, the thicker first source / drain metal layer, typically made of low-resistance Al, effectively reduces the resistance of the signal lines (by approximately 80%). This reduces the resistance-capacitance (RC) loading of the signal lines by an order of magnitude, increasing charging time and facilitating high-frequency pixel driving. It also helps reduce crosstalk between pixels.

[0384] The disclosed display substrate adopts a structure with a separation of semiconductor layer and routing layer, which can reduce the crosstalk of signal lines to the active layer in the transistor and reduce parasitic capacitance. Due to the large spacing between the first source and drain metal layer and other metal film layers, the optimization of the parasitic capacitance of signal lines and nodes is significantly improved. The parasitic capacitance of the signal line can be reduced by about 50% on average, and the RC delay can be reduced by an order of magnitude. The parasitic capacitance between the data signal and the first node N1 is an important parameter for generating crosstalk. The disclosed display substrate can effectively reduce this parasitic capacitance and optimize the performance indicators of crosstalk, which is beneficial to high frequency and reduces crosstalk to pixels.

[0385] The display substrate disclosed herein utilizes a 7T1C pixel drive circuit structure with a modular design. Multiple switching transistors are controlled by independent scanning signal lines, allowing for easy matching of gate drive circuits and flexible timing adjustment, facilitating expansion to compatible LTPO pixel circuit designs. For example, the second transistor T2 can be replaced with an oxide transistor.

[0386] The present disclosure adopts a display substrate having a 9T2C pixel driving circuit structure. By providing a first reference signal line extending along a first direction X in a main portion and a first reference connecting line extending along a second direction Y in a main portion, and interconnecting the first reference signal line and the first reference connecting line, a meshed network connection structure for transmitting a first reference signal is formed on the display substrate. This effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, and also effectively improves the uniformity of the first reference signal in the display substrate, thereby effectively improving display uniformity and enhancing display quality.

[0387] The present disclosure adopts a display substrate having a 7T1C pixel driving circuit structure. By providing a first initial signal line extending along a first direction X in the main portion and a first initial connecting line 73 extending along a second direction Y in the main portion, and interconnecting the first initial signal line and the first initial connecting line, a meshed network connection structure for transmitting the first initial signal is formed on the display substrate. This structure not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improves display uniformity, and improves display quality and display quality.

[0388] The present disclosure adopts a display substrate with a 7T1C pixel driving circuit structure. By providing a second initial signal line extending along a first direction X in the main portion and a second initial connecting line 73 extending along a second direction Y in the main portion, and interconnecting the second initial signal line and the second initial connecting line, a meshed network connection structure for transmitting the second initial signal is formed on the display substrate. This structure can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve display uniformity, and enhance display quality and display quality.

[0389] In the embodiment of the present disclosure, by providing the first power line to cover the first node N1 of the pixel driving circuit, other signals are effectively prevented from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0390] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0391] The structure and preparation process shown in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or reduced according to actual needs. For example, the polysilicon transistors in the display substrate can be replaced with oxide transistors, or some polysilicon transistors in the display substrate can be replaced with oxide transistors to form an LTPO display substrate. This disclosure is not limited to this.

[0392] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0393] The present disclosure also provides a method for preparing a display substrate, for preparing the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one of which includes a pixel driving circuit and a plurality of scanning signal lines connected to the pixel driving circuit, wherein the pixel driving circuit includes at least a plurality of transistors. The preparation method may include:

[0394] forming a first gate metal layer on a substrate, wherein a gate electrode of at least one transistor is disposed in the first gate metal layer;

[0395] A first source-drain metal layer is formed on the first gate metal layer. At least one scan signal line is provided on the first source-drain metal layer. The scan signal line is connected to the gate electrode through a via hole.

[0396] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0397] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and a plurality of scanning signal lines connected to the pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; in a direction perpendicular to the display substrate, the display substrate comprises at least a first gate metal layer arranged on a substrate and a first source-drain metal layer arranged on a side of the first gate metal layer away from the substrate, a gate electrode of at least one transistor is arranged in the first gate metal layer, at least one scanning signal line is arranged in the first source-drain metal layer, and the scanning signal line is connected to the gate electrode through a via.

2. The display substrate according to claim 1, wherein: The multiple transistors include at least a first transistor serving as a first initialization transistor, the first transistor including at least a first gate electrode, the first gate electrode being connected to a fourth scan signal line, and the first electrode of the first transistor being connected to the first initial signal line; the first gate electrode being arranged in the first gate metal layer, the fourth scan signal line being arranged in the first source-drain metal layer, and the fourth scan signal line being connected to the first gate electrode through a first gate via.

3. The display substrate according to claim 2, wherein: In the unit row direction, the first gate electrodes in at least two adjacent circuit units are interconnected as an integrated structure.

4. The display substrate according to claim 2, wherein: In the unit row direction, at least two adjacent circuit units share the same first gate via.

5. The display substrate according to claim 2, wherein: The shape of the first initial signal line is a straight line or a broken line extending along the unit row direction; at least one circuit unit also includes a first initial connection line, the shape of the first initial connection line is a straight line or a broken line extending along the unit column direction, and the first initial connection line is connected to the first initial signal line to form a network connection structure for transmitting the first initial signal.

6. The display substrate according to claim 5, wherein: The first initial connection line is arranged in the first gate metal layer, and the first initial signal line is arranged in the first source-drain metal layer.

7. The display substrate according to claim 2, wherein: The display substrate further includes a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate. The first initial signal line is in a straight line or a folded line extending along the unit column direction. The first initial signal line is disposed in the second source-drain metal layer.

8. The display substrate according to claim 1, wherein: The multiple transistors include at least a seventh transistor serving as a second initialization transistor, the seventh transistor including at least a seventh gate electrode, the seventh gate electrode being connected to a first scan signal line, and a first electrode of the seventh transistor being connected to a second initial signal line; the seventh gate electrode being arranged in the first gate metal layer, the first scan signal line being arranged in the first source-drain metal layer, and the first scan signal line being connected to the seventh gate electrode through a seventh gate via.

9. The display substrate according to claim 8, wherein: In the unit row direction, the seventh gate electrodes in at least two adjacent circuit units are interconnected as an integrated structure.

10. The display substrate according to claim 8, wherein: The shape of the second initial signal line is a straight line or a broken line extending along the unit row direction. At least one circuit unit also includes a second initial connection line, the shape of the second initial connection line is a straight line or a broken line extending along the unit column direction. The second initial connection line is connected to the second initial signal line to form a network connection structure for transmitting the second initial signal.

11. The display substrate according to claim 10, wherein: The second initial connection line is arranged in the first gate metal layer, and the second initial signal line is arranged in the first source-drain metal layer.

12. The display substrate according to claim 1, wherein: The multiple transistors include at least a third transistor as a driving transistor, a fifth transistor as a first light-emitting control transistor, and a sixth transistor as a second light-emitting control transistor, the fifth transistor includes at least a fifth gate electrode, the sixth transistor includes at least a sixth gate electrode, the fifth gate electrode is connected to the first light-emitting signal line, the first electrode of the fifth transistor is connected to the first power line, the second electrode of the fifth transistor is connected to the first electrode of the third transistor, the sixth gate electrode is connected to the second light-emitting signal line, and the first electrode of the sixth transistor is connected to the second electrode of the third transistor; the fifth gate electrode and the sixth gate electrode are arranged in the first gate metal layer, the first light-emitting signal line and the second light-emitting signal line are arranged in the first source-drain metal layer, the first light-emitting signal line is connected to the fifth gate electrode through a via, and the second light-emitting signal line is connected to the sixth gate electrode through a via.

13. The display substrate according to claim 1, wherein: The multiple transistors include at least a third transistor as a driving transistor, a fifth transistor as a first light-emitting control transistor, and a sixth transistor as a second light-emitting control transistor, the fifth transistor includes at least a fifth gate electrode, the sixth transistor includes at least a sixth gate electrode, the fifth gate electrode is connected to a light-emitting signal line, a first electrode of the fifth transistor is connected to a first power line, a second electrode of the fifth transistor is connected to a first electrode of the third transistor, the sixth gate electrode is connected to a light-emitting signal line, and a first electrode of the sixth transistor is connected to a second electrode of the third transistor; the fifth gate electrode and the sixth gate electrode are arranged in the first gate metal layer, the light-emitting signal line is arranged in the first source-drain metal layer, and the light-emitting signal line is connected to the fifth gate electrode and the sixth gate electrode through the same via.

14. The display substrate according to claim 13, wherein: In at least one circuit unit, the fifth gate electrode and the sixth gate electrode are an integrated structure connected to each other.

15. The display substrate according to claim 13, wherein: In the unit row direction, the sixth gate electrodes in at least two adjacent circuit units are interconnected as an integrated structure.

16. The display substrate according to any one of claims 1 to 15, wherein: The pixel driving circuit also includes a first capacitor and a second capacitor, the first capacitor includes at least a first electrode plate and a third electrode plate, the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate, the second capacitor includes at least a second electrode plate and a fourth electrode plate, the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate; the first electrode plate and the second electrode plate are arranged in the first gate metal layer, the third electrode plate and the fourth electrode plate are arranged in the first source and drain metal layer, and are an integrated structure connected to each other.

17. The display substrate according to any one of claims 1 to 15, wherein: The pixel driving circuit also includes a storage capacitor, which includes at least a fifth electrode plate and a sixth electrode plate, and the orthographic projection of the fifth electrode plate on the substrate at least partially overlaps with the orthographic projection of the sixth electrode plate on the substrate; the fifth electrode plate is arranged in the first gate metal layer, and the sixth electrode plate is arranged in the first source and drain metal layer.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. A method for preparing a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and a plurality of scanning signal lines connected to the pixel driving circuit, the pixel driving circuit comprising at least a plurality of transistors; the method comprising: forming a first gate metal layer on the substrate, wherein a gate electrode of at least one transistor is disposed in the first gate metal layer; A first source-drain metal layer is formed on the first gate metal layer, at least one scan signal line is arranged on the first source-drain metal layer, and the scan signal line is connected to the gate electrode through a via hole.

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