A low-orbit satellite digital logic anomaly inspection method and navigation baseband chip

Abstract

The application discloses a low-orbit satellite-borne digital logic abnormality inspection method and a navigation baseband chip. The method comprises the following steps: setting corresponding check data sets and configuration items for each digital logic unit; setting a timing duration to periodically inspect each digital logic unit in the chip; judging whether the current inspected digital logic unit is idle; if the digital logic unit is idle, the next step is executed; otherwise, the next digital logic unit is switched to continue the inspection; obtaining the check data set and the configuration item corresponding to the current digital logic unit; configuring according to the configuration item, sending standard data into the digital logic unit to start, and obtaining feature data; judging whether the feature data is consistent with expected data; if the feature data is consistent with the expected data, the digital logic unit is determined to be normal; if the feature data is not consistent with the expected data, the digital logic unit is determined to be abnormal; and repairing and reconfiguring the digital logic unit determined to be abnormal. The application can realize independent detection and abnormality repair of each digital logic unit, and is more targeted.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, in particular to a low-orbit satellite digital logic anomaly inspection method and a navigation baseband chip. BACKGROUND

[0002] Low-orbit satellites have been widely concerned and applied in recent years due to their low orbit height, strong signal power, and low construction cost. The coverage of a single low-orbit satellite is much smaller than that of a high-orbit satellite because of the rapid change of the constellation configuration. A low-orbit constellation is often composed of hundreds or even thousands of satellites. How to quickly and efficiently complete orbit determination has become one of the research hotspots. A low-orbit satellite carrying a Beidou navigation receiver will have more abundant satellite orbit determination means. However, the Beidou navigation receiver or core baseband chip needs to have the ability to work normally in low-orbit space and needs to cope with space radiation, single event upset effects, etc. At the same time, in the navigation field itself, the trend of using low-orbit satellites to broadcast navigation enhancement signals or integrated navigation signals is becoming more and more obvious. In the future, the low-orbit satellite payload in the integrated navigation field will have the ability of on-board Beidou navigation and the ability of receiving and transmitting enhanced integrated navigation signals. Considering that the digital circuits, storage units, etc. in the on-board payload are all affected by radiation and single event upset, higher requirements are put forward for the stability of the baseband performance of the on-board Beidou navigation and integrated navigation processing. We need to improve the space radiation resistance of the core digital baseband of the navigation receiver baseband and the integrated navigation processing baseband, as well as the identification ability when a single event upset occurs. Therefore, it is particularly important to propose a specific anomaly detection method for single event upset and logic anomaly in the on-board digital chip of a low-orbit satellite. SUMMARY

[0003] To solve the above technical problems, the embodiment of the present application provides a low-orbit satellite digital logic anomaly inspection method and a navigation baseband chip.

[0004] The technical scheme of the embodiment of the present application is implemented as follows:

[0005] The embodiment of the present application provides a low-orbit satellite digital logic anomaly inspection method, which comprises the following steps:

[0006] Step S1: setting a corresponding verification data set and a configuration item for each digital logic unit in the chip; the verification data set comprises standard data and expected data; the standard data is used to test whether the corresponding digital logic unit can work normally; the expected data is an output result obtained by processing the standard data when the digital logic unit works normally; and the configuration item is a configuration content required when the digital logic unit works normally;

[0007] Step S2: set a time duration, and perform a timing inspection on each digital logic unit in the chip; determine whether the current inspected digital logic unit is idle, if yes, continue to step S3, otherwise, switch to the next digital logic unit to continue the inspection;

[0008] Step S3: obtain the verification data set and the configuration item corresponding to the current inspected digital logic unit; configure the digital logic unit according to the configuration item, and send the standard data in the verification data set into the digital logic unit to start, and obtain the feature data output by the digital logic unit;

[0009] Step S4: determine whether the feature data is consistent with the expected data, if yes, determine that the digital logic unit is working normally; if not, determine that the digital logic unit has an abnormality;

[0010] Step S5: repair and reconfigure the digital logic unit determined to have an abnormality.

[0011] In an embodiment, the digital logic units in the chip include a capture engine, a tracking engine, a TURBO channel decoder, and a VITERBI channel decoder.

[0012] In an embodiment, the configuration item of the capture engine is coherent integration 1 ms, non-coherent 1 time, frequency window 3, center frequency 0 Hz, code rate fc consistent with the frequency point of the verification data; the standard data of the capture engine is 2 ms of Beidou B1I frequency IF data; and the expected data of the capture engine is the peak amplitude, phase and frequency results calculated by the capture engine working normally.

[0013] The configuration item of the tracking engine is coherent integration 1 ms, center frequency 0 Hz, code rate fc consistent with the frequency point of the verification data, and code start phase 0; the standard data of the tracking engine is 2 ms of Beidou B1I frequency IF data; and the expected data of the tracking engine is the IQ coherent integration results calculated by each correlator of the tracking engine working normally.

[0014] The configuration item of the TURBO channel decoder is to configure a TURBO decoder with a start-to-decode data length of L, and the iteration number is 3 times; the standard data of the TURBO channel decoder is soft information data with a length of L; and the expected data of the TURBO channel decoder is the correct decoding result bit information.

[0015] The configuration item of the VITERBI channel decoder is to configure the start of VITERBI decoding and truncation mode with the length of the data to be decoded being M; the standard data of the VITERBI channel decoder is the soft information data to be decoded with a length of M; the expected data of the VITERBI channel decoder is the correct decoding result bit information.

[0016] In one embodiment, determining whether the currently inspected digital logic unit is idle includes:

[0017] For the capture engine, if the logic module of the capture engine is currently performing normal capture processing or inspection and verification processing, the capture engine is determined to be in a busy state; if the logic module of the capture engine is currently not performing any processing, the capture engine is determined to be in an idle state;

[0018] For the tracking engine, if the logic module of the tracking engine is currently performing normal tracking processing or inspection and verification processing, the tracking engine is determined to be in a busy state; if the logic module of the tracking engine is currently not performing any processing, the tracking engine is determined to be in an idle state;

[0019] For a TURBO channel decoder, if the logic module of the TURBO channel decoder is currently performing normal decoding calculations or inspection and verification calculations, the TURBO channel decoder is determined to be in a busy state; if the logic module of the TURBO channel decoder is currently not performing any processing, the TURBO channel decoder is determined to be in an idle state;

[0020] For the VITERBI channel decoder, if the logic module of the VITERBI channel decoder is currently performing normal decoding calculations or patrol verification calculations, the VITERBI channel decoder is determined to be in a busy state; if the logic module of the VITERBI channel decoder is currently not performing any processing, the VITERBI channel decoder is determined to be in an idle state.

[0021] In one embodiment, repairing and reconfiguring a digital logic unit determined to have an abnormality includes:

[0022] If the abnormal digital logic unit is a capture engine, all logic modules of the capture engine are globally reset, registers are reconfigured, and data RAM is overwritten and written to zero;

[0023] If the abnormal digital logic unit is a trace engine, a local reset and register reconfiguration are performed on the abnormal sub-trace channel in the trace engine logic module;

[0024] If the abnormal digital logic unit is a TURBO channel decoder, the TURBO channel decoder is globally reset, register reconfigured, and turbo interleaving table reconfigured.

[0025] If the abnormal digital logic unit is a VITERBI channel decoder, the VITERBI channel decoder is globally reset and register reconfigured.

[0026] In an embodiment, before repairing and reconfiguring the digital logic unit determined to be abnormal, the method further comprises:

[0027] If the abnormal digital logic unit is a capture engine, the capture engine is abnormality inspected, and the abnormality of the capture engine is determined again.

[0028] If the abnormal digital logic unit is a tracking engine, the tracking engine is abnormality inspected and partial triple modular redundancy detected, and the abnormality of the tracking engine is determined again.

[0029] If the abnormal digital logic unit is a TURBO channel decoder, the TURBO channel decoder is abnormality inspected, and the abnormality of the TURBO channel decoder is determined again.

[0030] If the abnormal digital logic unit is a VITERBI channel decoder, the VITERBI channel decoder is abnormality inspected, and the abnormality of the VITERBI channel decoder is determined again.

[0031] In an embodiment, the timing duration is set to 100 ms.

[0032] The embodiment of the present application also provides a navigation baseband chip, comprising: a processor and a memory for storing a computer program capable of running on the processor; wherein the processor is used to run the computer program, and the steps of the above method are executed.

[0033] The embodiment has the following beneficial effects:

[0034] The embodiment utilizes the advantages of ASIC special chip area and computing power, and provides a low-cost, low-false-alarm digital baseband chip single event upset abnormality monitoring method, according to the characteristics of the detected unit, customizes the verification data set and configuration item, and only needs to repair the problematic unit during abnormality processing, so that the method is more targeted, reduces the influence range of abnormal points, and is more efficient. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 FIG. 1 is a flowchart of a low-orbit satellite digital logic abnormality inspection method according to an embodiment of the present application.

[0036] Figure 2A schematic diagram of an abnormal inspection process of a TURBO channel decoder according to an embodiment of the present application is shown in the figure;

[0037] Figure 3 An internal structure diagram of a computer device according to an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0038] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0039] An abnormal inspection method for low-orbit satellite digital logic according to an embodiment of the present application is provided, as shown in the figure, which comprises the following steps. Figure 1

[0040] Step S1: For each digital logic unit in a chip, a corresponding verification data set and configuration item are set; the verification data set comprises standard data and expected data; the standard data is used to test whether the corresponding digital logic unit can work normally; the expected data is an output result obtained by processing the standard data when the digital logic unit works normally; the configuration item is a configuration content required when the digital logic unit works normally;

[0041] Step S2: A timing duration is set, and each digital logic unit in the chip is inspected in a timing manner; it is judged whether the digital logic unit currently inspected is idle, if yes, step S3 is executed, otherwise, the next digital logic unit is switched to continue the inspection;

[0042] Step S3: The verification data set and configuration item corresponding to the digital logic unit currently inspected are obtained; the digital logic unit is configured according to the configuration item, and the standard data in the verification data set is sent into the digital logic unit to start, and the feature data output by the digital logic unit is obtained;

[0043] Step S4: It is judged whether the feature data is consistent with the expected data, if yes, it is determined that the digital logic unit works normally, if not, it is determined that the digital logic unit has an abnormality;

[0044] Step S5: The digital logic unit determined to have an abnormality is repaired and reconfigured.

[0045] ​The embodiment is directed to a specific anomaly detection method for single event upset, logic anomaly and other problems in low-orbit satellite on-board digital chips, and a Beidou navigation baseband chip is designed based on the method. Unlike the single event upset detection method based on traditional FPGA, the embodiment is based on ASIC, and the area and frequency advantages of ASIC are used to customize the anomaly detection measures for each special digital logic unit, subsystem or accelerator module in the chip, which has the characteristics of strong pertinence, easy implementation and extremely low false alarm rate.

[0046] Specifically, in step S1, the verification data set and configuration item of the digital logic unit in the customized chip are checked. The digital logic unit here refers to a logic module, logic subsystem, special operation accelerator, etc. that can complete specific functions such as control and calculation. Such digital logic units include (but are not limited to) registers, RAM, hard-wired logic, state machines, etc. In actual application, the digital logic unit can include a capture engine, a tracking engine, a TURBO channel decoder and a VITERBI channel decoder.

[0047] The verification data set here refers to standard input data used to test whether the digital logic unit is working normally, and expected result output data that should be obtained after the digital logic unit processes the standard input data. The configuration item here refers to the configuration content required for the digital logic unit to meet the current job function or normal work, including but not limited to working mode, algorithm implementation parameter, input configuration, output configuration, etc.

[0048] The verification data set and the configuration item can be stored in a storage unit with better process technology such as ECC data verification and anti-radiation performance, and are subjected to triple modular redundancy reinforcement, such as a flash unit.

[0049] The following is a list of verification data sets and configuration items for core digital logic units such as capture engines (AE), tracking engines (TE), TURBO channel decoders and VITERBI channel decoders in navigation baseband chips:

[0050] Table 1

[0051]

[0052] In step S2, the on-board baseband chip creates a timing inspection task, which is performed once every timing period, thereby cyclically traversing all chip digital logic units that need to be verified; the default value (reset value) of the timing period is fixed by hard-wired in the chip.

[0053] In the timing inspection, it is judged whether the chip digital logic unit X currently inspected is idle or not, i.e. whether it is in operation, if idle, then the chip digital logic unit is detected, if busy, the next chip digital logic unit Y is switched to continue the query;

[0054] Here, the idle and busy flags of the chip digital logic unit can be set, which are generated by the target chip digital logic unit of the inspection. If the target chip digital logic unit of the current inspection is working, the busy flag is valid and the idle flag is invalid; otherwise, if the target chip digital logic unit of the current inspection is not working, the idle flag is valid and the busy flag is invalid; the busy flag and the idle flag.

[0055] The preferred generation conditions in the typical core digital logic units such as the capture engine (AE), the tracking engine (TE), the TURBO channel decoder and the VITERBI channel decoder in the navigation baseband chip are shown in the following table:

[0056] Table 2

[0057]

[0058] In step S3, the space-based baseband chip selects the verification data set suitable for X from the verification data set customized in S1, extracts the standard data S_X and the expected data R_X corresponding to the processing result, wherein R_X is the expected generation result after S_X is input into the logic unit X; the verification data set and the configuration item are fixed by hard line in the chip, and the data content is customized and generated according to the functional characteristics of the logic unit X in the chip design stage.

[0059] The space-based baseband chip inputs the standard data S_X into the logic unit X and starts, and the logic unit X obtains the characteristic output result (characteristic data) after processing the data. In the design of the chip digital logic unit, a circuit for generating the characteristic data is added.

[0060] In step S4, after the characteristic data of the logic unit X is obtained, it is input into the expected judge for verification, to judge whether the actual generated characteristic data is consistent with the expected data R_X, if consistent, it can be considered that the detection result of the logic unit under the detection method of the application is normal. This can significantly improve the confidence of the system to the logic unit, and on the system level, combined with the classical three-mode redundancy and logic unit redundancy detection in the industry, the confidence can be further improved.

[0061] If the characteristic data is not consistent with the expected data, it is determined that an abnormality occurs in the logic unit X currently inspected; if the characteristic data is not consistent with the expected data, it can be determined that an abnormality occurs in the logic unit X or its surrounding logic, and the system needs to repair the logic unit.

[0062] In step S5, the abnormal logic unit module is soft-repaired and reconfigured. In the navigation baseband chip, the core digital logic units such as the acquisition engine (AE), tracking engine (TE), TURBO channel decoder and VITERBI channel decoder are typically found to have abnormalities during inspection. The preferred monitoring mechanism and repair method are shown in the following table:

[0063] Table 3

[0064]

[0065] The method of this embodiment can perform abnormal inspections on core digital logic units such as the acquisition engine (AE), tracking engine (TE), TURBO channel decoder and VITERBI channel decoder in a cyclic manner through regular inspection tasks, and repair the erroneous modules in a timely manner after an abnormality occurs, thereby effectively improving the stability and radiation resistance of the navigation baseband chip.

[0066] See also Figure 2 , the present solution will be described below with a specific embodiment.

[0067] S101: Develop a data checksum for all key digital logic units within the low-orbit satellite-borne baseband chip. For example, for the TURBO channel decoder, i.e., the turbo(192,60) decoder, a set of 4-bit random noise soft information with a length of 192 can be designed as standard data. The configuration items are set to 1 / 3 code rate, blocksize 60, iterations 3, and soft information 4 bits. The standard data and configuration items are passed to the turbo(192,60) decoder, and the number of decoder iterations is configured to the default value of 8. The soft information output and judgment result of the last SISO iteration after decoder processing are obtained as the expected data. The standard data, configuration items, and expected data constitute the data checksum.

[0068] S201: The onboard baseband chip creates a scheduled inspection task, performs an inspection every 100ms, and judges and processes the currently inspected logic unit. The triggering every 100ms is implemented by hard-wiring in the chip.

[0069] S301: If the currently inspected turbo (192, 60) decoder is idle, continue to execute the next step; otherwise, switch to the next logic unit to continue querying; the query of the turbo decoder status requires adding a circuit for generating idle and busy flags when designing the chip digital logic unit;

[0070] S401: The spaceborne baseband chip selects a check data set and configuration item of a turbo (192,60) decoder from the data check set customized in step S1, that is, 1 / 3 code rate, block size 60, iteration 3 times, and 4-bit soft information are taken as the input configuration of the turbo (192,60) decoder, 4-bit random noise soft information with a length of 192 is taken as standard data S_X, and expected data after normal decoding of the data set is taken as R_X; wherein the standard data and the configuration item need to be fixed by hard line in the chip;

[0071] S501: The spaceborne baseband chip transmits 4-bit random noise soft information with a length of 192 into the turbo (192,60) decoder, and the decoder obtains real-time feature output results (feature data) after processing the data; wherein the turbo decoder needs to increase a circuit for generating feature data when designed;

[0072] S601: The expected judge checks the expected data R_X obtained in step S4 and the feature data generated in real time in step S5, and if the data is consistent, it is initially considered that the turbo (192,60) decoder is working normally at this time, and if necessary, the classic abnormal inspection method in the industry can be combined to further judge the single event upset of the current inspection logic unit X;

[0073] S701: If the feature data is inconsistent with the expected data, it is determined that an abnormality has occurred in the turbo (192,60) decoder, such as a single event upset in the data of the storage unit;

[0074] S801: The turbo (192,60) decoder with an abnormality is repaired and reset, for example, the decoder is reset and the configuration parameters of the decoder are reinitialized.

[0075] The embodiment method has the following beneficial effects:

[0076] 1. A low-cost, low-false-alarm digital baseband chip single event upset abnormality monitoring method is provided by using the advantages of ASIC special chip area and computing power;

[0077] 2. A method of independent detection according to a chip digital logic unit (including a subsystem or an accelerator, etc.) is provided, the verification data set and the configuration item are customized according to the characteristics of the detected unit, and only the problematic unit needs to be repaired when the abnormality is handled, which is more targeted, reduces the influence range of the abnormal point, and is more efficient.

[0078] To implement the method of the embodiments of the present application, the embodiments of the present application further provide a navigation baseband chip, which comprises a processor and a memory for storing a computer program capable of running on the processor; wherein the processor is configured to run the computer program, and execute the steps of the method.

[0079] The navigation baseband chip and the method provided by the embodiments of the present application belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be described here.

[0080] Based on the hardware implementation of the program module, and to implement the method of the embodiments of the present application, the embodiments of the present application further provide an electronic device (computer device). Specifically, in one embodiment, the computer device can be a terminal, and its internal structure diagram can be as shown in Figure 3 The computer device comprises a processor A01, a network interface A02, a display screen A04, an input device A05 and a memory (not shown in the figure) connected through a system bus. Among them, the processor A01 of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the running of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is configured to communicate with external terminals through network connection. The computer program is executed by the processor A01 to implement the method of any one of the above embodiments. The display screen A04 of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device A05 of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0081] Those skilled in the art can understand that Figure 3 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. Specifically, the computer device can comprise more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0082] The device provided by the embodiments of the present application comprises a processor, a memory and a program stored in the memory and capable of running on the processor. The processor executes the program to implement the method of any one of the above embodiments.

[0083] Those skilled in the art will appreciate that embodiments of the application can be readily used as software, hardware, or a combination of software and hardware. In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0084] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0085] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0086] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0087] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0088] The memory can include non-persistent memory and / or persistent memory, such as flash memory, read-only memory (ROM), and / or volatile or non-volatile random access memory (RAM), among others. The memory is an example of computer-readable media.

[0089] Computer-readable media includes permanent and non-permanent, movable and non-movable media that can be implemented by any method or technology for storage of information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassette, magnetic tape disk storage, or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to computing devices. According to the definition herein, computer-readable media does not include transitory media, such as modulated data signals and carriers.

[0090] It can be understood that the memory of the embodiments of the present application can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a ferromagnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM can be used, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), sync link dynamic random access memory (SLDRAM), direct rambus random access memory (DRRAM).The memory described in the embodiments of the present application is intended to include, but not be limited to, the memory of these and any other suitable type of memory.

[0091] It should also be noted that the terms "comprising", "comprises", "including", "includes" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0092] The above only describes the embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A method for low earth orbit satellite-borne digital logic anomaly patrol, characterized in that, The method comprises: Step S1: for each digital logic unit in the chip, set a corresponding verification data set and a configuration item; the verification data set comprises standard data and expected data; the standard data is used to test whether the corresponding digital logic unit can work normally; the expected data is the output result obtained after the standard data is processed when the digital logic unit works normally; the configuration item is the configuration content required when the digital logic unit works normally; Step S2: set a timing duration, and periodically inspect each digital logic unit in the chip; determine whether the current inspected digital logic unit is idle, if yes, continue to execute step S3, otherwise, switch to the next digital logic unit to continue the inspection; Step S3: obtain the verification data set and the configuration item corresponding to the current inspected digital logic unit; configure the digital logic unit according to the configuration item, and input the standard data in the verification data set into the digital logic unit to start, and obtain the feature data output by the digital logic unit; Step S4: determine whether the feature data is consistent with the expected data, if yes, determine that the digital logic unit works normally; if not, determine that the digital logic unit has an abnormality; Step S5: repair and reconfigure the digital logic unit determined to have an abnormality; The digital logic unit in the chip comprises a capture engine, a tracking engine, a TURBO channel decoder and a VITERBI channel decoder; The repair and reconfiguration of the digital logic unit determined to have an abnormality comprises: if the abnormal digital logic unit is the capture engine, globally reset all logic modules of the capture engine, reconfigure the registers, and perform data RAM overwrite write to clear; if the abnormal digital logic unit is the tracking engine, locally reset the abnormal sub-tracking channel in the tracking engine logic module, and reconfigure the registers; if the abnormal digital logic unit is the TURBO channel decoder, globally reset the TURBO channel decoder, reconfigure the registers, and reconfigure the turbo interleaving table; if the abnormal digital logic unit is the VITERBI channel decoder, globally reset the VITERBI channel decoder, and reconfigure the registers.

2. The method of claim 1, wherein, The configuration item of the capture engine is coherent integration 1ms, non-coherent 1 time, frequency window 3, center frequency 0Hz, code rate fc consistent with the frequency point of the verification data; the standard data of the capture engine is 2ms of Beidou B1I frequency data; the expected data of the capture engine is the peak amplitude, phase and frequency result calculated by the capture engine when it works normally; The configuration item of the tracking engine is coherent integration 1ms, center frequency 0Hz, code rate fc consistent with the frequency point of the verification data, and code start phase 0; the standard data of the tracking engine is 2ms of Beidou B1I frequency data; the expected data of the tracking engine is the coherent integration result of each correlator calculation IQ path calculated by the tracking engine when it works normally. The configuration item of the TURBO channel decoder is to configure to start TURBO decoding of data with a length of L, and the iteration number is 3; the standard data of the TURBO channel decoder is soft information data with a length of L to be decoded; and the expected data of the TURBO channel decoder is the correct decoding result bit information. The configuration item of the VITERBI channel decoder is to configure to start VITERBI decoding of data with a length of M, and the truncation mode; the standard data of the VITERBI channel decoder is soft information data with a length of M to be decoded; and the expected data of the VITERBI channel decoder is the correct decoding result bit information.

3. The method of claim 2, wherein, The method further comprises the following steps before repairing and reconfiguring the digital logic unit determined to have an abnormality: If the abnormal digital logic unit is a capture engine, the capture engine is subjected to abnormality inspection, and the abnormality of the capture engine is determined again; If the abnormal digital logic unit is a tracking engine, the tracking engine is subjected to abnormality inspection and partial three-module redundancy detection, and the abnormality of the tracking engine is determined again; If the abnormal digital logic unit is a TURBO channel decoder, the TURBO channel decoder is subjected to abnormality inspection, and the abnormality of the TURBO channel decoder is determined again; If the abnormal digital logic unit is a VITERBI channel decoder, the VITERBI channel decoder is subjected to abnormality inspection, and the abnormality of the VITERBI channel decoder is determined again.

4. The method of claim 1, wherein, The timing duration is set to 100 ms. The method further comprises the following steps before repairing and reconfiguring the digital logic unit determined to have an abnormality: ​ ​ ​ 5. The method of claim 1, wherein, ​ 6. A navigation baseband chip, characterized by, ​ a processor and a memory for storing a computer program capable of running on the processor; wherein the processor is configured to execute the steps of the method according to any one of claims 1 to 5 when running the computer program.

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