Display device, control method of display device

Abstract

The application provides a display device and a control method of the display device. The display device comprises a display panel and a driving circuit. The display panel comprises a plurality of pixel rows, a plurality of data line groups and a plurality of scan line groups. A first data line in each data line group is electrically connected with a column of first sub-pixels and is arranged close to the corresponding column of first sub-pixels. A second data line in each data line group is electrically connected with a column of second sub-pixels through a switch module. The driving circuit is electrically connected with the plurality of scan line groups and the first data line in the plurality of data line groups. The driving circuit is used for controlling the switch module to be turned off at a first time point in a blanking period of a current frame and increasing a data voltage provided to the data line group at a second time point in the blanking period of the current frame. The first time point is earlier than or equal to the second time point. The display device can improve the vertical stripe problem of the display panel with the existing U-type pixel architecture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and a control method of the display device. BACKGROUND

[0002] At present, in order to reduce the cost of display, the display technical field has developed a U-Type pixel architecture. The U-Type pixel architecture controls a row of pixels by two rows of scanning lines, so that the number of data lines is halved and the number of scanning lines is doubled, and the increased scanning lines can be realized by a gate less mechanism to design a GOA (Gate Driven on Array) circuit on the side, so that the cost of Source IC (source chip) is saved.

[0003] However, in actual application, the display panel of the U-Type pixel architecture has a vertical stripe problem. When the screen displays an image, the vertical stripe appears randomly or regularly, which destroys the integrity of the picture, interferes with the image details, makes the color transition unnatural, and seriously affects the display effect and user experience. SUMMARY

[0004] Therefore, the main purpose of the present application is to provide a display device and a control method of the display device, which aims to solve the vertical stripe problem of the display panel of the existing U-Type pixel architecture.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a display device, which includes a display panel and a driving circuit; the display panel includes a plurality of pixel rows, a plurality of data line groups and a plurality of scan line groups. The plurality of pixel rows are arranged along the column direction, and each of the pixel rows includes a plurality of sub-pixels arranged along the row direction, and the plurality of sub-pixels include a first sub-pixel and a second sub-pixel; each of the data line groups includes a first data line, a second data line and a switch module; wherein the first data line in each of the data line groups is electrically connected to a column of the first sub-pixels and is arranged close to the first sub-pixels in the corresponding column; the second data line in each of the data line groups is electrically connected to the first data line through the switch module, and is electrically connected to a column of the second sub-pixels; each of the scan line groups includes a first scan line and a second scan line, and the first scan line and the second scan line in each of the scan line groups are arranged at intervals on one side of the corresponding pixel row, and The first scan line in each of the scan line groups is located between the second scan line and the corresponding pixel row, the first scan line in each of the scan line groups is electrically connected to all first sub-pixels in the corresponding pixel row, and the second scan line in each of the scan line groups is electrically connected to all second sub-pixels in the corresponding pixel row; the driving circuit is electrically connected to the multiple scan line groups and the first data line in the multiple data line groups in the display panel, respectively, and the driving circuit is used to control the switch module to turn off at a first moment in the blanking period of the current frame, and to increase the data voltage provided to the data line group at a second moment in the blanking period of the current frame; wherein the first moment is earlier than or equal to the second moment.

[0006] The display device provided in the embodiment of the present application provides a switch module between a first data line and a corresponding second data line, and controls the switch module to be turned off at a first moment in the blanking period of the current frame through a driving circuit, and increases the data voltage provided to the data line group at a second moment in the blanking period of the current frame. This allows the voltage jump generated by the pixel electrode in the first sub-pixel during the blanking period and the voltage attenuation thereof during the display period to at least partially offset, thereby reducing the difference between the voltage attenuation of the second sub-pixel and the voltage attenuation of the first sub-pixel, and further improving the vertical stripe problem of the display panel with the existing U-Type pixel architecture.

[0007] In some embodiments, the driving circuit is specifically configured to, at a second moment in a blanking period of a current frame, jump from providing a first data voltage Vdata1 to providing a second data voltage Vdata2 to the data line group; wherein the first data voltage Vdata1 is the data voltage provided to the data line group by the driving circuit at the last moment of a display period of the current frame, and the second data voltage Vdata2 is the sum of the first data voltage Vdata1 and a compensation voltage ΔV; wherein the compensation voltage ΔV is positively correlated with ΔV1-ΔV2, ΔV1 is a first voltage change of a first array common electrode in a first sub-pixel electrically connected to the data line group, the first voltage change is caused by a scan signal in a first scan line corresponding to the first array common electrode jumping from a high level to a low level, ΔV2 is a second voltage change of a second array common electrode in a second sub-pixel electrically connected to the data line group, the second voltage change is caused by a scan signal in a second scan line corresponding to the second array common electrode jumping from a high level to a low level.

[0008] In some embodiments, the driving circuit further includes a first detection circuit, a second detection circuit, and a timing controller. The first detection circuit is electrically connected to a first array common electrode in a first sub-pixel, configured to receive a first actual common voltage of the first array common electrode and output a first detection voltage based on the first actual common voltage; wherein, when a scan signal in a first scan line corresponding to the first array common electrode transitions from a high level to a low level, causing the first actual common voltage to decrease, the first detection voltage decreases accordingly; the second detection circuit is electrically connected to a second array common electrode in a second sub-pixel, configured to receive a second actual common voltage of the second array common electrode and output a second detection voltage based on the second actual common voltage; wherein, when a scan signal in a second scan line corresponding to the second array common electrode transitions from a high level to a low level, causing the second actual common voltage to decrease, the second detection voltage decreases accordingly; and the timing controller is electrically connected to both the first detection circuit and the second detection circuit, configured to obtain the first detection voltage from the first detection circuit, obtain the second detection voltage from the second detection circuit, and determine the compensation voltage ΔV based on the first detection voltage and the second detection voltage.

[0009] In some embodiments, the timing controller is used to determine the voltage value of the compensation voltage ΔV based on the difference obtained by subtracting the first minimum voltage value from the second minimum voltage value; wherein, the first minimum voltage value is the minimum value of the first detection voltage, and the second minimum voltage value is the minimum value of the second detection voltage.

[0010] In some embodiments, the first voltage variation is a difference between an initial common voltage and the first minimum voltage, and the second voltage variation is a difference between the initial common voltage and the second minimum voltage.

[0011] In some embodiments, the first detection circuit includes: a first diode, a first switching transistor, and a first capacitor. The cathode of the first diode is electrically connected to the first array common electrode in the first sub-pixel; the first switching transistor includes a first connection terminal and a second connection terminal, the first connection terminal of the first switching transistor being configured to receive an initial common voltage, and the second connection terminal of the first switching transistor being electrically connected to the anode of the first diode; the first terminal of the first capacitor being electrically connected to the anode of the first diode and the timing controller, and the second terminal of the first capacitor being grounded; wherein the first detection voltage output by the first detection circuit is the voltage at the first terminal of the first capacitor; during at least a portion of a period when a scan signal in a corresponding first scan line is at a high level, the first switching transistor is turned on to charge the first capacitor, thereby charging the first terminal of the first capacitor to the initial common voltage; and before the scan signal in the corresponding first scan line transitions from a high level to a low level, the first switching transistor is turned off, allowing the first capacitor to discharge to the first array common electrode through the first diode, thereby discharging the voltage at the first terminal of the first capacitor to the first minimum voltage.

[0012] In some embodiments, the first detection circuit further includes: a first voltage follower and a first analog-to-digital conversion circuit. The input end of the first voltage follower is electrically connected to the anode of the first diode; the first analog-to-digital conversion circuit is electrically connected between the output end of the first voltage follower and the timing controller, and is configured to receive the first detection voltage output by the first voltage follower, perform analog-to-digital conversion on the first detection voltage, and then output the first detection voltage to the timing controller.

[0013] In some embodiments, a first parasitic capacitor is formed between the first data line in each of the data line groups and the first sub-pixel in the corresponding column. At a second moment in the blanking period of the current frame, when the data voltage in the first data line in the data line group jumps, under the coupling action of the first parasitic capacitor, the first pixel electrode in the first sub-pixel corresponding to the first data line in the data line group generates a corresponding voltage jump.

[0014] In some embodiments, the driving circuit is further configured to control the switch module to be turned on at a starting time or before a starting time of a display period of a next frame after controlling the switch module to be turned off.

[0015] The second aspect of the present application also provides a control method for a display device, which is used to control the display device as described in the first aspect to perform display. The control method includes: at a first moment in the blanking period of the current frame, controlling the switch module to turn off; and at a second moment in the blanking period of the current frame, increasing the data voltage provided to the data line group; wherein the first moment is earlier than or equal to the second moment.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a display panel with a U-Type pixel architecture provided in an embodiment of the present application;

[0018] Figure 2 for Figure 1 Schematic diagram of part of the wiring of the first pixel row in ;

[0019] Figure 3 for Figure 1 Schematic diagram of a partial pixel circuit of the first pixel row in FIG;

[0020] Figure 4 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0021] Figure 5 for Figure 4 Schematic diagram of part of the wiring of the first pixel row in ;

[0022] Figure 6 for Figure 4 Schematic diagram of a partial pixel circuit of the first pixel row in FIG;

[0023] Figure 7 for Figure 4 A timing diagram of driving signals of the display device shown;

[0024] Figure 8 A schematic diagram of the circuit structure of a driving circuit provided in an embodiment of the present application;

[0025] Figure 9 Voltage waveform diagrams of the first actual common voltage and the second actual common voltage provided in the embodiment of the present application;

[0026] Figure 10 A timing diagram of the first control signal and the first detection voltage provided in an embodiment of the present application;

[0027] Figure 11 This is a flowchart of a method for controlling a display device provided in an embodiment of the present application.

[0028] The following are the descriptions of the reference numerals:

[0029] 100 - display device; 10 - display panel; 10' - display panel; 20 - driving circuit; 101 - pixel row; 11 - data line group; 12 - scan line group; P1 - first subpixel; P2 - second subpixel; 111 - first data line; 112 - second data line; 121 - first scan line; 122 - second scan line; TFT1 - first scan transistor; ACOM1 - first array common electrode; S - source; D - drain; G - gate; Cgs1 - second parasitic capacitor; Cgs2 - third parasitic capacitor; CFCOM - color film common electrode; Clc1 - first liquid crystal capacitor; Clc2 - second liquid crystal capacitor; Cst1 - first storage capacitor; Cst2 - second storage capacitor; Cp1 - fourth parasitic capacitor; Cp2 - fifth parasitic capacitor; TFT2 - second scan transistor; ACOM2 - second array common electrode; T1 - switch module; Cpd - first parasitic capacitor; 23 - timing Controller; 24-gate driver; 25-source driver; CLK-first clock signal; Gn-nth row scan signal; G2-2nd row scan signal; G1-1st row scan signal; Dm-data voltage; ΔV-compensation voltage; V_FB1-first actual common voltage; V_FB2-second actual common voltage; V1-first detection voltage; V10-first minimum voltage value; V20-second minimum voltage value; 21-first detection circuit; 22-second detection circuit; D1-first diode; Q1-first switch tube; C1-first capacitor; ADC1-first analog-to-digital conversion circuit; U1-first voltage follower; D2-second diode; Q2-second switch tube; C2-second capacitor; U2-second voltage follower; ADC2-second analog-to-digital conversion circuit; Ctrl1-first control signal; Ctrl2-second control signal; VACOM-initial common voltage; ACOM-common voltage source.

[0030] The following specific implementation methods will further illustrate this application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] In addition, the terms "first", "second", etc. in the description of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] It should be noted that, in the absence of conflict, the features in the embodiments of this application can be combined with each other.

[0034] See also Figure 1 , Figure 1 A schematic diagram of a display panel with a U-Type pixel architecture provided in an embodiment of the present application.

[0035] like Figure 1 As shown, a conventional display panel 10 ′ of a U-Type pixel architecture includes a plurality of pixel rows 101 , a plurality of data line groups 11 and a plurality of scan line groups 12 .

[0036] The plurality of pixel rows 101 are arranged along a column direction, and each of the pixel rows 101 includes a plurality of sub-pixels arranged along a row direction, and the plurality of sub-pixels include a first sub-pixel P1 and a second sub-pixel P2. Figure 1 As shown, the sub-pixels in the 1st to 6th columns are the first sub-pixels P1, and the sub-pixels in the 7th to 12th columns are the second sub-pixels P2.

[0037] Each data line group 11 includes a first data line 111 and a second data line 112. Each first data line 111 corresponds to a column of first sub-pixels P1, and each second data line 112 corresponds to a column of second sub-pixels P2. The first data line 111 in each data line group 11 is electrically connected to a column of first sub-pixels P1 and disposed adjacent to the corresponding column of first sub-pixels P1. The second data line 112 in each data line group 11 is electrically connected to the first data line 111 in the same data line group 11, and is electrically connected to a column of second sub-pixels P2, and disposed adjacent to the corresponding column of second sub-pixels P2.

[0038] For example, Figure 1As shown, the 1st to 6th column data lines are the first data lines 111, the 7th to 12th column data lines are the second data lines 112, the 1st column data lines and the 6th column data lines constitute the first data line group 11, the 2nd column data lines and the 7th column data lines constitute the second data line group 11, and so on.

[0039] Each of the scan line groups 12 includes a first scan line 121 and a second scan line 122. Each of the scan line groups 12 corresponds to a pixel row 101. The first scan line 121 and the second scan line 122 in each of the scan line groups 12 are alternately arranged on one side of the corresponding pixel row 101, and the first scan line 121 in each of the scan line groups 12 is located between the second scan line 122 in the scan line group 12 and the corresponding pixel row 101. For example, Figure 1 As shown, the odd-numbered scan lines are the first scan lines 121, the even-numbered scan lines are the second scan lines 122, and the 1st to 2nd scan lines constitute the first scan line group 12, corresponding to the 1st pixel row 101. The 1st scan line is located below the 1st pixel row 101, the 2nd scan line is located below the 1st scan line, and so on.

[0040] It is not difficult to see that the U-Type pixel architecture controls one row of pixels through two rows of scan lines, so the number of data lines is halved and the number of scan lines is doubled. The additional scan lines can be achieved by designing the GOA circuit on the side through the gate-less mechanism, thus saving the source IC cost.

[0041] However, in actual applications, the display panel with U-Type pixel architecture has vertical stripe problem. Figure 2~Figure 3 , Figure 2 for Figure 1 Partial wiring diagram of the first pixel row in the diagram, Figure 3 for Figure 1 Schematic diagram of a portion of the pixel circuit for the first pixel row in FIG.

[0042] like Figure 2~Figure 3As shown, the first subpixel P1 includes a first scanning transistor TFT1, a first pixel electrode (not labeled in the figure), and a first array common electrode ACOM1. The source electrode S of the first scanning transistor TFT1 is electrically connected to the first pixel electrode, the drain electrode D of the first scanning transistor TFT1 is electrically connected to the corresponding first data line 111, and the gate electrode G of the first scanning transistor TFT1 is electrically connected to the corresponding first scanning line 121. A second parasitic capacitor Cgs1 is formed between the source electrode S of the first scanning transistor TFT1 and the corresponding first scanning line 121. A first liquid crystal capacitor Clc1 is formed between the source electrode S of the first scanning transistor TFT1 and the color filter common electrode CFCOM. A first storage capacitor Cst1 is formed between the source electrode S of the first scanning transistor TFT1 and the first array common electrode ACOM1. A fourth parasitic capacitor Cp1 is formed between the first array common electrode ACOM1 and the corresponding first scanning line 121.

[0043] Then, when the scanning of the first scanning line 121 corresponding to the first sub-pixel P1 is completed, that is, when the scanning signal in the first scanning line 121 corresponding to the first sub-pixel P1 jumps from the high level VGH to the low level VGL, this voltage jump will be coupled to the source S of the first scanning transistor TFT1 through the second parasitic capacitor Cgs1 and the fourth parasitic capacitor Cp1, thereby causing the voltage of the source S of the first scanning transistor TFT1 to attenuate. Specifically, the voltage attenuation ΔVS1 of the source S of the first scanning transistor TFT1 satisfies the relationship (1) with the high level VGH and the low level VGL:

[0044] (1)

[0045] The second subpixel P2 includes a second scanning transistor TFT2, a second pixel electrode (not shown), and a second array common electrode ACOM2. The source electrode S of the second scanning transistor TFT2 is electrically connected to the second pixel electrode, the drain electrode D of the second scanning transistor TFT2 is electrically connected to the corresponding second data line 112, and the gate electrode G of the second scanning transistor TFT2 is electrically connected to the corresponding second scanning line 122. A third parasitic capacitor Cgs2 is formed between the source electrode S of the second scanning transistor TFT2 and the corresponding second scanning line 122. A second liquid crystal capacitor Clc2 is formed between the source electrode S of the second scanning transistor TFT2 and the color filter common electrode CFCOM. A second storage capacitor Cst2 is formed between the source electrode S of the second scanning transistor TFT2 and the second array common electrode ACOM2. A fifth parasitic capacitor Cp2 is formed between the corresponding second scanning line 122 and the corresponding first scanning line 121. Among them, since the first scanning line 121 corresponding to the second sub-pixel P2 is located between the source S of the second scanning transistor TFT2 and the second array common electrode ACOM2, the source S of the second scanning transistor TFT2 is isolated from the second array common electrode ACOM2, so that there is no parasitic capacitance between the source S of the second scanning transistor TFT2 and the second array common electrode ACOM2.

[0046] Then, when the scanning of the second scanning line 122 corresponding to the second sub-pixel P2 is completed, that is, when the scanning signal in the second scanning line 122 corresponding to the second sub-pixel P2 jumps from the high level VGH to the low level VGL, this voltage jump will be coupled to the source S of the second scanning transistor TFT2 through the third parasitic capacitor Cgs2, thereby causing the voltage of the source S of the second scanning transistor TFT2 to attenuate. Specifically, the voltage attenuation ΔVS2 of the source S of the second scanning transistor TFT2 satisfies the relationship (2) with the high level VGH and the low level VGL:

[0047] (2)

[0048] According to equations (1) to (2), Cst1≈Cst2, Clc1≈Clc2, and Cgs1≈Cgs2, and Cgs1+Cst in the first sub-pixel P1 must be greater than Cgs2 in the second sub-pixel P2. Therefore, the voltage attenuation ΔVS2 of the pixel electrode in the second sub-pixel P2 will be significantly smaller than the voltage attenuation ΔVS1 of the pixel electrode in the first sub-pixel P1. This difference in voltage attenuation will cause the display panel 10' of the existing U-Type pixel architecture to have a phenomenon of alternating light and dark vertical stripes.

[0049] In view of this, the embodiment of the present application provides a display device 100. Figure 4 , Figure 4A schematic structural diagram of a display device provided in an embodiment of the present application.

[0050] like Figure 4 As shown, the display device 100 includes a display panel 10 and a driving circuit 20. The display panel 10 includes a plurality of pixel rows 101, a plurality of data line groups 11 and a plurality of scan line groups 12.

[0051] The plurality of pixel rows 101 are arranged along a column direction, and each of the pixel rows 101 includes a plurality of sub-pixels arranged along a row direction. The plurality of sub-pixels include a first sub-pixel P1 and a second sub-pixel P2.

[0052] In the column direction, the sub-pixels in each pixel column are of the same category, that is, all the sub-pixels in any pixel column are either the first sub-pixels P1 or the second sub-pixels P2. For example, the sub-pixels in the 2×x×b+1 to (2×x+1)×b columns are the first sub-pixels P1, and the sub-pixels in the (2×x+1)×b+1 to (2×x+2)×b columns are the second sub-pixels P2, where 0≤x, 1 <b。

[0053] Each data line group 11 includes a first data line 111, a second data line 112, and a switch module T1. Each first data line 111 corresponds to a column of first sub-pixels P1, and each second data line 112 corresponds to a column of second sub-pixels P2. The first data line 111 in each data line group 11 is electrically connected to the first sub-pixels P1 in the corresponding column and is positioned adjacent to the first sub-pixels P1 in the corresponding column. The second data line 112 in each data line group 11 is electrically connected to the first data line 111 in the data line group 11 via the switch module T1 in the data line group 11, and is electrically connected to the second sub-pixels P2 in the corresponding column and is positioned adjacent to the second sub-pixels P2 in the corresponding column.

[0054] Each of the scan line groups 12 includes a first scan line 121 and a second scan line 122. Each of the scan line groups 12 corresponds to a pixel row 101. The first scan line 121 and the second scan line 122 in each of the scan line groups 12 are alternately arranged on one side of the corresponding pixel row 101 in the column direction, and in the column direction, the first scan line 121 in each of the scan line groups 12 is located between the second scan line 122 in the scan line group 12 and the corresponding pixel row 101. The first scan line 121 in each of the scan line groups 12 is electrically connected to all the first sub-pixels P1 in the corresponding pixel row 101, and the second scan line 122 in each of the scan line groups 12 is electrically connected to all the second sub-pixels P2 in the corresponding pixel row 101.

[0055] For example, Figure 4As shown, the odd-numbered scan lines are the first scan lines 121, and the even-numbered scan lines are the second scan lines 122. For example, the 1st to 2nd scan lines constitute the first scan line group 12, corresponding to the 1st pixel row 101. The 1st scan line is electrically connected to all the first sub-pixels P1 in the 1st pixel row 101, and the 2nd scan line is electrically connected to all the second sub-pixels P2 in the 1st pixel row 101, and so on.

[0056] The driving circuit 20 is electrically connected to the first scan line 121 and the second scan line 122 of the plurality of scan line groups 12 in the display panel 10, and the first data line 111 of the plurality of data line groups 11. The driving circuit 20 is configured to control the switch module T1 to turn off at a first moment in a blanking period (BlankingTime) of a current frame, and to increase the data voltage provided to the data line group 11 at a second moment in the blanking period of the current frame. The first moment is earlier than or equal to the second moment.

[0057] In some embodiments of the present application, the driving circuit 20 controls the switch module T1 to be turned off, which may refer to controlling all the switch modules T1 to be turned off. The driving circuit 20 increases the data voltage provided to the data line group 11, which may refer to increasing the data voltage provided to all the data line groups 11.

[0058] For example, Figure 4 As shown, b=6. Each data line group 11 includes two switch modules T1. The opposite ends of each second data line 112 are electrically connected to the corresponding first data line 111 via the two corresponding switch modules T1. During the display period of each frame, each switch module T1 is turned on. At this time, the second data lines 112 in the same data line group 11 are connected in parallel with the first data line 111. Therefore, each second data line 112 can receive the data voltage output by the driving circuit 20 through the corresponding switch module T1 and the corresponding first data line 111. This ensures that all second sub-pixels P2 can normally receive the data voltage through the corresponding second data line 112 during the display period of each frame. When each switch module T1 is turned off, the electrical connection between each second data line 112 and the corresponding first data line 111 is disconnected, so that each second data line 112 cannot receive the data voltage output by the driving circuit 20.

[0059] See also Figure 5~Figure 6 , Figure 5 for Figure 4 Partial wiring diagram of the first pixel row in the diagram, Figure 6 for Figure 4 Schematic diagram of a portion of the pixel circuit for the first pixel row in FIG.

[0060] like Figure 5~Figure 6 As shown, a first parasitic capacitor Cpd is formed between each first data line 111 in the data line group 11 and the first sub-pixel P1 in the corresponding column. At the second moment in the blanking period of the current frame, when the data voltage in the data line group 11 jumps, the pixel electrode in the first sub-pixel P1 corresponding to the first data line 111 in the data line group 11 experiences a corresponding voltage jump due to the coupling effect of the first parasitic capacitor Cpd. At this time, because the switch module T1 is turned off, each second data line 112 no longer receives the data voltage output by the driving circuit 20. Therefore, the voltage in each second data line 112 does not jump, and further, the pixel electrode in the second sub-pixel P2 corresponding to each second data line 112 does not experience a voltage jump.

[0061] Specifically, the voltage jump amount ΔVS of the first pixel electrode in the first sub-pixel P1 and the voltage jump of the corresponding data line group 11 at the second moment (ie, the compensation voltage ΔV hereinafter) satisfy the relationship (3):

[0062] (3)

[0063] Among them, Cgs1, Cst1, and Clc1 have been introduced in detail in the previous article and will not be repeated here.

[0064] In this way, by utilizing the coupling effect of the first parasitic capacitor Cpd between the first data line 111 and the corresponding first sub-pixel P1, the voltage jump amount ΔVS generated by the pixel electrode in the first sub-pixel P1 and the voltage attenuation amount ΔVS1 of the pixel electrode in the first sub-pixel P1 can be at least partially offset, thereby reducing the difference between ΔVS2 and ΔVS1, and further improving the vertical stripe problem of the existing U-Type pixel architecture display panel 10'.

[0065] In some embodiments of the present application, the driving circuit 20 increases the data voltage provided to the data line group 11, which means instantaneously increasing the data voltage provided to the data line group 11. That is, the data voltage received by the data line group 11 increases in a step-like manner. It is understood that the faster the rate of increase of the data voltage received by the first data line 111, the stronger the coupling effect of the first parasitic capacitor Cpd. Consequently, the larger the voltage jump ΔVS of the pixel electrode in the first sub-pixel P1 corresponding to the first data line 111 in the data line group 11, the more significant the improvement effect on the vertical streak problem.

[0066] The display device 100 provided in the embodiment of the present application provides a switch module T1 between the first data line 111 and the corresponding second data line 112, and controls the switch module T1 to be turned off at a first moment in the blanking period of the current frame through the driving circuit 20, and increases the data voltage provided to the data line group 11 at a second moment in the blanking period of the current frame. This allows the voltage jump generated by the pixel electrode of the first sub-pixel P1 during the blanking period and the voltage attenuation ΔVS1 thereof during the display period to at least partially offset, thereby reducing the difference between the voltage attenuation ΔVS2 of the second sub-pixel P2 and the voltage attenuation ΔVS1 of the first sub-pixel P1, thereby improving the vertical stripe problem of the existing display panel 10' with a U-Type pixel architecture.

[0067] like Figure 4 As shown, the driving circuit 20 includes a timing controller (TCON) 23, a gate driver 24, and a source driver 25. The gate driver 24 is electrically connected to each of the first scan lines 121 and each of the second scan lines 122. The source driver 25 is electrically connected to each of the first data lines 111. The timing controller 23 is electrically connected to the gate driver 24 and the source driver 25.

[0068] During operation, the timing controller 23 is configured to receive image signals representing image information from an external signal source and, based on the image signals, provide a plurality of voltage signals to drive the source driver 25 and the gate driver 24. The voltage signals are then transmitted by the source driver 25 and the gate driver 24 to each of the first sub-pixels P1 and each of the second sub-pixels P2, thereby driving the display panel 10 to perform display. Specifically, the timing controller 23 is configured to provide data timing signals to the source driver 25, so that the source driver 25 outputs corresponding data voltages to the corresponding columns of first sub-pixels P1 via each of the first data lines 111, and outputs corresponding data voltages to the corresponding columns of second sub-pixels P2 via each of the second data lines 112, based on the data timing signals. The timing controller 23 is also used to output a clock signal, etc. to the gate driver 24, so that the gate driver 24 outputs a corresponding scanning signal to the first sub-pixel P1 in the corresponding pixel row 101 through each of the first scanning lines 121 based on the clock signal, and outputs a corresponding scanning signal to the second sub-pixel P2 in the corresponding pixel row 101 through each of the second scanning lines 122.

[0069] The gate driver 24 is also electrically connected to the control terminal of each switch module T1 and is configured to output a first clock signal CLK to the control terminal of each switch module T1 to control the on / off state of each switch module T1. Specifically, the gate driver 24 is configured to control the on / off state of each switch module T1 at the first moment during the blanking time of the current frame. In other embodiments, the on / off state of each switch module T1 can also be controlled by other modules in the drive circuit 20 (e.g., the timing controller 23).

[0070] The source driver 25 is further configured to increase the data voltage provided to each of the data line groups 11 at a second moment in the blanking period of the current frame.

[0071] In some embodiments of the present application, the driving circuit 20 is further configured to control the switch module T1 to be turned on at or before the start time of the display period of the next frame after controlling the switch module T1 to be turned off.

[0072] See also Figure 7 , Figure 7 for Figure 4 The driving signal timing diagram of the display device shown in FIG. Figure 7 As shown, in some embodiments of the present application, the first moment and the second moment are both the starting moments of the blanking period of the current frame, and the gate driver 24 is also used to control the switch module T1 to be turned on at the starting moment of the display period of each frame of the switch module T1.

[0073] Wherein, G1 represents the first row scan signal output by the driving circuit 20 to the first row scan line, G2 represents the second row scan signal output by the driving circuit 20 to the second row scan line, Gn represents the n-th row scan signal output by the driving circuit 20 to the n-th row scan line, and Dm represents the data voltage output by the driving circuit 20 to the m-th column data line. When the first clock signal CLK is at a high level, the switch module T1 is turned on, and when the first clock signal CLK is at a low level, the switch module T1 is turned off.

[0074] In some embodiments of the present application, the source driver 25 is specifically used to maintain providing the first data voltage Vdata1 to the data line group 11 before the second moment in the blanking period of the current frame, and at the second moment, jump from providing the first data voltage Vdata1 to the data line group 11 to providing the second data voltage Vdata2 to the data line group 11.

[0075] The first data voltage Vdata1 is the data voltage provided by the driving circuit 20 to the data line group 11 at the last moment of the display period of the current frame. The second data voltage Vdata2 is the sum of the first data voltage Vdata1 and the compensation voltage ΔV, that is, Vdata2=Vdata1+ΔV.

[0076] It should be noted that the first data voltage Vdata1 is the data voltage provided by the driving circuit 20 to the data line group 11 at the last moment of the display period of the current frame, which means that the first data voltage Vdata1 of each data line group 11 is the data voltage provided by the driving circuit 20 to the data line group 11 at the last moment of the display period of the current frame. That is to say, for different data line groups 11, the voltage values ​​of their first data voltages Vdata1 may not be equal, and accordingly, their second data voltages Vdata2 may also not be equal.

[0077] The compensation voltage ΔV is positively correlated with ΔV1-ΔV2, that is, the larger ΔV1-ΔV2 is, the larger ΔV is, and the smaller ΔV1-ΔV2 is, the smaller ΔV is. ΔV1 is a first voltage change of the first array common electrode ACOM1 in the first sub-pixel P1 electrically connected to the data line group 11, the first voltage change being caused by a transition from a high level to a low level in the scan signal of the first scan line 121 corresponding to the first array common electrode ACOM1. ΔV2 is a second voltage change of the second array common electrode ACOM2 in the second sub-pixel P2 electrically connected to the data line group 11, the second voltage change being caused by a transition from a high level to a low level in the scan signal of the second scan line 122 corresponding to the second array common electrode ACOM2.

[0078] It should be noted that if Figure 6As shown, because a first storage capacitor Cst1 is formed between the source electrode S of the first scanning transistor TFT1 and the first array common electrode ACOM1, when the scanning signal on the first scanning line 121 transitions from a high level VGH to a low level VGL, the voltage attenuation ΔVS1 of the source electrode S of the first scanning transistor TFT1 is coupled to the first array common electrode ACOM1 through the first storage capacitor Cst1. That is, the voltage attenuation ΔVS1 of the source electrode S of the first scanning transistor TFT1 is proportional to the first voltage change ΔV1 of the first array common electrode ACOM1 in the first sub-pixel P1 to which it belongs. Similarly, the voltage attenuation ΔVS2 of the source electrode S of the second scanning transistor TFT2 is also proportional to the second voltage change ΔV2 of the second array common electrode ACOM2 in the second sub-pixel P2 to which it belongs. Therefore, the difference between the second voltage change ΔV2 and the first voltage change ΔV1 can reflect the difference between ΔVS2 and ΔVS1.

[0079] See also Figure 8 , Figure 8 Schematic diagram of the circuit structure of the driving circuit provided in the embodiment of the present application. In some embodiments of the present application, the driving circuit 20 further includes a first detection circuit 21 and a second detection circuit 22.

[0080] The first detection circuit 21 is electrically connected to the first array common electrode ACOM1 in the first sub-pixel P1. The first detection circuit 21 is configured to receive a first actual common voltage V_FB1 of the first array common electrode ACOM1 and output a first detection voltage V1 based on the first actual common voltage V_FB1. When the scan signal in the first scan line 121 corresponding to the first array common electrode ACOM1 transitions from a high level to a low level, causing the first actual common voltage V_FB1 to drop, the first detection voltage V1 decreases in response to the drop in the first actual common voltage V_FB1.

[0081] The second detection circuit 22 is electrically connected to the second array common electrode ACOM2 in the second sub-pixel P2. The second detection circuit 22 is configured to receive a second actual common voltage V_FB2 of the second array common electrode ACOM2 and output a second detection voltage V2 based on the second actual common voltage V_FB2. When the scan signal on the second scan line 122 corresponding to the second array common electrode ACOM2 transitions from a high level to a low level, causing the second actual common voltage V_FB2 to decrease, the second detection voltage V2 decreases accordingly.

[0082] The timing controller 23 is also electrically connected to the first detection circuit 21 and the second detection circuit 22. The timing controller 23 is used to obtain the first detection voltage V1 from the first detection circuit 21, obtain the second detection voltage V2 from the second detection circuit 22, and determine the compensation voltage ΔV based on the first detection voltage V1 and the second detection voltage V2.

[0083] After determining the compensation voltage ΔV, the timing controller 23 is further used to add the first data voltage Vdata1 provided by the data line group 11 and the compensation voltage ΔV to obtain the second data voltage Vdata2, and control the source driver 25 to jump from providing the first data voltage Vdata1 to the data line group 11 to providing the second data voltage Vdata2 to the data line group 11.

[0084] In this way, the timing controller 23 can determine the compensation voltage ΔV by detecting the first actual common voltage V_FB1 of the first array common electrode ACOM1 and the second actual common voltage V_FB2 of the first array common electrode ACOM1, so as to accurately control the voltage change of the first data line 111 at the second moment, and enable the compensation voltage ΔV to match the difference between ΔVS2 and ΔVS1, thereby achieving better compensation effect and better display effect.

[0085] It should be noted that, in the same display panel, since the capacitance values ​​of the parasitic capacitances, liquid crystal capacitances, and storage capacitances of different sub-pixels are approximately equal, the first voltage change ΔV1 and the second voltage change ΔV2 corresponding to different data line groups 11 are also approximately equal. Therefore, in some embodiments of the present application, the compensation voltages ΔV corresponding to different data line groups 11 can be equal. In this case, the compensation voltages ΔV corresponding to all data line groups 11 can be determined by detecting the first voltage change ΔV1 and the second voltage change ΔV2 corresponding to one data line group 11. This simplifies the circuit structure.

[0086] Of course, in some other embodiments, the compensation voltages ΔV corresponding to different data line groups 11 may also be unequal. In this case, it is necessary to separately provide the first detection circuit 21 and the second detection circuit 22 for different data line groups 11 to detect the corresponding first detection voltage V1 and second detection voltage V2. In this way, the compensation effect is better.

[0087] In some embodiments of the present application, the timing controller 23 is configured to determine the voltage value of the compensation voltage AV according to a difference between the second minimum voltage value V20 and the first minimum voltage value V10, wherein the first minimum voltage value V10 is the minimum value of the first detection voltage V1, and the second minimum voltage value V20 is the minimum value of the second detection voltage V2.

[0088] For example, AV and V20, V10 satisfy the following relationship (4):

[0089] AV = K x (V20-V10) (4)

[0090] wherein K is a preset compensation coefficient, which can be determined by experiment.

[0091] For example, the timing controller 23 is configured to determine the voltage value of the compensation voltage AV as the difference between the second minimum voltage value V20 and the first minimum voltage value V10, i.e., AV = V20-V10.

[0092] wherein the first voltage variation AV1 is a difference between the voltage value of the initial common voltage VACOM and the first minimum voltage value V10, i.e., AV1 = VACOM-V10, and the second voltage variation AV2 is a difference between the voltage value of the initial common voltage VACOM and the second minimum voltage value V20, i.e., AV2 = VACOM-V20.

[0093] In some embodiments of the present application, the first detection circuit 21 comprises a first diode D1, a first switch tube Q1, and a first capacitor C1.

[0094] wherein the cathode of the first diode D1 is electrically connected to a first array common electrode ACOM1 in the first sub-pixel P1.

[0095] The first switch tube Q1 comprises a first connection end and a second connection end, the first connection end of the first switch tube Q1 is configured to receive an initial common voltage VACOM from a common voltage source ACOM, and the second connection end of the first switch tube Q1 is electrically connected to the anode of the first diode D1.

[0096] The first end of the first capacitor C1 is electrically connected to the anode of the first diode D1 and the timing controller 23, and the second end of the first capacitor C1 is grounded.

[0097] The first detection voltage V1 output by the first detection circuit 21 is the voltage at the first terminal of the first capacitor C1. During at least a portion of a period in which the scan signal on the corresponding first scan line 121 (i.e., the first scan line 121 electrically connected to the first sub-pixel P1 electrically connected to the cathode of the first diode D1) is high, the first switch Q1 is turned on to charge the first capacitor C1 using the initial common voltage VACOM received at its first connection terminal, thereby charging the first terminal of the first capacitor C1 to the initial common voltage VACOM. Before the scan signal on the corresponding first scan line 121 transitions from a high level to a low level (including during and before the transition), the first switch Q1 is turned off, allowing the first capacitor C1 to discharge to the first array common electrode ACOM1 through the first diode D1, thereby discharging the voltage at the first terminal of the first capacitor C1 to the first minimum voltage V10.

[0098] In some embodiments of the present application, the first detection circuit 21 further includes a first voltage follower U1 and a first analog-to-digital conversion circuit ADC1.

[0099] An input terminal of the first voltage follower U1 is electrically connected to the anode of the first diode D1 .

[0100] The first analog-to-digital conversion circuit ADC1 is electrically connected between the output end of the first voltage follower U1 and the timing controller 23. The first analog-to-digital conversion circuit ADC1 is used to receive the first detection voltage V1 output by the first voltage follower U1, and perform analog-to-digital conversion on the first detection voltage V1 and then output it to the timing controller 23.

[0101] The first voltage follower U1 performs a conversion from high input impedance to low output impedance, and can provide a stable sampling signal for the first analog-to-digital conversion circuit ADC1.

[0102] In some embodiments of the present application, the circuit structure of the second detection circuit 22 is the same as that of the first detection circuit 21. Specifically, the second detection circuit 22 includes a second diode D2, a second switch tube Q2, and a second capacitor C2.

[0103] The cathode of the second diode D2 is electrically connected to a second array common electrode ACOM2 in the second sub-pixel P2.

[0104] The second switch tube Q2 includes a first connection end and a second connection end. The first connection end of the second switch tube Q2 is used to receive an initial common voltage VACOM from a common voltage source ACOM, and the second connection end of the second switch tube Q2 is electrically connected to the anode of the second diode D2.

[0105] A first end of the second capacitor C2 is electrically connected with an anode of the second diode D2 and the timing controller 23, and a second end of the second capacitor C2 is grounded.

[0106] The second detection circuit 22 outputs the second detection voltage V2 as the voltage of the first end of the second capacitor C2. During at least a period when the scan signal in the corresponding second scan line 122 (i.e., the second scan line 122 electrically connected with the second sub-pixel P2 having the cathode electrically connected with the second diode D2) is at a high level, the second switch Q2 is turned on to charge the second capacitor C2 with the initial common voltage VACOM received by the first connection end of the second switch Q2, so as to charge the first end of the second capacitor C2 to the initial common voltage VACOM. When the scan signal in the corresponding second scan line 122 jumps from the high level to the low level, the second switch Q2 is turned off, so that the second capacitor C2 is discharged to the second array common electrode ACOM2 through the second diode D2, so as to discharge the voltage value of the first end of the second capacitor C2 to the second lowest voltage value V20.

[0107] In some embodiments of the present application, the second detection circuit 22 further comprises a second voltage follower U2 and a second analog-to-digital conversion circuit ADC2.

[0108] The input end of the second voltage follower U2 is electrically connected with the anode of the second diode D2.

[0109] The second analog-to-digital conversion circuit ADC2 is electrically connected between the output end of the second voltage follower U2 and the timing controller 23, and is configured to receive the second detection voltage V2 output by the second voltage follower U2, and perform analog-to-digital conversion on the second detection voltage V2 and output to the timing controller 23.

[0110] The on-off state of the first switch Q1 is controlled by a first control signal Ctrl1, and the on-off state of the second switch Q2 is controlled by a second control signal Ctrl2. The first control signal Ctrl1 and the second control signal Ctrl2 can be output by the timing controller 23 or the gate driver 24.

[0111] In some embodiments, the first switch Q1 and the second switch Q2 are both PMOS tubes.

[0112] The working principles of the first detection circuit 21 and the second detection circuit 22 will be described in detail below. Figures 9 and 10 The working principles of the first detection circuit 21 and the second detection circuit 22 will be described in detail below. Figure 9Voltage waveform diagrams of the first actual common voltage and the second actual common voltage provided in the embodiment of the present application; Figure 10 This is a timing diagram of the first control signal and the first detection voltage provided in an embodiment of the present application.

[0113] like Figure 9 As shown, in the same scan line group 12, when the first scan line 121 jumps from a high level to a low level, affected by the level jump of the first scan line 121, the first actual common voltage V_FB1 of the first array common electrode ACOM1 in the first sub-pixel P1 in the pixel row 101 corresponding to the scan line group 12 will produce a corresponding jump, specifically, jump from the initial common voltage VACOM to the first minimum voltage value V10, and then recover to the initial common voltage VACOM after a certain time; when the second scan line 122 jumps from a high level to a low level, affected by the level jump of the second scan line 122, the second actual common voltage V_FB2 of the second array common electrode ACOM2 in the second sub-pixel P2 in the pixel row 101 corresponding to the scan line group 12 will produce a corresponding jump, specifically, jump from the initial common voltage VACOM to the second minimum voltage value V20, and then recover to the initial common voltage VACOM after a certain time. Obviously, the first minimum voltage value V10 is smaller than the second minimum voltage value V20 , and the first voltage variation ΔV1 of the first actual common voltage V_FB1 is larger than the second voltage variation ΔV2 of the second actual common voltage V_FB2 .

[0114] like Figure 10 As shown, taking the first scan line group 12, the first detection circuit 21 is electrically connected to the first sub-pixel (first sub-pixel P1) in the first pixel row 101, and the second detection circuit 22 is electrically connected to the seventh sub-pixel (second sub-pixel P2) in the first pixel row 101 as an example.

[0115] During at least a portion of the time when the scan signal on the first scan line is high, the first control signal Ctrl1 is pulled low to control the first switch Q1 to conduct, thereby charging the first end of the first capacitor C1 to the initial common voltage VACOM. This means that the first detection voltage V1 stabilizes at the initial common voltage VACOM. When the scan signal on the first scan line switches from a high level to a low level, the source electrodes S of the first scan transistors TFT1 in the sub-pixels of columns 1 through 6 experience a voltage decay, and the corresponding first array common electrodes ACOM1 also experience a voltage jump. Simultaneously, the first control signal Ctrl1 is pulled high to control the first switch Q1 to turn off. At this point, as the first actual common voltage V_FB1 of the first array common electrodes ACOM1 decreases, the first diode D1 becomes forward-biased and conducts, causing the charged first capacitor C1 to begin discharging until the voltage at the first end of the first capacitor C1 drops to the first minimum voltage V10 of the first actual common voltage V_FB1. Afterward, the first actual common voltage V_FB1 rebounds, and the second diode D2 is reversely cut off, thereby clamping the voltage at the first terminal of the first capacitor C1 to the first minimum voltage value V10. That is, the first detection voltage V1 is maintained at the first minimum voltage value V10. In this way, the valley voltage data of the first actual common voltage V_FB1 can be detected, that is, the first voltage change ΔV1 of the first actual common voltage V_FB1 can be detected.

[0116] Similarly, when the scanning signal in the second row of the scanning line switches from a high level to a low level, the source S of the first scanning transistor TFT1 in the 7th to 12th columns of the sub-pixels will experience voltage attenuation, and the same circuit mechanism can be used to detect the valley voltage data of the second actual common voltage V_FB2.

[0117] See also Figure 11 , Figure 11 Flowchart of a method for controlling a display device provided in an embodiment of the present application. Based on the same concept, an embodiment of the present application also provides a method for controlling a display device, the method for controlling the display device 100 as described in any of the above embodiments to perform display, the method comprising:

[0118] Step S1 : at the first moment in the blanking period of the current frame, controlling the switch module T1 to be turned off.

[0119] Step S2: at a second moment in the blanking period of the current frame, increasing the data voltage provided to the data line group 11.

[0120] The first moment is earlier than or equal to the second moment.

[0121] It should be noted that the control method of the display device corresponds to the solution of the display device 100 mentioned above. For more detailed description, please refer to the contents of the various embodiments of the display device 100 mentioned above, and will not be repeated here.

[0122] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display device comprising a display panel and a driving circuit; characterized in that: The display panel includes: A plurality of pixel rows arranged along a column direction, each of the pixel rows comprising a plurality of sub-pixels arranged along a row direction, the plurality of sub-pixels comprising a first sub-pixel and a second sub-pixel; a plurality of data line groups, each of the data line groups comprising a first data line, a second data line, and a switch module; wherein the first data line in each of the data line groups is electrically connected to a column of the first sub-pixels and is disposed adjacent to a corresponding column of the first sub-pixels; and the second data line in each of the data line groups is electrically connected to the first data line via the switch module and is electrically connected to a column of the second sub-pixels; and a plurality of scan line groups, each of the scan line groups comprising a first scan line and a second scan line, the first scan line and the second scan line in each of the scan line groups being alternately arranged on one side of a corresponding pixel row, and the first scan line in each of the scan line groups being located between the second scan line and the corresponding pixel row, the first scan line in each of the scan line groups being electrically connected to all first sub-pixels in the corresponding pixel row, and the second scan line in each of the scan line groups being electrically connected to all second sub-pixels in the corresponding pixel row; The driving circuit is electrically connected to the multiple scan line groups and the first data line of the multiple data line groups in the display panel, respectively. The driving circuit is used to control the switch module to turn off at a first moment in the blanking period of the current frame, and to increase the data voltage provided to the data line group at a second moment in the blanking period of the current frame; wherein the first moment is earlier than or equal to the second moment.

2. The display device according to claim 1, wherein The driving circuit is specifically configured to, at a second moment in a blanking period of a current frame, jump from providing a first data voltage Vdata1 to providing a second data voltage Vdata2 to the data line group; wherein the first data voltage Vdata1 is the data voltage provided to the data line group by the driving circuit at the last moment of a display period of the current frame, and the second data voltage Vdata2 is the sum of the first data voltage Vdata1 and a compensation voltage ΔV; wherein the compensation voltage ΔV is positively correlated with ΔV1-ΔV2, ΔV1 is a first voltage change of a first array common electrode in a first sub-pixel electrically connected to the data line group, the first voltage change is caused by a scan signal in a first scan line corresponding to the first array common electrode jumping from a high level to a low level, ΔV2 is a second voltage change of a second array common electrode in a second sub-pixel electrically connected to the data line group, the second voltage change is caused by a scan signal in a second scan line corresponding to the second array common electrode jumping from a high level to a low level.

3. The display device according to claim 2, wherein The driving circuit further includes: a first detection circuit electrically connected to a first array common electrode in the first sub-pixel, configured to receive a first actual common voltage of the first array common electrode and output a first detection voltage based on the first actual common voltage; wherein, when a scan signal in a first scan line corresponding to the first array common electrode transitions from a high level to a low level, causing the first actual common voltage to decrease, the first detection voltage decreases in response to the decrease in the first actual common voltage; a second detection circuit electrically connected to a second array common electrode in the second sub-pixel, configured to receive a second actual common voltage of the second array common electrode and output a second detection voltage based on the second actual common voltage; wherein, when the second actual common voltage decreases due to a transition of a scan signal in a second scan line corresponding to the second array common electrode from a high level to a low level, the second detection voltage decreases in response to the decrease in the second actual common voltage; and A timing controller is electrically connected to the first detection circuit and the second detection circuit, and is used to obtain the first detection voltage from the first detection circuit, obtain the second detection voltage from the second detection circuit, and determine the compensation voltage ΔV based on the first detection voltage and the second detection voltage.

4. The display device according to claim 3, wherein The timing controller is used to determine the voltage value of the compensation voltage ΔV based on the difference obtained by subtracting the first minimum voltage value from the second minimum voltage value; wherein the first minimum voltage value is the minimum value of the first detection voltage, and the second minimum voltage value is the minimum value of the second detection voltage.

5. The display device according to claim 4, wherein The first voltage variation is a difference obtained by subtracting the first minimum voltage value from the voltage value of the initial common voltage, and the second voltage variation is a difference obtained by subtracting the second minimum voltage value from the voltage value of the initial common voltage.

6. The display device according to claim 4, wherein The first detection circuit includes: a first diode, wherein a cathode of the first diode is electrically connected to a first array common electrode in the first sub-pixel; a first switching tube, comprising a first connecting end and a second connecting end, wherein the first connecting end of the first switching tube is used to receive an initial common voltage, and the second connecting end of the first switching tube is electrically connected to an anode of the first diode; and a first capacitor, wherein a first end of the first capacitor is electrically connected to the anode of the first diode and the timing controller, and a second end of the first capacitor is grounded; The first detection voltage output by the first detection circuit is the voltage at the first end of the first capacitor. During at least a portion of the time period when the scan signal in the corresponding first scan line is at a high level, the first switch tube is turned on to charge the first capacitor, thereby charging the first end of the first capacitor to the initial common voltage. Before the scan signal in the corresponding first scan line jumps from a high level to a low level, the first switch tube is turned off, so that the first capacitor discharges to the first array common electrode through the first diode, thereby discharging the voltage value of the first end of the first capacitor to the first minimum voltage value.

7. The display device according to claim 6, wherein The first detection circuit further includes: a first voltage follower, wherein an input terminal of the first voltage follower is electrically connected to an anode of the first diode; and The first analog-to-digital conversion circuit is electrically connected between the output end of the first voltage follower and the timing controller, and is used to receive the first detection voltage output by the first voltage follower, perform analog-to-digital conversion on the first detection voltage, and then output it to the timing controller.

8. The display device according to claim 1, wherein A first parasitic capacitor is formed between the first data line in each of the data line groups and the first sub-pixel in the corresponding column. At the second moment in the blanking period of the current frame, when the data voltage in the first data line in the data line group jumps, under the coupling action of the first parasitic capacitor, the first pixel electrode in the first sub-pixel corresponding to the first data line in the data line group generates a corresponding voltage jump.

9. The display device according to claim 3, wherein The driving circuit is further configured to control the switch module to be turned on at a starting time or before a starting time of a display period of a next frame after controlling the switch module to be turned off.

10. A method for controlling a display device, characterized in that: The control method is used to control the display device according to any one of claims 1 to 9 to perform display, and the control method includes: At a first moment in a blanking period of a current frame, controlling the switch module to turn off; and At a second moment in a blanking period of a current frame, the data voltage provided to the data line group is increased; wherein the first moment is earlier than or equal to the second moment.

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