Bipolar junction transistor element and manufacturing method thereof

Abstract

The invention discloses a bipolar junction transistor element and a manufacturing method thereof. The bipolar junction transistor element comprises a substrate of a first conductivity type; a first ion trap of a second conductivity type in the substrate; a second ion trap of the first conductivity type in the first ion trap; an emitter region of a second conductivity type in the second ion trap; a first trench isolation region surrounding the emitter region; a base region of the first conductivity type in the second ion trap; a second trench isolation region surrounding the base region; a third ion trap of a second conductivity type in the first ion trap and surrounding the second ion trap; and a collector region of a second conductivity type in the third ion trap and surrounding the second trench isolation region. The junction depth of the emitter region is deeper than the junction depth of the base region or the junction depth of the collector region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an improved bipolar junction transistor (BJT) device and a method for manufacturing the same. Background Art

[0002] Bipolar junction transistor (BJT) devices are commonly used as signal amplification devices or switching devices in semiconductor integrated circuits (ICs). A BJT device mainly consists of three doped active regions, including an emitter region, a base region, and a collector region. These regions form a first diode between the base region and the emitter region and a second diode between the base region and the collector region.

[0003] In current semiconductor high-voltage manufacturing processes, large-area low-voltage NPN BJT devices are prone to encounter mismatch problems. Therefore, there is still a need in this technical field for an improved BJT device and a method for manufacturing the same. Summary of the Invention

[0004] The main objective of the present invention is to provide an improved bipolar junction transistor device and a method for manufacturing the same, so as to solve the deficiencies or drawbacks of the prior art.

[0005] On the one hand, the present invention provides a bipolar junction transistor (BJT) device, comprising: a substrate of a first conductivity type; a second conductivity type first ion trap located in the substrate, wherein the second conductivity type is opposite to the first conductivity type; a first conductivity type second ion trap located in the first ion trap; a second conductivity type emitter region located in the second ion trap; a first trench isolation region surrounding the emitter region; a first conductivity type base region located in the second ion trap, wherein the base region surrounds the first trench isolation region; a second trench isolation region surrounding the base region; a second conductivity type third ion trap located in the first ion trap and surrounding the second ion trap; and a second conductivity type collector region located in the third ion trap and surrounding the second trench isolation region, wherein the junction depth of the emitter region is deeper than the junction depth of the base region or the junction depth of the collector region.

[0006] According to an embodiment of the present invention, the doping concentration of the emitter region is greater than the doping concentration of the collector region.

[0007] According to an embodiment of the present invention, the BJT device further comprises: an emitter silicide layer disposed on the emitter region; a base silicide layer disposed on the base region; and a collector silicide layer disposed on the collector region.

[0008] According to an embodiment of the present invention, the top surface of the emitter silicide layer is lower than the top surfaces of the base silicide layer and the collector silicide layer.

[0009] According to an embodiment of the present invention, the emitter silicide layer, the base silicide layer, and the collector silicide layer comprise cobalt silicide or nickel silicide.

[0010] According to an embodiment of the present invention, the BJT device further comprises: a recessed region located between the top surface of the emitter silicide layer and the first trench isolation region.

[0011] According to an embodiment of the present invention, the BJT device further comprises: a dielectric layer located on the substrate and covering the emitter region, the base region, and the collector region; an emitter contact located in the dielectric layer and electrically connected to the emitter silicide layer; a base contact located in the dielectric layer and electrically connected to the base silicide layer; and a collector contact located in the dielectric layer and electrically connected to the collector silicide layer.

[0012] According to an embodiment of the present invention, the emitter contact, the base contact, and the collector contact comprise tungsten.

[0013] According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0014] According to an embodiment of the present invention, the substrate comprises a silicon substrate.

[0015] On the other hand, the present invention provides a method for forming a bipolar junction transistor (BJT) device, comprising: providing a substrate of a first conductivity type; forming a first ion trap of a second conductivity type in the substrate, wherein the second conductivity type is opposite to the first conductivity type; forming a second ion trap of the first conductivity type in the first ion trap; forming an emitter region of the second conductivity type in the second ion trap; forming a first trench isolation region surrounding the emitter region; forming a base region of the first conductivity type in the second ion trap, wherein the base region surrounds the first trench isolation region; forming a second trench isolation region surrounding the base region; forming a third ion trap of the second conductivity type inside the first ion trap and around the second ion trap; and forming a collector region of the second conductivity type surrounding the second trench isolation region in the third ion trap, wherein the junction depth of the emitter region is deeper than the junction depth of the base region or the junction depth of the collector region.

[0016] According to an embodiment of the present invention, the doping concentration of the emitter region is greater than the doping concentration of the collector region.

[0017] According to an embodiment of the present invention, the method further comprises: forming an emitter silicide layer on the emitter region; forming a base silicide layer on the base region; and forming a collector silicide layer on the collector region.

[0018] According to an embodiment of the present invention, the top surface of the emitter silicide layer is lower than the top surfaces of the base silicide layer and the collector silicide layer.

[0019] According to an embodiment of the present invention, the emitter silicide layer, the base silicide layer, and the collector silicide layer contain cobalt silicide or nickel silicide.

[0020] According to an embodiment of the present invention, the method further includes: forming a recessed area between the top surface of the emitter silicide layer and the first trench isolation region.

[0021] According to an embodiment of the present invention, the method further includes: forming a dielectric layer on the substrate, and the dielectric layer covers the emitter region, the base region, and the collector region; forming an emitter contact in the dielectric layer and electrically connecting it to the emitter silicide layer; forming a base contact in the dielectric layer and electrically connecting it to the base silicide layer; and forming a collector contact in the dielectric layer and electrically connecting it to the collector silicide layer.

[0022] According to an embodiment of the present invention, the emitter contact, the base contact, and the collector contact contain tungsten.

[0023] According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0024] According to an embodiment of the present invention, the substrate includes a silicon substrate. Description of the Drawings

[0025] Figure 1 A top view schematic diagram of the semiconductor device illustrated in the embodiment of the present invention;

[0026] Figure 2 For Figure 1 The cross-sectional schematic diagram shown along the tangent line I-I' in

[0027] Figures 3 to 5 A schematic diagram of a method for forming a BJT device illustrated in the embodiment of the present invention.

[0028] Symbol Description

[0029] 1 Semiconductor device

[0030] 10 Bipolar Junction Transistor (BJT) device

[0031] 100 Substrate

[0032] 110 First ion trap

[0033] 120 Second ion trap

[0034] 130 Third ion trap

[0035] 210 Dielectric layer

[0036] CT1 Emitter Contact

[0037] CT2 Base Contact

[0038] CT3 Collector Contact

[0039] DR1, DR2, DR3 Heavily Doped Regions

[0040] JD1, JD2, JD3 Junction Depths

[0041] GOX1, GOX2, GOX3 Thick Silicon Oxide Layers

[0042] GOS1, GOS2, GOS3 Shielding Silicon Oxide Layers

[0043] ER Emitter Region

[0044] BR Base Region

[0045] CR Collector Region

[0046] RR Recessed Region

[0047] SAC1 Emitter Self - Aligned Silicide Layer

[0048] SAC2 Base Self - Aligned Silicide Layer

[0049] SAC3 Collector Self - Aligned Silicide Layer

[0050] ST1 First Trench Isolation Region

[0051] ST2 Second Trench Isolation Region

[0052] ST3 Third Trench Isolation Region

[0053] S1, S2, S3, S4 Top Surfaces Detailed Implementation Manner

[0054] In the following, details will be described with reference to the accompanying drawings, the content of which also constitutes a part of the detailed description of the specification and is illustrated in a specific example implementation manner. The following embodiments have described sufficient details for those of ordinary skill in the art to implement accordingly.

[0055] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered restrictive. Instead, the embodiments included therein will be defined by the appended claims.

[0056] Please refer to Figure 1 and Figure 2 , wherein, Figure 1A top view schematic diagram of a semiconductor device according to an embodiment of the present invention, Figure 2 is a cross-sectional schematic diagram taken along Figure 1 the tangent line I-I' shown in Figure 1 and Figure 2 As shown in Figure 1 , the semiconductor device 1 includes a substrate 100, for example, a silicon substrate, but not limited thereto. According to an embodiment of the present invention, the substrate 100 has a first conductivity type, for example, a P type. A plurality of bipolar junction transistor (BJT) elements 10 are formed in the substrate 100. According to an embodiment of the present invention, for example, the plurality of BJT elements 10 in Figure 1 can be arranged in a 3×3 array, but not limited thereto. Those skilled in the art should understand that the number, arrangement, and size of the plurality of BJT elements 10 in the figure are only illustrative. According to an embodiment of the present invention, each BJT element 10 includes an emitter region ER located in the center, a ring-shaped base region BR surrounding the emitter region ER, and a ring-shaped collector region CR surrounding the base region BR and the emitter region ER.

[0057] As shown in Figure 2 , a first ion trap 110 of a second conductivity type is provided in the substrate 100, where the second conductivity type is opposite to the first conductivity type. For example, the second conductivity type is an N type, and the first ion trap 110 is a deep N-type well. According to an embodiment of the present invention, a second ion trap 120 of the first conductivity type is provided in the first ion trap 110. For example, the first conductivity type is a P type, and the second ion trap 120 is a P-type well. According to an embodiment of the present invention, the emitter region ER of the second conductivity type and the base region BR of the first conductivity type are located in the second ion trap 120.

[0058] According to an embodiment of the present invention, each BJT element 10 further includes a ring-shaped first trench isolation region ST1 surrounding the emitter region ER. The base region BR surrounds the first trench isolation region ST1. According to an embodiment of the present invention, each BJT element 10 further includes a ring-shaped second trench isolation region ST2 surrounding the base region BR. According to an embodiment of the present invention, each BJT element 10 further includes a ring-shaped third trench isolation region ST3 surrounding the collector region CR.

[0059] According to an embodiment of the present invention, each BJT element 10 further includes a third ion trap 130 of the second conductivity type, which is located in the first ion trap 110 and surrounds the second ion trap 120. According to an embodiment of the present invention, the collector region ER of the second conductivity type is located in the third ion trap 130 and surrounds the second trench isolation region ST2. According to an embodiment of the present invention, the emitter region ER includes a heavily doped region DR1 of the second conductivity type, the base region BR includes a heavily doped region DR2 of the first conductivity type, and the collector region CR includes a heavily doped region DR3 of the second conductivity type. According to an embodiment of the present invention, for example, the heavily doped region DR1 can be a medium-voltage N + doped region, and the heavily doped region DR2 can be a low-voltage P+ The doped region, the heavily doped region DR3 can be a low-voltage N + doped region.

[0060] According to an embodiment of the present invention, the junction depth JD1 of the heavily doped region DR1 in the emitter region ER is deeper than the junction depth JD2 of the heavily doped region DR2 in the base region or the junction depth JD3 of the heavily doped region DR3 in the collector region CR. According to an embodiment of the present invention, the doping concentration of the heavily doped region DR1 in the emitter region ER is greater than the doping concentration of the heavily doped region DR3 in the collector region CR.

[0061] According to an embodiment of the present invention, each BJT element 10 further includes an emitter self-aligned silicide layer SAC1 disposed on the emitter region ER; a base self-aligned silicide layer SAC2 disposed on the base region BR; and a collector self-aligned silicide layer SAC3 disposed on the collector region CR. According to an embodiment of the present invention, the top surface S1 of the emitter self-aligned silicide layer SAC1 is lower than the top surface S2 of the base self-aligned silicide layer SAC2 and the top surface S3 of the collector self-aligned silicide layer SAC3. According to an embodiment of the present invention, the top surface S1 of the emitter self-aligned silicide layer SAC1 is lower than the top surface S4 of the first trench isolation region ST1. According to an embodiment of the present invention, the emitter self-aligned silicide layer SAC1, the base self-aligned silicide layer SAC2, and the collector self-aligned silicide layer SAC3 may include cobalt silicide or nickel silicide, but are not limited thereto.

[0062] According to an embodiment of the present invention, each BJT element 10 further includes a recessed region RR located between the top surface S1 of the emitter self-aligned silicide layer and the first trench isolation region ST1. More specifically, the recessed region RR is located between the top surface S1 of the emitter self-aligned silicide layer and the upper sidewall of the first trench isolation region ST1.

[0063] According to an embodiment of the present invention, each BJT element 10 further includes a dielectric layer 210 disposed on the substrate 100 and covering the emitter region ER, the base region BR, and the collector region CR. According to an embodiment of the present invention, the dielectric layer 210 is, for example, a silicon oxide layer or a low dielectric constant material layer, but is not limited thereto. According to an embodiment of the present invention, each BJT element 10 further includes an emitter contact CT1 located in the dielectric layer 210 and electrically connected to the emitter self-aligned silicide layer SAC1; a base contact CT2 located in the dielectric layer 210 and electrically connected to the base self-aligned silicide layer SAC2; and a collector contact CT3 located in the dielectric layer 210 and electrically connected to the collector self-aligned silicide layer SAC3. According to an embodiment of the present invention, for example, the emitter contact CT1, the base contact CT2, and the collector contact CT3 include tungsten.

[0064] Please refer to Figures 3 to 5 , which is a schematic diagram of a method for forming a bipolar junction transistor (BJT) element according to an embodiment of the present invention. AsFigure 3 As shown, the BJT element 10 is formed on a substrate 100, for example, a silicon substrate. According to an embodiment of the present invention, the substrate 100 has a first conductivity type, for example, P-type. A first ion trap 110 of a second conductivity type is formed in the substrate 100, where the second conductivity type is, for example, N-type. Then, a second ion trap 120 of the first conductivity type, for example, a P-type well, is formed in the first ion trap 110, and a third ion trap 130 of the second conductivity type, for example, an N-type well, is formed inside the first ion trap 110 and around the second ion trap 120.

[0065] According to an embodiment of the present invention, the BJT element 10 includes a central emitter region ER, a ring-shaped base region BR surrounding the emitter region ER, and a ring-shaped collector region CR surrounding the base region BR and the emitter region ER. After forming the second ion trap 120 and the third ion trap 130, a shallow trench isolation fabrication process is performed to form a first trench isolation region ST1 surrounding the emitter region ER, a second trench isolation region ST2 surrounding the base region BR, and a third trench isolation region ST3 surrounding the collector region CR.

[0066] Then, an oxidation fabrication process is performed to form a thick silicon oxide layer GOX1, a thick silicon oxide layer GOX2, and a thick silicon oxide layer GOX3 on the substrate 100 within the emitter region ER, the base region BR, and the collector region CR, respectively. The thicknesses of the thick silicon oxide layer GOX1, the thick silicon oxide layer GOX2, and the thick silicon oxide layer GOX3 are equal to the gate oxide layer thickness of a medium-voltage element. Then, an etch mask HM, for example, a photoresist pattern, is formed on the emitter region ER. The etch mask HM covers the thick silicon oxide layer GOX1 but exposes the thick silicon oxide layer GOX2 and the thick silicon oxide layer GOX3. According to an embodiment of the present invention, the etch mask HM may also cover the first trench isolation region ST1 surrounding the emitter region ER.

[0067] As Figure 4 shown, then an etching fabrication process, for example, a dry etching fabrication process, is performed to etch the thick silicon oxide layer GOX2 and the thick silicon oxide layer GOX3 not covered by the etch mask HM, and shielding silicon oxide layers GOS1, GOS2, and GOS3 with different thicknesses are formed in the emitter region ER, the base region BR, and the collector region CR, respectively.

[0068] Several ion implantation fabrication processes are further performed to inject different dopants into the substrate 100 within the emitter region ER, the base region BR, and the collector region CR through the shielding silicon oxide layers GOS1, GOS2, and GOS3, respectively, so as to form a heavily doped region DR1 of the second conductivity type, a heavily doped region DR2 of the first conductivity type, and a heavily doped region DR3 of the second conductivity type. According to an embodiment of the present invention, for example, the heavily doped region DR1 may be a medium-voltage N + doped region, and the heavily doped region DR2 may be a low-voltage P +The doped region, the heavily doped region DR3 can be a low-voltage N + doped region.

[0069] According to an embodiment of the present invention, the junction depth JD1 of the heavily doped region DR1 in the emitter region ER is deeper than the junction depth JD2 of the heavily doped region DR2 in the base region or the junction depth JD3 of the heavily doped region DR3 in the collector region CR. According to an embodiment of the present invention, the doping concentration of the heavily doped region DR1 in the emitter region ER is greater than the doping concentration of the heavily doped region DR3 in the collector region CR.

[0070] As Figure 5 shown, then the shielding silicon oxide layer GOS1, the shielding silicon oxide layer GOS2, and the shielding silicon oxide layer GOS3 are removed, and a recessed region RR is formed between the top surface of the emitter region ER and the first trench isolation region ST1. Then, a self-aligned silicided metal manufacturing process is performed to form an emitter self-aligned silicide layer SAC1 on the emitter region ER; a base self-aligned silicide layer SAC2 is formed on the base region BR; and a collector self-aligned silicide layer SAC3 is formed on the collector region CR. According to an embodiment of the present invention, the top surface of the emitter self-aligned silicide layer SAC1 is lower than the top surface of the base self-aligned silicide layer SAC2 and the top surface of the collector self-aligned silicide layer SAC3. According to an embodiment of the present invention, the emitter self-aligned silicide layer SAC1, the base self-aligned silicide layer SAC2, and the collector self-aligned silicide layer SAC3 contain, for example, cobalt silicide or nickel silicide.

[0071] Next, a chemical vapor deposition manufacturing process is performed to form a dielectric layer 210 on the substrate 100, so that the dielectric layer 210 covers the emitter region ER, the base region BR, and the collector region CR. Finally, an emitter contact CT1, a base contact CT2, and a collector contact CT3 are respectively formed in the dielectric layer 210 and are electrically connected to the emitter self-aligned silicide layer SAC1, the base self-aligned silicide layer SAC2, and the collector self-aligned silicide layer SAC3. According to an embodiment of the present invention, the emitter contact SAC1, the base contact SAC2, and the collector contact SAC3 contain, for example, tungsten.

[0072] The advantages of the present invention are that when performing the ion implantation manufacturing process of the heavily doped region DR1 in the emitter region ER, a relatively thick shielding silicon oxide layer GOS1 is retained on the emitter region ER. Therefore, the mismatch problem encountered by large-area low-voltage NPN BJT components in the semiconductor high-voltage manufacturing process can be improved. In addition, by forming a heavily doped region DR1 with a relatively high doping concentration in the emitter region ER, such as a medium-voltage N + doped region, the Delta beta value of the BJT component 10 can be improved, and the component operation efficiency can be enhanced.

[0073] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A bipolar junction transistor device, comprising: A substrate of a first conductivity type; A first ion trap of a second conductivity type, located in the substrate, wherein, The second conductivity type is opposite to the first conductivity type; A second ion trap of the first conductivity type, located in the first ion trap; An emitter region of the second conductivity type, located in the second ion trap; A first trench isolation region, surrounding the emitter region; A base region of the first conductivity type, located in the second ion trap, wherein the base region surrounds the first trench isolation region; A second trench isolation region, surrounding the base region; A third ion trap of the second conductivity type, located in the first ion trap and surrounding the second ion trap; And A collector region of the second conductivity type, located in the third ion trap and surrounding the second trench isolation region, wherein the junction depth of the emitter region is deeper than the junction depth of the base region or the junction depth of the collector region.

2. The bipolar junction transistor element according to claim 1, wherein The doping concentration of the emitter region is greater than the doping concentration of the collector region.

3. The bipolar junction transistor element according to claim 1, wherein, It further comprises: An emitter silicide layer, disposed on the emitter region; A base silicide layer, disposed on the base region; and A collector silicide layer, disposed on the collector region.

4. The bipolar junction transistor element according to claim 3, wherein, The top surface of the emitter silicide layer is lower than the top surfaces of the base silicide layer and the collector silicide layer.

5. The bipolar junction transistor element according to claim 4, wherein, The emitter silicide layer, the base silicide layer, and the collector silicide layer comprise cobalt silicide or nickel silicide.

6. The bipolar junction transistor element according to claim 4, wherein, It further comprises: A recessed region, located between the top surface of the emitter silicide layer and the first trench isolation region.

7. The bipolar junction transistor element according to claim 1, wherein, It further comprises: A dielectric layer, located on the substrate and covering the emitter region, the base region, and the collector region; An emitter contact, located in the dielectric layer and electrically connected to the emitter silicide layer; A base contact, located in the dielectric layer and electrically connected to the base silicide layer; And A collector contact, located in the dielectric layer and electrically connected to the collector silicide layer.

8. The bipolar junction transistor element according to claim 7, wherein, The emitter contact, the base contact, and the collector contact comprise tungsten.

9. The bipolar junction transistor element according to claim 1, wherein, The first conductivity type is P-type, and the second conductivity type is N-type.

10. The bipolar junction transistor element according to claim 1, wherein The substrate comprises a silicon substrate.

11. A method for forming a bipolar junction transistor device, comprising: Providing a substrate of a first conductivity type; A first ion trap of a second conductivity type is formed in the substrate, wherein, The second conductivity type is opposite to the first conductivity type; Forming a second ion trap of the first conductivity type in the first ion trap; Forming an emitter region of the second conductivity type in the second ion trap; Forming a first trench isolation region surrounding the emitter region; Forming a base region of the first conductivity type in the second ion trap, wherein the base region surrounds the first trench isolation region; Forming a second trench isolation region surrounding the base region; Forming a third ion trap of the second conductivity type inside the first ion trap and around the second ion trap; and Forming a collector region of the second conductivity type surrounding the second trench isolation region in the third ion trap, wherein the junction depth of the emitter region is deeper than the junction depth of the base region or the junction depth of the collector region.

12. The method according to claim 11, wherein The doping concentration of the emitter region is greater than the doping concentration of the collector region.

13. The method according to claim 11, wherein It further comprises: Forming an emitter silicide layer on the emitter region; Forming a base silicide layer on the base region; and Forming a collector silicide layer on the collector region.

14. The method according to claim 13, wherein, The top surface of the emitter silicide layer is lower than the top surfaces of the base silicide layer and the collector silicide layer.

15. The method according to claim 14, wherein, The emitter silicide layer, the base silicide layer, and the collector silicide layer comprise cobalt silicide or nickel silicide.

16. The method according to claim 14, wherein, It further comprises: A recessed region is formed between the top surface of the emitter silicide layer and the first trench isolation region.

17. The method according to claim 11, wherein, It further includes: A dielectric layer is formed on the substrate, and the dielectric layer covers the emitter region, the base region, and the collector region; An emitter contact is formed in the dielectric layer and electrically connected to the emitter silicide layer; A base contact is formed in the dielectric layer and electrically connected to the base silicide layer; And A collector contact is formed in the dielectric layer and electrically connected to the collector silicide layer.

18. The method according to claim 17, wherein, The emitter contact, the base contact, and the collector contact contain tungsten.

19. The method according to claim 11, wherein, The first conductivity type is P-type, and the second conductivity type is N-type.

20. The method according to claim 11, wherein, The substrate includes a silicon substrate.

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