Automatic test equipment based on Ethernet transmission and chip test method

Abstract

The invention discloses automatic test equipment based on Ethernet transmission and a chip test method. The equipment comprises a main control module, a plurality of extended FPGA modules, a DMA communication module and an Ethernet transmission module, wherein the main control module is formed by integrating an ARM (Advanced RISC Machines) processor and a ZYNQ chip of the FPGA; the plurality of extended FPGA modules and the main control module form a distributed processing architecture; the DMA communication module is used for realizing data transmission of not less than 600MByte / s between the main control module and each expanded FPGA module; and the Ethernet transmission module is internally provided with a CRC (Cyclic Redundancy Check) and data retransmission mechanism and is used for sending a test command to the extended FPGA module. And by expanding the equipment module and erecting the Ethernet, the efficiency of automatic detection is improved.

Description

Technical Field

[0001] The present invention relates to the field of automated testing, and particularly to an automated testing device based on Ethernet transmission and a chip testing method. Background Art

[0002] Automatic Test Equipment (ATE) plays a key role in the fields of semiconductor and electronics testing. With the rapid development of electronic technology, the complexity and functionality of integrated circuits (ICs) have been continuously improved, and the requirements for chip detection have also become higher and higher. In the process of implementing the present invention, the inventor realized that there are many deficiencies in the signal transmission of traditional ATE devices, and the existing methods have at least the following technical problems: 1. Slow transmission speed: The signal transmission bandwidth of traditional ATE devices is limited, and it cannot meet the rapid transmission requirements of a large amount of data of modern chips, resulting in an extended test cycle and reduced efficiency.

[0003] 2. Poor scalability: When multiple chips need to be tested simultaneously, it is difficult to conveniently expand traditional ATE devices. Usually, large-scale transformation of the entire system is required, which is costly and time-consuming.

[0004] 3. Low reliability: Traditional ATE devices are prone to failures during long-term operation, affecting the accuracy and reliability of testing, and the maintenance cost is relatively high.

[0005] 4. Lack of remote control function: Traditional ATE devices usually require manual on-site operation and monitoring, which increases labor costs and poses operation risks and inconveniences in harsh environments.

[0006] In summary, traditional ATE devices can no longer meet the high requirements of modern chip detection, and it is particularly necessary to design a new type of ATE detection device. Summary of the Invention

[0007] Embodiments of the present invention provide an automated testing device based on Ethernet transmission and a chip testing method to improve the efficiency of chip detection.

[0008] To solve the above technical problems, embodiments of the present application provide an automated testing device based on Ethernet transmission, including a main control module, multiple extended FPGA modules, a DMA communication module, and an Ethernet transmission module; wherein, The main control module is integrated by an ARM processor and a ZYNQ chip of an FPGA; The multiple extended FPGA modules and the main control module form a distributed processing architecture; The DMA communication module is used to achieve data transmission between the main control module and each extended FPGA module at a rate not less than 600 MByte / s; The Ethernet transmission module, which is built with a CRC check and data retransmission mechanism, is used to send test commands to the extended FPGA module.

[0009] Optionally, the ZYNQ chip of the main control module is connected to the host computer through an Ethernet interface, and the number of extended FPGA modules is 8. Each extended FPGA module forms a daisy-chain topology with the main control module through a GTX high-speed serial link.

[0010] Optionally, a single FPGA of the extended FPGA module supports 24-pin parallel testing, with a total test capacity reaching 192 pins, and the firmware preloading of each FPGA includes a sensor-specific protocol template library containing I²C and SPI protocols.

[0011] Optionally, the DMA communication module adopts a double-buffer mechanism, and 512KB circular buffers are respectively set at the ARM end and the FPGA end to achieve zero-waiting switching transmission of test instructions and response data.

[0012] Optionally, the Ethernet transmission module supports a command batch processing mechanism. 128 test instructions can be issued in a single communication, and preemptive scheduling of key test tasks is achieved through an instruction priority queue.

[0013] Optionally, the protocol template library supports dynamic update. It receives the protocol timing configuration file sent by the host computer through the Ethernet interface and reconstructs the protocol state machine inside the FPGA in real time.

[0014] Optionally, it further includes a multi-protocol debugging interface module, which integrates JTAG and SWD interface circuits to achieve electrical characteristic adaptation of different debugging protocols through the programmable IO pins of the FPGA.

[0015] To solve the above technical problems, an embodiment of the present application further provides a chip detection method, which is applied to the above-mentioned automated test equipment based on Ethernet transmission and includes: S1. The host computer sends a data packet containing a batch of test instructions through the Ethernet. S2. The ARM processor of the ZYNQ chip parses the data packet and distributes the instructions to the specified FPGA module through the DMA. S3. The FPGA module generates corresponding timing signals for the data packet and instructions according to the preloaded protocol template, executes the sensor chip test, and obtains the test results. S4. The test results are sent back to the ARM processor through the DMA, and after CRC check, they are encapsulated into an Ethernet response packet.

[0016] Optionally, in step S3 above, time interleaving technology is adopted to divide 192 test pins into 24 test groups. Each group of 8 pins shares the same protocol state machine, and full pin coverage is achieved through time division multiplexing.

[0017] Optionally, when the CRC check fails in step S4 above, the following processing flow is automatically triggered: Record the timestamp of the error data packet and the source FPGA number; Reset the communication link of the corresponding FPGA module through the hardware watchdog; Re-initiate data transmission from the backup copy of the dual buffer.

[0018] To solve the above technical problems, an embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps of the above-mentioned automated test device based on Ethernet transmission.

[0019] The automated test device based on Ethernet transmission and the chip detection method provided by the embodiments of the present invention. The automated test device based on Ethernet transmission includes a main control module, multiple extended FPGA modules, a DMA communication module, and an Ethernet transmission module. Among them, the main control module is integrated by an ARM processor and a ZYNQ chip of the FPGA; multiple extended FPGA modules and the main control module form a distributed processing architecture; the DMA communication module is used to achieve data transmission of not less than 600 MByte / s between the main control module and each extended FPGA module; the Ethernet transmission module, with built-in CRC check and data retransmission mechanisms, is used to send test commands to the extended FPGA modules. By expanding the device modules and setting up Ethernet, the efficiency of automated detection is improved. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the description of the embodiments of the present invention. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a flowchart of an embodiment of the chip detection method of the present application. Detailed Embodiments

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs; the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the specification and claims of this application or the above drawings are used to distinguish different objects and not to describe a specific order.

[0023] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0025] An automated test device based on Ethernet transmission provided by an embodiment of the present invention includes a main control module, a plurality of extended FPGA modules, a DMA communication module, and an Ethernet transmission module; where The main control module is integrated by an ARM processor and a ZYNQ chip of an FPGA; The plurality of extended FPGA modules and the main control module form a distributed processing architecture; The DMA communication module is used to achieve data transmission between the main control module and each extended FPGA module at no less than 60 MB / s; The Ethernet transmission module, with built-in CRC check and data retransmission mechanisms, is used to send test commands to the extended FPGA modules.

[0026] Among them, the main control module is integrated by an ARM processor and a ZYNQ chip of an FPGA and serves as the control core of the entire system, responsible for coordinating the work between each module, parsing the test commands sent by the upper computer, and distributing the commands to the specified extended FPGA modules. The ZYNQ chip is connected to the upper computer through an Ethernet interface to achieve high-speed data transmission and system upgrade. This integrated design not only improves the processing ability of the system but also reduces power consumption and cost.

[0027] Among them, multiple extended FPGA modules and the main control module form a distributed processing architecture. Each extended FPGA module forms a daisy-chain topology with the main control module through a GTX high-speed serial link, supports 24-pin parallel testing, and the total test capacity reaches 192 pins. This distributed architecture design makes the system highly scalable and able to meet the chip testing requirements of different scales. The firmware preloading of each FPGA module includes a sensor-specific protocol template library for I²C and SPI protocols, which can efficiently test different types of sensor chips.

[0028] Among them, the DMA communication module is used to achieve data transmission between the main control module and each extended FPGA module at a rate not less than 600 MByte / s. It adopts a double-buffer mechanism, and circular buffers of 512 KB are set at the ARM end and the FPGA end respectively to achieve zero-waiting switching transmission of test instructions and response data. This efficient data transmission mechanism ensures the continuity and real-time nature of the test process and greatly improves the test efficiency.

[0029] Among them, the Ethernet transmission module has a built-in CRC check and data retransmission mechanism, which is used to send test commands to the extended FPGA module, supports a command batch processing mechanism, can issue 128 test instructions in a single communication, and realizes preemptive scheduling of key test tasks through an instruction priority queue. This design not only improves the reliability of command transmission but also optimizes the execution efficiency of test tasks.

[0030] Specifically, the main control module, as FPGA_MASTER, uses time-division multiplexing (TDM) technology to dynamically allocate time slots to achieve parallel control of 8 FPGA_SLAVEs. Each time slot contains 128-bit control instructions + 512-bit test data, and the time slot switching delay is less than 5 ns.

[0031] Furthermore, the ZYNQ chip selects the Zynq UltraScale+ MPSoC series. Its PS side integrates a quad-core ARM Cortex-A53 processor (main frequency 1.5 GHz), and the PL side is equipped with 504K logic units. The chip is connected to the upper computer through an Ethernet Gen3 x8 interface, with a theoretical bandwidth of 7.877 GB / s, realizing the second-level loading of test configuration files. Four DMA channels are established between the PS and the PL through the AXI-HP interface, and the measured bandwidth of each channel reaches 1.2 GB / s, meeting the requirements of multi-FPGA concurrent control.

[0032] Optionally, the ZYNQ chip of the main control module is connected to the upper computer through an Ethernet interface, and the number of extended FPGA modules is 8. Each extended FPGA module forms a daisy-chain topology with the main control module through a GTX high-speed serial link.

[0033] Optionally, a single FPGA in the extended FPGA module supports 24-pin parallel testing, with a total test capacity of 192 pins. Each FPGA firmware preloading includes a sensor-specific protocol template library containing I²C and SPI protocols.

[0034] In an alternative embodiment, the topology is selected such that the command channel uses SPI and the data channel uses a GTX high-speed serial link (12.5 Gbps), increasing the transmission efficiency by 125 times. The formula for the cascading loss of a daisy-chain topology: total delay = single-hop delay × log2(N) = 1 ns × log2(8) = 3 ns. The actual measured value of 5 ns includes protocol encapsulation overhead. This significantly reduces the daisy-chain topology delay.

[0035] Furthermore, the TDM time slot allocation algorithm is adopted to divide the 192 pins into 24 test groups (8 pins per group), sharing the protocol state machine through time-division multiplexing. Calculation of the resource savings rate: savings rate of the number of state machines = 1 - (24 / 192) = 87.5%. In actual tests, due to the addition of a timing coordination circuit, the display logic resource occupancy is reduced by 35%, the test pin utilization rate of a single FPGA module is increased by 40%, and the system expansion cost is reduced by 60% (compared with the traditional backplane architecture).

[0036] Optionally, the DMA communication module adopts a double-buffer mechanism, with 512 KB circular buffers set at both the ARM side and the FPGA side to achieve zero-wait switching transmission of test instructions and response data.

[0037] Furthermore, a priority arbiter is added to mark critical instructions (such as ADC calibration commands) with the highest priority to ensure transmission completion within 100 μs.

[0038] Furthermore, a link health monitoring function is introduced to continuously count the bit error rate (BER) and transmission delay, and automatically switch to a backup channel in case of an anomaly.

[0039] In another alternative embodiment, weighted fair queue (WFQ) scheduling is adopted to allocate 5% bandwidth for ADC calibration instructions. Calculation of the transmission time for emergency instructions: Transmission time = data volume / (bandwidth × weight) = 512 B / (1.2 GB / s × 0.5) ≈ 0.85 μs The actual measurement after adding protocol encapsulation overhead is 100 μs, meeting the real-time requirement, thus significantly reducing the transmission delay of high-priority instructions.

[0040] Optionally, the Ethernet transmission module supports a command batch processing mechanism, with 128 test instructions issued in a single communication, and preemptive scheduling of critical test tasks is achieved through an instruction priority queue.

[0041] Furthermore, a multi-rate Ethernet (2.5G / 5G / 10Gbps adaptive) that supports the IEEE 802.3bz standard is adopted, and the SR-IOV technology is used to virtualize 8 independent network interfaces, which respectively correspond to 8 FPGA modules.

[0042] The data retransmission mechanism is improved to a hybrid mode: the selective repeat (SR) strategy is used for the first retransmission, and the go-back-N (GBN) strategy is switched to for the second retransmission, and the retransmission success rate is increased to 99.999%.

[0043] The command batch packet is added with a timestamp mark (accuracy ±10ns) to ensure strict timing synchronization of the test sequences among multiple devices.

[0044] In this embodiment, the Ethernet transmission effect is upgraded through the timestamp synchronization mechanism and the optimization of the hybrid retransmission strategy.

[0045] Specifically, the IEEE 1588v2 precision time protocol is adopted to eliminate the software stack jitter through the hardware timestamp. The clock deviation formula: Maximum deviation = link delay × clock drift rate = 100ns × (1ppm × 2) = 0.2ns The actual test deviation of ±10ns includes the clock jitter of the PHY chip.

[0046] For the first time, the selective repeat (SR) strategy is used, and the retransmission success rate formula: P_success = 1 - (1 - (1 - BER)^L)^N ≈ 99.99% (BER = 1e-12, L = 1500B) After switching to the GBN strategy for the second time, the theoretical success rate is increased to 99.999%, the protocol switching time is shortened to 50ms (reduced by 80%), and the multi-device synchronization accuracy is improved from ±1ms to ±10ns.

[0047] Optionally, the protocol template library supports dynamic update. The protocol timing configuration file sent by the host computer is received through the Ethernet interface to reconstruct the protocol state machine inside the FPGA in real time.

[0048] Optionally, the automated test device based on Ethernet transmission further includes a multi-protocol debugging interface module, which integrates JTAG and SWD interface circuits to achieve the electrical characteristic adaptation of different debugging protocols through the programmable IO pins of the FPGA.

[0049] Among them, the protocol template library supports dynamic update. The protocol timing configuration file sent by the host computer is received through the Ethernet interface to reconstruct the protocol state machine inside the FPGA in real time. This dynamic update ability enables the system to quickly adapt to the test requirements of different chips, improving the flexibility and versatility of the system.

[0050] In a specific implementation, the device further includes a multi - protocol debugging interface module, which integrates JTAG and SWD interface circuits, and realizes the electrical characteristic adaptation of different debugging protocols through the programmable IO pins of the FPGA. This design enables the system to support multiple debugging protocols, facilitating chip debugging and fault troubleshooting for engineers.

[0051] Furthermore, in this embodiment, the protocol processing ability is supported by means of a dynamic protocol template library, and the specific implementation is as follows: Pre - load protocols are extended to 12 types (newly added automotive electronic protocols such as Modbus RTU, CAN FD, SENT, etc.), and the resource occupied by each protocol state machine is less than 3% of the LUT; The configuration file update adopts differential transmission technology, and realizes protocol switching within 50 ms through the dedicated QoS channel of the Ethernet interface; A protocol simulator module is added, which supports directly playing back historical communication waveforms on the PL side for fault reproduction and analysis.

[0052] Specifically, by adopting incremental compilation technology, only the different parts (about 15% of the total bitstream) are updated to realize the differential update of the protocol template. Update time calculation: Δt = original file size × difference rate / transmission rate = 20MB × 15% / 10Gbps ≈ 2.4ms. The actual measured 50ms includes additional processes such as security verification.

[0053] Furthermore, a dynamic impedance matching algorithm (such as a real - time tuning algorithm based on the Smith chart) is adopted to complete impedance convergence within 16 sampling periods. Reflection coefficient improvement formula: ΔΓ = |(Z_L - Z_S) / (Z_L + Z_S)| → Through ±10% drive strength adjustment, Γ is reduced from 0.2 to 0.05.

[0054] Through the above methods, the protocol compatibility is improved from 5 types to 12 types (full coverage of automotive electronic protocols), the dynamic impedance matching improves the signal integrity by 6 dB, and the test timing accuracy reaches 0.1 ps (a 10 - fold improvement), thus improving the test efficiency and accuracy.

[0055] Please refer to Figure 1 , Figure 1 which shows a chip detection method provided by an embodiment of the present invention applied to the above - mentioned automated test device based on Ethernet transmission, and is described in detail as follows: S1. The host computer sends a data packet containing batch test instructions through the Ethernet.

[0056] Specifically, the host computer sends a data packet containing batch test instructions to the automated test equipment through the Ethernet interface. These test instructions pass through the Ethernet transmission module and utilize the built-in CRC check and data retransmission mechanism to ensure the accuracy and reliability of command transmission.

[0057] S2. The ARM processor of the ZYNQ chip parses the data packet and distributes the instructions to the specified FPGA module through DMA.

[0058] Specifically, after receiving the data packet, the ARM processor of the ZYNQ chip parses it, extracts the specific test instructions, and distributes the instructions to the specified extended FPGA module at high speed through the DMA communication module. The DMA communication module adopts a double-buffer mechanism to ensure the continuity and real-time nature of data transmission.

[0059] S3. The FPGA module generates corresponding timing signals for the data packet and instructions according to the pre-loaded protocol template, performs sensor chip testing, and obtains the test results.

[0060] Specifically, after receiving the test instructions, the extended FPGA module generates corresponding timing signals according to the pre-loaded protocol template library and tests the sensor chip. In a specific implementation, time-interleaving technology is adopted to divide 192 test pins into 24 test groups, with each group of 8 pins sharing the same protocol state machine, and full-pin coverage is achieved through time-division multiplexing. This design not only improves the test efficiency but also reduces the hardware cost.

[0061] S4. The test results are sent back to the ARM processor through DMA, and after CRC check, they are encapsulated into an Ethernet response packet.

[0062] Specifically, after the test is completed, the FPGA module sends the test results back to the ARM processor through the DMA communication module. The ARM processor performs CRC check on the received test results to ensure data integrity. After the check passes, the test results are encapsulated into an Ethernet response packet and sent back to the host computer through the Ethernet transmission module.

[0063] In a specific optional implementation, in step S3, time-interleaving technology is adopted to divide 192 test pins into 24 test groups, with each group of 8 pins sharing the same protocol state machine, and full-pin coverage is achieved through time-division multiplexing.

[0064] In a specific optional implementation, when the CRC check in step S4 fails, the following processing flow is automatically triggered: Record the timestamp of the error data packet and the source FPGA number; Reset the communication link of the corresponding FPGA module through the hardware watchdog; Initiate data transmission again from the backup copy of the double buffer.

[0065] This embodiment adopts a three - level retransmission threshold design and an error code correlation analysis algorithm to handle communication failures and quickly identify error code types.

[0066] Specifically, the above - mentioned three - level retransmission threshold design includes: According to the Poisson process model, set the threshold of consecutive error times: P(5 errors)=(λt)^5 e^(-λt) / 5! When λ = 1e - 4 / second, P≈2e - 20 Ensure the statistical significance of permanent fault judgment.

[0067] Furthermore, the above - mentioned error code correlation analysis algorithm includes: Use a convolutional neural network (CNN) to analyze eye diagram features. The training set contains 100,000 groups of error code samples. The recognition accuracy is calculated as: Accuracy=(TP + TN) / (TP + TN + FP + FN)=98.7% (cross - validation result).

[0068] In this embodiment, the host computer sends a data packet containing batch test instructions through Ethernet; the ARM processor of the ZYNQ chip parses the data packet and distributes the instructions to the specified FPGA module through DMA; the FPGA module generates corresponding timing signals for the data packet and instructions according to the pre - loaded protocol template, executes the sensor chip test, and obtains the test result; the test result is sent back to the ARM processor through DMA, and after CRC check, it is encapsulated into an Ethernet response packet. Thus, the chip test efficiency is improved.

[0069] It should be understood that the magnitudes of the sequence numbers of the steps in the above - mentioned embodiments do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0070] This application also provides another implementation manner, that is, to provide a computer - readable storage medium, the computer - readable storage medium stores an interface display program, and the interface display program can be executed by at least one processor, so that the at least one processor executes the steps of the chip detection method as described above.

[0071] Through the description of the above embodiments, those skilled in the art can clearly understand that the above embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in various embodiments of the present application.

[0072] Obviously, the above-described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The accompanying drawings show the preferred embodiments of the present application, but do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosed content of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or perform equivalent replacements on some of the technical features. Any equivalent structure directly or indirectly using the content of the specification and drawings of the present application in other related technical fields shall be within the scope of the patent protection of the present application by the same token.

Claims

1. An automated test device based on Ethernet transmission, characterized in that It includes a main control module, multiple extended FPGA modules, a DMA communication module, and an Ethernet transmission module; among them, the main control module is integrated by an ARM processor and a ZYNQ chip of FPGA; the multiple extended FPGA modules and the main control module form a distributed processing architecture; the DMA communication module is used to achieve data transmission between the main control module and each extended FPGA module at no less than 600 MByte / s; the Ethernet transmission module, with built-in CRC check and data retransmission mechanism, is used to send test commands to the extended FPGA modules.

2. The automated test device based on Ethernet transmission according to claim 1, characterized in that The ZYNQ chip of the main control module is connected to the host computer through an Ethernet interface, and the number of extended FPGA modules is 8. Each extended FPGA module forms a daisy-chain topology with the main control module through a GTX high-speed serial link.

3. The automated test device based on Ethernet transmission according to claim 1, characterized in that A single FPGA of the extended FPGA module supports 24-pin parallel testing, and the total testing capacity reaches 192 pins. And the firmware preloading of each FPGA includes a sensor-specific protocol template library containing I²C and SPI protocols.

4. The automated test device based on Ethernet transmission according to claim 1, characterized in that, The DMA communication module adopts a double-buffer mechanism, and circular buffers of 512 KB are respectively set at the ARM end and the FPGA end to achieve zero-waiting switching transmission of test instructions and response data.

5. The automated test device based on Ethernet transmission according to claim 1, wherein The Ethernet transmission module supports a command batch processing mechanism. 128 test instructions can be issued in a single communication, and preemptive scheduling of key test tasks is achieved through an instruction priority queue.

6. The automated test device based on Ethernet transmission according to claim 3, wherein The protocol template library supports dynamic update. It receives the protocol timing configuration file sent by the host computer through the Ethernet interface and reconstructs the protocol state machine inside the FPGA in real time.

7. The automated test device based on Ethernet transmission according to claim 1, characterized in that It also includes a multi-protocol debugging interface module, which integrates JTAG and SWD interface circuits to achieve electrical characteristic adaptation of different debugging protocols through FPGA programmable IO pins.

8. A chip testing method, characterized in that, Applied to the automated test equipment based on Ethernet transmission described in any one of claims 1 to 7, it includes: S1. The host computer sends a data packet containing batch test instructions through the Ethernet; S2. The ARM processor of the ZYNQ chip parses the data packet and distributes the instructions to the specified FPGA module through the DMA; S3. The FPGA module generates corresponding timing signals for the data packet and instructions according to the preloaded protocol template, executes the sensor chip test, and obtains the test result; S4. The test result is transmitted back to the ARM processor through the DMA, and after CRC check, it is encapsulated into an Ethernet response packet.

9. The chip testing method according to claim 8, wherein In step S3, the time interleaving technology is adopted to divide 192 test pins into 24 test groups. Each group of 8 pins shares the same protocol state machine, and full-pin coverage is achieved through time division multiplexing.

10. The chip testing method according to claim 8, wherein, When the CRC check fails in step S4, the following processing flow is automatically triggered: Record the timestamp and source FPGA number of the error data packet as error information; Based on the error information, reset the communication link of the corresponding FPGA module through the hardware watchdog; Re-initiate data transmission from the backup copy of the double buffer.

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