Electric control hardware test bench and test method

Abstract

The invention discloses an electric control hardware test bench and a test method. The electric control hardware test bench comprises a preparation module, an input module, a data test module and a bus test module. According to the invention, by replacing the tested equipment of the test bench, various controller hardware can be tested, the universality is high, the test cost is low, and the test efficiency is high; a test scheme can be designed according to tested equipment, test items can be flexibly increased and decreased to meet test requirements, higher flexibility and sufficiency are achieved, and the test is more accurate and efficient; in addition, the test development period is short, the abnormal condition is sent to the upper computer in time when the abnormity occurs in the test process, the test abnormity can be processed in time, and the stability and the reliability are high.

Description

Technical Field

[0001] The present invention relates to hardware testing of automotive controllers, and particularly to an electronic control hardware test bench and a test method. Background Art

[0002] Hardware testing of automotive controllers is an important link in controller development. In the FT, ET, and PT stages of controller design, it is necessary to strictly test the hardware performance of the controller, improve the controller design based on the test results. The adequacy of testing directly determines the hardware quality of the controller, the testing cost is directly allocated to the cost of the controller, the development cycle of the testing equipment directly affects the delivery cycle of the controller, and the testing efficiency directly affects the production efficiency of the controller.

[0003] Currently, there are various standard controller hardware test benches on the market. Such benches can only be used for testing simple controllers, such as traditional gateways with CAN, LIN, and a small number of IO functions. There are also customized controller hardware design benches on the market, which can only be used for testing controller hardware with clear and fixed requirements. These two types of benches have disadvantages such as insufficient testing, poor testing quality, high testing cost, long development cycle of testing equipment, and low testing efficiency.

[0004] In the prior art, there are test benches for manually building and modifying controller hardware, but such benches have insufficient testing of hardware performance, poor testing quality, high testing cost, and low testing efficiency. In the prior art, there are also customized dedicated controller hardware test benches, but their customization cycle is long, requiring 9 - 18 months, and they can only test simple controller hardware, or test some of their functions, and cannot test complex controller hardware. And the standard hardware test benches that can be purchased on the market today can only test simple controller hardware, or test some of their functions, and cannot test complex controller hardware. Summary of the Invention

[0005] To solve the problems of insufficient testing, poor testing quality, and low testing efficiency of the test bench in the prior art, the present invention provides an electronic control hardware test bench and a test method. For this purpose, the technical solution adopted by the present invention is as follows:

[0006] An electronic control hardware test bench is provided, including:

[0007] A preparation module, configured to send a first handshake request to the device under test and wait for receiving a first response message; and after receiving the first response message and the ready message in sequence within a preset time, set the signal inputs of each signal input module to an effective state and wait for receiving a first input test data message;

[0008] An input module, which is used to set the signal input to an invalid state after receiving the first input test data packet and wait for receiving the second input test data packet; after receiving the second input test data packet within a preset time, save the input test data.

[0009] A data test module, which is used to set a test scheme and test and collect the output test data of each group of test output modules according to the test scheme and the input test data, save the output test data and send it to the host computer.

[0010] A bus test module, which is used to send a second handshake request and a third handshake request to the device under test from the CAN bus and the LIN bus in sequence after sending the output test data and wait for receiving the second response packet and the third response packet in sequence; and after receiving the second response packet and the third response packet in sequence within a preset time, save the CAN bus test data and the LIN bus test data of this item and send it to the host computer.

[0011] According to the above scheme, the preparation module is further used to: if the first response packet is not received within a preset time, set a handshake exception and send the exception message to the host computer; and if the ready packet is not received within a preset time, set a ready exception and send the exception message to the host computer.

[0012] According to the above scheme, the input module is further used to: if the first input test data packet is not received within a preset time, set an input exception and send the exception message to the host computer; and if the second input test data packet is not received within a preset time, set an input exception and send the exception message to the host computer.

[0013] According to the above scheme, the bus test module is further used to: if the second response packet is not received within a preset time, set an exception for this CAN bus and send the exception message to the host computer; and if the third response packet is not received within a preset time, set an exception for this LIN bus and send the exception message to the host computer.

[0014] According to the above scheme, it further includes a display module, which is used to display, save and print the test data and abnormal results received by the host computer.

[0015] According to the above scheme, the signal input module includes an analog signal input module, a digital signal input module and a square wave signal input module.

[0016] According to the above scheme, the analog signal input module collects the analog output signal of the device under test through the analog signal acquisition port; the digital signal input module collects the digital output signal of the device under test through the digital signal input port; the square wave signal input module collects the square wave output signal of the device under test through the square wave signal input port.

[0017] According to the above scheme, the test output module includes an analog signal output module, a digital signal output module, a square wave signal output module, a sine wave signal output module, an oxygen sensor simulation module, a knock sensor simulation module, an injector simulation module, a high-pressure pump simulation module, an igniter simulation module, a throttle simulation module, a simulated load module, and a fault injection module.

[0018] According to the above scheme, the analog signal output module outputs the analog signal through the analog signal output port; the digital signal output module outputs the digital signal through the digital signal output port; the square wave signal output module outputs the square wave signal through the square wave signal output port; the sine wave signal output module outputs the sine wave signal through the sine wave signal output port; the oxygen sensor simulation module outputs the analog signal through the oxygen sensor analog output port; the knock sensor simulation module outputs the analog signal through the knock sensor analog output port; the injector simulation module outputs the analog signal through the injector simulation port; the high-pressure pump simulation module outputs the analog signal through the high-pressure pump simulation port; the igniter simulation module outputs the analog signal through the igniter simulation port; and the throttle simulation module outputs the analog signal through the throttle simulation port.

[0019] According to the above scheme, the fault injection module simulates open circuit, short circuit to power supply and short circuit to ground faults through the fault injection channel and injects them into the device under test; the simulated load module provides simulated load for the device under test through the simulated load channel.

[0020] According to the above scheme, the analog signal acquisition port, digital signal input port, square wave signal input port, analog signal output port, digital signal output port, square wave signal output port, sine wave signal output port, oxygen sensor analog output port, knock sensor analog output port, injector analog port, high pressure pump analog port, igniter analog port, and throttle analog port are respectively provided with short-circuit protection circuits for power supply and ground.

[0021] According to the above solution, each signal input module and test output module has a board card that can set module operating parameters.

[0022] According to the above scheme, the output test data of each group of test output modules is tested and collected as follows:

[0023] Set the number of test groups and the test output modules for each test group;

[0024] Send an output valid request to the device under test, test and collect test data when the output of each group of test output modules is valid according to the test plan and input test data;

[0025] After the test data when the output is valid is collected, an output invalidation request is sent to the device under test, and the test data when the output of the test output module of this group is invalid is collected to obtain the output test data of each group.

[0026] An electronic control hardware test bench test method is also provided. The method includes:

[0027] Sending a first handshake request to the device under test and waiting to receive a first response message; and after receiving the first response message and the ready message in sequence within a preset time, setting the signal inputs of each signal input module to an effective state and waiting to receive a first input test data message;

[0028] After receiving the first input test data message, setting the signal input to an invalid state and waiting to receive a second input test data message; after receiving the second input test data message within a preset time, saving the input test data;

[0029] Setting a test plan, and testing and collecting the output test data of each group of test output modules according to the test plan and the input test data, saving the output test data and sending it to the host computer;

[0030] After sending the output test data, sending a second handshake request and a third handshake request to the device under test from the CAN bus and the LIN bus in sequence, and waiting to receive the second response message and the third response message in sequence; and after receiving the second response message and the third response message in sequence within a preset time, saving the CAN bus test data and the LIN bus test data of this item and sending them to the host computer.

[0031] The beneficial effects of the present invention are as follows: By replacing the device under test on the test bench, the present invention can test various controller hardwares, with strong versatility, low test cost and high test efficiency; and a test plan can be designed according to the device under test, and test items can be flexibly increased or decreased to meet the test requirements, with higher flexibility and sufficiency, and the test is more accurate and efficient; in addition, the test development cycle of the present invention is short, and any abnormality during the test is promptly sent to the host computer, so that the test abnormality can be promptly processed, and the stability and reliability are relatively high. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of the module structure of an electronic control hardware test bench according to an embodiment of the present invention;

[0033] Figure 2 is a block diagram of an electronic control hardware test bench according to an embodiment of the present invention;

[0034] Figure 3 is a test flow block diagram of an electronic control hardware test bench according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] To make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0036] In the following embodiments, DUT represents the device under test.

[0037] Embodiment 1

[0038] In view of the deficiencies of the existing technical solutions, the embodiment of the present invention provides a general-purpose electronic control hardware test bench, which can test the performance of multiple controllers and automatically generate test reports. As Figure 1 shown, it includes:

[0039] A preparation module, configured to send a first handshake request to the device under test and wait for receiving a first response message; and after receiving the first response message and the ready message in sequence within a preset time, set the signal inputs of each signal input module to an effective state and wait for receiving a first input test data message;

[0040] An input module, configured to set the signal input to an invalid state after receiving the first input test data message and wait for receiving a second input test data message; after receiving the second input test data message within a preset time, save the input test data;

[0041] A data test module, configured to set a test scheme, and test and collect the output test data of each group of test output modules according to the test scheme and the input test data, save the output test data and send it to the upper computer;

[0042] A bus test module, configured to send a second handshake request and a third handshake request to the device under test from the CAN bus and the LIN bus in sequence after sending the output test data, and wait for receiving a second response message and a third response message in sequence; and after receiving the second response message and the third response message in sequence within a preset time, save the CAN bus test data and the LIN bus test data of this item and send them to the upper computer.

[0043] Specifically, the preparation module is further configured to: if the first response message is not received within the preset time, set a handshake exception and send an exception message to the upper computer; and if the ready message is not received within the preset time, set a ready exception and send an exception message to the upper computer.

[0044] Specifically, the input module is further configured to: if the first input test data message is not received within the preset time, set an input exception and send an exception message to the upper computer; and if the second input test data message is not received within the preset time, set an input exception and send an exception message to the upper computer.

[0045] Specifically, the bus test module is further configured to: if the second response message is not received within a preset time, set the corresponding CAN bus as abnormal and send the abnormal message to the host computer; and if the third response message is not received within a preset time, set the corresponding LIN bus as abnormal and send the abnormal message to the host computer.

[0046] In addition, the electronic control hardware test bench according to the embodiment of the present invention further includes a display module, which is configured to display, save, and print the test data and abnormal results received by the host computer.

[0047] Specifically, the signal input module includes an analog signal input module, a digital signal input module, and a square wave signal input module.

[0048] Specifically, the test output module includes an analog signal output module, a digital signal output module, a square wave signal output module, a sine wave signal output module, an oxygen sensor simulation module, a knock sensor simulation module, an injector simulation module, a high-pressure pump simulation module, an igniter simulation module, a throttle simulation module, an analog load module, and a fault injection module.

[0049] Among them, each signal input module and test output module has a board for setting the working parameters of the module.

[0050] Among them, the analog signal input module collects the analog output signal of the DUT through the analog signal acquisition port and provides an analog load for the analog output signal of the DUT. The analog signal input board of this module can be designed independently. In a preferred embodiment, the self-designed analog signal input board is specifically: the number of channels of the analog input signal is 64; the acquisition measurement accuracy of the analog input signal is 12 bits; the maximum load current of the analog input signal is 100 mA; the acquisition frequency of the analog input signal is 20 kS / s; the input acquisition accuracy of the analog input signal is 1%; the input voltage range of the measurable analog input signal is (0 - 40) V; the input port of the analog input signal is designed with a short-circuit protection circuit for power supply and ground.

[0051] Among them, the digital signal input module collects the digital output signal of the DUT through the digital signal input port and provides an analog load for the digital output signal of the DUT. The digital signal input board of this module can be designed independently. In a preferred embodiment, the self-designed digital signal input board is specifically: the number of channels of the digital input signal is 64; the maximum load current of the digital input signal is 15 mA; the acquisition frequency of the digital input signal is 200 S / s; the voltage range of the high level of the measurable digital input signal is (2.0 - 40) V, and the voltage range of the low level of the measurable digital input signal is ((-5.0) - 0.8) V; the input port of the analog input signal is designed with a short-circuit protection circuit for power supply and ground.

[0052] Among them, the square wave signal input module collects the square wave output signal of the DUT through the square wave signal input port and provides an analog load for the square wave output signal of the DUT. The square wave signal input board of this module can be designed independently. In a preferred embodiment, the self-designed square wave signal input board is specifically as follows: the number of input channels of the square wave signal is 16; the maximum load current of the square wave input signal is 15 mA; the measurable frequency range of the square wave signal is 0 - 200 kHz, and the measurement accuracy of the frequency is 1%; the measurable duty cycle range of the square wave signal is 0 - 100%, and the measurement accuracy of the duty cycle is 1%; the maximum rise time of the measurable square wave input signal is 6 μs, and the maximum fall time of the measurable square wave input signal is 4 μs; the voltage range of the high level of the measurable square wave input signal is (2 - 5) V or (2 - 3.3) V, and the voltage range of the low level of the measurable square wave input signal is (0 - 0.8) V; the square wave signal input port is designed with a short-circuit protection circuit for power supply and ground.

[0053] Among them, the analog signal output module outputs an analog signal to the DUT through the analog signal output port, and the DUT collects and measures this analog signal. The analog signal output board of this module can be designed independently. In a preferred embodiment, the analog signal output board is designed as follows: the number of output channels of the analog signal is 64; the back-capture measurement accuracy of the analog signal output is 12 bits; the maximum output current of the analog signal is 100 mA; the maximum back-capture frequency of the analog signal output is 20 kS / s; the output control accuracy of the analog signal is 1%; the output voltage range of the analog signal is 0 - 10 V; the analog signal output port is designed with a short-circuit protection circuit for power supply and ground, and includes 4 channels of 5 V / 300 mA and 3 channels of VB / ३00 mA controlled power supply outputs.

[0054] Among them, the digital signal output module outputs a digital signal to the DUT through the digital signal output port, and the DUT collects this digital signal. The digital signal output board of this module can be designed independently. In a preferred embodiment, the digital signal output board is designed as follows: the number of output channels of the digital signal is 64; the maximum load current of the digital output signal is 15 mA; the single-channel update rate of the digital signal output is 200 Hz; it can simulate high-side switches and low-side switches to achieve three states of grounding, connecting to VB, and NC; the voltage range of the output high level is ((VB - 1) - VB) V, and the voltage range of the output low level is (0 - 0.3) V; it can simulate the monitoring and scanning of a 5×5 keyboard matrix; the digital signal output port is designed with a short-circuit protection circuit for power supply and ground.

[0055] Among them, the square wave signal output module outputs a square wave signal to the DUT through the square wave signal output port, and the DUT collects this square wave signal. The square wave signal output board of this module can be designed independently. In a preferred embodiment, the square wave signal output board is designed as follows: the number of output channels of the square wave signal is 32; it can be set to two output modes: push-pull output and open-drain output; the maximum load current of the square wave output signal is 15 mA; the frequency range of the square wave signal output is 0 - 100 kHz, and the frequency accuracy is 1%; the duty cycle range of the square wave signal output is 0 - 100%, and the duty cycle accuracy is 1%; the maximum rise time of the square wave output signal is 4 μs, and the maximum fall time of the square wave output signal is 2 μs; the voltage range of the output high level is (4.5 - 5) V or (3 - 3.3) V, and the voltage range of the output low level is (0 - 0.3) V; the square wave signal output port is designed with a short-circuit protection circuit for power supply and ground.

[0056] Among them, the sine wave signal output module outputs a sine wave signal to the DUT through the sine wave signal output port, and the DUT collects this sine wave signal. The sine wave signal output board of this module can be designed independently. In a preferred embodiment, the sine wave signal output board is designed as follows: the number of output channels of the sine wave signal is 8; the maximum load current of the sine wave output signal is 10 mA; the frequency range of the sine wave signal output is 0.1 - 200 kHz, and the frequency accuracy is 1%; the waveform distortion rate is 10%; the sine wave peak-to-peak value is ±20 V, and the zero-point offset of the sine wave is ±0.5 V; it can simulate the engine tooth-missing signal; the sine wave signal output port is designed with a short-circuit protection circuit for power supply and ground.

[0057] Among them, the oxygen sensor simulation module outputs an analog signal to the DUT through the oxygen sensor analog output port, and the DUT collects this analog signal. The oxygen sensor analog board of this module can be designed independently. In a preferred embodiment, the oxygen sensor analog board is designed as follows: the number of channels for inputting the oxygen sensor analog output is 2, including the front oxygen signal and the rear oxygen signal; the oxygen content and oxygen temperature parameters can be programmed; the simulated λ value is 1.1 - 1.8; the temperature value is 0 - 900 °C; the oxygen sensor analog output port is designed with a short-circuit protection circuit for power supply and ground.

[0058] Among them, the knock sensor simulation module outputs an analog signal to the DUT through the knock sensor analog output port, and the DUT collects this analog signal. The knock sensor analog board of this module can be designed independently. In a preferred embodiment, the knock sensor analog board is designed as follows: the number of channels for knock sensor analog output is 2; the frequency of the knock signal can be set, and the knock signal frequency is 3 - 20 kHz; the amplitude of the knock signal can be set, and the knock signal amplitude is (0 - 5) V; the knock sensor analog output port is designed with a short-circuit protection circuit for power supply and ground.

[0059] Among them, the injector simulation module outputs a simulation signal to the DUT through the injector simulation port; a real injector load can be externally connected, and the output signal of the injector can be collected. The injector simulation board of this module can be designed independently. In a preferred embodiment, the injector simulation board is designed as follows: the number of channels for injector simulation is 4; the real state of the injector can be simulated, the maximum angle is 30°, the injection rise time meets the EMS recognition requirements; the working current of the injector is collected; the injection time and angle feedback by the injector are collected; the pressure boost time feedback by the fuel pump is collected; the ignition position and ignition current feedback by the igniter are collected; the current sampling accuracy is 5%, the time sampling accuracy is 0.1 us, and the sampling feedback time is 1 us; the injector acquisition input port is designed with a short-circuit protection circuit for power supply and ground.

[0060] Among them, the high-pressure pump simulation module outputs a simulation signal to the DUT through the high-pressure pump simulation port. The high-pressure pump simulation board of this module can be designed independently. In a preferred embodiment, the high-pressure pump simulation board is designed as follows: a real high-pressure pump load can be externally connected, and the output signal of the high-pressure pump can be collected; the number of channels for high-pressure pump simulation is 1; the real state of the high-pressure pump can be simulated, the pump rise time meets the EMS recognition requirements, the pressure boost time feedback by the fuel pump is collected, and its range is (0 - 100) ms; the working current of the high-pressure pump is collected; the fuel injection time is collected, and the time sampling accuracy is 1 us; the data acquisition feedback time is not greater than 1 us; the high-pressure pump acquisition input port is designed with a short-circuit protection circuit for power supply and ground.

[0061] Among them, the igniter simulation module outputs a simulation signal to the DUT through the igniter simulation port; a real igniter load can be externally connected, and the output signal of the igniter can be collected. The igniter simulation board of this module can be designed independently. In a preferred embodiment, the igniter simulation board is designed as follows: the number of channels for igniter simulation is 4; intelligent and non-intelligent ignition coils can be simulated; the working current of the igniter in the range of (0 - 30) A can be collected, and the sampling accuracy is 1%; the ignition advance angle of the igniter in the range of (0 - 30)° can be collected, and the sampling accuracy is 1%; the igniter simulation port is designed with a short-circuit protection circuit for power supply and ground.

[0062] Among them, the throttle simulation module outputs a simulation signal to the DUT through the throttle simulation port. The throttle simulation board of this module can be designed independently. In a preferred embodiment, the throttle simulation board is designed as follows: a real throttle load can be externally connected, and the output signal of the throttle can be collected; the number of channels for throttle simulation is 2; the throttle can be simulated; the working current of the throttle in the range of (0 - 10) A can be collected, and the sampling accuracy is 1%; the throttle simulation port is designed with a short-circuit protection circuit for power supply and ground.

[0063] Among them, the simulated load module provides a simulated load for the DUT through the simulated load channel. The simulated load board of this module can be designed independently. In a preferred embodiment, the simulated load board is designed as follows: the IO type load of 200 mA has 96 channels, and the programmable electronic load of 10 A or more has 48 channels; it can inject open-circuit, short-circuit-to-power-supply, and short-circuit-to-ground faults through software control; it can switch between low-end drive and high-end drive through software control; it can use the simulated load or an external real load through software control; the IO type load can feedback the IO status; the programmable electronic load can feedback the current, frequency, and duty cycle status.

[0064] Among them, the fault injection module can simulate open-circuit, short-circuit-to-power-supply, and short-circuit-to-ground faults and inject them into the DUT through the fault injection channel, and the fault type can be set in real time through software. The fault injection board of this module can be designed independently. In a preferred embodiment, the fault injection board is designed as follows: the number of channels with a short-circuit capacity greater than 2 A is 120, and the number of channels with a short-circuit capacity greater than 10 A is 32; the fault injection module can be bypassed.

[0065] Specifically, the test output module provides a simulated test running environment and executes tests together with the real-time processor module. In this embodiment, the real-time processor module uses NI's SB_RIO embedded real-time processor, configured as follows: the processor main frequency is 400 MHz, the ROM is 256 MB, and the RAM is 128 MB; it can run Labview RTOS; 96 FPGA data channels, 1 RS232 / RS485 bus; 1 100BASE_T Ethernet bus, 4 CAN buses with a maximum speed of 1 Mbps, and 2 LIN buses with a maximum speed of 20 kbps. In another embodiment of the present invention, other NI boards can also be used to replace the SB_RIO embedded real-time processor. The host computer module receives and displays the abnormal situations and test results that occur during the test. In this embodiment, the host computer uses Advantech's 610L industrial computer, configured as follows: the CPU is a 4-core processor, and the CPU main frequency is 3.1 GHz; the hard disk is 1 TB, and the RAM is 4 GB DDR3; 6 USB interfaces, 2 TCP / IP interfaces.

[0066] Specifically, in this embodiment, the output test data of each group of test output modules is tested and collected as follows:

[0067] Set the number of test groups and the test output modules of each group of test groups;

[0068] Send an output valid request to the device under test, and test and collect the test data when the output of each group of test output modules is valid according to the test plan and the input test data;

[0069] After the test data when the output is valid is collected, send a request for invalid output to the device under test, collect the test data when the output of the test output module in this group is invalid, and obtain the output test data for each group.

[0070] In addition, as Figure 2 shown, in this embodiment, the host computer of the electronic control hardware test bench is interconnected with the real-time processor through a network cable, the test output module and the signal input module are interconnected through a signal connection board, the device under test DUT is interconnected with the test bench through the signal connection board, the external real load is connected to the DUT, the external real load is connected to the test bench through the signal connection board, and the external load power supply is connected to the external load.

[0071] The electronic control hardware test bench provides power to the DUT through the programmable power supply module; in this embodiment, the output voltage of the programmable power supply module is (0 - 40) V, the output current is (0 - 60) A, the voltage and current can be displayed; it has overvoltage protection and over-temperature protection functions; and the voltage and current can be controlled through the host computer module to output any waveform.

[0072] In this embodiment, the CAN communication module is used to enable the CAN communication port to interact with the CAN communication port of the DUT. The CAN communication board is configured as follows: the number of channels of the CAN communication module is 8; the signal baud rate can be configured as 250k / 500k / 1Mbps; it integrates a CAN database and can import, edit, and use signals from DBC files; the CAN communication port is designed with a short-circuit protection circuit for power supply and ground.

[0073] In this embodiment, the LIN communication module is used to enable the LIN communication port to interact with the LIN communication port of the DUT. The LIN communication board is configured as follows: the number of channels of the LIN communication module is 8; the signal baud rate can reach 20kbps; the master and slave nodes can be set; the CAN communication port is designed with a short-circuit protection circuit for power supply and ground.

[0074] In addition, the programmable power supply module can output voltage according to the software settings of the host computer. The voltage modes are shown in Table 1:

[0075] Table 1 Voltage Modes

[0076]

[0077] In addition, the test configuration needs to be set according to the characteristics of the DUT and the load. The test configuration forms are shown in Table 2:

[0078] Table 2 Test Configuration

[0079]

[0080] The CAN frame forms are shown in Table 3:

[0081] Table 3 CAN Frame

[0082]

[0083] The LIN frame format is shown in Table 4 as follows:

[0084] Table 4 LIN Frame

[0085]

[0086] In this embodiment, the voltage mode setting examples are shown in Table 5 as follows:

[0087] Table 5 Voltage Mode Examples

[0088]

[0089] The test configuration format examples are shown in Table 6 as follows:

[0090] Table 6 Test Configuration Examples

[0091]

[0092] The CAN frame format is shown in Table 7 as follows:

[0093] Table 7 CAN Frame Examples

[0094]

[0095] The LIN frame format is shown in Table 8 as follows:

[0096] Table 8 LIN Frame Examples

[0097]

[0098] In addition, the embodiment of the present invention also provides a method for testing an electronic control hardware test bench, and the method includes:

[0099] Sending a first handshake request to the device under test and waiting to receive a first response message; and after receiving the first response message and the ready message in sequence within a preset time, setting the signal inputs of each signal input module to an effective state and waiting to receive a first input test data message;

[0100] After receiving the first input test data message, setting the signal input to an invalid state and waiting to receive a second input test data message; after receiving the second input test data message within a preset time, saving the input test data;

[0101] Setting a test scheme, and testing and collecting the output test data of each group of test output modules according to the test scheme and the input test data, saving the output test data and sending it to the upper computer;

[0102] After sending the output test data, the second handshake request and the third handshake request are successively sent from the CAN bus and the LIN bus to the device under test, and wait to successively receive the second response message and the third response message; and after successively receiving the second response message and the third response message within the preset time, save the CAN bus test data and the LIN bus test data of this strip and send them to the host computer.

[0103] The electronic control hardware test bench and test method provided by the embodiments of the present invention can perform various tests on various controller hardwares, such as VCU, EMT, DCT, EWP, BSG, STT, EMS, BCM, EPB, ADAS, IVI, BDC, CCM, VIU, PDC, GW, CGW, etc. by replacing the device under test of the test bench, including function test, performance test and network consistency test, with strong versatility and low test cost; and can design a test plan according to the device under test, such as changing the test sequence, the host computer interface and the test harness, can flexibly increase or decrease test items, and can also design a dedicated board for the test output module by itself to meet the test requirements, with higher flexibility and sufficiency, and the test is more accurate and efficient; in addition, the test development cycle of the present invention is short, and any abnormality during the test is sent to the host computer in time, and the test abnormality can be processed in time, with high stability and reliability.

[0104] Embodiment 2

[0105] Based on the electronic control hardware test bench described in Embodiment 1, this embodiment provides a test method for an electronic control hardware test bench, and its test process is as Figure 3 shown.

[0106] After connecting to the power supply and the test bench is powered on, initialize the real-time processor module and the host computer system, and initialize the programmable power supply module and set the dynamic output.

[0107] Send a handshake request message to the DUT through the CANx bus. If no response message is received on the CANx bus within 2 s, set the handshake exception and send the exception message to the host computer. If a response message is received, continue to wait for the Ready message sent by the DUT.

[0108] If the Ready message sent by the DUT is not received on the CANx bus within the agreed time, set the Ready exception and send the exception message to the host computer, and end the test. If the test bench receives the Ready message, set all inputs to the valid state.

[0109] Delay for 2 s. Within 1 s, if the test data packet sent by the DUT is not received on the CANx bus, set the input as abnormal, send the abnormal message to the host computer, and end the test. If the test bench receives the test data packet sent by the DUT, set all inputs to the invalid state.

[0110] Delay for 2 s. Within 1 s, if the test data packet sent by the DUT is not received on the CANx bus, set the input as abnormal, send the abnormal message to the host computer, and end the test. If the test bench receives the test data packet sent by the DUT, save the test data and send it to the host computer through the network cable.

[0111] Set the number of test groups N and the test output modules for each group of test groups. In this embodiment, set "N = 5". The first group includes an analog signal output module, a digital signal output module, a square wave signal output module, and a sine wave signal output module; the second group includes an oxygen sensor simulation module, a knock sensor simulation module, and an injector simulation module; the third group includes a high-pressure pump simulation module, an igniter simulation module, and a throttle simulation module; the fourth group includes an analog load module; the fifth group includes an analog load module and a fault injection module.

[0112] Judge whether N is greater than 0. If so, send a request for the Nth group output to be valid to the DUT, delay for 2 s, collect the test data when the Nth group output is valid according to the test plan, send a request for the Nth group output to be invalid to the DUT, delay for 2 s, collect the test data when the Nth group output is invalid, save the output test result and send it to the host computer through the network cable. Judge whether N is greater than 0. If N is greater than 0, make N = N - 1 and repeat this step. Loop like this until N is not greater than 0 and then transfer to the next step.

[0113] Send a handshake request to the DUT from the CANy bus. Judge whether the handshake response from the DUT is received on the CANy within the agreed time. If not, set the CANy as abnormal and send it to the host computer; if so, save the CANy test data and send it to the host computer through the network cable. Here, y in CANy is the number of the CAN bus. If multiple CAN buses need to be tested, they can be tested in parallel at the same time.

[0114] Send a handshake request to the DUT from the LINy bus. Judge whether the handshake response from the DUT is received on the LINy within the agreed time. If not, set the LINy as abnormal and send it to the host computer; if so, save the LINy test data and send it to the host computer through the network cable. Here, y in LINy is the number of the LIN bus. If multiple LIN buses need to be tested, they can be tested in parallel at the same time.

[0115] Finally, the host computer processes the received test data and abnormal results, and performs display, saving, and printing.

[0116] It should be noted that according to the needs of implementation, each step / component described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0117] In the above embodiments, the magnitudes of the sequence numbers of the steps do not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0118] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. An electronic control hardware test bench, characterized in that, Including: A preparation module, configured to send a first handshake request to the device under test and wait for receiving a first response message; And after receiving the first response message and the ready message in sequence within a preset time, set the signal inputs of each signal input module to an effective state and wait for receiving a first input test data message; An input module, configured to, after receiving the first input test data message, set the signal input to an invalid state and wait for receiving a second input test data message; After receiving the second input test data message within a preset time, save the input test data; A data test module, configured to set a test scheme, and test and collect the output test data of each group of test output modules according to the test scheme and the input test data, save the output test data and send it to the host computer; A bus test module, configured to, after sending the output test data, send a second handshake request and a third handshake request to the device under test from the CAN bus and the LIN bus in sequence and wait for receiving a second response message and a third response message in sequence; And after receiving the second response message and the third response message in sequence within a preset time, save the CAN bus test data and the LIN bus test data of this item and send them to the host computer.

2. The electric control hardware test bench according to claim 1, characterized in that, The preparation module is further configured to: if the first response message is not received within a preset time, set a handshake exception and send an exception message to the host computer; and if the ready message is not received within a preset time, set a ready exception and send an exception message to the host computer.

3. The electronic control hardware test bench according to claim 1, characterized in that, The input module is further configured to: if the first input test data message is not received within a preset time, set an input exception and send an exception message to the host computer; and if the second input test data message is not received within a preset time, set an input exception and send an exception message to the host computer.

4. The electronic control hardware test bench according to claim 1, wherein The bus test module is further configured to: if the second response message is not received within a preset time, set an exception for this CAN bus and send an exception message to the host computer; and if the third response message is not received within a preset time, set an exception for this LIN bus and send an exception message to the host computer.

5. The electronic control hardware test bench according to claims 1-4, characterized in that It further includes a display module, configured to display, save and print the test data and exception results received by the host computer.

6. The electric control hardware test bench according to claim 1, characterized in that, The signal input module includes an analog signal input module, a digital signal input module and a square wave signal input module.

7. The electronic control hardware test bench according to claim 6, wherein The analog signal input module collects the analog output signal of the device under test through an analog signal acquisition port; the digital signal input module collects the digital output signal of the device under test through a digital signal input port; the square wave signal input module collects the square wave output signal of the device under test through a square wave signal input port.

8. The electronic control hardware test bench according to claim 1, wherein The test output module includes an analog signal output module, a digital signal output module, a square wave signal output module, a sine wave signal output module, an oxygen sensor simulation module, a knock sensor simulation module, an injector simulation module, a high-pressure pump simulation module, an igniter simulation module, a throttle simulation module, an analog load module, a fault injection module.

9. The electronic control hardware test bench according to claim 8, characterized in that, The analog signal output module outputs an analog signal through an analog signal output port; The digital signal output module outputs digital signals through the digital signal output port; the square wave signal output module outputs square wave signals through the square wave signal output port; the sine wave signal output module outputs sine wave signals through the sine wave signal output port; the oxygen sensor analog module outputs analog signals through the oxygen sensor analog output port; the knock sensor analog module outputs analog signals through the knock sensor analog output port; the injector analog module outputs analog signals through the injector analog port; the high-pressure pump analog module outputs analog signals through the high-pressure pump analog port; the igniter analog module outputs analog signals through the igniter analog port; the throttle valve analog module outputs analog signals through the throttle valve analog port.

10. The electric control hardware test bench according to claim 8, characterized in that, The fault injection module simulates open circuit, short circuit to power supply and short circuit to ground faults through the fault injection channel and injects them into the device under test; the analog load module provides an analog load for the device under test through the analog load channel.

11. The electronic control hardware test bench according to claim 7 or 9, characterized in that, The analog signal acquisition port, digital signal input port, square wave signal input port, analog signal output port, digital signal output port, square wave signal output port, sine wave signal output port, oxygen sensor analog output port, knock sensor analog output port, injector analog port, high-pressure pump analog port, igniter analog port, and throttle valve analog port are respectively equipped with short-circuit protection circuits for power supply and ground.

12. The electric control hardware test bench according to claim 1, characterized in that, Each signal input module and test output module has a board for setting the working parameters of the module.

13. The electronic control hardware test bench according to claim 1, characterized in that, Specifically, the output test data of each group of test output modules is tested and collected as follows: Set the number of test groups and the test output modules of each test group; Send an output valid request to the device under test, and test and collect the test data when the output of each group of test output modules is valid according to the test plan and input test data; After the test data when the output is valid is collected, send an output invalid request to the device under test, and collect the test data when the output of this group of test output modules is invalid to obtain the output test data of each group.

14. A test method for an electronic control hardware test bench, characterized in that, The method includes: Send a first handshake request to the device under test and wait to receive the first response message; and after receiving the first response message and the ready message in sequence within the preset time, set the signal input of each signal input module to the valid state and wait to receive the first input test data message; After receiving the first input test data message, set the signal input to the invalid state and wait to receive the second input test data message; after receiving the second input test data message within the preset time, save the input test data; Set the test plan, and test and collect the output test data of each group of test output modules according to the test plan and input test data, save the output test data and send it to the host computer; After sending the output test data, send a second handshake request and a third handshake request to the device under test from the CAN bus and LIN bus in sequence and wait to receive the second response message and the third response message in sequence; and after receiving the second response message and the third response message in sequence within the preset time, save the CAN bus test data and LIN bus test data of this message and send it to the host computer.

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