Resource pool and reset control method thereof, and time sequence control method of main system

Abstract

The invention discloses a resource pool, a reset control method of the resource pool and a time sequence control method of a main system, and relates to the technical field of PCIe topological structures.At least one exchange board card and a management board card are integrated into the resource pool, and the management board card manages the at least one exchange board card; and the switching board card is respectively connected with the coprocessor resource pool and the main resource pool, so that various resources of the coprocessor resource pool are provided for various uplink main resources, and the uplink and downlink communication bandwidth and the number of communication equipment can be dynamically adjusted. Meanwhile, the management module carries out in-band management on at least one switching board card through an in-band management chip, and manages data transmitted by an external network interface arranged on the switching board card through an out-of-band management chip. Therefore, out-of-band network management and in-band network management are fused to realize hardware isolation of in-band and out-of-band network management, and the security of the system is greatly improved.

Description

Technical Field

[0001] This application relates to the technical field of PCIe topology structures, and in particular to a resource pool, a reset control method therefor, and a timing control method for a main system. Background Art

[0002] In a traditional PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) architecture, each CPU (central processing unit) in a single machine is connected to a SW (Switch) through a fixed PCIe link, and each SW is connected to each GPU through a fixed PCIe link, and each GPU exclusively occupies a fixed channel bandwidth (such as x16). For multi-machine networking, an IB network card (InfiniBand network adapter, a network adapter used in high-performance computing and data centers) or an RDMA network card (remote direct memory access) needs to be added to a single machine, and then paired with a switch to achieve multi-machine networking.

[0003] In related technologies, the PCIe architecture can only manage the internal network and cannot integrate the external network and the internal network. Summary of the Invention

[0004] This application provides a resource pool, a reset control method therefor, and a timing control method for a main system to at least solve the problem of how to integrate out-of-band network management and in-band network management to achieve hardware isolation of in-band and out-of-band network management.

[0005] This application provides a resource pool, including: at least one switching board and a management board, where the management board includes: a management module, an in-band management chip, and an out-of-band management chip, where The switching board is connected to at least one coprocessor resource pool and a main resource pool, and is used to implement data interaction between the coprocessor resource pool and the main resource pool, and connect to the external network based on an external network interface; The in-band management chip is connected to the switching board; The out-of-band management chip is connected to the switching board; The management module is respectively connected to the in-band management chip and the out-of-band management chip, and is used to perform in-band management on the switching board based on the in-band management chip, and is also used to manage the data transmitted through the external network interface based on the out-of-band management chip.

[0006] This application further provides a switching device, which includes the above-mentioned resource pool, including a box body. Along a first direction, a first area and a second area are arranged in the box body, where The first area is provided with a switching board, and the second area is provided with a management board. The switching board is detachably connected to the management board.

[0007] This application also provides a timing control method for a main system. The main system includes: a main resource pool, a coprocessor resource pool, and a resource pool as described above; or the main system includes: a main resource pool, a coprocessor resource pool, and a switching device as described above. The timing control method for the main system includes: After the main resource pool, the coprocessor resource pool, and the resource pool are powered on, the baseboard management controllers of the coprocessor resource pool and the main resource pool send a ready signal to the baseboard management controller of the resource pool. When receiving a power-on signal, the baseboard management controller of the resource pool controls the power-on based on a programmable logic device, and sends the power-on signal to the baseboard management controllers of the coprocessor resource pool and the resource pool respectively through the network. After the baseboard management controllers of the coprocessor resource pool and the resource pool receive the power-on signal and complete the power-on, they respectively feedback a power-on completion signal to the baseboard management controller of the resource pool. When receiving a power-off signal, the resource pool controls the power-off and outputs a relationship signal to the baseboard management controllers of the coprocessor resource pool and the resource pool respectively. The baseboard management controllers of the coprocessor resource pool and the resource pool receive the power-off signal and perform power-off respectively.

[0008] This application also provides a reset timing control method for a main system. The main system includes: a main resource pool, a coprocessor resource pool, and a resource pool as described above; or the main system includes: a main resource pool, a coprocessor resource pool, and a switching device as described above. The reset timing control method for the main system includes: After the main system is powered on, the management module of the resource pool scans the device identifiers of the coprocessor resource pool and the main resource pool respectively, and confirms the logical topology connection. When the main resource pool receives a reset signal, the programmable logic device of the main resource pool sends a reset signal to the switching board of the resource pool. After the switching board of the resource pool receives the reset signal and is reset, the switching board of the resource pool sends a reset signal to the programmable logic device of the coprocessor resource pool. The programmable logic device of the coprocessor resource pool receives the reset signal and performs a reset.

[0009] This application also provides a reset timing control method for a resource pool. The method is applied to the resource pool as described above, or the method is applied to the switching device as described above. The reset timing control method for the resource pool includes: The management module that controls the resource pool sends a reset instruction to the programmable logic device in the resource pool; The programmable logic device in the control resource pool resets the switching chip in the switching board card corresponding to the reset instruction, or sends a reset instruction to the coprocessor resource pool corresponding to the reset instruction.

[0010] Through this application, since at least one switching board card and a management board card are integrated into a resource pool, the management board card manages at least one switching board card, and is respectively connected to the coprocessor resource pool and the main resource pool through the switching board card. Thus, resources of a variety of coprocessor resource pools are provided for the upstream multiple main resources, and the communication bandwidth and the number of communication devices between the upper and lower rows can be dynamically adjusted. At the same time, the management module respectively performs in-band management on at least one switching board card through the in-band management chip, and manages the data transmitted through the external network interface set on the switching board card through the out-of-band management chip. Thus, the out-of-band network management and the in-band network management are integrated to achieve hardware isolation of the in-band and out-of-band network management, greatly improving the security of the system. Brief Description of the Drawings

[0011] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 It is a structural diagram of a resource pool provided by an embodiment of the present application; Figure 2 It is another structural diagram of a resource pool provided by an embodiment of the present application; Figure 3 It is an application diagram of a resource pool provided by an embodiment of the present application; Figure 4 It is still another structural diagram of a resource pool provided by an embodiment of the present application; Figure 5 It is yet another structural diagram of a resource pool provided by an embodiment of the present application; Figure 6 It is a topological structural diagram of a management board card in a resource pool provided by an embodiment of the present application; Figure 7 It is a topological structural diagram of a management module in a resource pool provided by an embodiment of the present application; Figure 8 It is a topological structural diagram of a switching chip in a resource pool provided by an embodiment of the present application; Figure 9 It is a physical structural diagram of a switching board card in a resource pool provided by an embodiment of the present application; Figure 10 A physical structure diagram of a management board in a resource pool provided by an embodiment of the present application; Figure 11 A front and rear structure physical diagram of a resource pool provided by an embodiment of the present application; Figure 12 A physical structure diagram of a resource pool provided by an embodiment of the present application; Figure 13 Another physical structure diagram of a resource pool provided by an embodiment of the present application; Figure 14 A flowchart of a timing control method for a main system provided by an embodiment of the present application; Figure 15 A flowchart of a reset timing control method for a main system provided by an embodiment of the present application. Detailed implementation manners

[0013] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0014] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0016] In the traditional PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) architecture, each CPU (central processing unit) in a single machine is connected to a SW (Switch) through a fixed PCIe link. Each SW is connected to each GPU through a fixed PCIe link, and each GPU exclusively occupies a fixed channel bandwidth (such as x16). For multi-machine networking, an IB network card (InfiniBand network adapter, a network adapter used in high-performance computing and data centers) or an RDMA network card (remote direct memory access) needs to be added to a single machine, and then combined with a switch to achieve multi-machine networking.

[0017] In the related technology, the PCIe architecture can only manage the internal network and cannot integrate the external network and the internal network. Moreover, when multi-machine networking, each machine needs to allocate independent PCIe resources to the IB network or the RDMA network card. And for the bandwidth of multi-machine networking, the PCIe resources occupied by these network cards account for nearly 50% of the PCIe resources available for expansion in a single machine, resulting in a shortage of PCIe resources.

[0018] With the rapid development of many complex computing scenarios such as artificial intelligence, machine learning, and high-performance computing, new requirements are put forward for the data center architecture. The three core contradictions faced by the traditional computing architecture in the AI large model training scenario: the contradiction between hardware resource isolation and large-scale computing requirements, the contradiction between fixed bandwidth allocation and dynamic load fluctuations, and the contradiction between physical device expansion limitations and the elastic demand of the computing power cluster. In GPU (Graphics Processing Unit) training and AI (Artificial Intelligence) large model applications, the PCIe resource pool becomes the key solution: the PCIe resource pool splits the physical channels into logical resource pools through virtualization technology, and combines intelligent scheduling algorithms (such as priority division based on QoS (Quality of Service)) to achieve on-demand bandwidth allocation. The PCIe tree topology naturally has limitations on the number of IDs (Identity document) and the depth of the hierarchy (the traditional architecture only supports 256 device IDs), while the training of AI large models often requires hundreds of GPUs to form a computing cluster. The resource pool reconstructs the physical topology into a mesh structure by introducing the latest PCIe technology and switching chips, significantly increasing the upper limit of the GPU cluster scale. Therefore, this paper proposes a design scheme for the PCIe resource pool architecture.

[0019] In the traditional PCIe architecture, each CPU (Central Processing Unit) in a single machine is connected to the SW through a fixed PCIe link, and each SW is connected to each GPU through a fixed PCIe link. Each GPU exclusively occupies a fixed channel bandwidth (such as x16). For multi-machine networking, an IB (InfiniBand protocol, an architecture designed specifically for high-performance computing) network card or an RDMA (remote direct memory access) network card needs to be added to the single machine, and then paired with a switch to achieve multi-machine networking. When multi-machine networking, each machine needs to provide independent PCIe resources for the IB network or the RDMA network card. Moreover, for the bandwidth of multi-machine networking, the PCIe resources occupied by these network cards account for nearly 50% of the PCIe resources available for expansion in the single machine. Additionally, since network cards, optical modules, and switches need to be added to the system, the price of the entire machine will further increase.

[0020] Embodiments of the present application provide a resource pool, as Figure 1 shown, including: at least one switching board A and a management board B. The management board B includes: a management module, an in-band management chip, and an out-of-band management chip, where The switching board A is connected to at least one co-processor resource pool and a main resource pool, and is used to implement data interaction between the co-processor resource pool and the main resource pool, and connect to the external network based on an external network interface; Specifically, the co-processor resource pool can be a device, specifically resources such as a GPU (Graphics Processing Unit), an SSD (Solid State Disk or Solid State Drive), an FPGA (Field Programmable Gate Array), a network card, and a memory. The main resource pool is specifically a Host resource pool. It is specifically connected to at least one co-processor resource pool and the main resource pool through an interface led out by the switching board A. The external network interface is specifically an RJ45. RJ45 is a type of connector for information sockets (i.e., communication outlets) in a wiring system. The external network interface can specifically connect to an external network switch device or a fan, etc. Multiple switching boards A are connected through PCIe links.

[0021] The in-band management chip is connected to the switching board; The out-of-band management chip is connected to the switching board; Specifically, the specific models of the in-band management chip and the out-of-band management chip are 88E6190X.

[0022] The management module is connected to the in-band management chip and the out-of-band management chip respectively, and is used for in-band management of the switching board based on the in-band management chip, and is also used for managing the data transmitted through the external network interface based on the out-of-band management chip.

[0023] Specifically, the management module performs in-band management of the switching board based on the in-band management chip, and the management module also manages the data transmitted through the external network interface based on the out-of-band management chip and the extended network management chip. Through the external network interface, the management module and any device can be accessed. At the same time, the switching board accesses the management module through the out-of-band management chip, serving as a shared management network interface of the management module. Thus, the out-of-band network management and the in-band network management are integrated to achieve hardware isolation of the in-band and out-of-band network management, greatly improving the security of the system.

[0024] Specifically, since at least one switching board A and a management board B are integrated into a resource pool, the management board B manages at least one switching board A, and is respectively connected to a coprocessor resource pool and a main resource pool through the switching board A. Thus, diverse resources of the coprocessor resource pool are provided for multiple main resources in the upstream, and the communication bandwidth and the number of communication devices between the upper and lower rows can be dynamically adjusted.

[0025] It should be noted that during on-site maintenance, the network interface of the out-of-band management chip on the right is used when necessary to improve the convenience of operation and maintenance.

[0026] Through this application, since at least one switching board A and a management board B are integrated into a resource pool, the management board B manages at least one switching board A, and is respectively connected to a coprocessor resource pool and a main resource pool through the switching board A. Thus, diverse resources of the coprocessor resource pool are provided for multiple main resources in the upstream, and the communication bandwidth and the number of communication devices between the upper and lower rows can be dynamically adjusted. At the same time, the management module performs in-band management of at least one switching board A through the in-band management chip respectively, and manages the data transmitted through the external network interface set on the switching board A through the out-of-band management chip. Thus, the out-of-band network management and the in-band network management are integrated to achieve hardware isolation of the in-band and out-of-band network management, greatly improving the security of the system.

[0027] In some optional embodiments, referring to Figure 2 , the switching board includes: a first channel interface, where The first end of the first channel interface is connected to the in-band management chip, and the second end of the first channel interface is selectively connected to the in-band management chip or the out-of-band management chip.

[0028] Specifically, the channel interface is MCIO (Mini Cool Edge IO, a multi-channel input / output technology), achieving PCIe x16 bandwidth. Each switching board includes at least one first channel interface.

[0029] Reference Figure 2 , taking four switching boards A as an example, the first end of the first channel interface of each switching board A is connected to the in-band management chip, specifically connected to the P2, P3, P4, P5, P6, P7, P9, and P10 pins of the in-band management chip respectively. The second end of the first channel interface of each switching board A is connected to the out-of-band management chip, specifically connected to the P5, P6, P7, and P10 pins of the out-of-band management chip respectively. For example, the second end of the first channel interface of switching board A can be selectively connected to P10 of the in-band management chip (dashed line) or P0 of the in-band management chip (solid line).

[0030] In some alternative embodiments, referring to Figure 2 , the management board further includes: a first network management chip, where The first network management chip is respectively connected to the second end of the first channel interface and the out-of-band management chip, and is used to enable the external network interface to communicate directly with the in-band network.

[0031] Specifically, the model of the network management chip can be 88E1512. The external network interface is directly connected to the in-band management chip through the first channel interface and the first network management chip, so as to directly establish a connection between the external network interface and the in-band network.

[0032] In some alternative embodiments, the management module, the in-band management chip, and the out-of-band management chip are arranged on the first baseboard. Referring to Figure 2 , the management module includes: at least one management module module, a second network management chip, and a baseboard management controller, where At least one management module module is connected to the in-band management chip and is used to control the in-band management chip; The second network management chip is respectively connected to the baseboard management controller and the out-of-band management chip; The baseboard management controller is connected to the second network management chip and is used to manage the external network interface based on the out-of-band management chip.

[0033] Specifically, the management module module is a CPU, and the management module module is connected to switching board A through the in-band management chip to control the in-band management chip and switching board A.

[0034] Exemplarily, as Figure 2As shown in the figure, there can be two management module modules, which are simultaneously connected to the in-band management chip. The information of the two management module modules can be synchronized through the network, accelerating the transmission of redundant information and enhancing the stability of the system.

[0035] Specifically, the baseboard management controller is a BMC. The baseboard management controller is connected to the in-band management chip through the second network management chip, thereby managing the external network interface, specifically transmitting data to the external network interface or receiving data transmitted from the external network.

[0036] It should be noted that the management module module can specifically adopt a low-power system management module module. In order to achieve efficient management of the switching chip, the management board is designed with two independent low-power system management module modules. These two management module modules are buckled on the management board in the form of a plug-in card and are redundant backups for each other during startup operation. By switching the signals (USB, network, I2C) of the management switching chip, uninterrupted management of the switching board card can be achieved, providing the stability of the PCIe resource pool. In order to achieve redundant monitoring, by switching the signals communicated through the baseboard management controller and the user interface signals, uninterrupted management of the user can be achieved, and the running state of the system can be understood at all times.

[0037] In some alternative embodiments, referring to Figure 2 , the switching board card includes: a second baseboard (not shown), a plurality of switching chips, a plurality of third network management chips, a plurality of fourth network management chips, and a second channel interface. Among them, The second channel interface is used to connect the switching chips within the switching board card to achieve communication between the switching chips within the switching board card; A plurality of switching chips are integrated on the second baseboard. The plurality of switching chips on this switching board card communicate with the plurality of switching chips on other switching board cards through the first channel interface, and are respectively connected to at least one coprocessor resource pool and the main resource pool; A plurality of switching chips are used to achieve data interaction between the coprocessor resource pool and the main resource pool; A plurality of third network management chips, each of which is connected between the external network interface and the first channel interface, is used to enable communication between the external network interface and the first channel interface; A plurality of fourth network management chips, each of which is connected between the first channel interface and the switching chip, is used to enable communication between the switching chip and the first channel interface.

[0038] Specifically, through the first channel interface and the second channel interface, all switching chips are connected to build a mesh PCIe topology that matches the CPUs in the main resource pool. Redundancy is achieved through multi-path interconnection, and there are multiple physical links between any two nodes. When one of the PCIe links fails, the data can be automatically switched to other available paths for transmission, avoiding the paralysis of the entire system caused by a single point of failure. Each PCIe endpoint (such as a GPU) can simultaneously establish independent channels with multiple targets, significantly improving the utilization rate of the effective bandwidth. Moreover, the concepts of modularization and dual management redundancy are incorporated into the system to provide sufficient guarantee for the management of the PCIe resource pool.

[0039] Specifically, the switching chip is a PCIe SW. The PCIe Switch is a hardware device that provides expansion or aggregation capabilities and allows more devices to be connected to a PCle port. Multiple switching chips within the same switching board are connected through the second channel interface, and the switching chips between different switching boards A are connected through the first channel interface. The number of the first channel interfaces corresponds to the number of switching chips within the switching board A, and the number of the second channel interfaces corresponds to the number of switching boards A. Additionally, the first channel interface and the second channel interface can be reserved to enable changes in the SW topology, not limited to two SWs using the PCIe x16 bandwidth for interconnection. Furthermore, by changing the connection method of the supplementary MCIO cable, different PCIe resource pool topologies can be built within a single machine.

[0040] Exemplarily, for a switching board A with two switching chips and four switching boards A, each switching chip includes a second channel interface for connecting to another switching chip within the same switching board, and also includes three second channel interfaces for connecting to three different switching boards A to achieve the interconnection of 4-layer switching boards.

[0041] Specifically, the baseboard management controller manages the external network interface based on the out-of-band management chip, the first channel interface, and the third network management chip. Meanwhile, at least one management module manages the coprocessor resource pool based on the in-band management chip, the first channel interface, and the fourth network management chip.

[0042] In some optional implementation manners, referring to Figure 4 , the switching board includes: a plurality of first selection paths, where a plurality of first selection paths, each first selection path is respectively connected to the second ends of a plurality of first channel interfaces and the in-band management chip, and is used for the in-band management chip to communicate with a plurality of switching boards simultaneously.

[0043] Specifically, the selection path is a MUX (i.e., a multiplexer). Through the first selection path, the second end of each first channel interface can be connected to the in-band management chip.

[0044] In some alternative embodiments, with reference to Figure 2 and Figure 3 , the baseboard management controller is used to configure the in-band management chip, the out-of-band management chip, the second network management chip, and each third network management chip; or, the in-band management chip is used to configure the first network management chip and each third network management chip based on the first selection path; or, each switching chip configures the connected fourth network management chip.

[0045] Specifically, the baseboard management controller performs initial configuration for the in-band management chip, the out-of-band management chip, the second network management chip, and each third network management chip. The in-band management chip can also perform initial configuration for the first network management chip and each third network management chip. Each switching chip can also perform initial configuration for the connected fourth network management chip.

[0046] In some alternative embodiments, when the resource pool includes multiple switching boards A, the switching boards A are stacked.

[0047] Specifically, stacking the switching boards A is used to save space.

[0048] In some alternative embodiments, the switching board further includes: a plurality of data center front-end interfaces, where the plurality of data center front-end interfaces are connected to one switching chip and to the coprocessor resource pool or the main resource pool, and are used to enable the switching chip to communicate with the coprocessor resource pool and the main resource pool respectively.

[0049] Specifically, the data center front-end interface is a CDFP (Data Center Front Panel) connector. The CDFP connector is an external X16 PCIe connector, and each layer of the switching board A leads out a plurality of data center front-end interfaces.

[0050] Specifically, the resource pool includes 4 layers of the same switching boards A, where a single-layer switching board A integrates 2 high-performance switching chips, 10 CDFP connectors, 8 X16 PCIe MCIO connectors (MCIO realizes interconnection between 8 switching chips through internal MCIO cables in the chassis), 1 external management network port, 1 board power supply connector, and 1 board management connector.

[0051] Through the extreme stacking of four-layer switch card A, it is possible to arrange 8 switch chips within a 2U space and also lead out 40 external PCIe ports. After stacking the switch card A, the 8 switch chips are connected through the internal MCIO cables of the chassis. Different connection methods can build different resource pool topologies, including but not limited to 1 2X1 plus 2X3, or 2 2X2, or 1 2X4, or full interconnection of 8 switch chips. Thus, it is possible to support the division of resource pools of different sizes, achieve hardware isolation of PCIe resource pools on the hardware, and realize higher resource pool security.

[0052] In some optional embodiments, the management card further includes: a second selection path, and the first baseboard includes: a baseboard interface. The second selection path is respectively connected to the baseboard management controller and the baseboard interface. The baseboard interface is respectively connected to the out-of-band management chip and at least one management module module, and is used to expand the signal path so that the baseboard management controller is respectively connected to the out-of-band management chip and at least one management module module for backup communication.

[0053] Specifically, the baseboard management controller is connected to the second selection path based on the communication method of NCSI (Network Controller – Sideband Interface technology, that is, network controller sideband interface technology). The second selection path establishes a connection with the baseboard interface based on the communication method of NCSI. The baseboard interface is respectively connected to at least one management module module based on the PCIe method, and the baseboard interface is connected to the in-band management chip based on the MDI (Ethernet port using twisted pair) method.

[0054] In some optional embodiments, the management card further includes: a high-speed connector, wherein, The high-speed connector is connected to the switch card and is used to connect an external management device or an expansion interface.

[0055] Specifically, the high-speed connector is a Slimline (thin cable) connector. The management card controls the switch card through the Slimline connector, which includes the error interrupt signal INT of the switch chip, the out-of-band management signal I2C, the network management signal SERDES (short for SERializer / DESerializer), and the power-on control signals PWREN and PWRGD, as well as the external SERDES signal passing through the slimline connector. The network management chip converts it into an MDI signal to provide an external network management interface for the management card.

[0056] In some optional embodiments, the management card further includes: a programmable logic device, wherein, A programmable logic device is connected to a baseboard management controller and is used to control the power-on and power-off timing and the reset timing, and send the power-on state and the reset state of the whole machine to the baseboard management controller.

[0057] Specifically, the programmable logic device is a CPLD (i.e., Complex Programmable Logic Device), which is used to control the power-off timing and the reset timing of the resource pool, and send the power-on state and the reset state of the resource pool to the baseboard management controller.

[0058] Specifically, the CPLD monitors the operating state through the GPIO of the low-power system management module. In addition to monitoring the operating state through the GPIO of the low-power system management module, the BMC chip also monitors the system information of the low-power system management module through the UART serial port. The two low-power system management modules also monitor each other's operating states through the GPIO. Monitoring the operating state of the low-power system management module through multiple links can achieve fast monitoring and fast switching after a fault. The BMC supports monitoring and managing the out-of-band information of the whole machine, monitoring the PSU status information, the status information of Power VR, the temperature information of the whole machine, and implementing fan control and system display.

[0059] In some optional implementation manners, the third network management chip and the fourth network management chip have the same address for easy management.

[0060] Specifically, for easy maintenance, the addresses of the third network management chip and the fourth network management chip on the four-layer switching board are designed to be the same, i.e., 0x00. Each high-performance switching chip is configured and managed as the Master of the network management chip. The 4 network ports on the four-layer switching board are respectively configured by an in-band management chip, an out-of-band management chip, and a BMC. Among them, the in-band management chip needs to configure the first network management chip and the third network management chip with two identical addresses. Therefore, an MUX needs to be added for time-sharing management. After configuring the network management chip with the first address of 0X00, the MUX needs to be switched, and then the other network management chip with the address of 0X00 is configured through MDIO. As the main master, the BMC can configure the in-band management chip, the out-of-band management chip, the third network management chip corresponding to a network port, and the second network management chip of the BMC itself. Their slave addresses are 0x02, 0x03, 0x00, and 0x01 respectively. According to such an MDIO topology design, the initial network configuration management within the PCIe resource pool can be realized, and the network can be used faster after startup for the in-band management of the switching chip and the out-of-band management of the network of the whole machine.

[0061] Reference Figure 8, as an embodiment, a single-piece switching board supports a maximum of 2 Broadcom PEX89144 series switching chips. Each switching chip has 9 groups of PCIe GEN5 x16 Lanes, and the full-duplex rate of a single group is as high as 128GB / s. The PCIe resources of each switching chip on the second backplane are connected to 5 X16 CDFP connectors and 4 X16 MCIO connectors. Through the tight layout of 10 CDFPs in the front window, the PCIe resources of 2 SWs can be fully led out. There are two MCIOs beside the switching chips of the switching board, which are used for interconnection of the switching chips inside the switching board. By reserving this MCIO, changes in the switching chip topology can be realized, not limited to the interconnection of two switching chips using PCIe x16 bandwidth. The back of the board has 6 PCIe x16 MCIOs, which are used to realize the interconnection of 4-layer switching boards. By changing the connection method of the MCIO cables at the back, different PCIe resource pool topologies can be constructed within a single machine.

[0062] Reference Figure 8 , in addition to PCIe signals, the CDFP connector also includes a 100M clk from the clock buffer, an I2C signal from the management board, and reset signals of the low-power system management module module, the baseboard management controller, and the PCA9555 controlled by the switching chip. The 100M CLK can provide a clock homologous to the switching chip for downstream devices, improving the stability of the system. The I2C signal of the management board can realize the automatic detection of upstream and downstream devices and the acquisition of out-of-band information of downstream devices. Through the joint control of the reset signal, the low-power system management module module, the baseboard management controller, and the switching chip can receive the reset signal sent by the upstream host and, according to the internal strategy control, realize the reset of downstream devices controlled by the low-power system management module module, the baseboard management controller, and the switching chip.

[0063] In order to maximize the utilization of the PCB (backplane) and minimize PCB waste, the AIC card (graphics card) position of the low-power system management module module adopts a cable vertical board form, reducing the waste of PCB materials in the fan area. Considering the size of the rear window devices, the PSU area is hollowed out, and the overall design is a quasi-rectangle. And for the heat dissipation of the low-power system management module module and the switching chip, the fan module is directly facing the low-power system management module module and the switching chip. Considering the power supply and management of the switching board, the power supply connector and the signal connector are placed in the upper left corner of the board. In order to reduce the wiring from the low-power system management module module to the baseboard management controller, the baseboard management controller is placed in the middle of the two low-power system management modules, reducing the PCIe link length of the AIC card, and the AIC card is placed on one side of the low-power system management module.

[0064] ReferenceFigure 3 , it can be connected to multiple main resource pools upwards, such as H1 to Hn, and can be connected to NVMEs, GPUs, FPGAs, NICs, etc. downwards. Specifically, referring to Figure 6 and Figure 7 , Figure 7 is the topological connection diagram of the management module module. COM Express is the form factor of a module computer (COM), which is a highly integrated and compact PC and can be used for designing applications like an integrated circuit component. Each COM Express module integrates a core CPU and memory functions, general-purpose I / O, USB, audio, graphics (PEG), and Ethernet. The low-power system management module board uses an Intel ATOM C3000 processor with a base frequency of 2.4 GHz. The size of the low-power system management module module is 95mm * 125mm, which is mainly responsible for functions such as data operation, memory control, and terminal processing, and is the core module of the server system. It supports the PEX8780 high-performance switching chip witch and supports the expansion of peripheral IO devices; the memory uses 2 * SoDIMM (64GB); it uses the low-power system management module Type7 standard interface (USB interface standard); it supports 2-way NVME (NVM Express, called the Non-Volatile Memory Host Controller Interface Specification) / SATA memory (flash module); it supports 4-way USB3.0&2.0, VGA (video transmission standard) / GE (Gigabit Ethernet, i.e., Ethernet with a transmission rate of 1000M) and other interfaces; it reserves one PCIE X8 and supports the function expansion such as AIC; 20 HSIOs are shared by PCIe / SATA / USB3.0; it supports eMMC (Embedded Multi Media Card, embedded memory) 5.0 and eMMC 4.5. Using an Intel platform CPU with low power consumption can achieve low-power management, and using a modular design to encapsulate the Intel CPU on a module can facilitate platform upgrade or switching during use. Moreover, during use, when the requirements for redundant management scenarios are not high, one low-power system management module module can be used with a baseboard management controller to reduce the overall machine cost.

[0065] An embodiment of the present application provides a switching device, such as Figure 9 shown, the switching device includes a resource pool as above, including a box body. Along the first direction, a first area and a second area are arranged in the box body, where a switching board card is arranged in the first area, and a management board card is arranged in the second area. The switching board card is detachably connected to the management board card.

[0066] Referring to Figure 9 and Figure 10 ,Figure 9 It is a multi-layer switching board card. At least one layer of trays is arranged in the first area, and at least one group of slideways is arranged on the inner side of the box body. Each tray is slidably arranged on each group of slideways, and at least one layer of switching chip boards is arranged in each tray; a locking hook structure is arranged inside the box body for locking the tray in the box body. In order to better maintain the switching board card and prevent the 4-layer switching board card from being taken out after being disassembled and assembled in sequence, the 4-layer switching board card is respectively arranged on two trays. Each tray can be pulled out independently using the handles on both sides. During installation, after the tray is installed in place, the locking mechanism is locked to fix the tray to the chassis, and then the cable assembly is carried out. Figure 10 It is a management board card. Among them, the locking hook structure can refer to Figure 13 .

[0067] In some alternative embodiments, the management module includes: a first management module module, a second management module module, and a baseboard management controller; The first management module module and the second management module module are arranged at intervals, and the baseboard management controller is arranged between the first management module module and the second management module module; the first management module module and the second management module module face in opposite directions.

[0068] Specifically, referring to Figure 10 , since the two management module modules are 1+1 redundant and the two management module modules share a baseboard management controller, in order to shorten the wiring distance of the PCIe signal, USB (Universal Serial Bus) signal, and LPC (Linear Predictive Coding) signal of the two management module modules to the baseboard management controller, the baseboard management controller is arranged between the two low-power system management module modules, and the two low-power system management module modules are placed symmetrically about the center. It is convenient for various signal switching of the two low-power system management module modules. That is to say, by arranging the baseboard management controller between the first management module module and the second management module module, and the first management module module and the second management module module face in opposite directions, the wiring from the baseboard management controller to the two management module modules is the shortest, greatly saving the wiring distance.

[0069] Referring to Figure 12 . Figure 12 It is the structure of the PCIe resource pool. In order to occupy fewer U numbers in the 42U space of the cabinet to arrange the PCIe resource pool and support a larger number of interfaces, the overall size of the machine is defined as 2U in height to maximize the support for 40 CDFP interfaces, realizing a high-density PCIe resource pool.

[0070] Referring to Figure 11, the management board also supports the power supply input and distribution of the whole machine, the heat dissipation control of the whole machine, and the resource expansion inside or outside the machine. It supports 1+1 PSU (power supply) power input (compatible with HVDC PSU (power supply unit) input), where the PSUs are stacked vertically and blindly inserted into the management board through the PSU backplane. When using HVDC PSU, since the HVDC PSU has no built-in fan, a fan connector is reserved on the management board, and the chassis built-in fan is used to specifically dissipate heat for the HVDC PSU. It supports N+1 rotor-level fan heat dissipation control, and the fans are directly blindly inserted into the management board.

[0071] Reference Figure 5 , it supports the resource expansion of the low-power system management module, including supporting one PCIe 3.0x8 network card, one PCIe 3.0 x2 NVMe M.2 hard disk or SATA 3.0 M.2 hard disk (the two hard disks are connected to the management board through a transfer board), and one PCIe 3.0 x4 debugging interface (for SW) and other IO resources respectively. It can be understood that the 1+1 PSU redundant design improves the redundancy and stability of the system, which not only meets the power supply requirements of the system but also reduces the power supply cost.

[0072] Reference Figure 11 , Figure 11 is the front and rear window views of the resource pool. The hanging ears on both sides are the user interface modules of the whole machine, including the power button, indicator lights, UID (user identifier), Type-C debug interface (USB interface form standard), VGA (Video Graphic Array), and the USB interface of the low-power system management module. In the middle of the front window is a 4-layer switching board, and each layer contains a whole machine management network port and 10 CDFP interfaces. The rear window contains 4 6056 fans, two half-height AIC (vendors using Nvidia display chip graphics cards are called Add-In Card vendors) network cards, and two 1+1 redundant PSUs.

[0073] An embodiment of the present application provides a timing control method for a main system, as Figure 13 shown, the main system includes: a main resource pool, a coprocessor resource pool, and a resource pool as above; or the main system includes: a main resource pool, a coprocessor resource pool, and a switching device as above; the timing control method of the main system includes: Step 1: After the main resource pool, the coprocessor resource pool, and the resource pool are powered on, the baseboard management controller of the coprocessor resource pool and the baseboard management controller of the main resource pool send the ready signal to the baseboard management controller of the resource pool; Step 2: When receiving the power-on signal, the baseboard management controller of the resource pool controls the power-on based on the programmable logic device, and sends the power-on signal to the baseboard management controller of the coprocessor resource pool and the baseboard management controller of the resource pool through the network respectively; Step 3: After the baseboard management controllers of the coprocessor resource pool and the resource pool receive the power-on signal and complete the power-on, they respectively feedback the power-on completion signal to the baseboard management controller of the resource pool; Step 4: When receiving the power-off signal, the resource pool controls the power-off and outputs the relationship signal to the baseboard management controller of the coprocessor resource pool and the baseboard management controller of the resource pool respectively; Step 5: The baseboard management controllers of the coprocessor resource pool and the resource pool receive the power-off signal and perform power-off respectively.

[0074] Specifically, referring to Figure 14 , the main resource pool includes: a management module module, devices, a power-on power conversion chip, a standby power conversion chip, a programmable logic device, a baseboard manager, and a power supply. The resource pool includes: a switch chip, a management module module, devices, a power-on power conversion chip, a standby power conversion chip, a programmable logic device, a baseboard manager, and a power supply. The coprocessor resource pool includes: a coprocessor, a power-on power conversion chip, a standby power conversion chip, a programmable logic device, a baseboard manager, and a power supply.

[0075] Specifically, the power-on and power-off timing control method of the main system can be carried out according to the following steps: 1. After the power supply in each resource pool is powered on, the standby power conversion chip turns out each standby power, and sends the (Power Good, a key signal used in computer hardware to indicate stable power output) of the last standby power to the programmable logic device.

[0076] 2. When the standby power in each chassis is powered on and the programmable logic device and the baseboard management controller work normally, the programmable logic devices in the main resource pool and the coprocessor resource pool send the standby power PG signal to the baseboard management controller through I2C (Inter-Integrated Circuit) / UART (Universal Asynchronous Receiver / Transmitter).

[0077] 3. The baseboard management controller of each resource pool sends the signal indicating the completion of standby power PG to the baseboard management controller of the PCIe resource pool through the network. Each resource pool waits for the power-on signal of the power button of the PCIe resource pool to perform the next operation.

[0078] 4. After pressing the power-on button of the PCIe resource pool, the power-on signal is given to the programmable logic device, and the programmable logic device controls the EN (enable) signal of the main power supply.

[0079] 5. The power-on signal is sent to the baseboard management controller, and the baseboard management controller sends the power-on signal to the baseboard management controllers of each resource pool through the network.

[0080] 6. The baseboard management controllers of each resource pool send the power-on signal to the programmable logic devices of each resource pool through I2C / UART. The programmable logic devices control the EN of each VR (voltage regulator), and after receiving the PG of the last power supply, send the power-on completion signal to the baseboard management controller of the PCIe resource pool and the low-power system management module through the network and the baseboard management controller.

[0081] 7. After powering off the whole machine through the baseboard management controller or powering off by long pressing the power-on button, the shutdown signal is given to the programmable logic device. The programmable logic device controls not to output the EN signal of the main power supply, and powers off the main power supply of the resource pool.

[0082] 8. The baseboard management controller of the PCIe resource pool sends the shutdown signal to the baseboard management controllers of each resource pool. The baseboard management controllers of each resource pool power off the main power supply of the resource pool through the programmable logic device.

[0083] It should be noted that through the above process of coordinated power-on and power-off of resource pools, coordinated work between multiple resource pools can be achieved, and the upstream resource pool can normally identify the downstream PCIe devices in accordance with the PCIe protocol specification. That is to say, the resource pools can coordinate the power-on and power-off timings of the main resource pool and the coprocessor resource pool simultaneously.

[0084] The embodiment of the present application provides a method for controlling the reset timing of a main system. As Figure 15 shown, the main system includes: a main resource pool, a coprocessor resource pool, and a resource pool as above; or the main system includes: a main resource pool, a coprocessor resource pool, and a switching device as above. The method for controlling the reset timing of the main system includes: Step 1: After the main system is powered on, the management module of the resource pool scans the device identifiers of the coprocessor resource pool and the main resource pool respectively, and confirms the logical topology connection; Step 2: When the main resource pool receives the reset signal, the programmable logic device of the main resource pool sends the reset signal to the switching board of the resource pool; Step 3: After the switching board of the resource pool receives the reset signal and resets, the switching board of the resource pool sends the reset signal to the programmable logic device of the coprocessor resource pool; Step 4: The programmable logic device of the coprocessor resource pool receives the reset signal and resets.

[0085] Specifically, the method for controlling the reset timing of the main system can be carried out according to the following steps: 1. After being powered on, each resource pool independently enters the standby power state. After the power-on is completed, the low-power system management module automatically boots up. The programmable logic device identifies the presence of the switching card and reports it to the low-power system management module; 2. The low-power system management module scans the peer coprocessor ID (device identifier) through SMB_HOST (Server Message Block, a network file sharing protocol). Confirm the topology connection of the front-end interface of the data center.

[0086] 3. After pressing the power-on button of the resource pool, the switching chip is powered on. The switching chip identifies its own ID and reports it to the low-power system management module. The low-power system management module creates a topology table and matches it with the ports of the switching chip, and configures whether the ports of the switching chip are uplink or downlink.

[0087] 4. After pressing the button, the baseboard management controller notifies each resource pool to apply main power through the switch.

[0088] 5. After each resource pool is powered on, it waits for the reset signal. The main resource pool sends a reset to each module by the management module module and the programmable logic device. The baseboard management controller of the main resource pool sends the reset information to the baseboard management controller of the PCIe resource pool through the switch.

[0089] 6. The reset of other devices in the PCIe resource pool except the switching chip is triggered by the reset of the low-power system management module; the reset of the switching chip can be forwarded through two levels of the front-end interface of the data center by the reset of the uplink main resource pool, or the baseboard management controller can inform the programmable logic device through I2C, and the programmable logic device sends a reset to the switching chip and the front-end interface of the data center.

[0090] 7. The coprocessor resource pool receives the reset from the front-end interface of the data center, sends it to the programmable logic device, and the programmable logic device sends it to each device, or directly sends it to the GPU or SSD.

[0091] It should be noted that through the above process of collaborative reset of the resource pool, the collaborative work between multiple resource pools can be achieved, and the uplink resource pool can normally identify the downstream PCIe devices in accordance with the PCIe protocol specification. That is to say, the resource pool can simultaneously coordinate the reset timing of the main resource pool and the coprocessor resource pool.

[0092] In some optional implementation manners, the reset timing control method of the main system further includes: Step (1): When the main resource pool receives the reset signal, the programmable logic device of the main resource pool sends a reset signal to the programmable logic device of the resource pool; Step (2): After the programmable logic device in the resource pool receives and resets the reset signal, the programmable logic device in the resource pool sends a reset signal to the programmable logic device in the co-processor resource pool, or the programmable logic device in the resource pool sends a reset signal to the switching card in the resource pool; Step (3): The programmable logic device in the co-processor resource pool receives the reset signal and performs a reset.

[0093] Specifically, the reset timing control method of the main system can also be implemented by the programmable logic devices in each resource pool. Of course, in another reset timing control method, the reset can be performed together by the programmable logic device and the switching chip.

[0094] An embodiment of the present application provides a reset timing control method for a resource pool. The method is applied to the resource pool as described above, or the method is applied to the switching device as described above; the reset timing control method for the resource pool includes: Step 1: Control the management module module of the resource pool to send a reset instruction to the programmable logic device in the resource pool; Step 2: Control the programmable logic device in the resource pool to reset the switching chip in the switching card corresponding to the reset instruction, or send a reset instruction to the co-processor resource pool corresponding to the reset instruction.

[0095] Specifically, the reset timing control method of this resource pool is controlled by the management module module of the resource pool. First, when the management module module needs to individually reset a certain switching chip or a certain device, the management module module sends an instruction to the front-end interface of the data center of the PCIe resource pool through I2C / UART. Then, the front-end interface of the data center of the Sw resource pool resets a certain switching chip or sends a reset signal to the front-end interface of the data center of the co-processor resource pool or GPU / SSD. Thus, the self-reset process of the resource pool is realized through the management module module.

[0096] In some optional embodiments, the reset timing control method for the resource pool further includes: Step (1): When the switching chip in the resource pool receives the reset signal from the main resource pool, send a reset signal to the co-processor resource pool; Step (2): The switching chip module in the resource pool sends a reset completion signal to the management module in the resource pool.

[0097] Specifically, the reset timing control method of this resource pool is controlled by the switching chip of the resource pool. First, for example, in some cases when the switching chip needs to reset the downstream device alone, after receiving the reset signal from the main resource pool, the switching chip actively sends the reset signal through the hardware link according to its own upstream and downstream configuration relationship. After the switching chip sends the reset signal by itself, it notifies the backplane management controller and the low-power system management module through the INT interrupt pin that the downstream device has been reset.

[0098] The above has introduced in detail a resource pool and its reset control method, and the timing control method of the main system provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A resource pool, characterized in that, Including: At least one switching board and a management board, the management board including: a management module, an in-band management chip, and an out-of-band management chip, where The switching board is connected to at least one coprocessor resource pool and a main resource pool, and is used to implement data interaction between the coprocessor resource pool and the main resource pool, and connect to the external network based on an external network interface; The in-band management chip is connected to the switching board; The out-of-band management chip is connected to the switching board; The management module, the management module is respectively connected to the in-band management chip and the out-of-band management chip, and is used to perform in-band management on the switching board based on the in-band management chip, and is also used to manage the data transmitted through the external network interface based on the out-of-band management chip.

2. The resource pool according to claim 1, wherein The switching board includes: a first channel interface, where A first end of the first channel interface is connected to the in-band management chip, and a second end of the first channel interface is selectively connected to the in-band management chip or the out-of-band management chip.

3. The resource pool according to claim 2, wherein The management board further includes: a first network management chip, where The first network management chip is respectively connected to the second end of the first channel interface and the out-of-band management chip, and is used to enable the external network interface to communicate directly with the in-band network.

4. The resource pool according to claim 2, wherein The management module, the in-band management chip, and the out-of-band management chip are arranged on a first baseboard, and the management module includes: at least one management module module, a second network management chip, and a baseboard management controller, where At least one management module module is connected to the in-band management chip and is used to control the in-band management chip; The second network management chip is respectively connected to the baseboard management controller and the out-of-band management chip; The baseboard management controller is connected to the second network management chip and is used to manage the external network interface based on the out-of-band management chip.

5. The resource pool according to claim 4, characterized in that, The switching board includes: a second baseboard, a plurality of switching chips, a plurality of third network management chips, a plurality of fourth network management chips, and a second channel interface, where The second channel interface is used to connect the switching chips within the switching board to realize communication between the switching chips within the switching board; A plurality of switching chips are integrated on the second baseboard, and the plurality of switching chips on other switching boards are communicatively connected through the first channel interface, and are respectively connected to at least one coprocessor resource pool and a main resource pool; A plurality of switching chips are used to implement data interaction between the coprocessor resource pool and the main resource pool; A plurality of third network management chips, each third network management chip is connected between the external network interface and the first channel interface, and is used to enable the external network interface to communicate with the first channel interface; A plurality of fourth network management chips, each is connected between the first channel interface and the switching chip, and is used to enable the switching chip to communicate with the first channel interface.

6. The resource pool according to claim 5, wherein The switching board includes: a plurality of first selection paths, where A plurality of first selection paths, each first selection path is respectively connected to the second ends of a plurality of first channel interfaces and the in-band management chip, and is used to enable the in-band management chip to communicate with a plurality of switching boards simultaneously.

7. The resource pool according to claim 6, wherein The floor management controller is used to configure the in-band management chip, out-of-band management chip, second network management chip, and each third network management chip; or, The in-band management chip is used to configure the first network management chip and configure each third network management chip based on the first selection path; or, Each of the switching chips configures the connected fourth network management chip.

8. The resource pool according to claim 3, wherein When the resource pool includes multiple switching boards, the switching boards are stacked.

9. The resource pool according to claim 4, wherein The switching board further includes: a plurality of data center front-end interfaces, where The plurality of data center front-end interfaces are connected to one switching chip and are connected to the coprocessor resource pool or the main resource pool, and are used to enable the switching chip to communicate with the coprocessor resource pool and the main resource pool respectively.

10. The resource pool according to claim 4, wherein The management board further includes: a second selection path, and the first floor includes: a floor interface, The second selection path is respectively connected to the floor management controller and the floor interface; The floor interface is respectively connected to the out-of-band management chip and at least one management module module, and is used to extend the signal path so that the floor management controller is respectively connected to the out-of-band management chip and at least one management module module for backup communication.

11. The resource pool according to claim 10, wherein The management board further includes: a high-speed connector, where The high-speed connector is connected to the switching board and is used to connect an external management device or an expansion interface.

12. The resource pool according to claim 11, wherein The management board further includes: a programmable logic device, where The programmable logic device is connected to the floor management controller and is used to control the power-on and power-off timing and the reset timing, and send the power-on state and reset state of the whole machine to the floor management controller.

13. The resource pool according to claim 12, wherein The addresses of the third network management chip and the fourth network management chip are the same for easy management.

14. An exchange device, characterized in that, The switching device includes the resource pool according to any one of claims 12 or 13, including a cabinet, and along a first direction, a first area and a second area are arranged in the cabinet, where The first area is provided with a switching board, and the second area is provided with a management board, and the switching board is detachably connected to the management board.

15. The switching device according to claim 14, wherein, The management module includes: a first management module module, a second management module module, and a floor management controller; The first management module module and the second management module module are arranged at intervals, and the floor management controller is arranged between the first management module module and the second management module module; the first management module module and the second management module module face in opposite directions.

16. A timing control method for a main system, characterized in that The main system includes: A main resource pool, a coprocessor resource pool, and the resource pool according to any one of claims 12 or 13; Or the main system includes: a main resource pool, a coprocessor resource pool, and the switching device according to any one of claims 14 or 15; the timing control method of the main system includes: After the main resource pool, the coprocessor resource pool, and the resource pool are powered on, the floor management controllers of the coprocessor resource pool and the main resource pool send a ready signal to the floor management controller of the resource pool; When receiving a power-on signal, the baseboard management controller of the resource pool controls the power-on based on the programmable logic device, and sends the power-on signal to the baseboard management controller of the coprocessor resource pool and the baseboard management controller of the resource pool through the network respectively; After the baseboard management controllers of the coprocessor resource pool and the resource pool receive the power-on signal and complete the power-on, they respectively feedback the power-on completion signal to the baseboard management controller of the resource pool; When receiving a power-off signal, the resource pool controls the power-off and outputs a relationship signal to the baseboard management controller of the coprocessor resource pool and the baseboard management controller of the resource pool respectively; The baseboard management controllers of the coprocessor resource pool and the resource pool receive the power-off signal and perform power-off respectively.

17. A method for reset timing control of a main system, characterized in that The main system includes: The main resource pool, the coprocessor resource pool and the resource pool according to any one of claims 12 or 13; Or the main system includes: the main resource pool, the coprocessor resource pool and the switching device according to any one of claims 14 or 15; The reset timing control method of the main system includes: After the main system powers on successfully, the management module of the resource pool scans the device identifiers of the coprocessor resource pool and the main resource pool respectively, and confirms the logical topology connection; When the main resource pool receives a reset signal, the programmable logic device of the main resource pool sends a reset signal to the switching board of the resource pool; After the switching board of the resource pool receives the reset signal and resets, the switching board of the resource pool sends a reset signal to the programmable logic device of the coprocessor resource pool; The programmable logic device of the coprocessor resource pool receives the reset signal and performs a reset.

18. The reset timing control method of the main system according to claim 17, characterized in that, It also includes: When the main resource pool receives a reset signal, the programmable logic device of the main resource pool sends a reset signal to the programmable logic device of the resource pool; After the programmable logic device of the resource pool receives the reset signal and resets, the programmable logic device of the resource pool sends a reset signal to the programmable logic device of the coprocessor resource pool, or the programmable logic device of the resource pool sends a reset signal to the switching board of the resource pool; The programmable logic device of the coprocessor resource pool receives the reset signal and performs a reset.

19. A method for reset timing control of a resource pool, characterized in that, The method is applied to the resource pool according to any one of claims 12 or 13, or the method is applied to the switching device according to any one of claims 14 or 15; The reset timing control method of the resource pool includes: Controlling the management module of the resource pool to send a reset instruction to the programmable logic device of the resource pool; Controlling the programmable logic device of the resource pool to reset the switching chip in the switching board corresponding to the reset instruction, or sending a reset instruction to the coprocessor resource pool corresponding to the reset instruction.

20. The method for controlling the reset timing of the resource pool according to claim 19, wherein, It also includes: When the switching chip of the resource pool receives the reset signal of the main resource pool, it sends a reset signal to the coprocessor resource pool; The switching chip module of the resource pool sends a reset completion signal to the management module of the resource pool.

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