Data transmission method and device and cache verification device
By dynamically adjusting the packet transmission time interval configured in the buffer queue empty flag in the computing device, and using back-to-back transmission method, the problem of low data transmission efficiency in the level 3 cache architecture is solved, and the data processing performance of the CPU is improved.
Patent Information
- Application Number
- CN202510522143.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-08-01
AI Technical Summary
In existing computing devices, the third-level cache architecture has low data transmission efficiency between CPU and DRAM, which has affected CPU data processing performance, especially in asynchronous mode, clock resources are severely wasted.
By configuring the transmission time interval between data packets based on the buffer queue empty flag, dynamically adjusting the transmission time interval between the flag field packets and the running data packets, adopting back-to-back transmission method to reduce waiting time and optimize data transmission.
It improves the CPU's data processing performance, reduces the waste of clock resources, and improves data transmission efficiency.
Smart Images
Figure CN120407233A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of computer technologies, and particularly to a data transmission method, apparatus, and cache verification apparatus. Background Art
[0002] For the requirement of a relatively high CPU operating frequency, in existing computing devices, a three-level cache architecture is adopted, and a three-level cache (cache) is added between the CPU and the DRAM to increase the CPU operating frequency. Therefore, how to ensure the normal operation of the three-level cache and improve the data processing performance of the CPU has become an urgent problem to be solved by those skilled in the art. Summary of the Invention
[0003] In view of this, the embodiments of the present application provide a data transmission method, apparatus, and cache verification apparatus to improve the data processing performance of the CPU.
[0004] To achieve the above object, the embodiments of the present invention provide the following technical solutions:
[0005] In a first aspect, the embodiments of the present application provide a data transmission method, including: obtaining data to be transmitted; the data to be transmitted includes a flag field packet and a corresponding running data packet; the flag field packet includes transmission time interval information, and the transmission time interval information indicates the transmission time interval between the flag field packet and the corresponding running data packet; the transmission time interval information is dynamically changed based on at least one buffer queue empty flag configuration, and the clock cycles between adjacent buffer queue empty flags are dynamically changed; transmitting the flag field packet and the corresponding running data packet according to the transmission time interval.
[0006] In a second aspect, the embodiments of the present application provide a data transmission apparatus, including: a transmission data obtaining module, configured to obtain data to be transmitted; the data to be transmitted includes a flag field packet and a corresponding running data packet; the flag field packet includes transmission time interval information, and the transmission time interval information indicates the transmission time interval between the flag field packet and the corresponding running data packet; the transmission time interval information is dynamically changed based on at least one buffer queue empty flag configuration, and the clock cycles between adjacent buffer queue empty flags are dynamically changed; a data transmission module, configured to transmit the flag field packet and the corresponding running data packet according to the transmission time interval.
[0007] In a third aspect, an embodiment of the present application provides a cache simulation component, including a request response module for receiving and processing test request data sent by the cache under test; a data transmission device as described above, disposed within the request response module, for sending response data to the cache under test; the response data including a flag field packet and a corresponding running data packet; the request response module replying the response data to the cache under test through the data transmission device as described above; a function processing module for sending a consistency request to the cache under test; a storage module for storing the status information of the cache simulation component; and a consistency maintenance module for updating the storage module and performing a consistency check on the storage module.
[0008] In a fourth aspect, an embodiment of the present application provides a cache verification method, including: sending first request data to a cache under test and receiving test response data returned by the cache under test; receiving test request data sent by the cache under test and returning first response data to the cache under test through the data transmission method as described above; and checking whether the test request data and the test response data of the cache under test are correct.
[0009] In a fifth aspect, an embodiment of the present application provides a cache verification system, including: a cache under test; an upstream cache module for receiving response data sent by the cache under test and sending request data to the cache under test; and a cache simulation component as described above for simulating a downstream cache of the cache under test to receive request data sent by the cache under test, return response data to the cache under test 100, and maintain data consistency between the cache under test and the cache simulation component.
[0010] In a sixth aspect, an embodiment of the present application provides a computing device, including a cache under test and the cache verification system as described above.
[0011] In a seventh aspect, an embodiment of the present application provides a storage medium storing computer instructions, and when the computer instructions are executed, the data transmission method as described above is implemented.
[0012] An embodiment of the present application further provides a storage medium storing a design program of a chip, and when the design program is executed, the power supply design method as described above is implemented.
[0013] An embodiment of the present application further provides a computer device including the chip as described above.
[0014] The data transmission method provided by the embodiments of the present application includes: obtaining data to be transmitted; the data to be transmitted includes a flag field packet and a corresponding running data packet; the flag field packet includes transmission time interval information, and the transmission time interval information indicates the transmission time interval of the flag field packet and the corresponding running data packet; the transmission time interval information changes dynamically based on at least one buffer queue empty flag configuration, and the clock cycles between adjacent buffer queue empty flags change dynamically; transmitting the flag field packet and the corresponding running data packet according to the transmission time interval.
[0015] It can be seen that by making the transmission time interval of the flag field packet and the corresponding running data packet during transmission based on the buffer queue empty flag configuration, the number of buffer queue empty flags is used to record the transmission time interval. Thus, by utilizing the characteristic that the clock cycles between adjacent buffer queue empty flags change dynamically, the transmission time interval of the possibly changing flag field packet and the corresponding running data packet during transmission is recorded by a fixed number of buffer queue empty flags. Therefore, the transmission time interval of the flag field packet and the corresponding running data packet during transmission can be dynamically configured according to transmission requirements, and the minimum is the number of one buffer queue empty flag, thereby shortening the waiting time required for the flag field packet and the corresponding running data packet during transmission, reducing the waste of clock resources, and improving the data processing performance of the CPU. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.
[0017] Figure 1 It is a schematic structural diagram of a three-level cache architecture;
[0018] Figure 2 It is a schematic structural diagram of a cache verification device;
[0019] Figure 3 It is a schematic flowchart of a data transmission method provided by the embodiments of the present application;
[0020] Figure 4 It is another schematic flowchart of a data transmission method provided by the embodiments of the present application;
[0021] Figure 5 It is a schematic timing diagram of a data transmission method provided by the embodiments of the present application;
[0022] Figure 6Another timing schematic diagram of the data transmission method provided by the embodiment of the present application;
[0023] Figure 7 Yet another timing schematic diagram of the data transmission method provided by the embodiment of the present application;
[0024] Figure 8 Structural schematic diagram of the data transmission device provided by the embodiment of the present application;
[0025] Figure 9 Structural schematic diagram of the cache verification device provided by the embodiment of the present application;
[0026] Figure 10 Timing relationship diagram of data interaction between the cache under test and the cache simulation component in the synchronous mode;
[0027] Figure 11 Timing relationship diagram of continuously sending multiple composite mode data. Detailed implementation manners
[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0029] For the requirement of a relatively high CPU working frequency, in the existing computing device, a three-level cache architecture is adopted, and a three-level cache (cache) is added between the CPU and the DRAM to improve the CPU working frequency. The existing CPUs are usually multi-core processor architectures. Each CPU core has an independent L1 cache and L2 cache, and all CPU cores share an L3 cache. The CPU cache and the storage system use data blocks of a fixed size for interaction, and this data block is called a cache line. L2 is in the middle position of the three-level cache. It mainly processes the request commands sent by the upstream L1 cache, and receives and processes the resp (response) information replied by the downstream L3 cache and replies it to the upstream L1 cache. For example, when the CPU needs to load a data block, it will first access the L1 cache. If the data block is found in the L1 cache, the L1 cache will make a reply and reply the data block to the CPU in the form of a response. If the data block is not found in the L1 cache, the L1 cache will access the L2 cache. Similar to the processing of the L1 cache, the L2 cache will also decide whether to directly reply to the L1 cache or send a request instruction to the downstream L3 cache according to the access result of the data block.
[0030] Specifically, a structural schematic diagram of a three-level cache structure is as Figure 1As shown, L2 is the second level of the three - level cache and also the outermost layer of the CPU core. As Figure 1 shown, existing CPUs mostly have a multi - core structure, that is, one L3 is connected to multiple CPU cores, and each CPU core corresponds to an L2 cache. The upstream of the L2 cache is the L1 cache, which is divided into ICache (instruction cache) and DCache (data cache). The downstream of the L2 cache is the L3 cache, which is responsible for handling data interaction between multi - core tasks and cache coherence checking.
[0031] When the CPU requests a certain data, it will access the above - mentioned three - level cache level by level. If it cannot find the data in the above - mentioned three - level cache, it will access the memory. If the data is found in a certain level of the above - mentioned three - level cache, the data will be returned to the CPU level by level along the above - mentioned three - level cache in the form of a response.
[0032] For the verification of the L2 cache, it is necessary to simultaneously pay attention to the data operations of the upstream and downstream of the L2 cache. For the upstream requests, they need to be processed and response information is sent back to the upstream according to the access results or processed requests are sent to the downstream. If there is response information transmitted from the downstream, the L2 will store this information in the L2 cache and continue to send response information back to the upstream L1 cache.
[0033] When verifying the L2 cache, generally, the function - complete verification under a single - core situation is given priority. If it can be ensured that the function of the L2 cache of a single core is complete, theoretically, in a multi - core environment, the function completeness of the L2 cache can also be guaranteed. Therefore, only a single L2 cache needs to be verified during the verification process of the L2 cache.
[0034] A structural schematic diagram of a verification environment for the L2 cache is as Figure 2 shown. By separately designing module components with the same functions as the upstream and downstream devices of the L2 cache, the data interaction method between the upstream and downstream and the L2 Cache is simulated to verify the function completeness of the L2 cache.
[0035] As Figure 2 shown in the verification environment, the L2 cache and the L3 cache are combined into one part to participate in the verification process of the L2 cache, and only the L2 cache and the L3 cache can be verified together based on the simulated data path module. This verification environment increases the complexity of verifying the L2 cache.
[0036] In this verification environment, the excitation can only simulate the data path module, which configures the L2 cache after passing through the L3 cache. For the L2 cache, it cannot directly receive the expected excitation effectively. When the excitation is processed and then sent to the L2 cache, there may be differences from the expected excitation. Secondly, if a problem is found during verification, during the process of locating the problem, it is necessary to start from the L3 cache and locate step by step until the L2 cache. For the L2 cache, this problem location process is too complex and cumbersome.
[0037] In addition, the response from the L3 cache to the L2 cache is sent to the L2 cache in the form of a data packet (package) composed of a bunch of different data. The data in the data packet can be roughly divided into two categories, namely handler_package (header file data packet) and data_package (running data packet). This data packet structure is called a composite mode (composite pattern). The handler_package mainly stores the operation valid flag field, and the data_package stores the running data (data) field from the L3 cache to the L2 cache in the response. Only when the corresponding valid flag in the handler_package is set to valid, the corresponding data in the data_package is valid.
[0038] There are two interaction modes when the L3 cache and the L2 cache perform data interaction, namely the synchronous mode and the asynchronous mode. In the synchronous mode, the corresponding handler_package and data_package are not sent to the L2 at the same time. There is a fixed clock cycle difference between the corresponding handler_package and data_package in the middle. The L3 cache first sends the handler_package, and then sends the data_package to the L2 cache after an interval of a fixed number of clock cycles.
[0039] In the asynchronous mode, the number of clock cycles between the corresponding handler_package and data_package is based on the empty / full judgment of the asynchronous first-in-first-out cache. At this time, if the number of clock cycles between the corresponding handler_package and data_package is to be a fixed number of clock cycles, the value of the fixed number of clock cycles may be dozens or even hundreds, resulting in too long waiting times for the handler_package and data_package, and thus wasting a large amount of clock resources and affecting the data processing performance of the CPU.
[0040] To solve the above problems, an embodiment of the present application provides a data transmission method, which improves data transmission efficiency by configuring the transmission time interval between data packets based on the buffer queue empty flag. As an alternative implementation, Figure 3 shows a schematic flowchart of the cache verification method provided by the embodiment of the present application. As Figure 3 shown, the cache verification method provided by the embodiment of the present application includes the following steps.
[0041] Step S10: Obtain the data to be transmitted. The data to be transmitted includes a flag field packet and a corresponding running data packet. The flag field packet includes transmission time interval information, and the transmission time interval information indicates the transmission time interval between the flag field packet and the corresponding running data packet; the transmission time interval information is configured based on at least one buffer queue empty flag, and the clock cycles between adjacent buffer queue empty flags change dynamically.
[0042] It should be noted that in the asynchronous mode, the data to be transmitted cannot be transmitted in any clock cycle. It is necessary to determine whether the data to be transmitted can be transmitted according to the empty / full flag signal of the asynchronous first-in-first-out cache (FIFO), that is, the buffer queue empty flag (fifordy). When the buffer queue empty flag is 0, it means that the buffer queue is full, and at this time, the data to be transmitted cannot be transmitted. When the buffer queue empty flag is 1, it indicates that the buffer queue is not full, and at this time, the data to be transmitted can be transmitted.
[0043] Furthermore, since the clock cycles between adjacent buffer queue empty flags change dynamically, the transmission time interval between the flag field packet and the running data packet cannot be a fixed clock cycle, but can be converted to record the time when the buffer queue flag is 0. And since when the buffer queue flag becomes 0, the system will fixedly consume one clock cycle to release the first-in-first-out cache, and then the buffer queue flag becomes 0. Therefore, the time when the buffer queue flag is 0 is also the number of times the buffer queue empty flag appears.
[0044] Step S20: Transmit the flag field packet and the corresponding running data packet according to the transmission time interval.
[0045] In this way, by configuring the transmission time interval between the flag field packet and the corresponding running data packet during transmission based on the buffer queue empty flag, the number of buffer queue empty flags is used to record the transmission time interval. Thus, by utilizing the characteristic that the clock cycles of the intervals between adjacent buffer queue empty flags change dynamically, the transmission time interval of the possibly changing flag field packet and the corresponding running data packet during transmission is recorded by a fixed number of buffer queue empty flags. As a result, the transmission time interval of the flag field packet and the corresponding running data packet during transmission can be dynamically configured according to the transmission requirements, and the minimum is the number of one buffer queue empty flag, thereby shortening the waiting time required for the flag field packet and the corresponding running data packet during transmission, reducing the waste of clock resources, and improving the data processing performance of the CPU.
[0046] Furthermore, in an alternative implementation, when the transmission time interval between the flag field packet and the running data packet is recorded in the form of the number of buffer queue empty flags that appear. To improve system performance, the transmission time interval between the flag field packet and the running data packet can be shortened to only one buffer queue empty flag appearing. Preferably, to avoid an overly long transmission time interval between the flag field packet and the running data packet, in an alternative implementation, the maximum value of the transmission time interval is 4 buffer queue empty flags appearing.
[0047] Furthermore, in an alternative implementation, the transmission rule between multiple flag field packets is back-to-back transmission. For example, the first flag field packet and the second flag field packet are back-to-back transmitted. The back-to-back transmission is B2B (Back-to-Back) transmission, which is a way of continuously sending data or instructions on a communication bus or interface, meaning that there is no idle or waiting period inserted between the two transmitted data packets.
[0048] Specifically, that is, immediately after the first flag field packet is sent, the second flag field packet starts to be sent. In this asynchronous mode, a time interval is supported during the transmission of adjacent running data packets, while there is no interval in the transmission of adjacent flag field packets.
[0049] For example, when the data to be transmitted includes a first flag field packet, a second flag field packet, a first running data packet, and a second running data packet, there is a separation of 1 fifordy between the first flag field packet and the first running data packet, and a separation of 4 fifordy between the second flag field packet and the second running data packet. At this time, it must be ensured that the first running data packet is sent before the second running data packet, and the scenario where the second running data packet is sent before the first running data packet cannot occur.
[0050] Further, when continuously transmitting multiple pieces of the data to be transmitted, it is also necessary to ensure that there is no trampling between the running data packets of two pieces of the data to be transmitted during the transmission process. That is, when continuously transmitting the first data to be transmitted and the second data to be transmitted, the running data packets of the second data to be transmitted must be transmitted after the running data packets of the first data to be transmitted, and cannot be transmitted simultaneously with the running data packets of the first data to be transmitted, nor can they be transmitted before the running data of the first data to be transmitted.
[0051] In an alternative implementation, the step of transmitting the flag field packet in step S20 includes step S31: obtaining the flag field packet to be transmitted and transmitting it.
[0052] Step S32: Detect whether there is an incompletely transmitted flag field packet. If there is an incompletely transmitted flag field packet, re-detect after waiting for one clock cycle until the incompletely transmitted flag field packet is completely sent.
[0053] If there is no incompletely transmitted previous flag field packet, then continue to execute step S33: Detect whether there is a flag field packet to be transmitted. If there is, obtain the flag field packet to be transmitted and transmit it. If not, transmit the running data packet according to the transmission time interval information in the flag field packet corresponding to the running data packet.
[0054] Further, in an alternative implementation, before transmitting the running data packet, it is necessary to ensure that the flag field packet corresponding to the currently transmitted running packet is completely transmitted and there is no incompletely transmitted running data packet. Therefore, the step of transmitting the running data packet according to the transmission time interval information in the flag field packet corresponding to the running data packet includes step S34: Detect whether the flag field packet corresponding to the currently to-be-transmitted running data packet has been completely transmitted. If it has been completely transmitted, execute the subsequent steps; otherwise, continue to wait until the flag field packet corresponding to the currently to-be-transmitted running data packet is completely transmitted.
[0055] Step S35: Detect whether there is an incompletely transmitted running data packet. If there is, re-detect after waiting for one clock cycle until the incompletely transmitted running data packet is completely transmitted.
[0056] If not, execute step S36: Transmit the currently to-be-transmitted running data packet according to the transmission time interval information in the flag field packet corresponding to the currently to-be-transmitted running data packet.
[0057] In the asynchronous mode, the transmission scenarios of a single flag field packet and a running data packet are as Figure 5 shown Figure 5Shows the transmission with a non-fixed time gap between the flag field packet and the running data packet during the period when the first-in-first-out buffer is not full (i.e., when fifordy = 1). As Figure 5 shown, there is a time difference of 2 fifordy durations between handler1_0 and data1_0, and a time difference of 4 fifordy durations between handler1_1 and data1_1.
[0058] During the simulation, in the asynchronous mode, due to the clock frequency difference between the buffer under test and the downstream buffer, the situation where the first-in-first-out buffer is full (fifordy = 0) often occurs. Therefore, the downstream buffer needs to support correct driving in such scenarios. As Figure 6 shown, the situation of fifordy = 0 is encountered during the transmission of a flag field packet and a running data packet. It can be seen that there is a time difference of 2 fifordy durations between handler1_0 and data1_0, and a time difference of 3 fifordy durations between handler1_1 and data1_1.
[0059] Another timing diagram of the data transmission method provided by the embodiment of the present application is as Figure 7 shown. Three flag field packets of the flag field packet and the running data packet are transmitted in a back-to-back form. It can be seen that in the back-to-back transmission, a split scenario occurs for the running data packet, that is, multiple running data packets are not continuously transmitted, and flag field packets may be transmitted between multiple running data packets. At the same time, there should be no trampling between multiple running data packets.
[0060] The embodiment of the present application also provides a data transmission device, which improves the data transmission efficiency by configuring the transmission time interval between data packets based on the buffer queue empty flag. As an optional implementation, Figure 8 shows a schematic structural diagram of the buffer verification device provided by the embodiment of the present application. As Figure 8 shown, the data transmission device provided by the embodiment of the present application includes the following structure.
[0061] A transmission data acquisition module 110, configured to acquire data to be transmitted; the data to be transmitted includes a flag field packet and a corresponding running data packet; the flag field packet includes transmission time interval information, and the transmission time interval information indicates the transmission time interval between the flag field packet and the corresponding running data packet; the transmission time interval information is configured based on at least one buffer queue empty flag, and the clock cycles between adjacent buffer queue empty flags change dynamically;
[0062] A data transmission module 120, configured to transmit the flag field packet and the corresponding running data packet according to the transmission time interval.
[0063] Further, in an alternative implementation, when the data transmission module 120 transmits multiple flag field packets, the transmission rule between multiple flag field packets is back-to-back transmission.
[0064] Further, in an alternative implementation, the data transmission module 120 is configured to detect whether there is a flag field packet to be transmitted and transmit it; detect whether there is a previous flag field packet that has not been fully transmitted; if there is a flag field packet that has not been fully transmitted, wait for one clock cycle and then re-detect until the previous flag field packet is completely sent; if there is no previous flag field packet that has not been fully transmitted, continue to detect whether there is a flag field packet to be transmitted and transmit it; transmit the corresponding running data packet according to the transmission time interval.
[0065] Further, in an alternative implementation, the data transmission module 120 is configured to detect whether the flag field packet corresponding to the currently to-be-transmitted running data packet has been completely transmitted; if not, wait for the corresponding flag field packet; if it has been completely transmitted, detect whether there is a running data packet that has not been fully transmitted; if there is, wait for one clock cycle and then re-detect; if not, transmit the currently to-be-transmitted running data packet according to the transmission time interval information in the flag field packet corresponding to the currently to-be-transmitted running data packet.
[0066] In this way, by configuring the transmission time interval of the flag field packet and the corresponding running data packet during transmission based on the buffer queue empty flag, the number of buffer queue empty flags is used to record the transmission time interval. Thus, by utilizing the characteristic that the clock cycle of the interval between adjacent buffer queue empty flags changes dynamically, the transmission time interval of the possibly changing flag field packet and the corresponding running data packet during transmission is recorded by a fixed number of buffer queue empty flags. As a result, the transmission time interval of the flag field packet and the corresponding running data packet during transmission can be dynamically configured according to the transmission requirements, and the minimum is the number of buffer queue empty flags, thereby shortening the waiting time required for the flag field packet and the corresponding running data packet during transmission, reducing the waste of clock resources, and improving the data processing performance of the CPU.
[0067] To solve the above problems, an embodiment of the present application provides a cache simulation component by using the data transmission method and the simulated L3 cache as described above. As an alternative implementation, Figure 9 shows a schematic structural diagram of the cache verification device provided by the embodiment of the present application. As Figure 9 shown, the cache simulation component provided by the embodiment of the present application includes the following structure.
[0068] A request response module 310 is configured to receive and process test request data sent by a cache under test. A data transmission device 313 as described above is provided in the request response module 310 for sending response data to the cache under test; the response data includes a flag field packet and a corresponding running data packet. The request response module 310 replies the response data to the cache under test through the data transmission device 313 as described above.
[0069] Further, in an alternative implementation, the request response module 310 includes: a request monitor 311 (Req_monitor) and a request processing unit 312 (Req_handler). The data transmission device 313 as described above is provided in the request response module 310.
[0070] The request monitor 311 is configured to detect and receive a request data packet (ReqPackage) sent by the cache under test 100. The request processing unit 312 is configured to perform corresponding processing on the request data packet from the cache under test 100 to obtain a response data packet (resp package) generated after processing corresponding to the request data packet.
[0071] Further, for the data interaction between the cache under test 100 and the cache simulation component 300, the default transmission mode is a synchronous mode, i.e., a fixed period. In a transmission scenario that requires an asynchronous mode, it is necessary to optimize the transmission mode to adapt to the non-fixed period transmission of the asynchronous mode.
[0072] The timing diagram of the data interaction between the cache under test 100 and the cache simulation component 300 in the synchronous mode is as Figure 10 shown. The size of a running data in the cache is 512 bits, and since the size of the running data packet for transmitting data is 256 bits, a running data needs to be transmitted by two running data packets. Similarly, two flag field packets are required for transmitting the flag field. Two flag field packets and two running data packets form composite mode data. As can be seen from Figure 10 it, after the flag field packet is sent, the corresponding running data packet of each flag field packet starts to be transmitted at the moment of the fourth fixed clock cycle.
[0073] The above shows the transmission of a single composite mode data with a fixed period. Figure 11 The timing diagram shown is for continuously sending multiple composite mode data. The multiple composite mode data are transmitted in a back-to-back manner. As shown in Figure 11 it, there is no time gap between the transmissions of the flag field packets of three composite mode data, and there is also no time gap between the corresponding running data packets of the flag field packets.
[0074] If the data interaction between the cache 100 to be measured and the cache simulation component 300 is in an asynchronous mode, the number of clock cycles between the flag field packet and the running data packet is not a fixed number of clock cycles at this time. Instead, it is determined according to the empty / full status of the first-in-first-out cache when to perform the transmission. If the above timing relationship is still used for transmission, the number of clock cycles between the flag field packet and the running data packet may be dozens or even hundreds of clock cycles, resulting in a large waste of clock resources and affecting the data transmission efficiency.
[0075] For the data in the asynchronous mode, the transmission method executed by the data transmission device 313 includes obtaining the data to be transmitted; the data to be transmitted includes a flag field packet and a corresponding running data packet; the flag field packet includes transmission time interval information, and the transmission time interval information indicates the transmission time interval between the flag field packet and the corresponding running data packet; the transmission time interval information is dynamically changed based on at least one buffer queue empty flag configuration, and the clock cycles between adjacent buffer queue empty flags change dynamically; the flag field packet and the corresponding running data packet are transmitted according to the transmission time interval.
[0076] In this way, by basing the transmission time interval between the flag field packet and the corresponding running data packet on the buffer queue empty flag configuration during transmission, the number of buffer queue empty flags is used to record the transmission time interval. Thus, by utilizing the characteristic that the clock cycles between adjacent buffer queue empty flags change dynamically, the transmission time interval between the possibly changing flag field packet and the corresponding running data packet is recorded by a fixed number of buffer queue empty flags. As a result, the transmission time interval between the flag field packet and the corresponding running data packet during transmission can be dynamically configured according to the transmission requirements, and the minimum is the number of one buffer queue empty flag, thereby shortening the waiting time required for the flag field packet and the corresponding running data packet during transmission, reducing the waste of clock resources, and improving the data processing performance of the CPU.
[0077] The function processing module 320 is used to send a coherence request to the cache to be measured. The function processing module 320 includes: a probe request module 321 and a pull request module 322.
[0078] The probe request module 321, that is, the probe function module (Probe_agent). The probe request is a signal for maintaining cache coherence in a multi-processor or multi-core system. By sending a probe request, a processor can obtain the status of data blocks in other caches, coordinate read and write operations of data, and ensure that data copies in all caches are consistent.
[0079] The detection request module 321 internally includes a detection request generation unit (Probe req generator) for generating a detection request data packet to simulate the detection operation of the cache simulation component 300 on the cache under test 100. The detection request module 321 further includes a detection request data packet driving unit (Probe driver) for sending the detection request data packet (probe package) to the cache under test 100. Since the cache under test 100 is a real design platform, it will process the detection request data packet from the cache simulation component 300, generate a corresponding detection response data packet (probe resp package) and return it to the cache simulation component 300. The detection request module 321 also includes a detection response monitoring unit (Probe Resp monitor) for sampling the detection response data packet.
[0080] The Pull request module 322, that is, the Pull_agent (pull function module). The pull request is an operation in which the cache actively requests data from the next lower storage layer (such as a higher-level cache or main memory). When the data required by the processor is not in the current cache level, a cache miss will occur. At this time, the cache needs to send a pull request to the next lower memory to obtain the data.
[0081] The pull request module 322 internally includes a pull request generation unit (Pull req generater) for generating a pull request data packet (pull req package) to simulate the pull operation of the cache simulation component 300 on the cache under test 100. The pull request module 322 also includes a pull request data packet driving unit (Pull driver) for sending the pull request data packet including the pull operation to the cache under test 100. After receiving the pull request data packet sent by the cache simulation component 300, the cache under test 100 will perform corresponding processing inside the cache under test 100, generate a corresponding pull response data packet and return it to the cache simulation component 300. The pull request module 322 also includes a pull response monitoring unit (Pull Resp monitor) for sampling the pull response data packet.
[0082] Further, in an optional implementation, the cache simulation component 300 further includes a storage module 330 for storing the state information of the cache simulation component 300. Specifically, the storage module 330 includes a shadow tag macro unit (STM, Shadow Tag Macro) 331 and a level 3 cache macro module (L3M) 332.
[0083] The shadow tag macro cell 331 is an auxiliary structure for cache simulation and verification, mainly used to mirror the tag state of the cache. It acts as a shadow copy of the cache tag, recording various status information of the cache line, such as the valid bit, dirty bit, and tag.
[0084] The shadow tag macro cell 331 of the cache simulation component 300 contains a copy of the tag of the cache 100 to be tested existing in each core, including the address and status of the cache line. The cache simulation component 300 uses this to view the status of a certain cache line in the current cache 100 to be tested. Every time the cache simulation component 300 interacts with the cache 10 to be tested, it needs to synchronously check the specific status in the shadow tag macro cell 331.
[0085] The level 3 cache macro module (L3M, Level 3 Cache Model) 332 is used to store the data loaded from the main memory or the next-level cache to improve the data access speed. It stores the tag information and data information of the cache lines of the cache simulation component 300. According to the upstream and downstream operations, it updates the status of the corresponding cache lines in the cache simulation component 300 in real time and performs cache coherence detection, thereby achieving the purpose of maintaining cache coherence.
[0086] Further, in an alternative implementation, the cache simulation component includes a coherence maintenance module 340, which is used to update the shadow tag macro cell 331 and the level 3 cache macro module 332 and perform cache coherence checks on the shadow tag macro cell 331.
[0087] Further, in an alternative implementation, the coherence maintenance module 340 is used for status update. According to the data sampled by each different detection unit, it updates the status of the cache lines of the shadow tag macro cell 331 and the level 3 cache macro module 332 inside the cache simulation component 300 according to the cache coherence protocol.
[0088] Further, in an alternative implementation, the coherence maintenance module 340 is also used for cache coherence checks on the shadow tag macro cell 331.
[0089] Specifically, for interaction of the request-response type, according to the combination of the request type of the cache 100 to be tested, the current state of the cache line in the shadow tag macro cell 331, and the resp state of the response of the cache simulation component 300 to the cache 100 to be tested, a check is performed in the cache of the cache simulation component 300. If it conforms to the coherence protocol, the shadow tag macro cell 331 is updated accordingly.
[0090] For the interaction related to the probe request, according to the combination of the type of the pull request sent by the cache simulation component 300 to the cache under test 100, the status of the current cache line in the shadow tag macro cell 331, and the status of the response from the cache under test 100 to the cache simulation component 300 (probe resp state), check in the cache of the cache simulation component 300. If it conforms to the coherence protocol, update the shadow tag macro cell 33 accordingly.
[0091] For the interaction related to the pull request, the operation sources of the general pull operation include: the victim operation of the cache under test 100, the write request (wrsize req) of the cache under test 100, and the probe request operation. Pulling is mainly responsible for transmitting the data of the cache under test 100 to the cache simulation component 300 and even the downstream data transmission path. Determine whether to update the shadow tag macro cell 331 according to the type of the operation source. The victim type operation of the cache under test 100 will trigger a pull and update the status of the cache line in the shadow tag macro cell 331 to invalid. The pull triggered by the probe operation does not update the shadow tag macro cell 331. The pull caused by the write request also does not update the shadow tag macro cell 331. Because the cache simulation component 300 will update the shadow tag macro cell 331 based on the probe operation and the request itself of the write request.
[0092] The embodiment of the present application also provides a cache verification method, which improves the verification efficiency of the L2 cache by using the data transmission method and the simulated L3 cache as described above. As an optional implementation, the cache verification device provided by the embodiment of the present application includes the following steps.
[0093] Send the first request data to the cache under test and receive the test response data returned by the cache under test; receive the test request data sent by the cache under test and return the first response data to the cache under test through the data transmission method as described above; check whether the test request data and the test response data of the cache under test are correct.
[0094] The embodiment of the present application also provides a cache verification device, which improves the verification efficiency of the L2 cache by using the data transmission method and the simulated L3 cache as described above. As an optional implementation, Figure 9 The structural schematic diagram of the cache verification device provided by the embodiment of the present application is shown. As Figure 9 shown, the cache verification device provided by the embodiment of the present application includes the following structure.
[0095] The upstream cache module 200 is used to receive the test response data sent by the cache under test 100 and send the first request data to the cache under test.
[0096] The cache simulation component 300 as described above is used to simulate the downstream cache of the cache under test 100, receive the request data under test sent by the cache under test 100, return the first response data to the cache under test 100, and maintain data consistency between the cache under test 100 and the cache simulation component 300.
[0097] In this way, the cache verification device configures the transmission time interval when the flag field packet of the response data and the corresponding running data packet are transmitted based on the buffer queue empty flag, and records the transmission time interval using the number of buffer queue empty flags. Thus, by utilizing the characteristic that the clock cycle of the adjacent buffer queue empty flag intervals changes dynamically, the transmission time interval when the flag field packet and the corresponding running data packet are transmitted is recorded using a fixed number of buffer queue empty flags. As a result, the transmission time interval when the flag field packet and the corresponding running data packet are transmitted can be dynamically configured according to the transmission requirements, and the minimum is the number of one buffer queue empty flag, thereby shortening the waiting time required when the flag field packet and the corresponding running data packet are transmitted, improving the data transmission efficiency between the cache under test and the cache simulation component, and improving the verification efficiency of the cache under test.
[0098] An embodiment of the present application further provides a cache verification architecture, including a cache under test and the cache verification device as described above.
[0099] An embodiment of the present application further provides a storage medium, which stores computer instructions, and when the computer instructions are executed, the data transmission method as described above is implemented.
[0100] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.
Claims
1. A data transmission method, characterized in that including: obtaining data to be transmitted; the data to be transmitted includes a flag field packet and a corresponding running data packet; the flag field packet includes transmission time interval information, and the transmission time interval information indicates the transmission time interval of the flag field packet and the corresponding running data packet; the transmission time interval information is configured based on at least one buffer queue empty flag, and the clock cycles between adjacent buffer queue empty flags vary dynamically; transmitting the flag field packet and the corresponding running data packet according to the transmission time interval.
2. The data transmission method according to claim 1, wherein The transmission rule between multiple flag field packets is back-to-back transmission.
3. The data transmission method according to claim 1, wherein The step of transmitting the flag field packet and the corresponding running data packet according to the transmission time interval includes: obtaining a flag field packet to be transmitted and transmitting it; detecting whether there is an incompletely transmitted flag field packet; if so, waiting for one clock cycle and then detecting again; if there is no incompletely transmitted previous flag field packet, then detecting whether there is a flag field packet to be transmitted; if so, obtaining the flag field packet to be transmitted and transmitting it; if not, sending the running data packet according to the transmission time interval information in the flag field packet corresponding to the running data packet.
4. The data transmission method according to claim 3, wherein The step of sending the running data packet according to the transmission time interval information in the flag field packet corresponding to the running data packet includes: detecting whether the flag field packet corresponding to the currently to-be-transmitted running data packet has been transmitted completely; if not, waiting for the corresponding flag field packet; if it has been transmitted completely, then detecting whether there is an incompletely transmitted running data packet; if so, waiting for one clock cycle and then detecting again; if not, sending the currently to-be-transmitted running data packet according to the transmission time interval information in the flag field packet corresponding to the currently to-be-transmitted running data packet.
5. A data transmission device, characterized in that, including: a transmission data acquisition module for obtaining data to be transmitted; the data to be transmitted includes a flag field packet and a corresponding running data packet; the flag field packet includes transmission time interval information, and the transmission time interval information indicates the transmission time interval of the flag field packet and the corresponding running data packet; the transmission time interval information is configured based on at least one buffer queue empty flag, and the clock cycles between adjacent buffer queue empty flags vary dynamically; a data transmission module for transmitting the flag field packet and the corresponding running data packet according to the transmission time interval.
6. The data transmission device according to claim 5, wherein When the data transmission module transmits multiple flag field packets, the transmission rule between multiple flag field packets is back-to-back transmission.
7. The data transmission device according to claim 5, characterized in that, The data transmission module is used to obtain a flag field packet to be transmitted and transmit it; detect whether there is an incompletely transmitted flag field packet; if so, wait for one clock cycle and then detect again; if there is no incompletely transmitted previous flag field packet, then detect whether there is a flag field packet to be transmitted; if so, obtain the flag field packet to be transmitted and transmit it; if not, send the running data packet according to the transmission time interval information in the flag field packet corresponding to the running data packet.
8. The data transmission device according to claim 7, wherein The data transmission module is further configured to detect whether the flag field packet corresponding to the current operation data packet to be transmitted has been completely transmitted; if not, wait for the corresponding flag field packet; if it has been completely transmitted, detect whether there is an operation data packet that has not been completely transmitted. If there is, re-detect after waiting for one clock cycle. If not, send the current operation data packet to be transmitted according to the transmission time interval information in the flag field packet corresponding to the current operation data packet to be transmitted.
9. A cache simulation component, characterized in that, It includes: A request reply module, configured to receive and process the to-be-verified test request data sent by the to-be-tested cache. The data transmission device according to any one of claims 5-8, which is arranged in the request reply module and is configured to send response data to the to-be-tested cache; the response data includes a flag field packet and a corresponding operation data packet; the request reply module replies the response data to the to-be-tested cache through the data transmission device as described above. A function processing module, configured to send a consistency request to the to-be-tested cache. A storage module, configured to store the status information of the cache simulation component. A consistency maintenance module, configured to update the storage module and perform a consistency check on the storage module.
10. The cache simulation component of claim 9, characterized in that, The consistency request includes a probe request and a pull request. The function processing module includes: a probe function module, configured to process the probe request. The pull function module is configured to process the pull request.
11. The cache simulation component as described in claim 9, wherein, The storage module includes: a shadow tag macro cell and a three-level cache macro module.
12. The cache simulation component according to claim 11, wherein The consistency check module includes: A status update module, configured to update the shadow tag macro cell and the three-level cache macro module according to the consistency protocol. A shadow tag macro cell check module, configured to perform a consistency check on the cache of the shadow tag macro cell.
13. A cache verification method, characterized in that, It includes: Send first request data to the to-be-tested cache and receive the to-be-tested response data returned by the to-be-tested cache. Receive the to-be-tested request data sent by the to-be-tested cache and return first response data to the to-be-tested cache through the data transmission method according to any one of claims 1-4. Check whether the to-be-tested request data and the to-be-tested response data of the to-be-tested cache are correct.
14. A cache verification system, characterized in that, It includes: The to-be-tested cache. An upstream cache module, configured to receive the response data sent by the to-be-tested cache and send request data to the to-be-tested cache. The cache simulation component according to any one of claims 9-12, configured to simulate the downstream cache of the to-be-tested cache, so as to receive the request data sent by the to-be-tested cache, return response data to the to-be-tested cache, and maintain the data consistency between the to-be-tested cache and the cache simulation component.
15. A computing device, characterized in that, It includes the cache verification system according to claim 14.
16. A storage medium, characterized in that, The storage medium stores computer instructions, and when the computer instructions are executed, the data transmission method according to any one of claims 1-4 is implemented.