I2C pressure test method

Abstract

The invention provides an I2C pressure test method, which is applied to a first platform, the first platform is connected with a plurality of servers, and the method comprises the following steps: obtaining a test instruction of at least one I2C link in a target server; the test instruction is used for indicating to test at least one I2C link; determining a link address and a test rule of the I2C link based on the test instruction; the first platform pre-stores respective link addresses and test rules of a plurality of I2C links; combining the link address and the test rule to a preset program template corresponding to the target server to obtain a test program; the test program is used for carrying out pressure test on the I2C link. Therefore, the test efficiency and reusability of the large-scale I2C pressure test can be improved, and the user experience is improved.

Description

Technical Field

[0001] This application relates to the technical field of server testing, and in particular, to an I2C stress testing method. Background Art

[0002] In a server, the I2C (inter-integrated circuit) bus is a key communication line. It is mainly used to monitor and control each single board and component inside the server, such as temperature sensors, voltage monitors, etc. Therefore, when testing I2C, it should not be limited to the signal timing test of the I2C function, but should also cover the I2C stress test of the single board and hardware devices. It is extremely important to ensure the correctness, reliability, and integrity of the I2C stress test.

[0003] There are two common I2C stress testing methods: One is to rely on software developers to customize and develop a dedicated software package according to the product hardware version characteristics, I2C link topology structure, and user requirements, and run it in the server to provide the total number of test times and test results (Fail or PASS). The other is to let users write software scripts by themselves according to the test requirements, run them in the server, and manually search the test logs and give the judgment of the test results. However, when facing the situation of a large-scale I2C link in the server and variable test scenarios, both of these methods have problems of high manual dependence and low reusability. Summary of the Invention

[0004] The embodiments of this application provide an I2C stress testing method and a computing device, which can improve the test efficiency and reusability of large-scale I2C stress testing.

[0005] In a first aspect, the embodiments of this application provide an I2C stress testing method, which is applied to a first platform. The first platform is connected to multiple servers. The method includes: obtaining a test instruction for at least one I2C link in a target server; the test instruction is used to indicate to test at least one I2C link; determining the link address and test rule of the I2C link based on the test instruction; the first platform prestores the link address and test rule of each of the multiple I2C links; combining the link address and test rule into a preset program template corresponding to the target server to obtain a test program; the test program is used to perform a stress test on the I2C link.

[0006] Accordingly, the embodiments of the present application provide an application platform for I2C stress testing. The platform prestores the test process parameters of each I2C link. By obtaining a test instruction and performing a test operation on at least one I2C link, large-scale I2C link stress testing can be achieved, thereby improving the test efficiency. In addition, it uses a preset program template corresponding to the server to normalize the test process parameters of each I2C link into a standardized test program, which can reduce the impact of differences between testers on the test results, thereby improving the reusability of the test program and the accuracy of the test results, as well as enhancing the user experience.

[0007] In a possible implementation manner, combining the link address and the test rule into the preset program template corresponding to the target server includes: parameterizing the link address and filling it into the preset program template, and writing test logic code according to the test rule and adding it to the preset program template to obtain a test program.

[0008] Thus, a test program for the I2C link can be generated according to the preset program template, the link address, and the test rule.

[0009] In a possible implementation manner, obtaining a test instruction for at least one I2C link in the target server includes: in response to a user performing a first operation on a first interface of a first platform, obtaining a test instruction for at least one I2C link in the target server.

[0010] Thus, by using the first interface provided by the first platform, the user can conveniently set the target server and start the stress testing of at least one I2C link in the target server.

[0011] In a possible implementation manner, before obtaining a test instruction for at least one I2C link in the target server, the method includes: in response to a user performing a second operation on a first interface of a first platform, obtaining the link addresses and test rules of multiple I2C links and storing them.

[0012] Thus, by simultaneously importing the link addresses and test rules of at least one I2C link through the second operation, the requirements for large-scale I2C stress testing can be conveniently met.

[0013] In a possible implementation manner, determining the link address and test rule of the I2C link based on the test instruction includes: determining the link address and test rule of the I2C link based on the link identifier included in the test instruction; the link identifier is assigned by the target server.

[0014] Thus, the link address and test rule of the I2C link can be determined based on the test instruction.

[0015] In a possible implementation, the method further includes: determining read / write data required for stress testing the I2C link based on a test instruction; the first platform pre-storing read / write data corresponding to each of multiple I2C links; the read / write data including at least one of the following, a read / write data value, and a read / write data length; combining the link address and the test rule into a preset program template corresponding to the target server, including: combining the read / write data, the link address, and the test rule into a preset program template corresponding to the target server.

[0016] In a possible implementation, the link address includes the address of the target hardware in the target server to which the I2C link is connected, and at most three-layer topology information; the topology information includes a topology address and a topology channel; the test rule includes at least one of the following, a test interval time, a test number of times, and an error encounter abort rule.

[0017] In a possible implementation, the preset program template includes at least one of the following, a polling principle, a comparison principle, and a logical judgment principle.

[0018] Thus, by setting a preset program template for the server and normalizing the test process parameters of each I2C link into a standardized test program, the influence of differences among testers on the test results can be reduced, thereby improving the reusability of the test program and the accuracy of the test results, as well as enhancing the user experience.

[0019] In a possible implementation, the method further includes: displaying an operation log of the second operation and a test result of the stress test on a first interface.

[0020] Thus, the first platform provides real-time refresh and echo on the first interface, displaying user operation logs, stress test results, etc., which can enhance the friendliness of user operations, the credibility of the test process, and the intuitiveness of the test results.

[0021] In a second aspect, an embodiment of the present application provides a computing device, including:

[0022] Multiple memories for storing programs;

[0023] Multiple processors for executing the programs stored in the memories, and when the programs stored in the memories are executed, the processors are used to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0024] In a third aspect, an embodiment of the present application provides a computer storage medium, in which instructions are stored, and when the instructions run on a computer, the computer is caused to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0025] Fourthly, an embodiment of the present application provides a computer program product including instructions. When the instructions run on a computer, the computer is enabled to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0026] It can be understood that for the beneficial effects of the above second aspect to the fourth aspect, reference can be made to the relevant descriptions in the first aspect above, which will not be elaborated here. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1a An application platform for I2C stress testing provided by an embodiment of the present application;

[0029] Figure 1b An application platform for I2C stress testing provided by an embodiment of the present application;

[0030] Figure 2 A flowchart of an I2C stress testing method provided by an embodiment of the present application;

[0031] Figure 3 A schematic diagram of a configuration file provided by an embodiment of the present application;

[0032] Figure 4 A topology diagram of I2C port expansion provided by an embodiment of the present application;

[0033] Figure 5 A retrieval schematic diagram of test process parameters provided by an embodiment of the present application;

[0034] Figure 6 A flowchart of detecting link configuration and topology configuration of I2C stress testing provided by an embodiment of the present application;

[0035] Figure 7 A flowchart of detecting read / write data and test rules of I2C stress testing provided by an embodiment of the present application;

[0036] Figure 8 A schematic diagram of the structure of a computing device provided by an embodiment of the present application. Detailed Embodiments

[0037] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the drawings.

[0038] In the description of the embodiments of the present application, any embodiment or design solution described as "exemplary", "for example", or "for instance" should not be understood as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary", "for example", or "for instance" is intended to present relevant concepts in a specific manner.

[0039] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. The terms "comprise", "include", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways. "A plurality" may be one or more, where a plurality is two or more.

[0040] The I2C stress test in the server is a test process specifically for the I2C bus inside the server. When performing the I2C stress test, special test tools or software are usually used, which can simulate a large number of I2C communication requests and perform continuous read and write operations on the I2C bus in the server, so as to evaluate its performance under high load. In this way, it can be ensured that the server can perform I2C communication stably and reliably during actual operation and meet various monitoring and management requirements.

[0041] Currently, common I2C stress test tools or software have problems of high manual dependence and low reusability when facing the situation of large-scale I2C links and variable test scenarios in the server.

[0042] The embodiments of the present application provide an application platform for I2C stress testing. The platform pre-stores the test process parameters of each I2C link. By obtaining test instructions and performing test operations on at least one I2C link, stress testing of large-scale I2C links can be realized, thereby improving the test efficiency. In addition, it uses a preset program template corresponding to the server to normalize the test process parameters of each I2C link into a standardized test program, which can reduce the impact of differences between testers on the test results, thereby improving the reusability of the test program and the accuracy of the test results, as well as enhancing the user experience.

[0043] Exemplarily, Figure 1a shows an application platform for I2C stress testing provided by the embodiments of the present application.

[0044] As Figure 1aAs shown, the application platform can be an integrated tool or software. Taking the integrated tool as an example, the tool provides a graphical user interface (GUI) 100 for I2C stress testing, with the title "I2C Stress Tool". The integrated tool is connected to multiple servers and is used to perform stress testing on the I2C link between the management chip and the monitored I2C hardware in the target server under user control, which is applicable to the application scenario of large-scale I2C link stress testing. Among them, the I2C hardware is a hardware device or component related to the I2C communication protocol in the target server. The management chip can be the baseboard management controller (BMC) in the target server, which is used to manage the I2C link in the target server.

[0045] In the graphical user interface 100, the navigation bar 110 includes a "Main Interface" option and multiple "I2C Link Under Test Interfaces" options (I2C Link Under Test Interfaces 1 to n), and each I2C link corresponds to an "I2C Link Under Test Interface". The "Main Interface" option is used to control the simultaneous stress testing of multiple I2C links, and the "I2C Link Under Test Interface" option is used to control the separate stress testing of a single I2C link.

[0046] When the "Main Interface" option is activated, the main interface 200 is displayed. The main interface 200 mainly includes a configuration area 210, a control button area 220, and an operation log display area 230.

[0047] In the configuration area 210, the "BMC IP Address" label provides a corresponding input box for the user to enter the IP address of the BMC in the target server, for example, XXX.XXX.XXX.XXX. The "User Name" and "Password" labels provide two corresponding input boxes, which are respectively used for the user to enter user authentication information including the user name and password for accessing the BMC. The "Log Save Path" label provides a corresponding input box for the user to specify the save path of the test log. After the log save path is selected, relevant logs will be automatically generated according to the test situation and saved to the specified path. The "One-Click Import Configuration" label provides a corresponding input box for the user to quickly import the test process parameters of multiple I2C links. The test process parameters include link addresses and test rules. The user can be a test maintenance personnel who uses this integrated tool to implement I2C stress testing.

[0048] In the control button area 220, the "Total Run / Stop" button is used for the user to issue a test instruction to simultaneously start or stop the stress test of multiple I2C links. The "Current Overall Test Result" button provides a corresponding display box for displaying the current overall test result. The "Failed Link" button provides a corresponding display box for displaying the link identifiers of the I2C links that failed the test.

[0049] In the operation log display area 230, the "Operation Log Echo" label provides a corresponding display box for displaying the operation log information during the test, such as the results of the ping command, the user login status, etc.

[0050] As Figure 1a shown, in the "Operation Log Echo" display box, some examples of operation log information are given, such as:

[0051] ping XXX.XXX.XXX.XXX

[0052] Login is successfu

[0053] XXXXXXX

[0054] XXXXXXX

[0055] The above examples indicate connecting to the BMC with the IP address XXX.XXX.XXX.XXX, and the user successfully logging in to the BMC according to the specified authentication information.

[0056] Exemplarily, Table 1 lists the meanings of the labels or buttons included in the main interface 200:

[0057] Table 1

[0058]

[0059]

[0060] Exemplarily, when initializing the graphical user interface 100, the main interface 200 option is displayed by default. The user can add multiple "I2C Links Under Test Interface" options through the add button provided in the "Navigation Bar 110", or can import the test process parameters of multiple I2C links through the "One-Click Import Configuration" label, and automatically add multiple "I2C Links Under Test Interface" options.

[0061] Exemplarily, Figure 1b shows an application platform for I2C stress testing provided by an embodiment of the present application.

[0062] As Figure 1b shown, continuing Figure 1aThe example in shows a graphical user interface 100 named "I2C Stress Tool", and multiple "I2C link under test interface" options respectively correspond to the same I2C link under test interface 300. When the option of the "I2C link under test interface" (such as the I2C link under test interface 1) of the target I2C link under test is activated, the corresponding I2C link under test interface 300 is displayed. The I2C link under test interface 300 includes a test process parameter configuration area 310, a link control button area 320, and a test log display area 330.

[0063] In the test process parameter configuration area 310, the "link identifier" label provides a corresponding input box for specifying the link identifier assigned by the target server for the I2C link. The "primary I2C topology address" and "primary I2C topology channel" labels provide two corresponding input boxes for configuring the primary topology address and channel of the I2C link respectively. Similarly, the "secondary I2C topology address" and "secondary I2C topology channel", and the "tertiary I2C topology address" and "tertiary I2C topology channel" have the same functions. The "I2C hardware address" label provides a corresponding input box for specifying the address of the I2C hardware connected to the I2C link under test. The "read / write data information" label provides a corresponding input box for specifying the data value and data length during read / write tests. The "test interval time" label provides a corresponding input box for setting the time interval between two tests. The "number of test times" label provides a corresponding input box for setting the number of executions of the I2C link stress test. The "whether to stop on encountering an error" label provides a corresponding input box for specifying whether to stop the test when an error is encountered.

[0064] It can be understood that the input boxes provided by these labels are also used to display the test process parameters of multiple I2C links imported by the user based on the "one-key import configuration" label. The user can perform personalized modifications to the test process parameters of the target I2C link under test on the basis of performing a quick import operation.

[0065] In the link control button area 320, there is a "run / stop" button for the user to start or stop the stress test of the target I2C link under test. The "current number of runs" button provides a corresponding display box for displaying the current number of runs. The "number of error times" button provides a corresponding display box for displaying the current number of error times.

[0066] In the test log display area 330, the "test log echo" label provides a corresponding display box for displaying the test log information of the target I2C link under test during the test process.

[0067] As Figure 1b shown, in the "test log echo" display box, some examples of test log information are given, such as:

[0068] At 10:12 on November 4th, run number 1, write OX02, read OX02, result PASS

[0069] At 10:15 on November 4th, run number 2, write OX02, read OX02, result PASS

[0070] At 10:17 on November 4th, run number 3, write OX02, read error, result Fail

[0071] At 10:19 on November 4th, run number 4, write error, read error, result Fail

[0072] XXXXXXX

[0073] The above examples show the data information, read and write results, and test results of the first to fourth data read and write operations during the stress test of the target I2C link under test.

[0074] Exemplarily, Table 2 lists the meanings of the labels or buttons included in the interface 300 of the I2C link under test:

[0075] Table 2

[0076]

[0077]

[0078] Furthermore, based on Figure 1a or on the basis of the user configuration parameters obtained in 1b, the integration tool combines the user configuration parameters into the preset program template corresponding to the target server to obtain a test program. To use the test program to perform a stress test on the target I2C link in the target server.

[0079] Thus, the above application platform enables users to conveniently perform stress tests on I2C links. In addition, using the graphical interface provided by the application platform, users can conveniently set the target server, configure the test process parameters of each I2C link, start the test, view the test results and log information to perform real-time analysis of the stress test situation of the I2C link.

[0080] Based on the above content, a detailed introduction to an I2C stress test method proposed in this application is given.

[0081] Exemplarily, Figure 2The figure shows a flowchart of an I2C stress test method provided by an embodiment of the present application. This method is applied to a first platform, which can be an integrated tool or software deployed on any computing device, personal PC, server, or server cluster with processing and computing capabilities. The first platform is connected to multiple servers. The test method mainly includes the following execution steps:

[0082] Step S201, obtain test instructions for at least one I2C link in the target server. The test instructions are used to indicate testing at least one I2C link.

[0083] In one embodiment, the first platform provides a first interface, such as Figure 1a the graphical user interface 100 shown in FIG. 1b or 1b. The target server is the target device where the I2C link to be tested is located. The target server includes at least one I2C link.

[0084] Exemplarily, the multiple servers include a management chip BMC. The user can determine the target server by setting the IP address of the BMC in the main interface 200. The user can also input user authentication information to obtain permission to access the BMC.

[0085] In response to the user performing a first operation on the first interface of the first platform, obtain test instructions for at least one I2C link in the target server.

[0086] In one implementation, the first interface activates the main interface 200, and the first operation includes clicking the "Total Run / Stop" button in the main interface 200. The user issues a test instruction by performing the first operation, and the test instruction indicates performing a stress test on at least one I2C link in the target server simultaneously.

[0087] In another implementation, the first interface activates the I2C link interface 300 to be tested, which corresponds to the target I2C link to be tested, and the first operation includes clicking the "Run / Stop" button in the I2C link interface 300 to be tested. The user issues a test instruction by performing the first operation, and the test instruction indicates performing a stress test on a single I2C link.

[0088] Thus, using the graphical interface provided by the first platform, the user can conveniently set the target server and start a stress test on at least one I2C link in the target server.

[0089] Exemplarily, the first platform also obtains in advance a preset program template corresponding to multiple servers. And based on the IP address of the BMC, establish a correspondence between the target server and the preset program template. When the user sets the target server, the first platform determines the preset program template corresponding to the target server according to the IP address of the BMC in the target server.

[0090] A preset program template is a pre-designed program structure or framework that can provide a set of standardized codes to guide the execution of specific types of tasks. In this application, the preset program template is used to create a test program for the I2C link in the target server. The template includes invariant parameters and variable parameters. The variable parameters are the test process parameters of the I2C link under test, and the test process parameters include the link address and test rules of the I2C link under test. The invariant parameters are common parameters that are used in the test programs of each I2C link, and these parameters are uniformly encapsulated in the preset program template. The variable parameters are specific parameters required for performing stress tests on each I2C link, and users can set these parameters through the first platform by themselves.

[0091] Exemplarily, the invariant parameters include at least one of the following: the polling principle, the comparison principle, and the logical judgment principle. The polling principle includes actively querying the data read / write status information of the I2C link under test at a predetermined time interval, such as querying the data read / write status information every 1 s or 2 s. The comparison principle includes the process of making a decision by comparing the data values written to and read from the hardware connected to the I2C link. For example, if the comparison results are consistent, it indicates that the test result is PASS, otherwise it is Fail. The logical judgment principle includes defining the judgment criteria for the data read / write status. For example, using the aforementioned comparison principle to evaluate the data read / write status, or judging the data read / write status by verifying whether the data of the hardware device connected to the I2C link can be successfully read.

[0092] Optionally, the rule instructions are pre-generated according to the script rules. These script rules help to automate the test process, ensure the consistency and repeatability of the test, and can quickly identify and diagnose problems in the I2C link. In this way, the test efficiency can be improved and human errors can be reduced.

[0093] Thus, by setting a preset program template for the server and normalizing the test process parameters of each I2C link into a standardized test program, the influence of differences among testers on the test results can be reduced, thereby improving the reusability of the test program and the accuracy of the test results, as well as enhancing the user experience.

[0094] In addition, designing invariant parameters and variable parameters in the preset program template, and uniformly encapsulating the invariant parameters in the preset program template can reduce the introduction of variables, thereby improving the test efficiency.

[0095] Step S202, determine the link address and test rules of the I2C link based on the test instruction. The first platform pre-stores the link addresses and test rules of multiple I2C links respectively.

[0096] Exemplarily, the test instruction includes the link identifier of the I2C link under test, and the link identifier is assigned by the target server. Multiple I2C links' respective link addresses and test rules are pre-stored in the first platform. The link address and test rule of the I2C link under test can be determined through indexing by this link identifier.

[0097] Before executing step S201, in response to the user performing a second operation on the first interface of the first platform, the link addresses and test rules of multiple I2C links are obtained and stored. The link address includes the address of the target hardware (i.e., I2C hardware) in the target server to which the I2C link is connected, and at most three-layer topology information. The topology information includes the topology address and topology channel. The test rule includes at least one of the following: test interval time, number of tests, and error-abort rule when an error is encountered.

[0098] Optionally, in response to the user performing a second operation on the first interface of the first platform, the read / write data required for each of the multiple I2C links during stress testing is also obtained. It can be understood that the first platform also pre-stores this read / write data. The read / write data includes at least one of the following: read / write data value, and read / write data length.

[0099] In one implementation, the first interface activates the main interface 200, and the second operation includes: one-key importing a configuration file including test process parameters of at least one I2C link on the main interface 200. The test process parameters include the link address and test rule.

[0100] In another implementation, the first interface activates the I2C link under test interface 300, and the second operation includes: filling in or modifying the information in the input boxes of each label in the test process parameter configuration area 310.

[0101] Thus, using the graphical interface provided by the first platform, the user can conveniently configure the test process parameters of each I2C link. Additionally, by one-key importing the test process parameters of multiple I2C links on the main interface 200, the requirements for large-scale I2C stress testing can be conveniently met. By editing the test process parameters of a single I2C link on the I2C link under test interface, the personalized stress testing requirements of a single I2C link can be met.

[0102] Exemplarily, Figure 3 Fig. shows a schematic diagram of a configuration file provided by an embodiment of the present application.

[0103] As Figure 3As shown, the configuration file establishes a link index for each I2C link, and each index corresponds to the test process parameters of an I2C link. According to practical experience, an I2C topology structure with a maximum level of 3 is set for each I2C link. It can be understood that more levels of I2C topology structure can also be set according to specific implementations and the I2C bus specifications of the server.

[0104] Taking the index I2C link (M)=1 as an example, its corresponding test process parameters include the link identifier assigned by the target server to the I2C link, that is, the link identifier (A)=1. For each layer of topology, the test process parameters include the address and channel of this topology. For example, for the first-level I2C topology, its address (B)=OXE0, and the channel (C)=OX02. It can be seen from the configuration file that this I2C link includes a two-layer I2C topology structure.

[0105] Furthermore, the test process parameters also include the I2C hardware address (H)=OXAE, and the read / write data information (J), and the read / write data information includes at least one of the following information: the data value OXA2 and the data length OXA3.

[0106] Even further, the test process parameters also include test operation information, including the test interval time (K)=5, the test times (L)=1000, and whether to stop when encountering an error (M)=Y.

[0107] Thus, through the one-key import configuration function, the needs of large-scale I2C stress testing can be conveniently met. The user only needs to fill in the corresponding configuration file according to their test needs, and then import it into the first platform through the one-key import operation. The first platform will automatically retrieve and analyze these configuration files, so as to quickly complete the configuration of the test process parameters of multiple I2C links, which can improve the test efficiency.

[0108] Specifically, first, the configuration file imported with one key includes the link identifier assigned by the target server to the target I2C link. And it includes the hardware address of the I2C hardware connected to the I2C link and the read / write data information. The hardware address is used to indicate the address of the target device for data reading and writing. When the I2C link is connected with an I2C port expansion chip, the configuration file also includes hierarchical topology information. The link identifier and hierarchical topology information are used for the BMC to connect and address the I2C hardware through the I2C link.

[0109] The hierarchical topology of the I2C port refers to the hierarchical structure of the I2C bus in hardware connection, which can be achieved by using expansion chips such as multiplexers or hubs, allowing more devices to be connected to the I2C bus. The number of layers of the hierarchical topology can be expanded as needed, but the specific maximum number of layers depends on the specific implementation and the I2C bus specification of the server. Therefore, the I2C link can include multiple hierarchical structures, and each hierarchical structure is addressed through a topology address and a topology channel. The address obtained from the addressing operation is used to determine the I2C hardware connected to the I2C link.

[0110] Exemplarily, Figure 4 Fig. shows an I2C port expansion topology diagram provided by an embodiment of the present application.

[0111] As Figure 4 shown, an I2C port expansion chip 1 is connected under a specific I2C link of the BMC. The chip includes 4 channels, and its addressing method includes channel selection based on the primary I2C topology address. Among them, the primary I2C topology address is the address assigned to the I2C port expansion chip 1 in the target server. Channel selection includes different channel selections through different combinations of pin 1 and pin 2. For example, grounding (GND) pin 1 and pin 2 selects channel 0, pulling pin 1 to a high level and grounding pin 2 selects channel 1, etc. Four different combinations can be achieved through two pins 1 and 2, and each combination corresponds to a channel of chip 1. Thus, the primary I2C topology of the I2C link can be realized, expanding one I2C link into 4 I2C links, so as to achieve the purpose of connecting more I2C hardware.

[0112] It can be understood that in order to connect more I2C hardware through the I2C bus, an I2C port expansion chip 2 can also be connected under the channel (such as channel 3) of expansion chip 1 to realize the secondary I2C topology. Its addressing method includes channel selection based on the secondary I2C topology address on the premise of channel selection based on the primary I2C topology address, such as channel selection through pin 3 and pin 4 of expansion chip 2. If there is a tertiary I2C topology, its addressing method can be deduced by analogy.

[0113] Secondly, the configuration file also includes the read and write data information of the I2C link. The read and write data includes at least one of the following: the read and write data value, and the read and write data length.

[0114] Furthermore, the configuration file also includes test rules. The test rules include at least one of the following: the test interval time, the number of test times, and the error encounter abort rule. The error encounter abort rule indicates whether to stop the current stress test when an error is encountered.

[0115] Thus, the standardization of test process parameters can be achieved. On the basis of uniformly encapsulating the invariant parameters in advance, by indexing the parameter values input by the user and assigning the parameter values to the corresponding test process parameters, the introduction of variables can be reduced, thereby simplifying the test process and improving its reliability.

[0116] Step S203: Combine the link address and the test rules into the preset program template corresponding to the target server to obtain a test program. The test program is used to perform a stress test on the I2C link.

[0117] Exemplarily, combine the read / write data, link address, and test rules required for performing a stress test on the I2C link into the preset program template corresponding to the target server to obtain a test program.

[0118] The above combination process includes parameterizing the read / write data and link address and filling them into the preset program template, and writing test logic code according to the test rules and adding it to the preset program template to obtain a test program.

[0119] Specifically, by converting the link address into a parameter, these addresses can be flexibly referenced and used in the test program. Write the corresponding test logic code according to the test rules, which includes how to execute the test (e.g., read and write operations), how to verify the test results, and how to abort the test when an error occurs, etc. Combine these two steps and fill them into the preset program template to generate the final test program. This process usually involves programming and scripting, as well as using specific programming languages and tools, etc., which will not be elaborated here.

[0120] Finally, use the test program to perform stress tests on their respective corresponding I2C links. This process includes: The BMC performs addressing of the I2C link based on the link address to find the I2C hardware, then performs data reading and writing of the I2C hardware according to the read / write data, test rules, and invariant parameters, and makes a judgment on the test results to obtain the stress test results (Fail or PASS) of the I2C link.

[0121] During the entire stress test process, the logs generated by the first platform include: Fail logs, operation logs, and test logs.

[0122] Exemplarily, display the IP address of the BMC, the authentication information of the user, the current overall test results of at least one I2C link, and the operation logs of the first operation, second operation, and other user operations on the main interface 200.

[0123] Exemplarily, on the DUT I2C link interface 300, the test process parameters and test results of the corresponding I2C link are displayed, as well as the operation logs of the first operation, the second operation, and other user operations on the DUT I2C link interface 300. For example, after the user imports the configuration file with one key on the main interface 200, the DUT I2C link interfaces echo the test process parameter information of the corresponding I2C link in the configuration file. Based on this, the user can edit the test process parameters of a single I2C link in real time on the DUT I2C link interface, and the first platform will automatically save the edited content.

[0124] Thus, the first platform provides real-time refresh and echo of the first interface, displaying user input information, test results, operation logs, etc., which can improve the friendliness of user operations, the credibility of the test process, and the intuitiveness of test results.

[0125] In summary, the embodiment of the present application provides an application platform for I2C stress testing. The platform prestores the test process parameters of each I2C link. By obtaining a test instruction and performing a test operation on at least one I2C link, large-scale I2C link stress testing can be realized, thereby improving the test efficiency. In addition, it uses the preset program template corresponding to the server to normalize the test process parameters of each I2C link into a standardized test program, which can reduce the influence of differences between testers on test results, thereby improving the reusability of the test program and the accuracy of test results, as well as enhancing the user experience.

[0126] Exemplarily, Figure 5 shows a retrieval schematic diagram of test process parameters provided by an embodiment of the present application.

[0127] As Figure 5 shown, the process of the first platform retrieving the test process parameters of the I2C link according to the configuration file includes the following steps:

[0128] Step S501, obtain the I2C link index of the I2C link in the configuration file imported with one key.

[0129] Exemplarily, the first platform receives the configuration file imported with one key and obtains the indexes of n I2C links, such as Figure 3 the 2 shown. Each I2C link index corresponds to the test process parameters of an I2C link.

[0130] Step S502, perform link configuration detection for I2C stress testing.

[0131] Exemplarily, for the test process parameters of each I2C link, detect the link identifier of the corresponding I2C link.

[0132] For the test process parameters of each I2C link, determine whether there is a link identifier corresponding to the I2C link. If the determination result is yes, go to step S503. Otherwise, re-enter the link identifier of the link in the I2C link under test interface 300.

[0133] Step S503, perform topology configuration detection for I2C stress testing.

[0134] Exemplarily, for the test process parameters of each I2C link, determine whether there is hierarchical topology information. If there is, generate gating information based on the link identifier and the hierarchical topology information. The gating information is used for I2C link addressing. If not, directly go to step S504.

[0135] Step S504, perform read / write data detection for I2C stress testing.

[0136] Exemplarily, generate read / write information based on the results of I2C stress testing read / write data detection.

[0137] Specifically, for the test process parameters of each I2C link, generate read / write information according to the link identifier of the I2C link, the address of the I2C hardware connected to the I2C link, and the read / write data.

[0138] Step S505, perform test rule detection for I2C stress testing.

[0139] Exemplarily, for the test process parameters of each I2C link, the test rules include at least one of the following: test interval time, number of tests, and error stop rule when encountered. Generate test rule information according to the test rules.

[0140] Finally, generate variable parameter information according to the gating information, read / write information, and test rule information, and combine the variable parameter information into a preset program template to obtain a test program.

[0141] Exemplarily, Figure 6 shows a flowchart of link configuration and topology configuration detection for I2C stress testing provided by an embodiment of the present application.

[0142] As Figure 6 shown, based on Figure 3 a configuration file in the shown format, the I2C stress testing link configuration and topology configuration detection process mainly includes the following actions:

[0143] When the user imports Figure 3After the configuration file in the shown format, first, perform Action 1: Obtain user configuration parameters, and perform Action 2: Determine whether the link identifier is obtained. If so, perform Action 4: Obtain the link identifier (A). If not, perform Action 3: Log and echo the error of the prompt message, and modify the filled value, and then perform Action 2 again.

[0144] Secondly, perform Action 5: Obtain the primary I2C topology address. If so, perform Action 6: Obtain the primary I2C topology address (B). If not, enter the Figure 5 next stage in, and perform Action 24: Perform I2C stress test read / write data detection. Perform Action 7: Obtain the primary I2C topology channel. If so, perform Action 8: Obtain the primary I2C topology channel (C). If not, perform Action 9: Log and echo the error of the prompt message, and modify the filled value, and then perform Action 7 again. Perform Action 10: Generate the strobe information 1 according to A\B\C.

[0145] Next, perform Action 11: Obtain the secondary I2C topology address. If not, perform Action 24: Perform I2C stress test read / write data detection. If so, perform Action 12: Obtain the secondary I2C topology address (D), perform Action 13: Obtain the secondary I2C topology channel. If so, perform Action 14: Obtain the secondary I2C topology channel (E). If not, perform Action 15: Log and echo the error of the prompt message, and modify the filled value, and then perform Action 13 again. Perform Action 16: Generate the strobe information 2 according to A\D\E.

[0146] Furthermore, perform Action 17: Obtain the tertiary I2C topology address. If not, perform Action 24: Perform I2C stress test read / write data detection. If so, perform Action 18: Obtain the tertiary I2C topology address (F), perform Action 19: Obtain the tertiary I2C topology channel. If so, perform Action 20: Obtain the tertiary I2C topology channel (G). If not, perform Action 21: Log and echo the error of the prompt message, and modify the filled value, and then perform Action 19 again. Perform Action 22: Generate the strobe information 3 according to A\F\G.

[0147] Finally, perform Action 23: Save the generated strobe information 1-3 in the database. The strobe information 1-3 is used for the BMC to identify the I2C link under test, so as to address the I2C hardware connected to the I2C link.

[0148] Exemplarily, Figure 7 shows a flowchart for detecting read / write data and test rules of an I2C stress test provided by an embodiment of the present application.

[0149] As Figure 7 shown, based on Figure 3For the configuration file in the shown format, the read / write data and test rule detection of the I2C stress test mainly include the following steps:

[0150] When the user imports Figure 3 the configuration file in the shown format, first, perform Action 31: Obtain user configuration parameters, perform Action 32: Detect the address of the I2C hardware connected to the I2C link. If not, perform Action 33: Log and echo the error message and modify the filled value, and then perform Action 32 again. If so, perform Action 34: Obtain the hardware address (H).

[0151] Secondly, perform Action 35: Detect the read / write data information. If not, perform Action 36: Log and echo the error message and modify the filled value, and then perform Action 35 again. If so, perform Action 37: Obtain the read / write data information (J), and perform Action 47: Generate read / write information based on A, H, and J.

[0152] Next, perform Action 38: Detect the test interval time. If not, perform Action 39: Log and echo the error message and modify the filled value, and then perform Action 38 again. If so, perform Action 40: Obtain the test interval time (K).

[0153] Furthermore, perform Action 41: Detect the number of test times. If not, perform Action 42: Log and echo the error message and modify the filled value, and then perform Action 41 again. If so, perform Action 43: Obtain the number of test times (L).

[0154] Even further, perform Action 44: Detect whether to stop when an error is encountered. If not, perform Action 45: Obtain that the interrupt instruction does not take effect during the test (M). If so, perform Action 46: Obtain that the interrupt instruction takes effect during the test (M). Generate test rule information based on the values of K and L and the interrupt strategy M.

[0155] Finally, perform Action 48: Read the strobe information in the database, and based on the results of Actions 40, 43, 47, 48, and 45 or 46, perform Action 49: Generate variable parameters.

[0156] It can be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not indicate the sequence of execution. The execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. In addition, in some possible implementation manners, the steps in the above embodiments can be selectively executed according to the actual situation, can be partially executed, or can be fully executed, which is not limited herein. Additionally, all or part of any feature in the above embodiments can be freely combined in any way without contradiction. The combined technical solutions are also within the scope of the present application.

[0157] Exemplarily, an embodiment of the present application further provides a computing device 1000. As Figure 8 shown, the computing device 1000 includes: a bus 1002, a processor 1004, a memory 1006, and a communication interface 1008. The processor 1004, the memory 1006, and the communication interface 1008 communicate with each other through the bus 1002. It should be understood that the present application does not limit the number of processors and memories in the computing device 1000.

[0158] The bus 1002 may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 8 it is represented by a single line in the figure, but it does not mean that there is only one bus or one type of bus. The bus 1004 may include a path for transmitting information between various components of the computing device 1000 (for example, the memory 1006, the processor 1004, and the communication interface 1008).

[0159] The processor 1004 may include any one or more of a central processing unit, a graphics processing unit (GPU), a microprocessor (MP), a digital signal processor (DSP), a baseboard management controller, and other processors.

[0160] The memory 1006 may include volatile memory, such as random access memory (RAM). The processor 1004 may also include non-volatile memory, such as read-only memory (ROM), flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0161] The communication interface 1008 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 1000 or a cluster composed of multiple computing devices 1000 and other devices or a communication network.

[0162] Inside the computing device 1000, there is a network device, or the computing device 1000 is externally connected to multiple network devices. The internal network device communicates with the processor 1004, the memory 1006, and the communication interface 1008 through the bus 1002. The external network device communicates with the computing device 1000 through interfaces such as Ethernet, Fibre Channel, and InfiniBand.

[0163] The memory 1006 stores executable program codes / instructions, and the processor 1004 executes the executable program codes / instructions to implement Figure 2 the process shown in, thereby implementing all or part of the steps of the method in the above embodiments. In other words, the memory 1006 stores a program / instructions for executing all or part of the steps of the method in the above embodiments.

[0164] An embodiment of the present application provides a computing device, including: a memory and a processor; the memory and the processor are coupled; the memory is used to store a program; the processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method in the above embodiments.

[0165] Based on the method in the above embodiments, an embodiment of the present application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program runs on a processor, the processor is caused to execute the method in the above embodiments.

[0166] Based on the method in the above embodiments, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor is caused to execute the method in the above embodiments.

[0167] The method steps in the embodiments of the present application can be implemented in a hardware manner or by a processor executing software instructions. The software instructions can be composed of corresponding software modules. The software modules can be stored in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a removable hard disk, a CD-ROM, or any other form of storage medium well-known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0168] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0169] It can be understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application.

Claims

1. An I2C pressure test method, characterized in that, Applied to a first platform, the first platform being connected to multiple servers, the method includes: Obtaining test instructions for at least one I2C link in a target server; the test instructions are used to indicate testing of at least one I2C link: Determining the link address and test rules of the I2C link based on the test instructions; the first platform pre-stores the link address and test rules of each of multiple I2C links; Combining the link address and test rules into a preset program template corresponding to the target server to obtain a test program; the test program is used to perform a stress test on the I2C link.

2. The method according to claim 1, wherein The combining the link address and test rules into a preset program template corresponding to the target server includes: Parametrizing the link address and filling it into the preset program template, and writing test logic code according to the test rules and adding it to the preset program template to obtain the test program.

3. The method according to claim 1, characterized in that, The obtaining test instructions for at least one l2C link in a target server includes: In response to a user performing a first operation on a first interface of the first platform, obtaining test instructions for at least one I2C link in a target server.

4. The method according to claim 1, wherein Before the obtaining test instructions for at least one I2C link in a target server, the method includes: In response to a user performing a second operation on a first interface of the first platform, obtaining the link address and test rules of each of multiple I2C links for storage.

5. The method according to claim 1, characterized in that The determining the link address and test rules of the I2C link based on the test instructions includes: Based on the link identifier included in the test instructions, determining the link address and test rules of the I2C link; the link identifier is assigned by the target server.

6. The method according to claim 1, wherein The method further includes: Determining the read / write data required for performing a stress test on the I2C link based on the test instructions; the first platform pre-stores the read / write data corresponding to each of multiple I2C links; the read / write data includes at least one of the following, read / write data value, and read / write data length; The combining the link address and test rules into a preset program template corresponding to the target server includes: Combining the read / write data, the link address and the test rules into a preset program template corresponding to the target server.

7. The method according to claim 1, wherein The link address includes the address of target hardware in the target server to which the I2C link is connected, and at most three-layer topology information; the topology information includes a topology address and a topology channel; The test rules include at least one of the following, test interval time, number of tests, and error-abort rule when an error is encountered.

8. The method according to claim 1, characterized in that, The preset program template includes at least one of the following, polling principle, comparison principle, and logical judgment principle.

9. The method according to claim 4, characterized in that, The method further includes: Displaying the operation log of the second operation and the test results of the stress test on the first interface.

10. A computing device, characterized in that, Includes: Multiple memories for storing programs; Multiple processors for executing the programs stored in the memories, and when the programs stored in the memories are executed, the processors are used to execute the method according to any one of claims 1-9.

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