Man-machine cooperation function test fault analysis and cross-domain optimization method and system and medium

Abstract

The invention discloses a man-machine cooperation function test fault analysis and cross-domain optimization method and system and a medium, and relates to the technical field of electronic information, and the method comprises the steps: constructing a fault tree, carrying out the reverse quantitative analysis based on a fault tree structure, converting the test proportion of a test item corresponding to an intermediate event into the test proportion of a bottom event, and carrying out the fault analysis. Calculating the product of the occurrence probability of the bottom event and the test proportion of the bottom event which is not subjected to the function test, so as to obtain the probability of leak detection and badness of the mainboard; a test proportion optimization model oriented to the mainboard function test process is constructed, an objective function of the test proportion optimization model is constructed based on the test proportion of the test items and the probability that the mainboard is missed and bad, and the test proportion optimization model is solved to obtain an optimal mainboard function test strategy so as to test the mainboard; according to the function test cross-domain overall optimization method, the cross-domain overall optimization capacity is improved, and cost reduction and efficiency improvement in the mainboard function test process are achieved.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and particularly to a method, system and medium for fault analysis and cross-domain optimization of human-machine collaboration function testing. Background Art

[0002] Function testing is an important process for evaluating the functionality of electronic products to ensure product quality. It mainly includes two processes: motherboard testing and repair, and is widely used in production lines of different types of electronic products. Among them, in the motherboard testing process, the motherboard is initially tested, and in the motherboard repair process, the finished product quality is ensured through further testing. Since function testing needs to mix and test motherboards of different batches and models, it is a typical flexible manufacturing process. Reducing costs and increasing efficiency in this process is the basis for realizing flexible manufacturing of motherboards.

[0003] With the increase in the complexity of integrated circuits, the cost of the function testing process is also increasing. This cost consists of the time costs required for the testing process and the repair process. Since the motherboard function testing strategy directly affects the testing time cost and repair time cost of defective motherboards or finished products, cross-domain overall optimization of the motherboard testing and repair processes to obtain an efficient testing strategy is the key means to reduce costs and increase efficiency in the motherboard function testing process.

[0004] Selective testing of test items is a common method for designing testing strategies. Since motherboard modules are interrelated and the test results of corresponding test items are often similar, using a clustering algorithm to group test items and then perform selective testing has been proven to be an effective means of reducing costs and increasing efficiency. However, existing methods only independently process sample attributes and do not consider attribute importance, which will lead to insufficient accuracy of the optimization model and it is difficult to give an effective cross-domain overall optimization strategy.

[0005] In addition, system fault information is important information in the function testing process and has an important impact on the time costs of testing and repair. Therefore, it is the basis for realizing cross-domain overall optimization. Fault analysis is an effective way to obtain system fault information. Fault tree analysis is an important type of fault analysis method. Compared with other methods, fault tree analysis can construct an intuitive tree diagram during the process of analyzing the root cause of system faults and can perform qualitative analysis and quantitative calculation accordingly. Therefore, it is more widely used in the fault analysis of various systems. Although there are already relevant studies on fault tree analysis for the motherboard function testing process, existing methods only independently process sample attributes and do not consider attribute importance, which will lead to insufficient accuracy of the optimization model and it is difficult to give an effective cross-domain overall optimization strategy. Summary of the Invention

[0006] Based on the technical problems existing in the background art, the present invention proposes a method, system and medium for fault analysis and cross-domain optimization of human-machine collaborative function testing, which improves the overall cross-domain optimization ability and realizes cost reduction and efficiency improvement in the main board function testing process.

[0007] The method for fault analysis and cross-domain optimization of human-machine collaborative function testing proposed by the present invention includes: Construct a fault tree, where the top event of the fault tree is the poor main board function testing, the intermediate event is the main board test item fault, and the root cause of the main board test item fault is the bottom event; Based on the reverse quantitative analysis of the fault tree structure, convert the test ratio of the intermediate event corresponding test item into the test ratio of the bottom event, calculate the product of the occurrence probability of the bottom event and the test ratio of the bottom event not undergoing function testing, and thereby obtain the probability of the main board being undetected and defective; Construct a test ratio optimization model for the main board function testing process, construct the objective function of the test ratio optimization model based on the test ratio of the test item and the probability of the main board being undetected and defective, and solve the test ratio optimization model to obtain the optimal main board function testing strategy for testing the main board.

[0008] Further, the conversion of the test ratio of the intermediate event corresponding test item into the test ratio of the bottom event is specifically: Take the product of the test ratios of the bottom event where the intermediate event corresponding test items are not tested as the test ratio of the bottom event not undergoing function testing; Based on the test ratio of the bottom event not undergoing function testing, the test ratio of the bottom event can be calculated.

[0009] Further, the calculation of the product of the occurrence probability of the bottom event and the test ratio of the bottom event not undergoing function testing to obtain the probability of the main board being undetected and defective is specifically: Classify according to whether the bottom event occurs and whether the bottom event has undergone function testing, and take the bottom event that has occurred and the bottom event that has not undergone function testing as the D-type bottom event; Calculate the product of the occurrence probability of the D-type bottom event and the non-function testing ratio of the D-type bottom event to obtain the occurrence probability of the undetected bottom event; By calculating the occurrence probability that all bottom events are not undetected bottom events as the probability of non-undetected defective main boards; Take the complement of the probability of non-undetected defective main boards as the probability of the main board being undetected and defective.

[0010] Further, the objective function of the test ratio optimization model is the sum of the average test time cost and the average repair time cost.

[0011] Further, the average test time cost is equal to the sum of the average test time costs of each test item on the main board, and the average test time cost of the test item is equal to the product of the average test time of the test item and the test ratio of the test item; The sum of the average repair time costs is equal to the product of the probability that the main board is undetected and defective and the repair time cost of each defective main board; Set a constraint function for the test ratio optimization model, and solve the test ratio optimization model with the objective function and constraint conditions set to obtain the optimal main board function test strategy.

[0012] Further, the constraint function includes an average test time constraint, an undetected defective main board rate constraint, and an upper and lower limit constraint on the test ratio of the test item; The formula for the average test time constraint is as follows: ; Where is the maximum average test time of each main board, is the average test time cost of the main board under the function test strategy ; The formula for the undetected defective main board rate constraint is as follows: ; Where is the undetected defective main board rate under the function test strategy , is the maximum undetected defective main board rate set based on expert experience during the main board function test, and the undetected defective main board rate is equal to the ratio of the undetected and defective main boards among the defective main boards; The formula for the upper and lower limit constraint on the test ratio of the test item is as follows: ; Where is the test ratio of the th intermediate event, that is, the test ratio corresponding to the th test item.

[0013] Further, optimize the upper and lower limit constraint on the test ratio of the test item in the constraint function based on the density peak clustering algorithm, specifically: Obtain the clustering decision value corresponding to the main board function test item based on the density peak clustering algorithm; Normalize the clustering decision value corresponding to the main board function test item, normalize the maximum clustering decision value to the original test ratio upper limit of the test ratio optimization model, normalize the minimum clustering decision value to the original test ratio lower limit of the test ratio optimization model, and normalize the other test item corresponding clustering decision values to between the original test ratio upper and lower limit constraints of the test ratio optimization model.

[0014] Furthermore, the optimized formulas for the upper and lower limits of the test ratio of the measurement items in the objective function are as follows: , when is the measurement item of the clustering center; , when is the measurement item of non-clustering center; Among them, is the initial clustering decision value of the measurement item , is the minimum value among the clustering decision values corresponding to all measurement items, is the maximum value among the clustering decision values corresponding to all measurement items, is the original upper limit of the test ratio of the test ratio optimization model, is the original lower limit of the test ratio of the test ratio optimization model.

[0015] The human-machine collaborative function test fault analysis and cross-domain optimization system includes a fault tree construction module, a reverse quantitative analysis module, and a main board test module; The fault tree construction module is used to construct a fault tree, which takes the poor main board function test as the top event, the main board measurement item fault as the intermediate event, and the root cause of the main board measurement item fault as the bottom event; The reverse quantitative analysis module is based on the reverse quantitative analysis of the fault tree structure, converts the test ratio of the measurement item corresponding to the intermediate event into the test ratio of the bottom event, calculates the product of the occurrence probability of the bottom event and the test ratio of the bottom event without performing the function test, and obtains the probability of undetected and poor main board based on this; The main board test module is used to construct a test ratio optimization model for the main board function test process, construct an objective function of the test ratio optimization model based on the test ratio of the measurement item and the probability of undetected and poor main board, and solve the test ratio optimization model to obtain the optimal main board function test strategy for testing the main board.

[0016] A computer-readable storage medium stores a number of classification programs thereon, and the number of classification programs is used to be called by a processor and execute the optimization method as described above.

[0017] The advantages of the human-machine collaborative function test fault analysis and cross-domain optimization method, system and medium provided by the present invention are as follows: Based on expert experience, fault tree analysis is carried out to establish a fault tree analysis model for the main board function test stage, and then a reverse quantitative analysis method is designed based on the fault tree structure to convert the test ratio of the measurement item corresponding to the intermediate event into the test ratio of the corresponding bottom event, improving the accuracy of the key index calculation method of the test ratio optimization model, and realizing cost reduction and efficiency improvement in the main board function test process. Description of the Drawings

[0018] Figure 1 It is a schematic flow diagram of the present invention; Figure 2 It is a schematic diagram of the connection of the mainboard circuit modules of a typical business laptop; Figure 3 It is a schematic diagram of a fault tree analysis model for the mainboard function test phase. Specific implementation manners

[0019] Next, the technical solution of the present invention will be described in detail through specific embodiments. Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific implementations disclosed below.

[0020] As Figures 1 to 3 shown, the human-machine collaborative function test fault analysis and cross-domain optimization method proposed by the present invention includes Step 1 to Step 3: Step 1, construct a fault tree, where the top event of the fault tree is the poor mainboard function test, the intermediate events are the mainboard test item faults, and the root causes of the mainboard test item faults are the bottom events; Step 2, based on the reverse quantitative analysis of the fault tree structure, convert the test ratio of the item corresponding to the intermediate event into the test ratio of the bottom event, calculate the product of the occurrence probability of the bottom event and the test ratio of the bottom event without performing the function test, and thereby obtain the probability of undetected and poor mainboard; Step 3, construct an optimization model for the test ratio in the process of mainboard function test, construct the objective function of the test ratio optimization model based on the test ratio of the item and the probability of undetected and poor mainboard, and solve the test ratio optimization model to obtain the optimal mainboard function test strategy for testing the mainboard.

[0021] To solve the problem that the existing methods independently process sample attributes and do not consider the importance of attributes, resulting in insufficient accuracy of the optimization model and difficulty in giving an effective cross-domain overall optimization strategy. In this embodiment, through Step 1 to Step 3, taking the mainboard of a typical business laptop as the object, fault tree analysis is carried out based on expert experience to establish a fault tree analysis model for the mainboard function test phase, and then a reverse quantitative analysis method is designed based on the fault tree structure to convert the test ratio of the item corresponding to the intermediate event into the corresponding test ratio of the bottom event, improving the accuracy of the calculation method of the key indicators of the test ratio optimization model, and designing a mainboard function test strategy with cross-domain overall optimization ability based on this embodiment to achieve cost reduction and efficiency improvement in the process of mainboard function test.

[0022] In one embodiment, Step 1, construct a fault tree, specifically: Figure 2 Shows a schematic diagram of the connection of the mainboard circuit modules of a typical business laptop computer. Figure 3 Shows a fault tree analysis model for the mainboard function testing phase. In fault tree analysis, events are classified into top events, intermediate events, and bottom events according to the causal relationship. The top event is the fault state that the system does not expect to occur. The bottom event is the event for which the cause of the fault cannot or does not need to be investigated further. The intermediate event is the factor that causes the top event to occur other than the bottom event. Based on the above fault tree analysis theory and the composition and connection relationship of each component in the mainboard circuit, a fault tree is constructed with the poor mainboard function testing as the top event (denoted as T), the mainboard test item fault as the intermediate event, and the root cause of the mainboard test item fault as the bottom event.

[0023] During the mainboard function testing process, the functions of the components outside the circuit diagram will be tested. Each component corresponds to a mainboard function test item. If any test item of the mainboard fails, it will result in poor mainboard function testing. Therefore, each mainboard function test item corresponds to an intermediate event in the fault tree. The faults of each test item are connected to the top event through a logical OR gate as intermediate events. The intermediate events of the mainboard of a typical business laptop computer and their corresponding function test items are shown in Table 1, where , , and are intermediate events that occur during the fault tree analysis process. The corresponding components are not tested during the mainboard function testing phase, so this intermediate event does not correspond to a mainboard function test item.

[0024] Table 1 Intermediate events of the mainboard of a typical business laptop computer and their corresponding function test items

[0025] The fault tree is gradually constructed according to the fault tree analysis process in the order from the top event to the intermediate event and finally to the bottom event. The top event T includes all the faults of the test items for the mainboard function testing (as shown in Table 1). Based on expert experience, the reasons for the faults of the corresponding mainboard components for each test item can be summarized into the following three aspects: First, the test item fault may be due to a fault in the components of the mainboard component corresponding to the test item. For example, the touchpad may not work properly due to manufacturing defects or physical damage. In this case, even if other related components and connection lines are normal, the problem with the touchpad component itself will still cause a touchpad fault.

[0026] Second, other motherboard components connected to the components corresponding to the test item may also be the root cause of the failure. These connected motherboard components may not be directly functionally tested. However, if such components fail, it will also lead to poor functional test results for the components connected to them. For example, if the Embedded Controller (EC) on the motherboard fails, in this case, even if the touchpad components themselves are not faulty, due to the incorrect transmission of control signals, the touchpad functional test results will still be poor. That is, there is a mutual dependence relationship between the motherboard components and other connected components, and the failure of one component may affect other components.

[0027] Third, a fault in the connection line between this component and other motherboard components is also a possible cause of the failure. The faults in the connection line may include poor soldering or physical damage, etc. For example, if there is poor soldering in the connection line between the touchpad and the EC, even if the touchpad and the EC are both not faulty, the touchpad function still cannot be used normally.

[0028] For motherboard components other than the components corresponding to the functional tests in Table 1 on the motherboard, such as the Central Processing Unit (CPU), Platform Controller Hub (PCH) chipset, audio decoder, and Embedded Controller (EC), this type of component is not directly functionally tested and is mainly composed of chips. Based on expert experience, the reasons for the failure of its own components can be specifically divided into the following two sub - aspects: The first sub - aspect is that the chip itself may be faulty. Tiny defects or electrostatic damage, etc., that may occur during the chip manufacturing process can cause the chip to malfunction. For example, if there is an internal circuit short - circuit, open - circuit, or electrostatic damage in the PCH chipset chip during the manufacturing process, then this defect may cause the PCH chipset chip to be unable to control or coordinate other components on the motherboard normally, thereby leading to poor functional test results for relevant test items.

[0029] The second sub - aspect is that poor soldering between the chip and the motherboard is also a possible cause of the failure. During the soldering process, situations such as insufficient soldering, solder joint cracks, and solder quality problems will all result in poor soldering. This poor soldering will cause unreliable contact between the chip and the motherboard, resulting in unstable or interrupted electrical signal transmission, thereby triggering abnormal functions of the components. Taking the PCH chipset as an example, poor soldering problems between the PCH chipset chip and the motherboard during the motherboard functional test may lead to unstable communication or even disconnection between the PCH chip and other motherboard components, thereby causing faults in relevant test items.

[0030] Based on the above-mentioned causes of measurement item failures obtained from expert experience, fault tree analysis is performed on all intermediate events in Table 1, and the basic events included in all intermediate events are obtained. The basic events included in the fault tree with the poor motherboard test as the top event are shown in Table 2. Subsequently, with the poor motherboard test as the top event and the failures of each measurement item as intermediate events, the root causes of the failures of each measurement item analyzed are used as basic events to construct a fault tree analysis model for the motherboard function test stage, as shown in Figure 3 shown. The intermediate events corresponding to the failures of each component and the basic events they contain are shown in Table 3.

[0031] Table 2 Basic Events of the Fault Tree Analysis Model for the Motherboard of a Typical Business Laptop

[0032] Table 3 Basic Event Symbol Corresponding to the Intermediate Event of the Fault Tree Analysis Model for the Motherboard Function Test Stage

[0033] In one embodiment, Step 2: Reverse quantitative analysis based on the fault tree structure. Convert the test ratio of the measurement item corresponding to the intermediate event into the test ratio of the basic event, and calculate the product of the occurrence probability of the basic event and the test ratio of the basic event without performing the function test, so as to obtain the probability of undetected and defective motherboards, specifically: The probability of undetected and defective motherboards directly affects the calculation result of the repair time cost, and further affects the calculation of the objective function of the test ratio optimization model. Accurately calculating the probability of undetected and defective motherboards is a key step in determining the objective function. Different intermediate events in the fault tree may contain multiple identical basic events. When a measurement item corresponding to a certain intermediate event does not perform the function test, but another measurement item with the same basic event as the intermediate event corresponding to this measurement item performs the function test, and the actual failure of the measurement item undergoing the function test is this same basic event, the test results of the measurement items corresponding to the intermediate events with the same basic event are all defective. This is because in the fault tree for the motherboard function test, the basic event and the intermediate event are connected by a logical OR gate. When the same basic event fails, the measurement items corresponding to the intermediate events containing this basic event will all fail. In this case, although some measurement items do not perform the function test, their test results can be inferred from the test results of the measurement items with the same basic event and undergoing the test.

[0034] Therefore, there is a certain error in calculating the probability of undetected and defective motherboards using the test ratio of the measurement item corresponding to the intermediate event and the occurrence probability of the intermediate event. This calculation method calculates the undetected situation of some measurement items that will fail simultaneously independently, resulting in an overestimated calculation result of the probability of undetected and defective motherboards, and further affecting the accuracy of the motherboard repair time cost and the objective function of the test ratio optimization model.

[0035] To eliminate the error problem that exists when calculating the probability of undetected and defective main boards using the test ratio of the test items corresponding to intermediate events and the occurrence probability of intermediate events, the test ratio of basic events and the occurrence probability of basic events are used to calculate the probability of undetected and defective main boards. Since different basic events in the fault tree are independent of each other, whether a certain basic event occurs has nothing to do with the test results of other basic events. Therefore, using the relevant indicators of basic events to replace the relevant indicators of intermediate events for calculation will not result in error problems. And according to the relationship between intermediate events and basic events in the fault tree analysis model for the main board function test stage, the test ratio of the test items corresponding to intermediate events can be converted into the test ratio of basic events, so that the test ratio of basic events can change correspondingly according to the change of the test ratio corresponding to the intermediate events during the optimization process of the test ratio, meeting the requirements of the test ratio optimization process.

[0036] The test ratio of basic events can be calculated and obtained based on the test ratio of the test items corresponding to intermediate events. In the fault tree for the main board function test stage, one intermediate event contains multiple basic events, and one basic event may correspond to multiple intermediate events. According to the relationship between intermediate events and basic events in the table, any basic event corresponds to all intermediate events, as shown in Table 4. Among them, since intermediate events , , and are only intermediate events that appear in the process of fault tree analysis and do not have corresponding main board function test items, there is no corresponding test ratio for such intermediate events, and it will not affect the calculation of the test ratio of basic events. Therefore, such intermediate events are not included in the analysis process in the analysis of the intermediate events corresponding to basic events.

[0037] Table 4 Intermediate event numbers corresponding to basic events in the fault tree analysis model for the main board function test stage

[0038] In this embodiment, the probability of undetected and defective main boards is obtained by calculating the product of the occurrence probability of basic events and the test ratio of basic events not undergoing function tests. Specifically: the product of the test ratios of the test items corresponding to the intermediate events of the basic events that are not tested is used as the test ratio of the basic events not undergoing function tests; based on the test ratio of the basic events not undergoing function tests, the test ratio of basic events can be calculated.

[0039] Specifically, for a certain basic event, when all the test items corresponding to the intermediate events containing this basic event are not subjected to function tests, this basic event actually does not undergo function tests. Therefore, the test ratio of the basic event not undergoing function tests is the product of the test ratios of the test items corresponding to the intermediate events containing this basic event that are not tested, and its calculation formula is: ; Among them, is the basic event number, is the set of intermediate events containing the basic event , is the test ratio of the th test item.

[0040] The test ratio of not performing functional tests based on basic events By calculation, the test ratio of basic events can be obtained , and the calculation formula is as follows: .

[0041] Based on the above formula and the relationship between intermediate events corresponding to basic events in the fault tree analysis model for the main board functional test stage, the test ratio of the test item corresponding to the intermediate event can be converted into the test ratio of the basic event.

[0042] In this embodiment, based on the test ratio of basic events, the probability of undetected and defective main boards can be calculated. Specifically: Classify according to whether the basic event occurs and whether the basic event has undergone functional testing. Consider the basic event that has occurred and the basic event that has not undergone functional testing as D-class basic events; calculate the product of the occurrence probability of D-class basic events and the non-functional test ratio of D-class basic events to obtain the occurrence probability of undetected basic events; calculate the probability that all basic events are not undetected basic events as the probability of non-undetected defective main boards; take the complement of the probability of non-undetected defective main boards as the probability of undetected and defective main boards.

[0043] Specifically, the probability of undetected and defective main boards is specifically: According to whether the main board undergoes functional testing and whether the main board is faulty during the main board functional test process, the main board can be classified as shown in Table 5; Table 5 Main board classification table based on main board functional test status

[0044] Among them, A-class and C-class main boards undergo functional testing and there will be no undetected situation. B-class main boards do not undergo functional testing but their own status is good and will not cause an increase in the number of undetected defective main boards. While D-class main boards are faulty main boards, and the fact that such main boards do not undergo functional testing will cause an increase in the number of undetected defective main boards, thus affecting the probability of undetected and defective main boards. Therefore, calculating the probability of D-class main boards appearing during the main board functional test process can obtain the probability of undetected and defective main boards.

[0045] Based on the fault tree analysis model for the motherboard function test phase, the motherboard function test includes several basic event tests. The occurrence of any basic event will lead to the top event of the fault tree, that is, the poor motherboard function test occurs. Therefore, for the basic event test of type D motherboards, there are basic event faults in the basic event test of this type of motherboard and the basic event has not been functionally tested. Therefore, when and only when all basic events are non-missed-inspection defective basic events, this motherboard is a non-missed-inspection defective motherboard. Based on the above analysis, the probability of type D motherboards occurring during the motherboard function test is related to the probability of missed-inspection basic events occurring.

[0046] Similar to motherboard classification, basic events can be classified according to whether the basic event occurs and whether the basic event has been functionally tested, as shown in Table 6; Table 6 Classification Table of Basic Events for the Fault Tree Analysis Model in the Motherboard Function Test Phase

[0047] Among them, type A and type C basic events participate in the function test and there will be no missed-inspection situation. Type B basic events do not undergo function tests but they do not occur, which will not cause an increase in the number of missed-inspection basic events. However, type D basic events have occurred and this type of basic event has not participated in the function test, resulting in an increase in the number of missed-inspection basic events, thereby affecting the probability of missed-inspection basic events occurring. Based on the above analysis, the probability of type D basic events occurring is the probability of missed-inspection basic events occurring , which is equal to the product of the probability of the basic event occurring and the proportion of the basic event not undergoing function test. The calculation formula is as follows: ; Among them, is the probability of basic event occurring, is the test proportion of the basic event.

[0048] Since the occurrence of any basic event will lead to poor motherboard function test, for any motherboard during the motherboard function test, if a type D basic event appears, then this motherboard is defective and missed-inspected. Therefore, when the basic event included in the intermediate event corresponding to any test item on the motherboard occurs and is missed-inspected, this motherboard is a missed-inspection defective motherboard; when the basic events included in the intermediate events corresponding to all test items on the motherboard do not occur or are not missed-inspected, this motherboard is a non-missed-inspection defective motherboard. Based on the above analysis, the probability that the motherboard is a non-missed-inspection defective motherboard is the probability that all the basic events it contains are not type D basic events. The calculation formula is as follows: ; Among them, is the number of basic events.

[0049] The probability that the motherboard is missed-inspected and defective It is the probability that all basic events exist, including Class D basic events, that is, the complement of the probability that the main board is a non-missed inspection defective main board. The calculation formula is as follows: ; Therefore, according to the proposed reverse quantitative analysis method based on the fault tree structure, the probability that the main board is missed inspection and defective can be calculated. Based on this, the objective function and constraint function of the test ratio optimization model for the main board function test process are further determined.

[0050] In this embodiment, Step 3: Construct a test ratio optimization model for the main board function test process. Based on the test ratio of test items and the probability that the main board is missed inspection and defective, construct the objective function of the test ratio optimization model, specifically: The objective function is the core component of the test ratio optimization model, which defines the goal and direction of the optimization problem. The objective function quantifies the optimization goal, compares the advantages and disadvantages of different solutions of the test ratio optimization model, and thus selects the optimal solution of the test ratio optimization model. A good objective function can fully reflect the actual problem requirements and ensure that the optimization result meets the actual application requirements. In the problem of optimizing the main board function test ratio, reducing the functional test time cost is the primary goal of the optimization process. To achieve cost reduction and efficiency improvement in the main board function test process, it is necessary to comprehensively consider the test cost and repair cost for cross-domain overall optimization. Therefore, the return value of the objective function should be set as the average total test time cost per main board. The average total test time cost includes the average test time cost and the average repair time cost. The test time cost refers to the cost of performing functional tests on each test item of the main board, and the repair time cost refers to the cost that the product needs to be returned to the factory for repair due to the failure of the functional test to effectively detect the test item failure. Both the test time cost and the repair time cost are measured using time cost. The average test time cost is related to the test ratio of functional test items, and the average repair time cost is related to the missed inspection rate of defective main boards. Therefore, the objective function can be designed as a function of the test ratio of test items and the missed inspection rate of defective main boards.

[0051] The average test time cost of the main board is equal to the sum of the average test time costs of each test item on the main board. The average test time cost of a test item is equal to the product of the average test time of the test item and its test ratio. Therefore, under the test strategy the average test time cost of the main board is: ; Among them, represents the number of test items, represents the th average test time of the test item, represents the th test ratio of performing functional tests on the test item, represents according to the test strategy A set of test ratios for performing functional tests on each determined test item.

[0052] The average repair time cost of the main board is equal to the product of the probability that the main board is undetected and defective and the repair time cost of each defective main board. Therefore, under the test strategy the average repair time cost of the main board is: ; where is the probability that the main board is undetected and defective, and is the average repair time cost of each defective main board.

[0053] When the main board is defective and the main board has not undergone a functional test, the main board will incur a repair time cost. Therefore, under the functional test strategy the average repair time cost of the main board is the product of the probability that the main board is undetected and defective and the average repair time cost of each defective main board. The calculation formula is as follows: .

[0054] The average total test time cost of each main board is the sum of the average total test time cost and the average total repair time cost. Therefore, under the functional test strategy the average total test time cost of each main board is: .

[0055] Therefore, based on the calculation formula of the average total test time cost of each main board under the functional test strategy under the functional test strategy the objective function of the test ratio optimization model finally has the following expression: .

[0056] The design of this objective function fully considers the most important optimization objective in the process of the main board functional test, realizes cross-domain overall optimization by comprehensively considering the test cost and the repair cost, and uses the test ratio of the bottom event to replace the test ratio of the corresponding item of the intermediate event in the calculation process of the repair time cost, making the calculation of the repair time cost more accurate and reasonable, and thus ensuring the accuracy and rationality of the test ratio optimization model.

[0057] In this embodiment, the constraint function in the test ratio optimization model defines the solution space that satisfies all constraint conditions, helps the optimization model search for solutions within the solution space to avoid invalid searches, and is used to ensure that the solutions to the optimization problem meet the constraints of the actual problem. At the same time, the constraint function can help the optimization model balance multiple objectives by transforming some objectives into constraint conditions to simplify the optimization problem. To ensure the feasibility and effectiveness of the optimization results of the test ratio optimization model during the main board function test, according to the actual requirements of the main board function test process and expert experience, the constraint functions of the test ratio optimization model are respectively set as the average test time constraint, the undetected defective main board rate constraint, and the upper and lower limits constraint of the test item test ratio.

[0058] The average test time of the main board directly affects the average test time cost of the main board. The average test time cost of the main board is an important indicator to measure the quality of the main board function test strategy. Therefore, there are certain requirements for the average test time of the main board during the main board function test process. If no constraint is set for this indicator, the optimization results of the test ratio optimization model will not be effective during the main board function test process. Based on the above analysis, the average test time constraint is set to ensure that the function test of each main board is completed within a reasonable time. For the maximum average test time of each given main board , based on the requirements of the main board function test process and expert experience, set the percentage of test items for function testing , then The calculation formula is: ; Among them, represents the average test time of the th test item.

[0059] According to the average test time cost of the main board under the function test strategy [[ID=2३]], the average test time constraint can be expressed as: ; That is, ; Among them, is the maximum average test time for each given main board. If the average test time cost of the main board under the test strategy meets this inequality constraint, then this test ratio is a solution to the optimization function. Otherwise, if the average test time exceeds the given maximum value, this test ratio is invalid.

[0060] By setting the undetected defective main board rate constraint, ensure that the ability of the obtained test ratio to intercept defective main boards is within the requirements of the function test process. Since the occurrence of any basic event will cause the main board to be defective, the probability of the main board being good The calculation formula is as follows: ; wherein, is the occurrence probability of the basic event .

[0061] Based on the good probability of the main board the bad probability of the main board can be obtained , and the calculation formula is as follows: ; The proportion of undetected and bad main boards among the bad main boards is the undetected bad main board rate , and the calculation formula is as follows: ; Based on the undetected bad main board rate calculated by the above process, the constraint of the undetected bad main board rate in the optimization process under the test strategy can be expressed as: ; wherein, is the maximum undetected bad main board rate set based on expert experience in the main board function test process. If the undetected bad main board rate under the test strategy satisfies this inequality constraint, then this test ratio is a solution of the optimization function; otherwise, if the undetected bad main board rate exceeds the given maximum value, this test ratio is invalid.

[0062] By setting the upper and lower limits of the test ratio constraints for each test item to ensure that the test ratio of each test item is within a reasonable range. When there are specified requirements for the test ratio of some test items, the test ratio of the corresponding test item is adjusted to within the specified range to meet the actual requirements of the function test process; when there are no specified requirements for the test ratio of each test item in the main board function test, the test ratio of each test item is uniformly specified to be between 0 and 1, then the upper and lower limit constraint conditions of the test ratio of the test item can be expressed as: .

[0063] In summary, the final expression of the constraint function of the test ratio optimization model is as follows: ; This constraint function design fully considers the important indicators and expert experience in the main board function test process, ensures that the optimization result meets the actual requirements of the main board function test, and uses the test ratio of the basic event to replace the test ratio of the corresponding test item of the intermediate event in the calculation process of the undetected bad main board rate constraint condition, making the calculation of this constraint condition more accurate and reasonable, and further ensuring the accuracy and reasonableness of the test ratio optimization model.

[0064] In one embodiment, the upper and lower limits of the test ratio of the measurement items in the constraint function are optimized based on the density peak clustering algorithm: the clustering decision values corresponding to the main board function measurement items are obtained based on the density peak clustering algorithm; the clustering decision values corresponding to the main board function measurement items are normalized, and the maximum clustering decision value is normalized to the original upper limit of the test ratio of the test ratio optimization model, the minimum clustering decision value is normalized to the original lower limit of the test ratio of the test ratio optimization model, and the clustering decision values corresponding to other measurement items are normalized between the original upper and lower limits of the test ratio of the test ratio optimization model.

[0065] Specifically, the design of the constraint conditions in the test ratio optimization model is related to the size of the solution space of the optimization model. A reasonable design of the constraint conditions can help the optimization algorithm search for solutions in the solution space, so that the optimization solution result meets the requirements of the actual problem. For the design of the upper and lower limits of the test ratio in the test ratio optimization model, the design of the upper and lower limits of the test ratio in the original test ratio optimization model only considered the rationality of the optimal solution, and the upper and lower limits of the test ratio were uniformly set to . This constraint condition does not distinguish the importance of attributes based on expert guidance and cannot effectively guide the optimization direction of the test strategy.

[0066] In the clustering groups obtained based on the density peak clustering algorithm, the attributes of the clustering center are strongly correlated with other attributes in the same clustering group. Compared with other non-clustering center attributes, the sample data of the clustering center attributes can effectively reflect the distribution of the sample data of this clustering group. Therefore, based on expert guidance, it can be known that in the main board function test ratio optimization model, the importance of the clustering center attributes is stronger than that of the non-clustering center attributes. By increasing the test ratio of the clustering center measurement items and decreasing the test ratio of the non-clustering center measurement items, it is an effective way to reduce the total time cost of the function test.

[0067] The density peak clustering algorithm calculates the size of the decision value according to the local density and relative distance of different attributes to determine the clustering center and the clustering group results. The calculation formula of the clustering decision value is as follows: .

[0068] Taking the local density of the measurement item as the abscissa and the relative distance as the ordinate, the measurement item in the coordinate system is the projection of the measurement item on the coordinate system. The local density reflects the number of other measurement items around the measurement item. The measurement items in the clustering center area are dense, so the higher the local density of the measurement item, the greater the probability of becoming a clustering center. The relative distance reflects the distance from the measurement item to other measurement items with higher local density. The relative distance between clustering centers is generally higher to ensure sufficient distance between different clustering groups. Therefore, the higher the relative distance of the measurement item, the greater the probability of becoming a clustering center. Based on the above analysis, since the decision value is the product of the local density and relative distance of the measurement item, the higher the decision value of the measurement item, the greater the probability of becoming a clustering center.

[0069] Normalize the clustering decision values corresponding to the measurement items in the clustering group. Normalize the maximum clustering decision value to the original test ratio upper limit of the test optimization model, and normalize the minimum clustering decision value to the original test ratio lower limit of the test ratio optimization model. Normalize the corresponding clustering decision values of other attributes to between the original test ratio constraint conditions of the test ratio optimization model. The formula is as follows: ; Among them, is the test ratio boundary value corresponding to the normalized attribute, is the initial clustering decision value of the attribute, is the minimum value among all the clustering decision values corresponding to the attributes, is the maximum value among all the clustering decision values corresponding to the attributes, is the original test ratio upper limit of the test ratio optimization model, is the original test ratio lower limit of the test ratio optimization model.

[0070] In the fault tree of the motherboard function test process, the intermediate events corresponding to different attributes may contain the same basic events. Based on expert experience, the more basic events are included in different intermediate events, the greater their mechanism correlation. Therefore, the greater the mixed correlation measurement value between these intermediate events. Consequently, the greater the local density and relative distance calculated based on the correlation measurement results, and the greater the clustering decision value. Based on the above analysis, the more the same basic events are included between the corresponding intermediate events, the greater the probability that the attribute corresponding to this intermediate event becomes a clustering center. The number of the same basic events included in the intermediate events corresponding to the clustering center attributes is more than that of the intermediate events corresponding to other attributes. Therefore, increasing the lower limit of the test ratio value range corresponding to the clustering center attributes and decreasing the upper limit of the test ratio value range corresponding to the non-clustering center attributes can strengthen the constraint function of the test ratio optimization model, making the optimal solution set concentrated in the optimal region of the objective function. Furthermore, the coverage rate of the optimal solution of the basic event test variables corresponding to the optimal solution of the test ratio of the attributes is higher, so as to further fully reduce the key indicators.

[0071] Based on the above analysis, increasing the lower limit of the test ratio of the clustering center measurement items in the test ratio optimization model can ensure that the clustering center measurement items are fully covered during the testing process, improve the comprehensiveness of the testing process, and reduce the risk of increased rework time costs caused by insufficient testing. At the same time, reducing the upper limit of the test ratio of non-clustering center measurement items in the test ratio optimization model can reduce redundant testing of marginal measurement items and lower the functional testing time cost. Therefore, based on expert guidance, the lower limit of the test ratio of the clustering center measurement items in the test ratio optimization model is adjusted from the original lower limit of the test ratio to the normalized result of the corresponding clustering decision value of this measurement item, and the calculation formula is as follows: , when is a clustering center measurement item; where is the th initial clustering decision value of the measurement item.

[0072] At the same time, based on expert guidance, the upper limit of the test ratio of non-clustering center measurement items is adjusted from the original upper limit of the test ratio to the normalized result of the corresponding clustering decision value of this measurement item, and the calculation formula is as follows: , when is a non-clustering center measurement item.

[0073] Based on the above method for adjusting the upper and lower limits of the test ratio in the test ratio optimization model corresponding to different attributes based on density peak clustering, the constraint conditions of the test ratio optimization model are reconstructed. The upper and lower limit constraint expressions of the test ratio of the adjusted test ratio optimization model are: , when is a clustering center measurement item; , when is a non-clustering center measurement item.

[0074] Based on the above expert guidance, the upper and lower limit constraint conditions of the test ratio of the test ratio optimization model are reconstructed to fully consider the number of common basic events included in the intermediate events corresponding to different attributes in the clustering result, as well as the test redundancy caused by the testing of the same basic events, and further optimize the design of the test ratio optimization model.

[0075] This embodiment solves the problem that the existing method independently processes sample attributes and does not consider the importance of attributes, resulting in insufficient accuracy of the test ratio optimization model and difficulty in giving an effective cross-domain overall optimization strategy.

[0076] Based on expert experience, this embodiment designs a fault tree and a top-down reverse quantitative analysis method based on the structure of the fault tree. At the same time, using the clustering results of the improved density peak clustering algorithm, the importance of attributes is determined through expert guidance, and constraint conditions are designed accordingly. The method proposed in this embodiment can be used to design a motherboard function test strategy with cross-domain overall optimization ability, which helps to reduce costs and improve efficiency in the motherboard function test process.

[0077] This embodiment uses three parameters, namely the undetected defective motherboard rate, the average test time, and the average total test time cost, as evaluation indicators. These indicators reflect the ability of the test strategy to intercept defective motherboards, the time benefit, and the overall time cost. The undetected defective motherboard rate is the ratio of undetected defective motherboards to the total number of defective motherboards. The average test time is the average of the test times for each motherboard, and the average total test time cost is the sum of the average repair time and the average test time.

[0078] The optimization method (FTA-DPC-FM) of this embodiment is compared with the following four methods in turn: The first comparison method is the density peak clustering algorithm based on hybrid modeling (Hybrid-DPC-S). This algorithm is a binary selection method that realizes the density peak clustering of motherboard function test items by performing hybrid modeling on the correlation of test items, and determines the motherboard function test strategy based on the clustering results. The specific method details can be referred to Patent CN118194059A.

[0079] The second comparison method is the traditional test proportion optimization method (TPO-FM) that only optimizes the modeling based on the test proportion corresponding to the intermediate event. This method is the ablation experiment of this embodiment. This method does not use the reverse quantitative analysis method based on the fault tree structure proposed in this embodiment to analyze the test proportion of bottom events, and does not reconstruct the constraint conditions of the optimization model based on the clustering decision value. It only optimizes the test proportion of motherboard function test items based on the test proportion of test items.

[0080] The third comparison method is the test strategy design method (FTA-FM) that optimizes the modeling based on the reverse quantitative analysis of the fault tree structure. This method is the ablation experiment of this embodiment. This method uses the reverse quantitative analysis method based on the fault tree structure proposed in this embodiment and does not use the method for reconstructing the constraint conditions of the optimization model based on the clustering decision value. It optimizes the test proportion of motherboard function test items based on the obtained test proportion of bottom events.

[0081] The fourth comparison method is the traditional test proportion optimization method (TPO-DPC-FM) reconstructed based on the clustering decision value constraint condition. This method is the ablation experiment of this embodiment. This method does not use the reverse quantitative analysis method based on the fault tree structure proposed in this embodiment. On the basis of the second comparison method, it uses the optimization model constraint condition reconstruction method based on the clustering decision value proposed in this embodiment, strengthens the constraint condition of the optimization model, and optimizes the test proportion of the main board function test items based on the test item test proportion.

[0082] The test strategies and their performance indicators based on five different methods are compared as shown in Tables 7 and 8; Table 7 Test strategies obtained by the optimization method of this embodiment and the comparison methods

[0083] Table 8 Performance comparison of test strategies obtained by the optimization method of this embodiment and the comparison methods

[0084] The results show that the average test time of the proposed FTA-DPC-FM method is higher than that of the Hybrid-DPC-S method, but its undetected defective main board rate is significantly lower than that of the Hybrid-DPC-S method, making the average total test time cost of the FTA-FM method and the TPO-FM method lower. This shows that compared with the binary selection method, the proposed test proportion optimization method realizes the precise allocation of test resources by solving the continuous optimal solution of the main board function test strategy, thus fully reducing the redundant tests in the main board function test process, and therefore can further reduce the total time cost of the main board function test.

[0085] The undetected defective main board rate of the FTA-FM method is slightly higher than that of the TPO-FM method, but its average test time is significantly lower than that of the TPO-FM method, making the average total test time cost of the FTA-FM method lower than that of the TPO-FM method. This shows that the proposed FTA-FM method can effectively reduce the calculation error of the key indicators of the test proportion optimization model, and thus reduce the average total test time cost of the main board.

[0086] The undetected defective motherboard rate of the FTA-DPC-FM method is significantly lower than that of the Hybrid-DPC-S method and higher than that of the TPO-DPC-FM method. The average test time of the FTA-DPC-FM method is significantly lower than that of the TPO-DPC-FM method and higher than that of the Hybrid-DPC-S method, making the average total test time cost of the FTA-DPC-FM method significantly lower than that of the Hybrid-DPC-S method and the TPO-DPC-FM method. Moreover, both the undetected defective motherboard rate and the average test time of the FTA-DPC-FM method are slightly lower than those of the FTA-FM method, making the average total test time cost of the FTA-DPC-FM method lower than that of the FTA-FM method. This indicates that the proposed FTA-DPC-FM method can effectively enhance the constraint conditions of the optimization model, thereby fully reducing the average total test time cost of the motherboard.

[0087] The above analysis shows that the proposed FTA-DPC-FM method improves the design of the objective function and constraint conditions of the motherboard functional test ratio optimization model by reducing the calculation error of key indicators and compressing the value range of decision variables respectively. The proposed method can fully reduce the total time cost of the motherboard functional test and provide a continuous optimal solution for the optimization problem of the motherboard functional test time cost.

[0088] The method proposed in this embodiment conducts fault tree analysis based on expert experience, performs reverse quantitative analysis on the obtained fault tree structure, and compresses the upper and lower limits of the test ratio based on expert guidance, effectively reducing the calculation error of the key indicators of the test ratio optimization model and enhancing the constraint conditions of the test ratio optimization model, improving the cross-domain overall optimization ability of the motherboard functional test strategy design. The test strategy obtained based on the method of this embodiment significantly reduces the undetected defective motherboard rate while slightly increasing the average test time of the motherboard, thereby fully reducing the average total test time cost of the motherboard and achieving cost reduction and efficiency improvement in the motherboard functional test process.

[0089] As an embodiment; Taking the motherboard of a typical business laptop as the object, first establish a fault tree analysis model for the motherboard functional test stage according to the circuit module connection schematic diagram of the typical business laptop motherboard, then design a reverse quantitative analysis method based on the fault tree structure, convert the test ratio of the corresponding test item of the intermediate event into the test ratio of the corresponding bottom event, design the objective function and constraint conditions accordingly, and establish an optimization model for the motherboard functional test process. Finally, compress the upper and lower limits of the test ratio corresponding to different attributes based on the clustering decision value, adjust the constraint conditions, and perform optimization and solution. The specific implementation steps are as follows: A1. According to the electronic components included in the motherboard of a typical business laptop and the physical connection relationship between the components, construct the circuit module connection schematic diagram of the typical business laptop motherboard as shown in Figure 2 the figure; A2. Taking the motherboard test failure as the top event, the failures of each test item as intermediate events, and the root causes of the failures of each test item obtained from the failure analysis as bottom events, a fault tree analysis model for the motherboard function test stage is constructed; A3. Based on the fault tree structure in the fault tree analysis model for the motherboard function test stage (as Figure 3 shown), a reverse quantitative analysis method is designed; A4. According to the reverse quantitative analysis method in A3 and the relationship between the bottom events and intermediate events corresponding to the bottom events in Table 4, the test ratio of the intermediate event corresponding test item is converted into the test ratio of the corresponding bottom event; A5. Based on the test ratio of the bottom events obtained in A4, the key indicators of the test ratio optimization model are calculated, including the probability of undetected and defective motherboards and the average repair time cost of the motherboards; A6. According to the key indicators of the test ratio optimization model, the objective function and constraint function are designed, and a test ratio optimization model for the motherboard function test process is established; A7. Based on the density peak clustering algorithm, the clustering decision values corresponding to the motherboard function test items are obtained, and the clustering decision values corresponding to the motherboard function test items are normalized. The maximum clustering decision value is normalized to the original test ratio upper limit of the test ratio optimization model, the minimum clustering decision value is normalized to the original test ratio lower limit of the test ratio optimization model, and the clustering decision values corresponding to other test items are normalized between the original test ratio constraint conditions of the optimization model; A8. The lower limit of the test ratio of the clustering center test item in the test ratio optimization model is adjusted from the original test ratio lower limit to the normalized result of the clustering decision value corresponding to this test item; A9. The upper limit of the test ratio of the non-clustering center test item in the optimization model is adjusted from the original test ratio upper limit to the normalized result of the clustering decision value corresponding to this test item; A10. Based on the test ratio upper and lower limit adjustment methods of the test ratio optimization model corresponding to different test items in A8 and A9, the constraint conditions of the test ratio optimization model are reconstructed and optimized for solution; A11. According to the evaluation index, the test strategies obtained by the optimization method and the comparison method in this embodiment are compared and evaluated to verify the effectiveness of the method proposed in this embodiment. [[ID=2)3]]

[0090] In this embodiment, a human-machine collaborative function test failure analysis and cross-domain optimization system is set up, including a fault tree construction module, a reverse quantitative analysis module, and a motherboard test module; The fault tree construction module is used to construct a fault tree, which takes the motherboard function test failure as the top event, the motherboard test item failure as the intermediate event, and the root cause of the motherboard test item failure as the bottom event; The reverse quantitative analysis module is based on the reverse quantitative analysis of the fault tree structure, converts the test ratio of the test items corresponding to the intermediate events into the test ratio of the bottom events, calculates the product of the occurrence probability of the bottom events and the test ratio of the bottom events without functional testing, and thereby obtains the probability of undetected and defective main boards. The main board test module is used to construct an optimization model of the test ratio for the main board function test process, constructs the objective function of the test ratio optimization model based on the test ratio of the test items and the probability of undetected and defective main boards, and solves the test ratio optimization model to obtain the optimal main board function test strategy for testing the main board.

[0091] In addition, in this embodiment, a computer-readable storage medium is provided, and a number of classification programs are stored on the computer-readable storage medium. The number of classification programs are used to be called by a processor and execute the optimization method as described above.

[0092] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: various media such as ROM, RAM, magnetic disk or optical disk that can store program codes.

[0093] The above is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution of the present invention and its inventive concept, makes an equivalent replacement or change, and should be covered by the protection scope of the present invention.

Claims

1. A method for fault analysis and cross-domain optimization of human-machine collaborative function tests, characterized in that, Including: Construct a fault tree, where the top event of the fault tree is the poor motherboard function test, the intermediate event is the motherboard test item fault, and the root cause of the motherboard test item fault is the bottom event; Based on the reverse quantitative analysis of the fault tree structure, convert the test ratio of the intermediate event corresponding test item into the test ratio of the bottom event, calculate the product of the occurrence probability of the bottom event and the test ratio of the bottom event not undergoing function test, and obtain the probability of the motherboard being undetected and defective accordingly; Construct an optimization model for the test ratio for the motherboard function test process, construct the objective function of the test ratio optimization model based on the test ratio of the test item and the probability of the motherboard being undetected and defective, solve the test ratio optimization model to obtain the optimal motherboard function test strategy for testing the motherboard.

2. The human-machine collaborative function test fault analysis and cross-domain optimization method according to claim 1, wherein The conversion of the test ratio of the intermediate event corresponding test item into the test ratio of the bottom event is specifically as follows: Take the product of the test ratios of the intermediate event corresponding test items of the bottom event that are not tested as the test ratio of the bottom event not undergoing function test; Based on the test ratio of the bottom event not undergoing function test, the test ratio of the bottom event can be calculated.

3. The human-machine collaborative function test fault analysis and cross-domain optimization method according to claim 1, characterized in that The calculation of the product of the occurrence probability of the bottom event and the test ratio of the bottom event not undergoing function test to obtain the probability of the motherboard being undetected and defective is specifically as follows: Classify according to whether the bottom event occurs and whether the bottom event has undergone function test, and take the bottom event that has occurred and the bottom event that has not undergone function test as the D-type bottom event; Calculate the product of the occurrence probability of the D-type bottom event and the non-function test ratio of the D-type bottom event to obtain the occurrence probability of the undetected bottom event; By calculating the occurrence probability that all bottom events are not undetected bottom events, it is used as the probability of non-undetected defective motherboards; Take the complement of the probability of non-undetected defective motherboards as the probability of the motherboard being undetected and defective.

4. The human-machine collaborative function test fault analysis and cross-domain optimization method according to claim 1, characterized in that The objective function of the test ratio optimization model is the sum of the average test time cost and the average rework time cost; The average test time cost is equal to the sum of the average test time costs of each test item on the motherboard, and the average test time cost of the test item is equal to the product of the average test time of the test item and the test ratio of the test item; The sum of the average rework time costs is equal to the product of the probability of the motherboard being undetected and defective and the rework time cost of each defective motherboard.

5. The method for analyzing faults and cross-domain optimization in human-machine collaborative function testing according to claim 1, wherein Set a constraint function for the test ratio optimization model, and solve the test ratio optimization model with the set objective function and constraint conditions to obtain the optimal motherboard function test strategy.

6. The human-machine collaborative function test fault analysis and cross-domain optimization method according to claim 5, characterized in that The constraint function includes the average test time constraint, the undetected defective motherboard rate constraint, and the upper and lower limit constraints of the test ratio of the test item; The formula for the average test time constraint is as follows: ； Among them, is the maximum average test time for each main board, is the functional test strategy and is the average test time cost of the main board under it; The formula for the undetected defective motherboard rate constraint is as follows: ； Among them, is the undetected defective mainboard rate under the functional test strategy, which is the maximum undetected defective mainboard rate during the mainboard functional test set based on expert experience. The undetected defective mainboard rate is equal to the proportion of undetected and defective mainboards among the defective mainboards; The formula for the upper and lower limit constraints of the test ratio of the test item is as follows: ； Among them, is the test ratio of the th intermediate event, that is, the test ratio corresponding to the th test item.

7. The human-machine collaborative function test fault analysis and cross-domain optimization method according to claim 6, wherein, Optimize the upper and lower limit constraints of the test ratio of the test item in the constraint function based on the density peak clustering algorithm, specifically as follows: Obtain the clustering decision value corresponding to the motherboard function test item based on the density peak clustering algorithm; Normalize the clustering decision values corresponding to the main board function test items. Normalize the maximum clustering decision value to the original upper limit of the test ratio of the test ratio optimization model, normalize the minimum clustering decision value to the original lower limit of the test ratio of the test ratio optimization model, and normalize the clustering decision values corresponding to other test items to between the original upper and lower limits of the test ratio of the test ratio optimization model.

8. The method for human-machine collaborative function test fault analysis and cross-domain optimization according to claim 7, wherein, The optimized formulas for the upper and lower limits of the test ratio of the test items in the objective function are as follows: When is the measurement item of the clustering center; When is a non-cluster center measurement item; Among them, is the measurement item Initial clustering decision value, is the minimum value among the clustering decision values corresponding to all measurement items, is the maximum value among the clustering decision values corresponding to all measurement items, is the original upper limit of the test ratio of the test ratio optimization model, is the original lower limit of the test ratio of the test ratio optimization model.

9. Human-machine collaborative function test fault analysis and cross-domain optimization system, characterized in that, It includes a fault tree construction module, a reverse quantitative analysis module, and a main board test module; The fault tree construction module is used to construct a fault tree. The fault tree takes the poor main board function test as the top event, the main board test item failure as the intermediate event, and the root cause of the main board test item failure as the bottom event; The reverse quantitative analysis module, based on the reverse quantitative analysis of the fault tree structure, converts the test ratio of the intermediate event corresponding test item into the test ratio of the bottom event, calculates the product of the occurrence probability of the bottom event and the test ratio of the bottom event not undergoing functional testing, and thereby obtains the probability of the main board being undetected and defective; The main board test module is used to construct a test ratio optimization model for the main board function test process, construct the objective function of the test ratio optimization model based on the test ratio of the test items and the probability of the main board being undetected and defective, solve the test ratio optimization model to obtain the optimal main board function test strategy, and thereby test the main board.

10. A computer-readable storage medium, characterized in that, A number of classification programs are stored on the computer-readable storage medium, and the number of classification programs are used to be called by the processor and execute the optimization method according to any one of claims 1 to 8.

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