Data transmission method, device and system and storage medium

Abstract

The invention relates to a data transmission method, device and system and a storage medium. The method is used for DMA of a device side, the device side is connected with a host side through PCIe, and the method comprises the steps that the DMA receives a descriptor; the DMA obtains target data corresponding to the source address in the descriptor and sends the target data to the PCIe, and the PCIe is used for writing the target data into the destination address; the DMA sends a data reading request to the PCIe under the condition that the target data is sent to the PCIe and the indication information of the descriptor is a preset value; and when the DMA receives the data corresponding to the data reading request returned by the PCIe, sending interruption information to a CPU (Central Processing Unit) at the host side, so that the CPU reads the data corresponding to the destination address. According to the embodiment of the invention, the target data can be correctly and completely read from the destination address by the CPU through the cooperation of a software level and a hardware level, and the integrity and correctness of data transmission are ensured.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data processing, and in particular, to a data transmission method, apparatus, system, and storage medium. Background Art

[0002] In a computer system, data transmission between the device side and the host side is usually performed through direct memory access (DMA). During the data transmission process, data is communicated through a peripheral component interconnect express (PCIe) bus. The use of DMA can significantly improve the data transmission speed and system efficiency. At the same time, as the underlying transmission channel, PCIe provides reliable high-speed data transmission capabilities. However, in the scenario where DMA writes data from the device side to the host side through PCIe, after DMA receives the completion reply for the write data request sent by PCIe, it will consider the data transmission completed and report an interruption to the central processing unit (CPU) on the host side. However, at this time, the data may not have been written into the system memory on the host side, and there is a situation where DMA reports an interruption to the host side in advance, resulting in the CPU on the host side being unable to read the correct data from the system memory. Summary of the Invention

[0003] In view of this, the present disclosure provides a data transmission method, apparatus, system, and storage medium.

[0004] According to an aspect of the present disclosure, a data transmission method is provided. The method is used for direct memory access (DMA) on the device side, and the device side is connected to the host side through a peripheral component interconnect express (PCIe) bus. The method includes:

[0005] DMA receives a descriptor, where the descriptor includes a source address, a destination address, and indication information;

[0006] DMA obtains target data corresponding to the source address in the descriptor, and sends the target data to PCIe, where PCIe is used to write the target data to the destination address;

[0007] When the target data has been sent to PCIe and the indication information in the descriptor is a preset value, DMA sends a read data request to PCIe;

[0008] When DMA receives the data corresponding to the read data request returned by PCIe, it sends interruption information to the central processing unit (CPU) on the host side, causing the CPU to read the data corresponding to the destination address.

[0009] In a possible implementation, the indication information is determined and configured based on the source address and the destination address.

[0010] In a possible implementation, when the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor is configured as a preset value.

[0011] In a possible implementation, when the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor is configured as a non-preset value or a default value.

[0012] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read the data corresponding to the reference address, where the reference address is determined by the DMA based on the destination address.

[0013] According to another aspect of the present disclosure, a data transmission device is provided. The device is used for direct memory access (DMA) on the device side, and the device side is connected to the host side through a high-speed serial bus (PCIe). The device includes:

[0014] A receiving module, configured to receive a descriptor for the DMA, where the descriptor includes a source address, a destination address, and indication information;

[0015] A first sending module, configured to obtain, by the DMA, the target data corresponding to the source address in the descriptor and send the target data to the PCIe, where the PCIe is configured to write the target data to the destination address;

[0016] A second sending module, configured to send, by the DMA, a read data request to the PCIe when the target data has been sent to the PCIe and the indication information in the descriptor is a preset value;

[0017] A third sending module, configured to send, by the DMA, interrupt information to the central processing unit (CPU) on the host side when receiving the data corresponding to the read data request returned by the PCIe, so that the CPU reads the target data corresponding to the destination address.

[0018] In a possible implementation, the indication information is determined and configured based on the source address and the destination address.

[0019] In a possible implementation, when the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor is configured as a preset value.

[0020] In a possible implementation, when the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor is configured as a non-preset value or a default value.

[0021] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read the data corresponding to the reference address, where the reference address is determined by the DMA based on the destination address.

[0022] According to another aspect of the present disclosure, a data transmission system is provided. The system includes a device side and a host side, and the device side and the host side are connected through a high-speed serial bus PCIe.

[0023] The direct memory access (DMA) on the device side is configured to:

[0024] Receive a descriptor, where the descriptor includes a source address, a destination address, and indication information;

[0025] Obtain the target data corresponding to the source address in the descriptor and send the target data to the PCIe;

[0026] When the target data has been sent to the PCIe and the indication information in the descriptor is a preset value, send a read data request to the PCIe;

[0027] When receiving the data corresponding to the read data request returned by the PCIe, send interrupt information to the central processing unit (CPU) on the host side;

[0028] The CPU is configured to:

[0029] In response to receiving the interrupt information, read the target data corresponding to the destination address;

[0030] The PCIe is configured to:

[0031] Write the target data to the destination address.

[0032] In a possible implementation, the indication information is determined and configured based on the source address and the destination address.

[0033] In a possible implementation, when the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor is configured as a preset value.

[0034] In a possible implementation, when the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor is configured as a non-preset value or a default value.

[0035] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read the data corresponding to the reference address, where the reference address is determined by the DMA based on the destination address.

[0036] According to another aspect of the present disclosure, there is provided a data transmission device, including: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0037] According to another aspect of the present disclosure, there is provided a non-volatile computer-readable storage medium, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0038] According to another aspect of the present disclosure, there is provided a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code, when the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0039] According to an embodiment of the present disclosure, the device-side DMA receives a descriptor and obtains target data corresponding to the source address in the descriptor, and sends the target data to the PCIe, where the PCIe is used to write the target data to the destination address, the descriptor includes a source address, a destination address, and indication information, the DMA sends a read data request to the PCIe when the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, and the DMA sends interrupt information to the CPU on the host side when receiving the data corresponding to the read data request returned by the PCIe, so that the CPU reads the data corresponding to the destination address, utilizes the characteristics of the PCIe, realizes the cooperation at the software level (adding a field of indication information in the descriptor) and the hardware level (the DMA automatically sends a read data request based on the newly added indication information field), enables the target data to be correctly and completely read by the CPU on the host side from the destination address, ensures the integrity and correctness of data transmission, and makes the data transmitted on the device side and the data read by the CPU on the host side consistent.

[0040] According to the following detailed description of exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are included in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the present disclosure together with the specification, and are used to explain the principles of the present disclosure.

[0042] Figure 1 A structural diagram showing a data transmission system according to an embodiment of the present disclosure.

[0043] Figure 2 A flowchart showing a data transmission method according to an embodiment of the present disclosure.

[0044] Figure 3Schematic diagram showing a descriptor according to an embodiment of the present disclosure.

[0045] Figure 4 Structural diagram showing a data transmission device according to an embodiment of the present disclosure.

[0046] Figure 5 Block diagram of a device 1900 for data transmission shown according to an exemplary embodiment. Detailed implementation

[0047] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0048] The term "exemplary" used herein means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" herein is not necessarily to be construed as superior or better than other embodiments.

[0049] In addition, for a better description of the present disclosure, numerous specific details are given in the following detailed implementation. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0050] In a computer system, data transfer between the device side and the host side is usually performed through direct memory access (DMA). During the data transfer process, data is communicated through a peripheral component interconnect express (PCIe) bus. The use of DMA can significantly improve the data transfer speed and system efficiency. At the same time, as the underlying transfer channel, PCIe provides reliable high-speed data transfer capabilities. However, in the scenario where DMA writes data from the device side to the host side through PCIe, after DMA receives the completion reply for the write data request sent by PCIe, it will consider the data transfer completed and report an interrupt to the central processing unit (CPU) on the host side. However, at this time, the data may not have been written into the system memory on the host side, and there may be a situation where DMA reports an interrupt to the host side in advance, resulting in the CPU on the host side being unable to read the correct data from the system memory.

[0051] In view of this, the present disclosure provides a data transmission method, apparatus, system, and storage medium. In the method according to an embodiment of the present disclosure, a DMA on the device side receives a descriptor and obtains target data corresponding to a source address in the descriptor, and sends the target data to PCIe, where PCIe is used to write the target data to a destination address. The descriptor includes a source address, a destination address, and indication information. When the target data has been sent to PCIe and the indication information of the descriptor is a preset value, the DMA sends a read data request to PCIe. When the DMA receives the data corresponding to the read data request returned by PCIe, the DMA sends interrupt information to the CPU on the host side, causing the CPU to read the data corresponding to the destination address. By utilizing the characteristics of PCIe, the cooperation between the software level (adding a field of indication information in the descriptor) and the hardware level (the DMA automatically sends a read data request based on the added field of indication information) is achieved, so that the target data can be correctly and completely read by the CPU on the host side from the destination address, ensuring the integrity and correctness of data transmission, and making the data transmitted on the device side consistent with the data read by the CPU on the host side.

[0052] Figure 1 FIG. shows a structural diagram of a data transmission system according to an embodiment of the present disclosure. The data transmission system according to an embodiment of the present disclosure may include a device side (Device side) and a host side (Host side). As Figure 1 shown, the device side may include a DMA and device-side memory (Device Memory), and the device-side memory is a memory or buffer on the device side; the host side may include a CPU and system memory (System Memory), and the system memory can be used to store data and programs of a computer system. The host side and the device side can perform data transmission and communication through PCIe.

[0053] Among them, the host side may be a terminal device or a server. The terminal device may be any one or more of a mobile phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), a vehicle-mounted device, etc.; the server may be a physical device.

[0054] The device side may be an external device or an expansion card connected to the host, such as an image capture card, a network adapter, a graphics card, a storage controller, etc.

[0055] The data transmission method according to an embodiment of the present disclosure can be applied to Figure 1 the data transmission system shown to implement data transmission between the device side and the host side. The following is throughFigure 2 , an introduction to the data transmission method of the embodiments of the present disclosure will be given.

[0056] Figure 2 A flowchart showing the data transmission method according to the embodiments of the present disclosure is shown. This method can be used for DMA on the device side, such as Figure 2 As shown, this method may include:

[0057] Step S201, the DMA receives a descriptor.

[0058] The descriptor may include a source address, a destination address, and indication information. The descriptor may be configured by a driver on the device side and sent to the DMA. Among them, the driver may configure the descriptor after receiving a data transmission request from the upper layer (such as the application layer or the protocol stack) (such as indicating that data is to be written from the device side to the host side).

[0059] Figure 3 A schematic diagram showing the descriptor according to the embodiments of the present disclosure is shown. As Figure 3 shown, the descriptor may include a source address (such as src_address in the figure), a destination address (such as dst_address in the figure), and indication information (such as trans_dir in the figure). The DMA may generate a write data request according to the descriptor, indicating to read the target data at the source address and write the target data to the destination address.

[0060] Among them, the indication information is determined and configured based on the source address and the destination address. When the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor may be configured as a preset value (such as 1), indicating that the transmission direction of the target data is from the device side to the host side; when the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor may be configured as a non-preset value (such as 0) or a default value, indicating that the transmission direction of the target data is from the host side to the device side. The descriptor may also include the size of the target data (such as trans_size in the figure, such as 1G).

[0061] In the embodiments of the present disclosure, by adding new indication information to the descriptor, the subsequent DMA can also automatically generate a read data request according to the indication information after sending the target data to the PCIe based on the descriptor (without the driver configuring the descriptor again), realizing the cooperation between software and hardware to ensure the consistency of data transmission and reading.

[0062] Step S202, the DMA obtains the target data corresponding to the source address in the descriptor and sends the target data to the PCIe.

[0063] The DMA on the device side can retrieve the target data from the source address according to the descriptor and send the target data to the PCIe, which can be used to write the target data to the destination address.

[0064] In a possible implementation, the source address in the descriptor is the address of the device-side memory, the destination address is the address of the system memory on the host side, the indication information is 1, the size of the target data is 1G, the DMA can retrieve 1G of target data from the address of the device-side memory and send it to the PCIe, and the PCIe can receive the target data and write the target data to the address of the system memory on the host side.

[0065] Among them, after the PCIe receives the target data sent by the DMA, it will usually directly send a reply to the DMA indicating that the target data has been received. When the DMA receives the reply sent by the PCIe, it will consider that the target data has been transferred successfully. However, at this time, the target data may not have been written to the destination address (such as the system memory). If the DMA considers that the data has been transferred successfully and reports an interruption to the CPU on the host side, the CPU cannot read the correct data from the destination address. To prevent the above situation from occurring, in the embodiments of the present disclosure, the DMA can, according to the indication information in the descriptor, when the indication information is a preset value, automatically generate a read data request without the need for the device-side driver to configure the descriptor, and ensure that all target data has been written to the system memory on the host side before the DMA sends the interruption information through a combination of software (adding a new indication information in the descriptor) and hardware (when the indication information in the descriptor is a preset value, the DMA generates a read data request), as described below.

[0066] Step S203, when the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, the DMA sends a read data request to the PCIe.

[0067] The read data request sent by the DMA to the PCIe can be used to read the data corresponding to the reference address, where the reference address can be determined by the DMA based on the destination address. For example, the read data request that the DMA can send to the PCIe can be used to read the data of the same size as the target data in the destination address, or can be used to read more or less data than the target data. For example, the destination address in the descriptor is the address of the system memory on the host side, the indication information is 1, the size of the target data is 1G, the read data request can be used to read the 1G of data in the address of the system memory on the host side. At this time, the reference address is the destination address, and the read data request can also be used to only read less than 1G of data (such as one or more bits) in the address of the system memory on the host side. At this time, the reference address can be a partial address in the destination address, thereby saving the data transfer volume during the read data process.

[0068] Step S204, when the DMA receives the data corresponding to the read data request returned by the PCIe, it sends interrupt information to the CPU on the host side, causing the CPU to read the data corresponding to the destination address.

[0069] In the present disclosure, the characteristics of the PCIe are utilized, that is, the read data request of the PCIe will not start until all the write data requests before the read data request are completed. Therefore, in the present disclosure, by generating and sending a read data request to the PCIe by the DMA according to the indication information in the descriptor, when the read data request is completed (that is, when the DMA receives the data corresponding to the read data request returned by the PCIe), it means that all the write data requests before the read data request have been completed, so that it can be ensured that the target data has been written into the system memory on the host side.

[0070] The interrupt information can be used to request the attention of the CPU and cause the CPU to pause the currently executing task and instead process the task where the interrupt event occurs. In the present disclosure, the task where the interrupt event occurs can be implemented based on the target data written to the destination address. The CPU can read the corresponding data from the destination address and execute the corresponding task after receiving the interrupt information.

[0071] The generation method of the interrupt information can be implemented based on the prior art, and the present application does not limit this.

[0072] According to the embodiments of the present disclosure, the DMA on the device side receives the descriptor and obtains the target data corresponding to the source address in the descriptor, and sends the target data to the PCIe, where the PCIe is used to write the target data to the destination address. The descriptor includes the source address, the destination address, and the indication information. When the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, the DMA sends a read data request to the PCIe. When the DMA receives the data corresponding to the read data request returned by the PCIe, it sends interrupt information to the CPU on the host side, causing the CPU to read the data corresponding to the destination address. By utilizing the characteristics of the PCIe, the cooperation at the software level (adding a field of indication information in the descriptor) and the hardware level (the DMA automatically sends a read data request based on the newly added field of indication information) is realized, so that the target data can be correctly and completely read by the CPU on the host side from the destination address, ensuring the integrity and correctness of data transmission, and making the data transmitted on the device side and the data read by the CPU on the host side consistent.

[0073] The method may further include: when the target data has been sent to the PCIe and the indication information of the descriptor is a non-preset value or a default value, the DMA sends interrupt information to the CPU on the host side, causing the CPU to read the data corresponding to the destination address.

[0074] At this time, the source address may not be the address of the device-side memory, or the destination address may be the address of the system memory on the host side, and the DMA may no longer need to generate a read data request.

[0075] Figure 4 The structural diagram of a data transmission device according to an embodiment of the present disclosure is shown. The device is used for direct memory access (DMA) on the device side, and the device side is connected to the host side through a high-speed serial bus PCIe, as Figure 4 shown. The device includes:

[0076] A receiving module 401, configured to receive a DMA descriptor, where the descriptor includes a source address, a destination address, and indication information;

[0077] A first sending module 402, configured to obtain target data corresponding to the source address in the descriptor by the DMA, and send the target data to the PCIe, where the PCIe is configured to write the target data to the destination address;

[0078] A second sending module 403, configured to send a read data request to the PCIe when the target data has been sent to the PCIe and the indication information in the descriptor is a preset value;

[0079] A third sending module 404, configured to send interrupt information to the central processing unit (CPU) on the host side when the DMA receives the data corresponding to the read data request returned by the PCIe, so that the CPU reads the target data corresponding to the destination address.

[0080] In a possible implementation, the indication information is determined and configured based on the source address and the destination address.

[0081] In a possible implementation, when the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor is configured as a preset value.

[0082] In a possible implementation, when the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor is configured as a non-preset value or a default value.

[0083] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read the data corresponding to the reference address, where the reference address is determined by the DMA based on the destination address.

[0084] According to an embodiment of the present disclosure, the DMA on the device side receives a descriptor and obtains the target data corresponding to the source address in the descriptor, and sends the target data to the PCIe, where the PCIe is used to write the target data to the destination address. The descriptor includes a source address, a destination address, and indication information. When the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, the DMA sends a read data request to the PCIe. When the DMA receives the data corresponding to the read data request returned by the PCIe, the DMA sends an interrupt message to the CPU on the host side, causing the CPU to read the data corresponding to the destination address. By utilizing the characteristics of the PCIe, the cooperation at the software level (adding a field of indication information in the descriptor) and the hardware level (the DMA automatically sends a read data request based on the newly added indication information field) is achieved, enabling the target data to be correctly and completely read by the CPU on the host side from the destination address, ensuring the integrity and correctness of data transmission, and making the data transmitted on the device side consistent with the data read by the CPU on the host side.

[0085] An embodiment of the present disclosure also proposes a data transmission system. The system includes a device side and a host side, and the device side and the host side are connected through a high-speed serial bus PCIe.

[0086] The direct memory access (DMA) on the device side is used for:

[0087] Receiving a descriptor, where the descriptor includes a source address, a destination address, and indication information;

[0088] Obtaining the target data corresponding to the source address in the descriptor and sending the target data to the PCIe;

[0089] When the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, sending a read data request to the PCIe;

[0090] When receiving the data corresponding to the read data request returned by the PCIe, sending an interrupt message to the central processing unit (CPU) on the host side;

[0091] The CPU is used for:

[0092] In response to receiving the interrupt message, reading the target data corresponding to the destination address;

[0093] The PCIe is used for:

[0094] Writing the target data to the destination address.

[0095] In a possible implementation manner, the indication information is determined and configured based on the source address and the destination address.

[0096] In a possible implementation, when the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor is configured as a preset value.

[0097] In a possible implementation, when the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor is configured as a non-preset value or a default value.

[0098] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read the data corresponding to the reference address, where the reference address is determined by the DMA based on the destination address.

[0099] According to the embodiments of the present disclosure, the DMA on the device side receives the descriptor and obtains the target data corresponding to the source address in the descriptor, and sends the target data to the PCIe. The PCIe is used to write the target data to the destination address. The descriptor includes the source address, the destination address, and the indication information. When the target data has been sent to the PCIe and the indication information of the descriptor is the preset value, the DMA sends a read data request to the PCIe. When the DMA receives the data corresponding to the read data request returned by the PCIe, it sends an interrupt message to the CPU on the host side, causing the CPU to read the data corresponding to the destination address. By utilizing the characteristics of the PCIe, the cooperation between the software level (adding a field of indication information in the descriptor) and the hardware level (the DMA automatically sends a read data request based on the newly added indication information field) is achieved, so that the target data can be correctly and completely read by the CPU on the host side from the destination address, ensuring the integrity and correctness of data transmission, and making the data transmitted on the device side consistent with the data read by the CPU on the host side.

[0100] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0101] The embodiments of the present disclosure also propose a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above methods are implemented. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0102] The embodiments of the present disclosure also propose a data transmission device, including: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to implement the above methods when executing the instructions stored in the memory.

[0103] Embodiments of the present disclosure also provide a computer program product, including computer-readable code or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0104] Figure 5 FIG. 4 is a block diagram of an apparatus 1900 for data transmission according to an exemplary embodiment. For example, the apparatus 1900 may be provided as a server or a terminal device. Referring to Figure 5 FIG. 4, the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by a memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in the memory 1932 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0105] The apparatus 1900 may also include a power component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input / output interface (I / O interface) 1958. The apparatus 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server TM , MacOS X TM , Unix TM , Linux TM , FreeBSD TM or the like.

[0106] In an exemplary embodiment, there is also provided a non-volatile computer-readable storage medium, such as the memory 1932 including computer program instructions, and the above computer program instructions can be executed by the processing component 1922 of the apparatus 1900 to complete the above method.

[0107] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0108] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example—but not limited to—an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium as used herein is not construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0109] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or can be downloaded to an external computer or an external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include a copper transmission cable, an optical fiber transmission, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0110] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine - related instructions, microcode, firmware instructions, state - setting data, or source code or object code written in any combination of one or more programming languages, including object - oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer - readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand - alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, by using the state information of the computer - readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field - programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer - readable program instructions to implement various aspects of the present disclosure.

[0111] Aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer - readable program instructions.

[0112] These computer - readable program instructions can be provided to a processor of a general - purpose computer, a special - purpose computer, or other programmable data - processing apparatus to produce a machine such that when the instructions are executed by the processor of the computer or other programmable data - processing apparatus, a device is produced that implements the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer - readable program instructions can also be stored in a computer - readable storage medium, which causes a computer, a programmable data - processing apparatus, and / or other devices to operate in a particular manner, so that the computer - readable medium storing the instructions includes a manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0113] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0114] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of code, or a portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special-purpose hardware-based systems that perform the specified functions or acts, or by combinations of special-purpose hardware and computer instructions.

[0115] The embodiments of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A data transmission method, characterized in that The method is used for direct memory access (DMA) on the device side. The device side is connected to the host side through a high-speed serial bus, PCIe. The method includes: The DMA receives a descriptor, which includes a source address, a destination address, and indication information; The DMA obtains the target data corresponding to the source address in the descriptor and sends the target data to the PCIe, which is used to write the target data to the destination address; When the target data has been sent to the PCIe and the indication information in the descriptor is a preset value, the DMA sends a read data request to the PCIe; When the DMA receives the data corresponding to the read data request returned by the PCIe, the DMA sends interrupt information to the central processing unit (CPU) on the host side, causing the CPU to read the data corresponding to the destination address.

2. The method according to claim 1, characterized in that, The indication information is determined and configured based on the source address and the destination address.

3. The method according to claim 2, wherein When the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor is configured as the preset value.

4. The method according to claim 2, characterized in that, When the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor is configured as a non-preset value or a default value.

5. The method according to claim 2, characterized in that, The read data request sent by the DMA to the PCIe is used to read the data corresponding to a reference address, where the reference address is determined by the DMA based on the destination address.

6. A data transmission device, characterized in that, The apparatus is used for direct memory access (DMA) on the device side. The device side is connected to the host side through a high-speed serial bus, PCIe. The apparatus includes: A receiving module, configured to receive, by the DMA, a descriptor, which includes a source address, a destination address, and indication information; A first sending module, configured to obtain, by the DMA, the target data corresponding to the source address in the descriptor and send the target data to the PCIe, where the PCIe is used to write the target data to the destination address; A second sending module, configured to send, by the DMA, a read data request to the PCIe when the target data has been sent to the PCIe and the indication information in the descriptor is the preset value; A third sending module, configured to send, by the DMA, interrupt information to the central processing unit (CPU) on the host side when the DMA receives the data corresponding to the read data request returned by the PCIe, causing the CPU to read the target data corresponding to the destination address.

7. A data transmission system, characterized in that, The system includes a device side and a host side. The device side and the host side are connected through a high-speed serial bus, PCIe. The direct memory access (DMA) on the device side is used to: Receive a descriptor, which includes a source address, a destination address, and indication information; Obtain the target data corresponding to the source address in the descriptor and send the target data to the PCIe; Send a read data request to the PCIe when the target data has been sent to the PCIe and the indication information in the descriptor is the preset value; When receiving the data corresponding to the read data request returned by the PCIe, send interrupt information to the central processing unit (CPU) on the host side; The CPU is configured to: In response to receiving the interrupt information, read the target data corresponding to the destination address; The PCIe is configured to: Write the target data to the destination address.

8. The system according to claim 7, wherein The indication information is determined and configured based on the source address and the destination address.

9. The system according to claim 8, characterized in that, When the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor is configured as the preset value.

10. The system according to claim 8, wherein When the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor is configured as a non-preset value or a default value.

11. A data transmission device, characterized in that, Comprising: A processor; A memory for storing processor-executable instructions; Wherein, the processor is configured to implement the method according to any one of claims 1 to 5 when executing the instructions stored in the memory.

12. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, the method according to any one of claims 1 to 5 is implemented.

13. A computer program product, comprising a computer program, or a non-volatile computer-readable storage medium carrying the computer program, characterized in that, When the computer program is executed by the processor, the method according to any one of claims 1 to 5 is implemented.

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