Model determination system and method, electronic equipment, storage medium and product

Abstract

The invention discloses a model determination system and method, an electronic device, a storage medium and a product, and relates to the technical field of server systems, the system comprises a first control module, a second control module, a first multiplexing module, a second multiplexing module and a plurality of serial communication devices deployed on a graphic processing module; the first control module and the second control module respectively output two buses, the buses are respectively connected with the first multiplexing module and the second multiplexing module, and the second control module is used for acquiring the address of the serial communication equipment and the model of the graphic processing module; the first multiplexing module and the second multiplexing module respectively output a bus to be connected with a plurality of serial communication devices on the graphic processing module, and device addresses are stored on the serial communication devices, so that the technical problems that additional materials and production processes are needed and the cost is increased in a related scheme are solved, and the purposes that additional materials and production processes are not needed, and the cost is reduced are achieved. And the cost increase is avoided.

Description

Technical Field

[0001] This application relates to the technical field of server systems, and particularly to a model determination system, method, electronic device, storage medium, and product. Background Art

[0002] In the context of the rapid development of current artificial intelligence servers, as an important expansion module for hosting high-performance computing units, the model identification and management logic configuration of the graphics processing module have become a key link in system design.

[0003] In related model determination solutions, the model of the graphics processing module is usually determined by a derivative hardware board or an external plug-in cable, which requires additional materials and production processes, resulting in increased costs. Summary of the Invention

[0004] This application provides a model determination system, method, electronic device, storage medium, and product to at least solve the problem in related technologies that determining the model of the graphics processing module by a derivative hardware board or an external plug-in cable requires additional materials and production processes, resulting in increased costs.

[0005] This application provides a model determination system, including: A first control module, a second control module, a first multiplexing module, a second multiplexing module, and multiple serial communication devices deployed on the graphics processing module; The first control module and the second control module respectively output two buses, and the buses are respectively connected to the first multiplexing module and the second multiplexing module. The first control module is used to control the power-on of the graphics processing module, and the second control module is used to obtain the addresses of the serial communication devices and the model of the graphics processing module; The first multiplexing module and the second multiplexing module respectively output one bus to be connected to multiple serial communication devices on the graphics processing module. The first multiplexing module is used to switch the connection line with the first serial communication device among multiple serial communication devices, and the second multiplexing module is used to switch the connection line with the second serial communication device among multiple serial communication devices; Device addresses are stored on the serial communication devices.

[0006] This application provides a model determination method, including: In response to the completion of the loading of the second control module, obtain a control signal; Using the control signal, control the first multiplexing module and the second multiplexing module to switch to a first target connection line, where the first target connection line is the connection line between the second control module and multiple serial communication devices; Determine the addresses of the serial communication devices using the first target connection line; Determine the graphics processing module model according to the mapping relationship between the addresses of the serial communication devices and the graphics processing module models.

[0007] This application also provides a model determination device, including: An acquisition unit, configured to acquire a control signal in response to the completion of the loading of the second control module; A control unit, configured to use the control signal to control the first multiplexing module and the second multiplexing module to switch to a first target connection line, where the first target connection line is the connection line between the second control module and multiple serial communication devices; A first determination unit, configured to determine the addresses of the serial communication devices by using the first target connection line; A second determination unit, configured to determine the graphics processing module model according to the mapping relationship between the addresses of the serial communication devices and the graphics processing module models.

[0008] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of the above-mentioned model determination method when executing the computer program.

[0009] This application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned model determination method are implemented.

[0010] This application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned model determination method are implemented.

[0011] Through this application, it includes a first control module, a second control module, a first multiplexing module, a second multiplexing module, and multiple serial communication devices deployed on the graphics processing module; the first control module and the second control module respectively output two buses, and the buses are respectively connected to the first multiplexing module and the second multiplexing module, and the second control module is configured to acquire the addresses of the serial communication devices and the models of the graphics processing modules; the first multiplexing module and the second multiplexing module respectively output one bus to be connected to the multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, which solves the technical problem in the related solutions that additional materials and production processes are required, increasing the cost, and achieves the technical effect of not requiring additional materials and production processes and avoiding cost increase. Description of the Drawings

[0012] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 The structural schematic diagram of a model determination system provided by an embodiment of the present application; Figure 2 The structural schematic diagram of a model determination system provided by an embodiment of the present application; Figure 3 The flowchart of a model determination method provided by an embodiment of the present application; Figure 4 The flowchart of a model matching provided by an embodiment of the present application; Figure 5 The flowchart of a server power-on process provided by an embodiment of the present application; Figure 6 The structural schematic diagram of a model determination device provided by an embodiment of the present application. Detailed implementation manners

[0014] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0015] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To facilitate better understanding of the technical solutions described in the embodiments of the present disclosure by those skilled in the art, the following explanations are made for the technical terms in the embodiments of the present disclosure before introducing the embodiments of the present disclosure.

[0017] The Baseboard Management Controller (BMC) is used to manage and monitor the hardware of a server or other electronic devices. Specifically, it can monitor the temperature of each component inside the system in real time, including the Central Processing Unit (CPU), memory, storage devices, etc., and can also monitor and control the speed of the fan to maintain an appropriate cooling effect. It can also provide status monitoring of the power supply unit, including power input and output conditions, redundant power supply status, etc.

[0018] Complex Programmable Logic Device (CPLD): A CPLD is a programmable logic device that allows the implementation of digital circuit functions through software programming. It has a high degree of integration and flexibility and is suitable for application scenarios that require fast response times, such as signal processing, protocol conversion, etc.

[0019] Basic Input Output System (BIOS): The BIOS is firmware in a computer used to perform hardware initialization and provide runtime services for the operating system. It plays a crucial role in the computer startup process, responsible for detecting and initializing hardware components (such as hard disks, keyboards, mice, etc.) and loading the operating system.

[0020] General-Purpose Input / Output (GPIO): GPIO is used for communication between integrated circuits (such as microcontrollers, CPUs, etc.) and external devices. Through the GPIO interface, the chip can configure pins as input or output modes according to needs to achieve data reading or sending.

[0021] Graphics Processing Unit (GPU): A processor used to quickly process image and video data.

[0022] Graphics Processing Unit BOX (GPU BOX), a hardware unit used to accommodate one or more GPUs, for enhancing the computing power of servers or workstations. Usually, the module after deploying 8 GPUs on a general substrate is represented as the image processing module as the GPU BOX in this application.

[0023] Currently, with the rapid development of the information technology industry, the demand for servers in the industry is increasing. Especially in recent years, with the booming development of Artificial Intelligence (AI), the demand for AI servers has also increased significantly. AI servers used for large model training require very high performance. The Card Electromechanical Module (CEM) size cards of the traditional Peripheral Component Interconnect Express (PCIe) do not optimize in terms of AI workloads. These workloads require increasing bandwidth and the flexibility of data / model parallel interconnection. Therefore, the Open Accelerator Infrastructure (OAI) / Open Compute Project Accelerator Module (OAM) was born. Multiple OAM modules (usually 8) are paired with a Universal Baseboard (UBB) and combined with other necessary modules to form an AI server, which plays a key role in machine learning, deep learning, and high-performance computing.

[0024] In 2023, the OCP OAI organization launched the UBB2.0 specification and adopted the upstream (HGX) interface definition at the same time to normalize the GPU BOX interface, ensuring that GPU BOXes made by different manufacturers according to the UBB2.0 standard can be inserted and used interchangeably in terms of hardware compatibility, which can reduce the waste of manpower caused by the new development and design of boards due to adaptation during the R & D stage. Although the GPU BOXes are consistent in terms of interfaces, due to the internal circuits and functions not being clearly defined in the specification, there are significant differences in the internal circuit and function designs of different manufacturers. There are differences in the management schemes of different models of GPU BOXes, and there are also differences in the power-on sequence and power-on timeout alarm time, which pose great difficulties for the host (Host) to identify and manage the power-on of the GPU BOX.

[0025] The following briefly introduces two schemes for determining the GPU BOX model in related technologies: Scheme A: The UBB designed according to the UBB2.0 specification in Scheme A is designed according to the HGX interface specification. The server distinguishes different GPU BOXes mainly by using derivative hardware boards. By changing certain feature IDs of the boards and providing them to the BMC, BIOS, and CPLD, the recognition of different GPU BOXes is achieved, and corresponding logical management is carried out, such as the logical management of the power-on and power-off sequence control and the logical management of the power-on timeout timing.

[0026]

[0027] Table 1 Derived Hardware Board Model Determination Solution B: Solution B uses additional external plug-in cables to implement the BOM relationship binding between the cables and the GPU BOX. When different GPU BOXes are paired, corresponding cables need to be plugged in. The BMC, BIOS, and CPLD distinguish the GPU BOXes through different connection relationships of the cables, and then perform corresponding logical management.

[0028]

[0029] Table 2 External Plug-in Cable Model Determination The above solutions also have the following disadvantages: When identifying different models of GPU BOXes, a relatively large number of board part numbers need to be developed. The more GPU BOXes to be adapted, the more board part numbers will be generated, resulting in poor versatility. This poses great challenges to production and subsequent board maintenance, and it is very easy to cause material stagnation. Stagnant materials not only increase costs but also have a great impact on warehousing.

[0030] Binding the GPU BOX to the cable requires customizing multiple different cables for different GPU BOXes. A large number of cables not only increase the difficulty of material control but also raise production costs. In addition, an extra process of inserting the cable is required in production, and as the number of cables increases, the probability of inserting the wrong cable during production also increases, reducing the production qualification rate.

[0031] In summary, in the related GPU BOX model determination solutions, the model of the graphics processing module is usually determined by using derived hardware boards or external plug-in cables, which requires additional materials and production processes, resulting in increased costs.

[0032] Through this application, it includes a first control module, a second control module, a first multiplexing module, a second multiplexing module, and multiple serial communication devices deployed on the graphics processing module; the first control module and the second control module respectively output two buses, and the buses are respectively connected to the first multiplexing module and the second multiplexing module. The second control module is used to obtain the addresses of the serial communication devices and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus to be connected to the multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, solving the technical problem of additional materials and production processes in the related solutions and increasing costs, and achieving the technical effect of not requiring additional materials and production processes and avoiding cost increase.

[0033] In order to enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific implementation manners.

[0034] Figure 1The structural schematic diagram of a model determination system provided by an embodiment of the present disclosure.

[0035] As Figure 1 shown, the model determination system includes a first control module, a second control module, a first multiplexing module, a second multiplexing module, and a plurality of serial communication devices deployed on a graphics processing module; The first control module and the second control module respectively output two buses, and the buses are respectively connected to the first multiplexing module and the second multiplexing module. The first control module is used to control the power-on of the graphics processing module, and the second control module is used to obtain the addresses of the serial communication devices and the model of the graphics processing module; The first multiplexing module and the second multiplexing module respectively output a bus to be connected to a plurality of serial communication devices on the graphics processing module. The first multiplexing module is used to switch the connection line with the first serial communication device among the plurality of serial communication devices, and the second multiplexing module is used to switch the connection line with the second serial communication device among the plurality of serial communication devices; Device addresses are stored on the serial communication devices.

[0036] In some embodiments, the first output terminal of the first control module is connected to the first input terminal of the first multiplexing module, and the second output terminal of the first control module is connected to the first input terminal of the second multiplexing module; the first output terminal of the second control module is connected to the second input terminal of the first multiplexing module, and the second output terminal of the second control module is connected to the second input terminal of the second multiplexing module. The second control module is used to perform an address scan on the serial communication devices to obtain a target address, and the second control module is further used to determine the model of the graphics processing module corresponding to the target address according to the mapping relationship between the addresses of the serial communication devices and the model of the graphics processing module.

[0037] In some embodiments, the output terminal of the first multiplexing module is connected to the input terminal of the first serial communication device among the plurality of serial communication devices, and the output terminal of the second multiplexing module is connected to the input terminal of the second serial communication device among the plurality of serial communication devices.

[0038] In some embodiments, the first control module is usually the host-side BMC or the CPU controller, and is used to manage the graphics processing module during the normal operation stage of the system, such as power-on and power-off, status monitoring, etc.

[0039] In some embodiments, the second control module may include, but is not limited to, a CPLD, a Field-Programmable Gate Array (FPGA), or a Microcontroller Unit (MCU), and is used to perform an address scan on the connected serial communication devices and identify the model of the graphics processing module during the system initialization stage.

[0040] In some embodiments, the first multiplexing module and the second multiplexing module refer to an Inter-Integrated Circuit (IIC) multiplexer chip (Multiplexer, MUX), which is used to select different IIC channels according to a control signal, thereby switching communication connection lines.

[0041] In some embodiments, the Graphics Processing Unit (GPU) module is used to host AI acceleration hardware such as the OAM module and the UBB board. Different manufacturers may design different internal circuits, but they need to be connected to the host through a unified interface; the serial communication device refers to a slave device that supports the serial communication protocol, which may include but is not limited to a temperature sensor and an Electrically Erasable Programmable Read-Only Memory (EEPROM).

[0042] In some embodiments, there may be multiple serial communication devices, but both the first multiplexing module and the second multiplexing module are at least connected to one serial communication device, and the device address of each serial communication device is unique.

[0043] Through the present application, it includes a first control module, a second control module, a first multiplexing module, a second multiplexing module, and multiple serial communication devices deployed on the graphics processing module; the first control module and the second control module respectively output two buses, and the buses are respectively connected to the first multiplexing module and the second multiplexing module. The second control module is used to obtain the addresses of the serial communication devices and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus to be connected to the multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, which solves the technical problem in the related solutions that additional materials and production processes are required, increasing costs, and achieves the technical effect of not requiring additional materials and production processes and avoiding cost increase.

[0044] In some embodiments, the model determination system further includes a Basic Input / Output System (BIOS), and the output end of the BIOS is connected to the second input end of the second control module. The BIOS is used to allocate resources of the graphics processing module.

[0045] In some embodiments, at the system startup stage, the BIOS identifies and allocates the hardware resources of the GPU BOX, such as memory addresses, interrupt requests, PCIe resources, etc., to ensure that it can be correctly loaded and used by the operating system.

[0046] In some embodiments, the BIOS can load the corresponding driver and resource policy according to the identified GPU BOX model, reducing manual configuration and improving the system's adaptability.

[0047] In some embodiments, the first multiplexing module and the second multiplexing module are connected to multiple serial communication devices through an upstream interface.

[0048] In some embodiments, the upstream interface refers to the HGX interface, and both the IIC MUX 1 and the IIC MUX 2 are connected to the serial communication devices through the HGX interface.

[0049] In some embodiments, the first multiplexing module and the second multiplexing module are connected to multiple serial communication devices through an upstream interface, which can support multiple models of GPU BOXes to share a unified interface.

[0050] In some embodiments, the first multiplexing module and the second multiplexing module are used to switch the connection lines to the serial communication devices according to a control signal, and the control signal is determined by a general-purpose input / output signal output by the second control module.

[0051] In some embodiments, the control signal is used to control which channel of the electrical signal is selected by the first multiplexing module and the second multiplexing module, and is usually determined by the state combination of several GPIO pins.

[0052] In some embodiments, the control signal is determined according to the general-purpose input / output signal. For example, when the GPIO is at a high level, the connection line to the serial communication device is switched to connection line two. Connection line two refers to the line between the second control module and the serial communication device. As Figure 1 shown, connection line two includes the routes where the second control module is connected to the first multiplexing module (IICMUX 1) and the second multiplexing module (IIC MUX 2). During power-on initialization, the CPLD can quickly access the serial communication devices on the GPU BOX. Exemplarily, multiple EEPROM chips with IIC interfaces are deployed on the GPU BOX. The Host-side BMC and the motherboard CPLD each have a group of IIC control buses, and different controllers need to be used to access these IIC devices at different stages. Two IIC MUXs are used as connection line switching devices, and the CPLD outputs GPIO control signals for channel selection. The CPLD accesses multiple IIC devices on the GPU BOX through the IIC MUXs (IIC MUX 1, IIC MUX 2) respectively.

[0053] In some embodiments, the third output terminal of the first control module is connected to the first input terminal of the second control module, and the first control module is used to determine the power-on control logic corresponding to the model of the graphics processing module according to the model of the graphics processing module.

[0054] In some embodiments, after the model identification is completed, the CPLD controls the IIC MUX 1 and IIC MUX 2 to switch to connect to Line 1. The CPLD sends the identified GPU BOX model to the Host-side BMC through a Universal Asynchronous Receiver (UART), GPIO, or Serial Peripheral Interface (SPI). The Host-side BMC controls the subsequent communication, and the BMC loads the corresponding driver program and power management policy according to the model.

[0055] In some embodiments, it refers to a specific power-on action sequence designed for different models of GPU BOX, including power supply timing, delay control, status monitoring, timeout judgment, etc., to ensure the safe startup of the device.

[0056] In some embodiments, such as Figure 2 shown, Figure 2 As shown in the figure, it is a schematic structural diagram of a model determination system provided by an embodiment of the present application, including a Host-side BMC, a motherboard CPLD, an IIC MUX 1, an IIC MUX 2, a GPU BOX, and several IIC devices. The Host-side BMC and the motherboard CPLD respectively connect out 2 IIC buses. Among them, the IIC bus path connected out by the Host-side BMC is defined as Line 1, and the IIC bus path connected out by the motherboard CPLD is defined as Line 2; the inputs of the IIC MUX 1 and the IIC MUX 2 are respectively connected to the IIC buses connected out by the Host-side BMC and the motherboard CPLD, and the output IIC buses are connected to the GPU BOX, and at least one IIC device is connected to the two IIC buses connected to the GPU BOX; the channel selection of the IIC MUX 1 and the IIC MUX 2 is controlled by the GPIO signal output by the motherboard CPLD.

[0057] The embodiments of the present disclosure also provide a model determination method.

[0058] In some embodiments, such as Figure 3 shown, Figure 3 As shown in the figure, it is a schematic flowchart of a model determination method provided by an embodiment of the present application. The method includes the following steps: Step 301, in response to the completion of the loading of the second control module, obtain a control signal; In some embodiments, after the AC power of the server is connected, the second control module can quickly complete the firmware loading and start working. The CPLD starts to prepare to execute the tasks in the initialization phase. The CPLD outputs a group of GPIO control signals, such as GPIO being 1 to control the IIC MUX 1 and the IIC MUX 2 to select the connection line.

[0059] In some embodiments, the control signal refers to a signal determined by the general-purpose input / output pins of the second control module, and the high level and the low level respectively control different connection routes.

[0060] Step 302: Using the control signal, control the first multiplexing module and the second multiplexing module to switch to the first target connection line, where the first target connection line is the connection line between the second control module and multiple serial communication devices; In some embodiments, the first target connection line is the line through which the CPLD connects to the serial communication devices on the GPU BOX via the IIC MUX. Specifically, IIC MUX 1 selects the IIC2 bus controlled by the CPLD; IIC MUX 2 selects the IIC2 bus controlled by the CPLD, and the CPLD can directly access all the serial communication devices on the GPU BOX.

[0061] Step 303: Determine the addresses of the serial communication devices using the first target connection line; In some embodiments, using the first target connection line, the CPLD respectively scans the devices on the two IIC buses of the GPU BOX. For example, IIC1 scans device addresses 0x21 and 0x24, and IIC2 scans device addresses 0x50 and 0x70.

[0062] Step 304: Determine the graphics processing module model according to the mapping relationship between the addresses of the serial communication devices and the graphics processing module model.

[0063] In some embodiments, the mapping relationship between the addresses of the serial communication devices and the graphics processing module model can be embodied in the form of a mapping table or in the form of a mapping array. This application does not limit this. Exemplarily, as shown in Table 3, Table 3 is an IIC device table for adapting to the GPU BOX in an embodiment of this application. The table gives the GPUBOX IIC device addresses, including the device addresses of IIC1 and IIC2, the model of the GPU BOX, the corresponding feature identifier (Identity Document, ID) for each model, the management logic and the power-on timeout time corresponding to each GPU BOX model.

[0064]

[0065] Table 3 IIC Device Table for Adapting to GPU BOX In some embodiments, the main board CPLD scans the devices on two IIC buses of the GPU BOX respectively. After IIC1 scans device addresses 0x21 and 0x24, and IIC2 scans device addresses 0x50 and 0x70, according to the mapping relationship in Table 3 above, the main board CPLD matches this as a GPU BOX of model A, with the corresponding feature ID being ID 1. The power-on timing control is performed using management logic 1, and the power-on timeout is 30 seconds.

[0066] In some embodiments, by responding to the completion of the loading of the second control module, a control signal is obtained; using the control signal, the first multiplexing module and the second multiplexing module are controlled to switch to the first target connection line, where the first target connection line is the connection line between the second control module and multiple serial communication devices; the address of the serial communication device is determined using the first target connection line; according to the mapping relationship between the address of the serial communication device and the graphics processing module model, the graphics processing module model is determined, which can complete model identification at the initial stage of system power-on, improve the startup efficiency, and only need to update the mapping relationship between the address of the serial communication device and the graphics processing module model to adapt to new GPU BOX types, achieving multi-model adaptation.

[0067] In some embodiments, the address of the serial communication device includes the address of the first serial communication device and the address of the second serial communication device: Determining the graphics processing module model according to the mapping relationship between the address of the serial communication device and the graphics processing module model includes: Determining the graphics processing module model according to the mapping relationship of the address of the first serial communication device, the address of the second serial communication device, and the graphics processing module model.

[0068] In some embodiments, it is necessary to combine the address of the first serial communication device and the address of the second serial communication device to determine the graphics processing module model. Taking the GPU BOX model A in Table 3 above as an example, if IIC1 scans device addresses 0x21 and 0x24, and IIC2 scans device addresses 0x60 and 0x80, the match is unsuccessful. In short, it is necessary for the device addresses of each serial communication device to match successfully to determine the corresponding GPU BOX model.

[0069] In some embodiments, by determining the graphics processing module model according to the mapping relationship of the address of the first serial communication device, the address of the second serial communication device, and the graphics processing module model, and using the combination of the addresses of multiple serial communication devices, it avoids misjudgment caused by a single address conflict and improves the recognition accuracy of the GPU BOX model.

[0070] In some embodiments, after determining the graphics processing module model according to the mapping relationship between the address of the serial communication device and the graphics processing module model, the model determination method further includes: Determine the feature identifier, power-on timeout duration, and power-on control logic corresponding to the graphics processing module model.

[0071] In some embodiments, the feature identifier is used to identify graphics processing modules of different models. The feature identifier can be a manufacturer code, device ID, address combination, etc., which is convenient for subsequent searching of configuration parameters.

[0072] In some embodiments, the power-on timeout duration refers to the maximum waiting time (e.g., 30 seconds) set by the system for the power-on process of the GPU BOX. If the power-on is not completed within this time, it is determined that the power-on fails.

[0073] In some embodiments, the power-on control logic refers to the specific operation steps such as the power sequence, delay control, and reset signal triggering required for the power-on operation of the GPU BOX. Exemplarily, the power-on control logic can be to synchronously turn on all power domains, delay for 100 ms, and start the reset signal.

[0074] In some embodiments, the CPLD sequentially controls each power domain of the GPU BOX according to the matched power-on control logic. A watchdog timer (such as 30 seconds) can be used. If the power-on is not completed within the specified time, a timeout alarm is triggered and an error log is recorded.

[0075] In some embodiments, by determining the power-on timeout duration corresponding to the graphics processing module model, resource waste caused by long-term unresponsiveness can be avoided.

[0076] In some embodiments, after matching the power-on timeout duration and the power-on control logic corresponding to the feature identifier, the model determination method includes: Control the first multiplexing module and the second multiplexing module to switch to the second target connection line, where the second target connection line is the connection line between the first control module and multiple serial communication devices.

[0077] In some embodiments, after the model matching is completed, the CPLD changes the GPIO output state. For example, if GPIO is 0, to switch IICMUX 1 and IIC MUX 2 to the second target connection line (corresponding to Figure 1 line 1 in the figure), and wait for the power-on instruction.

[0078] In some embodiments, the second target connection line is the connection line for the first control module (Host-side BMC) to control and access the internal serial communication device of the GPUBOX.

[0079] In some embodiments, after receiving the power-on instruction, the BMC on the Host side can access the serial communication device on the GPU BOX through the IIC bus to perform operations such as reading the firmware version information, obtaining the device health status, executing remote diagnostic commands, and starting the power-on action.

[0080] In some embodiments, by controlling the first multiplexing module and the second multiplexing module to switch to the second target connection line, the entire connection line switching process does not require manual intervention, which can improve the automation degree of the system.

[0081] In some embodiments, after controlling the first multiplexing module and the second multiplexing module to switch to the second target connection line, the model determination method includes: In response to receiving the power-on instruction, obtain the first power-on timestamp; In some embodiments, the power-on instruction refers to a startup command from the BMC on the Host side or the operating system, indicating that a power-on action needs to be performed on the GPU BOX or other graphics processing modules. The first power-on timestamp represents the time point when the power-on action starts and is used to calculate the duration of the power-on action.

[0082] The second control module performs power-on according to the power-on control logic; In some embodiments, the power-on control logic refers to the aforementioned power-on control logic corresponding to the GPU BOX model.

[0083] Obtain the second power-on timestamp; In some embodiments, the second power-on timestamp represents the time point when the power-on action is completed and is used to compare with the first timestamp to calculate the total duration.

[0084] Based on the second power-on timestamp, the first power-on timestamp, and the power-on timeout duration, determine the power-on result of the electronic device. The power-on result includes power-on completion and power-on timeout.

[0085] In some embodiments, the electronic device can be a server, a mobile device, an industrial control device, etc. In this application, the electronic device takes a server as an example.

[0086] In some embodiments, power-on completion means successfully completing all power-on actions within the specified time; power-on timeout means not completing within the specified time.

[0087] In some embodiments, determining the power-on result of the electronic device based on the second power-on timestamp, the first power-on timestamp, and the power-on timeout duration includes: Based on the second power-on timestamp and the first power-on timestamp, determine the power-on duration of the electronic device; In response to the power-on duration of the electronic device being greater than the power-on timeout duration and the electronic device being in the power-on state, determine that the electronic device has a power-on timeout; In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in the power-on state, continue to power on according to the power-on control logic; In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in the power-on completion state, determine that the power-on of the electronic device is completed.

[0088] In some embodiments, the power-on duration of the electronic device refers to the time actually used for the power-on operation, specifically the difference between the second timestamp and the first timestamp.

[0089] In some embodiments, the power-on state means that the power-on operation has not been completed and is still in progress.

[0090] In some embodiments, at the startup moment of the electronic device, obtain the first power-on timestamp, start to execute the power-on control logic, continuously monitor the current state and obtain the second timestamp, and determine whether it is completed or timed out.

[0091] In some embodiments, in response to the power-on duration of the electronic device being greater than the power-on timeout duration and the electronic device being in the power-on state, after determining that the power-on of the electronic device times out, the model determination method includes: Obtain the power-on timeout information of the electronic device; In some embodiments, the power-on timeout information of the electronic device refers to the information that the power-on operation has not been completed within the preset time, including the timeout duration, the current state, etc.

[0092] Generate an alarm message corresponding to the power-on timeout information of the electronic device and send it to the controller. The alarm message includes at least one of the graphics processing module model, the feature identifier of the graphics processing module, and the identifier of the power-on control logic.

[0093] In some embodiments, the alarm message is structured data for fault location, facilitating analysis and response by the remote management platform.

[0094] In some embodiments, by generating an alarm message corresponding to the power-on timeout information of the electronic device and sending it to the controller, which includes complete diagnostic information, it is convenient to quickly locate the root cause of the problem, support automatic reporting to the BMC, without manual intervention, and can achieve fault traceability and automated alarm.

[0095] In some embodiments, as Figure 4 shown, Figure 4A schematic flowchart of a model matching process provided by an embodiment of this application. After the AC power supply of the server is connected, the main board CPLD will quickly complete the loading and start working. At this time, the main board CPLD controls the IIC MUX 1 and IIC MUX 2 to switch to connection line 2. The main board CPLD scans the devices on the two IIC buses of the GPU BOX respectively. The IIC1 scans the device addresses 0x21 and 0x24, and the IIC2 scans the device addresses 0x50 and 0x70. The main board CPLD matches this as a GPU BOX of model A through table lookup, with the corresponding feature ID being ID 1, and uses management logic 1 for power-on timing control, and the power-on timeout is 30 seconds at the same time. After the matching is completed, the main board CPLD switches the IIC MUX 1 and IIC MUX 2 to connection line 1 and waits for the power-on instruction.

[0096] In some embodiments, as Figure 5 shown, Figure 5 A schematic flowchart of the server power-on process provided by an embodiment of this application. After receiving the power-on instruction, the main board CPLD executes the power-on control logic and synchronously starts the power-on timeout timing. The main board CPLD will monitor the server power-on status and the power-on timeout timing at the same time. If the server power-on status is completed before the power-on timeout timing expires, the server successfully completes the power-on of the entire system; if the server power-on status is not completed when the power-on timeout timing expires, the main board records the power-on timeout.

[0097] Through this application, it includes a first control module, a second control module, a first multiplexing module, a second multiplexing module, and multiple serial communication devices deployed on the graphics processing module; the first control module and the second control module respectively output two buses, and the buses are respectively connected to the first multiplexing module and the second multiplexing module. The second control module is used to obtain the addresses of the serial communication devices and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus to be connected to multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, solving the technical problem of additional materials and production processes in related solutions and increasing costs, and achieving the technical effect of avoiding additional materials and production processes and avoiding cost increase.

[0098] An embodiment of this application also provides a model determination device 600, Figure 6 A schematic structural diagram of a model determination device provided by an embodiment of this disclosure. As Figure 6 shown, it includes: An acquisition unit 601, configured to acquire a control signal in response to the completion of the loading of the second control module; A control unit 602, configured to use a control signal to control the first multiplexing module and the second multiplexing module to switch to a first target connection line, where the first target connection line is a connection line between a second control module and multiple serial communication devices; A first determination unit 603, configured to determine the address of a serial communication device by using the first target connection line; A second determination unit 604, configured to determine the graphics processing module model according to the mapping relationship between the address of the serial communication device and the graphics processing module model.

[0099] Further, in a possible implementation manner of the embodiment of the present disclosure, the address of the serial communication device includes the address of a first serial communication device and the address of a second serial communication device: Further, in a possible implementation manner of the embodiment of the present disclosure, the second determination unit 604 is configured to: Determine the graphics processing module model according to the mapping relationship between the address of the first serial communication device, the address of the second serial communication device, and the graphics processing module model.

[0100] Further, in a possible implementation manner of the embodiment of the present disclosure, the model determination device 600 includes a matching unit, and the matching unit is configured to: Determine a feature identifier, a power-on timeout duration, and a power-on control logic corresponding to the graphics processing module model.

[0101] Further, in a possible implementation manner of the embodiment of the present disclosure, the model determination device 600 includes a switching unit, and the switching unit is configured to: Control the first multiplexing module and the second multiplexing module to switch to a second target connection line, where the second target connection line is a connection line between a first control module and multiple serial communication devices.

[0102] Further, in a possible implementation manner of the embodiment of the present disclosure, the model determination device 600 includes a power-on result determination unit, and the power-on result determination unit is configured to: In response to receiving a power-on instruction, obtain a first power-on timestamp; The second control module is powered on according to the power-on control logic; Obtain a second power-on timestamp; Based on the second power-on timestamp, the first power-on timestamp, and the power-on timeout duration, determine the power-on result of the electronic device, where the power-on result includes power-on completion and power-on timeout.

[0103] Further, in a possible implementation manner of the embodiment of the present disclosure, the power-on result determination unit is further configured to: Based on the second power-on timestamp and the first power-on timestamp, determine the power-on duration of the electronic device; Determine that the power-on of the electronic device times out in response to the power-on duration of the electronic device being greater than the power-on timeout duration and the electronic device being in the power-on state; Continue to power on according to the power-on control logic in response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in the power-on state; Determine that the power-on of the electronic device is completed in response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in the power-off state.

[0104] Further, in a possible implementation manner of the embodiments of the present disclosure, the model determination device 600 includes an alarm information generation unit, and the alarm information generation unit is configured to: Obtain the power-on timeout information of the electronic device; Generate alarm information corresponding to the power-on timeout information of the electronic device and send it to the controller. The alarm information includes at least one of the graphics processing module model, the feature identifier of the graphics processing module, and the identifier of the power-on control logic.

[0105] Through this application, a first control module, a second control module, a first multiplexing module, a second multiplexing module, and multiple serial communication devices deployed on the graphics processing module; the first control module and the second control module respectively output two buses, and the buses are respectively connected to the first multiplexing module and the second multiplexing module. The second control module is used to obtain the addresses of the serial communication devices and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus and are connected to multiple serial communication devices on the graphics processing module. The device addresses are stored on the serial communication devices, which solves the technical problem of additional materials and production processes in related solutions and increases costs, and achieves the technical effect of avoiding additional materials and production processes and avoiding cost increase.

[0106] For the description of the features in the embodiments corresponding to the model determination device, reference can be made to the relevant descriptions in the embodiments corresponding to the model determination method, which will not be elaborated here one by one.

[0107] The embodiments of the present application further provide an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the embodiments of the above model determination method.

[0108] The embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any one of the embodiments of the above model determination method when running.

[0109] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM), random access memory (RAM), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0110] The embodiments of the present application also provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described method embodiments for determining the model.

[0111] The embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described method embodiments for determining the model.

[0112] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0113] The above has introduced in detail a model determination system, method, electronic device, storage medium, and product provided by the present application. Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A model determination system, characterized in that, Including: A first control module, a second control module, a first multiplexing module, a second multiplexing module, and multiple serial communication devices deployed on a graphics processing module; The first control module and the second control module respectively output two buses, and the buses are respectively connected to the first multiplexing module and the second multiplexing module. The first control module is used for power-on control of the graphics processing module, and the second control module is used for obtaining the addresses of the serial communication devices and the model of the graphics processing module; The first multiplexing module and the second multiplexing module respectively output one bus to be connected to the multiple serial communication devices on the graphics processing module. The first multiplexing module is used for switching the connection line with the first serial communication device among the multiple serial communication devices, and the second multiplexing module is used for switching the connection line with the second serial communication device among the multiple serial communication devices; Device addresses are stored on the serial communication devices.

2. The model determination system according to claim 1, characterized in that, The system further includes a basic input / output system, and the output end of the basic input / output system is connected to the second input end of the second control module. The basic input / output system is used for allocating resources of the graphics processing module.

3. The model determination system according to claim 1, characterized in that, The first multiplexing module and the second multiplexing module are connected to the multiple serial communication devices through an upstream interface.

4. The model determination system according to claim 1, characterized in that The first multiplexing module and the second multiplexing module are used for switching the connection lines with the serial communication devices according to a control signal, and the control signal is determined by a general input / output signal output by the second control module.

5. The model determination system according to claim 1, characterized in that The third output end of the first control module is connected to the first input end of the second control module. The first control module is used for determining the power-on control logic corresponding to the model of the graphics processing module according to the model of the graphics processing module.

6. A model determination method, characterized in that, The method is applied to a model determination system as described in any one of claims 1-5. The method includes: In response to the completion of loading of the second control module, obtaining a control signal; Using the control signal, controlling the first multiplexing module and the second multiplexing module to switch to a first target connection line, and the first target connection line is the connection line between the second control module and the multiple serial communication devices; Using the first target connection line to determine the addresses of the serial communication devices; According to the mapping relationship between the addresses of the serial communication devices and the model of the graphics processing module, determining the model of the graphics processing module.

7. The model determination method according to claim 6, wherein The addresses of the serial communication devices include the address of the first serial communication device and the address of the second serial communication device: According to the mapping relationship between the addresses of the serial communication devices and the model of the graphics processing module, determining the model of the graphics processing module includes: Determining the model of the graphics processing module according to the mapping relationship of the address of the first serial communication device, the address of the second serial communication device, and the model of the graphics processing module.

8. The model determination method according to claim 6, characterized in that After determining the model of the graphics processing module according to the mapping relationship between the addresses of the serial communication devices and the model of the graphics processing module, the method further includes: Determining the characteristic identifier, power-on timeout duration, and power-on control logic corresponding to the model of the graphics processing module.

9. The model determination method according to claim 8, characterized in that After matching the power-on timeout duration and power-on control logic corresponding to the feature identifier, the method includes: Controlling the first multiplexing module and the second multiplexing module to switch to a second target connection line, where the second target connection line is the connection line between the first control module and the multiple serial communication devices.

10. The model determination method according to claim 9, characterized in that After controlling the first multiplexing module and the second multiplexing module to switch to the second target connection line, the method includes: In response to receiving a power-on instruction, obtaining a first power-on timestamp; The second control module powers on according to the power-on control logic; Obtaining a second power-on timestamp; Based on the second power-on timestamp, the first power-on timestamp, and the power-on timeout duration, determining the power-on result of the electronic device, where the power-on result includes power-on completion and power-on timeout.

11. The model determination method according to claim 10, characterized in that The determining the power-on result of the electronic device based on the second power-on timestamp, the first power-on timestamp, and the power-on timeout duration includes: Based on the second power-on timestamp and the first power-on timestamp, determining the power-on duration of the electronic device; In response to the power-on duration of the electronic device being greater than the power-on timeout duration and the electronic device being in a power-on state, determining that the electronic device has a power-on timeout; In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in a power-on state, continuing to power on according to the power-on control logic; In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in an end-of-power-on state, determining that the electronic device has completed power-on.

12. The model determination method according to claim 11, characterized in that, After determining that the electronic device has a power-on timeout in response to the power-on duration of the electronic device being greater than the power-on timeout duration and the electronic device being in a power-on state, the method includes: Obtaining the power-on timeout information of the electronic device; Generating an alarm message corresponding to the power-on timeout information of the electronic device and sending it to the controller, where the alarm message includes at least one of the graphics processing module model, the feature identifier of the graphics processing module, and the identifier of the power-on control logic.

13. An electronic device, characterized in that, Includes: A memory for storing a computer program; A processor for implementing the steps of the model determination method according to any one of claims 6-12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, where the computer program implements the steps of the model determination method according to any one of claims 6-12 when executed by a processor.

15. A computer program product, comprising a computer program, characterized in that, The computer program implements the steps of the model determination method according to any one of claims 6-12 when executed by a processor.

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