IO pin multiplexing circuit, control method, chip and electronic equipment

Abstract

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an I / O pin multiplexing circuit, control method, chip, and electronic device. Background Technology

[0002] The input / output (I / O) unit of a chip is the core interface for interaction between the integrated circuit and the external environment. Its functional design directly affects the chip's versatility, reliability, and system scalability. The functions of the I / O unit can be summarized as follows: 1. Basic Functions: Signal Interaction and Level Adaptation Signal input detects external voltage or current states (such as button triggers or sensor signals) and converts them into digital levels recognizable by the chip's internal logic. For example, GPIO input mode can read switch states, and ADC input pins quantize analog signals into digital values. Signal output drives external loads (such as LEDs or motors), converting the chip's internal logic levels into voltage / current levels that meet the requirements of the external device. For example, PWM output pins control motor speed by adjusting the duty cycle. Level conversion ensures compatibility with different voltage domains (such as 0.9V chips and 1.8V peripherals) through level shifting circuits, enabling cross-voltage communication and preventing signal and circuit damage.

[0003] 2. Reusable Functionality: Dynamic Resource Configuration To address the challenges of limited pin resources and diverse functional requirements, modern I / O systems generally support multiplexing. By enabling and configuring gating units or registers, the same physical pin can dynamically switch between digital signal input / output, control word writing, SPI, and I / O. 2 C and other functions. For example, a certain pin is used for control word writing during system startup and switches to digital signal input during operation.

[0004] 3. Protection Functions Electrostatic discharge (ESD) protection diodes prevent electrostatic breakdown and improve stability in industrial environments.

[0005] In modern integrated circuit design, the control word serves as the core carrier of chip function configuration, enabling precise control of internal modules (such as module enable, power mode, and signal path) through preset binary code. With increasing chip complexity and diversified application scenarios, control word writing technology needs to balance multiple requirements, including speed, flexibility, pin resources, and power consumption. Currently, mainstream writing solutions are based on standardized interfaces and direct hardware connection logic. The following are common existing technologies: 1. SPI (Serial Peripheral Interface): With its full-duplex capability and high clock frequency (up to 100MHz and above), SPI has become the preferred solution for transmitting large-capacity control words. This interface uses a four-wire system (SCLK (clock), MOSI (master-output, slave-in), MISO (master-in, slave-output), and CS (chip select) to achieve master-slave communication, transmitting data bit by bit in byte units. For example, when configuring an RF front-end chip, the master MCU continuously sends 16-bit control words via SPI to sequentially set the frequency band, gain, and filtering parameters. Its advantages include low protocol overhead and strong real-time performance, but it requires an independent chip select signal for each slave device, resulting in a higher pin count in multi-module systems. Typical applications include Flash memory initialization and high-speed ADC calibration.

[0006] 2. I 2 C (Inter-Integrated Circuit): I 2 The C-band employs a two-wire system (SDA data line, SCL clock line) and a multi-master, multi-slave architecture, achieving bus sharing through device address addressing. This makes it particularly suitable for low-power scenarios such as sensor networks and wearable devices. Taking the biosensor in a smart bracelet as an example, the main control chip uses I-band... 2 C sends an 8-bit control word to the heart rate module to dynamically adjust the sampling rate and operating mode. 2 The simplified pinout and hot-swappable features of the C-type reduce hardware design complexity, but its half-duplex mode and maximum speed of 3.4 Mbps limit its application in high-throughput scenarios.

[0007] 3. GPIO Parallel Direct Writing: For timing-sensitive real-time control systems (such as motor drives and laser modulation), GPIO parallel direct writing transmits data synchronously through multiple pins, bypassing the latency caused by protocol parsing. For example, an industrial robotic arm controller directly writes the joint angle control word to the driver chip through an 8-bit GPIO port, latching the data on the rising edge of the clock with the write enable (WE) signal. This solution can achieve latency as low as nanoseconds and does not require complex communication protocols. However, an N-bit control word requires N+2 pins (data + clock / enable), making it less practical in microchips with limited pin resources. It is more commonly found in FPGA configurations or high-precision instruments.

[0008] Despite SPI, I 2 Parallel writing using C and GPIO is the mainstream solution for chip control word configuration, but its limitations become apparent in different scenarios. The SPI interface consumes a significant amount of pin resources; in multi-slave systems, an independent chip select (CS) signal needs to be allocated to each device, leading to a surge in pin usage. Furthermore, the SPI interface lacks a standardized protocol; data packet format and error checking (such as CRC) must be customized, and compatibility depends on design specifications. 2The standard mode rate of the C interface is only 100kbps, and even the high-speed mode (3.4Mbps) is far lower than SPI, making it difficult to meet high-speed control requirements. While GPIO parallel direct writing offers extremely fast transmission rates, its N-bit control word requires N+2 pins (data lines + clock / enable), consuming significant pin resources and resulting in excessive cost in microchips. SPI and I... 2 The C control word writing method inevitably uses the clock signal for multiple cycles, which not only leads to speed bottlenecks and dynamic power consumption, but also increases clock crosstalk to the signal and requires more digital resources, increasing the complexity and area of ​​the chip. Summary of the Invention

[0009] To overcome one or more of the above-mentioned technical defects, the present invention provides an IO pin multiplexing circuit and control method. By adopting pin function multiplexing technology and enabling the switching function of the enable signal, the control word writing function can be realized when the chip is first started, and the digital signal transmission function can be realized when the chip is running normally, thereby reducing hardware costs and reducing the consumption of pin resources.

[0010] To address the aforementioned problems, the first aspect of this invention discloses an I / O pin multiplexing circuit, comprising: The gating module, connected to the chip core, is used to send a first enable signal and / or a second enable signal according to the on-chip control signal; The control word encoding module is connected to the gating module and an external chip respectively, and is used to enable the IO pin to work in control word encoding mode according to the first enable signal; A digital signal input module is connected to the gating module and an external chip respectively, and is used to enable the IO pin to work in digital signal input mode according to the second enable signal; The ESD module is connected to the digital signal input module and the control word encoding module to provide electrostatic protection.

[0011] Furthermore, the gating module includes a first NOT gate and a second NOT gate connected in series. The input terminal of the first NOT gate is connected to the chip core, and the output terminal of the first NOT gate is also connected to the digital signal input module. The output terminal of the second NOT gate is connected to the control word encoding module.

[0012] Furthermore, the digital signal input module includes a level conversion unit and a buffer and logic unit. The input terminal of the level conversion unit is connected to the ESD module, the output terminal of the level conversion unit is connected to the buffer and logic unit, the input terminal of the buffer and logic unit is also connected to the gating module to receive a second enable signal, and the output terminal of the buffer and logic unit is connected to the on-chip module.

[0013] Furthermore, the level conversion unit includes a third NOT gate, a fourth NOT gate, a fifth NOT gate, a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a fourth field-effect transistor. The input of the third NOT gate is connected to the ESD module, the output of the third NOT gate is connected to the gates of the fourth NOT gate and the first field-effect transistor, and the output of the fourth NOT gate is connected to the gate of the second field-effect transistor. The source of the first field-effect transistor is grounded, and its drain is connected to the drain of the third field-effect transistor and the gate of the fourth field-effect transistor. The source of the second field-effect transistor is grounded, and its drain is connected to the gate of the third field-effect transistor and the drain of the fourth field-effect transistor, forming a cross-coupled structure. The drain of the second field-effect transistor is also connected to the logic unit through the fifth NOT gate and the cache.

[0014] Furthermore, the cache and logic unit includes at least one AND gate, one input of which is connected to the gating module, the other input of which is connected to the output of the fifth NOT gate, and the output is connected to the on-chip module.

[0015] Furthermore, the cache and logic unit includes a first AND gate, a second AND gate, and several series-connected D flip-flops. One input of the first AND gate is connected to a level conversion unit, the other input of the first AND gate is connected to a gating module, and the output of the first AND gate is connected to the D flip-flops. One input of the second AND gate is connected to the gating module, the other input of the second AND gate is connected to the on-chip clock signal generation module, and the output of the second AND gate is connected to the clock signal port of each D flip-flop.

[0016] Furthermore, the control word encoding module includes a voltage divider unit, a comparison unit, and an encoding unit. One input terminal of the comparison unit is connected to the ESD module, and the other input terminal of the comparison unit is connected to the output terminal of the voltage divider unit. The comparison result of the comparison unit is output to the encoding unit for encoding to output the control word.

[0017] A second aspect of this invention discloses an I / O pin multiplexing control method, applied to the aforementioned I / O pin multiplexing circuit, comprising: If the on-chip control signal is detected to be low, the first enable signal to be high, and the second enable signal to be low, the IO pins are controlled to operate in control word encoding mode through the gating module and the control word encoding module; if the chip has completed power-on and the on-chip control signal is detected to be high, the first enable signal to be low, and the second enable signal to be high, the IO pins are controlled to operate in digital signal input mode through the gating module and the digital signal input module.

[0018] A third aspect of the present invention discloses a chip, including a chip core and the aforementioned I / O pin multiplexing circuit.

[0019] The fourth aspect of the present invention discloses an electronic device, including a device body and the aforementioned IO pin multiplexing circuit or the aforementioned chip disposed on the device body.

[0020] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses an I / O pin multiplexing circuit and control method. The I / O pin multiplexing circuit includes a gating module, a digital signal input module, a control word encoding module, and an ESD module. The gating module is connected to the chip core and is used to send a first enable signal and / or a second enable signal according to an on-chip control signal. The control word encoding module is connected to the gating module and an external component, and is used to enable the I / O pin to operate in control word encoding mode according to the first enable signal. The digital signal input module is connected to the gating module and an external component, and is used to enable the I / O pin to operate in digital signal input mode according to the second enable signal. The ESD module is connected to the digital signal input module and the control word encoding module to provide electrostatic discharge protection. By employing pin function multiplexing technology and switching the enable signal, the control word writing function can be realized when the chip is first started, and the digital signal transmission function can be realized when the chip is running normally, thereby reducing hardware costs and pin resource consumption. Attached Figure Description

[0021] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the IO pin multiplexing circuit described in the embodiments of this application; Figure 2 This is a circuit diagram of the gating module of the IO pin multiplexing circuit described in the embodiments of this application; Figure 3 This is a circuit diagram of the ESD module of the IO pin multiplexing circuit described in the embodiments of this application; Figure 4 This is a circuit diagram of the level conversion unit of the IO pin multiplexing circuit described in the embodiments of this application; Figure 5 This is a schematic diagram of the buffer and logic unit circuit of the IO pin multiplexing circuit described in the embodiments of this application. Figure 1 ; Figure 6 This is a schematic diagram of the buffer and logic unit circuit of the IO pin multiplexing circuit described in the embodiments of this application. Figure 2 ; Figure 7 Simulation effect of digital signal input function of the IO pin multiplexing circuit described in the embodiments of this application. Figure 1; Figure 8 Simulation effect of digital signal input function of the IO pin multiplexing circuit described in the embodiments of this application. Figure 2 ; Figure 9 This is a circuit diagram of the control word encoding module of the IO pin multiplexing circuit described in an embodiment of this application; Figure 10 This is a simulation diagram of the control word encoding function of the IO pin multiplexing circuit described in the embodiments of this application; Figure 11 This is a flowchart of the IO pin multiplexing control method described in the embodiments of this application; Labeling descriptions: 100, gating module; 200, control word encoding module; 300, digital signal input module; 310, level conversion unit; 320, buffer and logic unit. Detailed Implementation

[0022] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0023] To enable those skilled in the art to better understand the solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] In the embodiments of the present invention, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0025] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0026] In the description of embodiments of the present invention, terms such as "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of the present invention is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of terms such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0027] Furthermore, in the embodiments of the present invention, "multiple" refers to two or more. Therefore, in the embodiments of the present invention, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could be A, B, C, A and B, A and C, B and C, or A and B and C.

[0028] It should be noted that in the embodiments of the present invention, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0029] This invention provides an I / O pin multiplexing circuit, such as... Figure 1 The system includes a gating module 100, a control word encoding module 200, a digital signal input module 300, and an ESD module. The gating module 100 is connected to the chip core and is used to send a first enable signal ENN and / or a second enable signal ENP according to the on-chip control signal Initial_done. The control word encoding module 200 is connected to the gating module 100 and the off-chip R_off_chip, and is used to enable the IO pins to work in control word encoding mode according to the first enable signal ENN and output a control word. The digital signal input module 300 is connected to the gating module 100 and the off-chip R_off_chip, and is used to enable the IO pins to work in digital signal input mode according to the second enable signal ENP and output a digital signal. The ESD module is connected to the control word encoding module 200, the digital signal input module 300, and the off-chip R_off_chip, and provides electrostatic discharge protection.

[0030] Specifically, such as Figure 2The gating module 100 includes a first NOT gate F1 and a second NOT gate F2 connected in series. The input of the first NOT gate F1 is connected to the chip core to obtain the on-chip control signal Initial_done. The output of the first NOT gate F1 is also connected to the control word encoding module 200 to output a first enable signal ENN. The output of the second NOT gate F2 is connected to the digital signal input module 300 to output a second enable signal ENP. During the initial power-on phase of the chip, the on-chip control signal Initial_done is low. After the chip initialization is completed, the on-chip control signal Initial_done is high. When the on-chip control signal Initial_done is high, the first enable signal ENN is low and the second enable signal ENP is high, enabling the digital signal input function. During normal chip operation, when the on-chip control signal Initial_done is low, the first enable signal ENN is high and the second enable signal ENP is low, enabling the control word encoding function.

[0031] When the control word encoding function is enabled, an external resistor or direct voltage input is used to output the control word bus through the control word encoding module. The control word is used to enable and control various modules within the chip. When the digital signal input function is enabled, the input signal is output as one or more bits of data through the digital signal input module for data input to on-chip modules, such as digital-to-analog converter modules. This is used for control word writing during system initialization to initialize and configure certain modules, and switches to digital signal input during operation.

[0032] Specifically, the digital signal input module 300 includes a level conversion unit 310 and a buffer and logic unit 320. The input terminal of the level conversion unit 310 is connected to the ESD module, the output terminal of the level conversion unit 310 is connected to the buffer and logic unit 320, the input terminal of the buffer and logic unit 320 is also connected to the gating module 100 to receive the second enable signal ENP, and the output terminal of the buffer and logic unit 320 is connected to the on-chip module.

[0033] In one embodiment, such as Figure 3 The ESD module includes diodes D1 and D2 and an INOUT terminal. The INOUT terminal is connected to the control word encoding module 200 and the level conversion unit 310, respectively. The positive terminal of diode D1 is connected to the INOUT terminal, and the negative terminal of diode D1 is connected to VDD. The positive terminal of diode D2 is grounded to GND, and the negative terminal of diode D2 is connected to the INOUT terminal.

[0034] Specifically, such as Figure 4The level conversion unit includes a third NOT gate F3, a fourth NOT gate F4, a fifth NOT gate F5, a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, and a fourth field-effect transistor M4. The input of the third NOT gate F3 is connected to the ESD module, and the output of the third NOT gate F3 is connected to the gates of the fourth NOT gate F4 and the first field-effect transistor M1, respectively. The output of the fourth NOT gate F4 is connected to the gate of the second field-effect transistor M2. The source of the first field-effect transistor M1 is grounded, and the drain of the first field-effect transistor M1 is connected to the drain of the third field-effect transistor M3 and the gate of the fourth field-effect transistor M4, respectively. The source of the second field-effect transistor M2 is grounded, and the drain of the second field-effect transistor M2 is connected to the gate of the third field-effect transistor M3 and the drain of the fourth field-effect transistor M4, respectively. The third field-effect transistor M3 and the fourth field-effect transistor M4 form a cross-coupled structure. The drain of the second field-effect transistor M2 is also connected to the logic unit through the fifth NOT gate F5 and a cache.

[0035] The level conversion unit converts the input digital level VDD1 to VDD2. When INPUT is at a high level (VDD1), the gate of the first field-effect transistor M1 is low, and the gate of the second field-effect transistor M2 is high. At this time, the first field-effect transistor M1 is off, and the second field-effect transistor M2 is on. The drains of the second field-effect transistor M2 and the fourth field-effect transistor M4 (i.e., the gate of the third field-effect transistor M3) are pulled down by a certain voltage, causing the third field-effect transistor M3 to turn on. This, in turn, charges the drains of the first field-effect transistor M1 and the third field-effect transistor M3 (i.e., the gate of the fourth field-effect transistor M4). As the conduction of the fourth field-effect transistor M4 weakens, the drains of the second field-effect transistor M2 and the fourth field-effect transistor M4 will continue to decrease by a certain voltage. The third field-effect transistor M3 and the fourth field-effect transistor M4 are cross-coupled, forming positive feedback. Ultimately, the fourth field-effect transistor M4 is turned off, and the drains of the second field-effect transistor M2 and the fourth field-effect transistor M4 will be pulled down. Finally, the output voltage is at a high level (VDD2), realizing the conversion of data between different voltage domains.

[0036] In one embodiment, such as Figure 5 The buffer and logic unit includes at least one AND gate Y0. One input of AND gate Y0 is connected to the gating module, and the other input of AND gate Y0 is connected to the output of the fifth NOT gate F5. The output is connected to the on-chip module. When the second enable signal ENP is low, the digital signal input module outputs a low level; when the second enable signal ENP is high, the output digital logic is equal to the input digital logic, realizing the level conversion from VDD1 to VDD2.

[0037] In one embodiment, such as Figure 6The cache and logic unit includes a first AND gate Y1, a second AND gate Y2, and several cascaded D flip-flops (DFFs) for data shifting, storage, arithmetic, or encoding. One input of the first AND gate Y1 is connected to a level conversion unit, the other input of the first AND gate Y1 is connected to a gating module, and the output of the first AND gate Y1 is connected to the D flip-flops. One input of the second AND gate Y2 is connected to the gating module, the other input of the second AND gate Y2 is connected to the on-chip clock signal generation module, and the output of the second AND gate Y2 is connected to the clock signal port CLK of each D flip-flop.

[0038] The level shifting unit can achieve low-level to high-level or high-level to low-level conversion, such as... Figure 7 When the digital signal input function is enabled, and the buffer and logic unit uses an AND gate, the input 1.8V level signal is converted to 0.9V, and then the digital signal is output through the AND gate. Figure 7 The simulation results show that the level conversion is correct and the digital signal transmission is correct.

[0039] like Figure 8 When the digital signal input function is enabled, and the buffer and logic unit uses two AND gates and a series-connected D flip-flop, it can convert the input 1.8V level signal to 0.9V and then perform DFF shifting. In the simulation, one bit is input every 10ns, the clock signal CLK period is 10ns, and the input sequence is 101011. Figure 8 The simulation results show that the output of the DFF is a sequential shift of the input signal, with correct level conversion and correct digital signal transmission.

[0040] Specifically, such as Figure 9 The control word encoding module includes a voltage divider unit, a comparator unit, and an encoding unit. One input of the comparator unit is connected to the ESD module, and the other input is connected to the output of the voltage divider unit. The comparison result of the comparator unit is output to the encoding unit for encoding to output the control word. In one embodiment, the voltage divider unit includes five resistors connected in series with resistance values ​​of R, 2R, 2R, 2R, and R, respectively, generating four threshold voltages (VTH1, VTH2, VTH3, and VTH4) corresponding to VDD*1 / 8, VDD*3 / 8, VDD*5 / 8, and VDD*7 / 8, and outputting them to the four comparators COMP1, COMP2, COMP3, and COMP4 of the comparator unit for comparison. Specifically, the encoding unit includes three NOT gates and two AND gates. The comparison result is processed by the encoding unit to obtain a three-bit output control word. Different control word outputs can be obtained by changing the external resistor values ​​or the input voltage values. The number of resistors connected in series in the voltage divider unit, the number of comparators in the comparator unit, and the type and number of logic gates in the encoding unit can be selected according to the actual situation.

[0041] like Figure 10 When the control word encoding function is enabled, and the external resistors are connected in sequence at 10kΩ, 70kΩ, 200kΩ, 600kΩ, and 2MΩ, the outputs of D<2:0> correspond to 100, 101, 110, 111, and 011, respectively. The minimum resistor value allows the I / O pin to be shorted to ground, while the maximum resistor value allows the I / O pin to be left floating (open circuit), yielding consistent results. Simulation results demonstrate that different external resistor values ​​can change the control word.

[0042] This invention employs pin multiplexing technology, enabling control word writing during chip startup and digital signal transmission during normal chip operation, thus reducing the consumption of chip pin resources. Control word writing utilizes external resistors or external input voltages (i.e., hard-wired control), combined with comparators and logic gates to output the control word. This approach is characterized by simplicity, low hardware cost, minimal pin resource consumption, high-frequency real-time control, and the elimination of the need for prolonged use of clock signals and SPI master chips.

[0043] For microchips or modules with high control speed requirements, compared to using SPI and / or I2C, the writing method is simple, does not require large-scale digital modules and area, does not require a master control chip, greatly improves the writing speed, and reduces the chip area. Compared to the method of parallel writing using GPIO, the present invention greatly reduces the number of IOs. When the present invention uses the three NOT gates and two AND gates as logic units to output a three-bit control word as described in the above embodiments, the number of IOs required for parallel writing can be reduced by a factor of several compared to GPIO parallel writing.

[0044] This invention provides an I / O pin multiplexing circuit capable of both control word encoding and digital signal input, switching between them via a first enable signal and a second enable signal. The control word encoding module controls the output control word through an externally connected resistor or an externally input voltage, i.e., control is achieved by changing the external hardware. It features a nanosecond-level response speed, significantly reducing system cost for simple control signals, and eliminates the need for software coding. The I / O pin multiplexing circuit provided by this invention is characterized by its simplicity, low hardware cost, low pin resource consumption, high-frequency real-time control, and elimination of the need for prolonged use of clock signals and SPI control chips.

[0045] Based on the same inventive concept, embodiments of the present invention also provide an I / O pin multiplexing control method applied to the above-mentioned I / O pin multiplexing circuit, such as... Figure 11 ,include: If the on-chip control signal is detected to be low, the first enable signal ENN is high, and the second enable signal ENP is low, the IO pin is controlled to work in control word encoding mode through the gating module and the control word encoding module. If the chip is powered on and the on-chip control signal is detected to be high, the first enable signal ENN to be low, and the second enable signal ENP to be high, the IO pins will be controlled to work in digital signal input mode through the gating module and the digital signal input module.

[0046] In one embodiment, the present invention provides a chip including a chip core and the aforementioned I / O pin multiplexing circuit. The chip may be an integrated circuit (IC), also known as a microcircuit, microchip, or wafer / chip. The chip may be, but is not limited to, a system-on-chip (SOC) or system-in-package (SIP) chip.

[0047] Because the chip is equipped with the IO pin multiplexing circuit of the above embodiments, it has all the beneficial effects of the IO pin multiplexing circuit in any of the above embodiments, which will not be repeated here.

[0048] In one embodiment, the present invention provides an electronic device, including a device body and the aforementioned IO pin multiplexing circuit or the aforementioned chip disposed on the device body.

[0049] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Therefore, any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. An I / O pin multiplexing circuit, characterized in that, include: The gating module, connected to the chip core, is used to send a first enable signal and / or a second enable signal according to the on-chip control signal; The control word encoding module is connected to the gating module and an external chip respectively, and is used to enable the chip's IO pins to work in control word encoding mode according to the first enable signal; A digital signal input module is connected to the gating module and an external chip respectively, and is used to enable the chip's IO pins to operate in digital signal input mode according to the second enable signal; The ESD module is connected to the digital signal input module and the control word encoding module to provide electrostatic protection.

2. The I / O pin multiplexing circuit according to claim 1, characterized in that, The gating module includes a first NOT gate and a second NOT gate connected in series. The input of the first NOT gate is connected to the chip core, and the output of the first NOT gate is also connected to the digital signal input module. The output of the second NOT gate is connected to the control word encoding module.

3. The I / O pin multiplexing circuit according to claim 1, characterized in that, The digital signal input module includes a level conversion unit and a buffer and logic unit. The input terminal of the level conversion unit is connected to the ESD module, the output terminal of the level conversion unit is connected to the buffer and logic unit, the input terminal of the buffer and logic unit is also connected to the gating module to receive a second enable signal, and the output terminal of the buffer and logic unit is connected to the on-chip module.

4. The I / O pin multiplexing circuit according to claim 3, characterized in that, The level conversion unit includes a third NOT gate, a fourth NOT gate, a fifth NOT gate, a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a fourth field-effect transistor. The input of the third NOT gate is connected to the ESD module, the output of the third NOT gate is connected to the gates of the fourth NOT gate and the first field-effect transistor, and the output of the fourth NOT gate is connected to the gate of the second field-effect transistor. The source of the first field-effect transistor is grounded, and its drain is connected to the drain of the third field-effect transistor and the gate of the fourth field-effect transistor. The source of the second field-effect transistor is grounded, and its drain is connected to the gate of the third field-effect transistor and the drain of the fourth field-effect transistor, forming a cross-coupled structure. The drain of the second field-effect transistor is also connected to the logic unit through the fifth NOT gate and the cache.

5. The I / O pin multiplexing circuit according to claim 4, characterized in that, The cache and logic unit includes at least one AND gate. One input of the AND gate is connected to the gating module, the other input of the AND gate is connected to the output of the fifth NOT gate, and the output is connected to the on-chip module.

6. The I / O pin multiplexing circuit according to claim 4, characterized in that, The cache and logic unit includes a first AND gate, a second AND gate, and several D flip-flops connected in series. One input of the first AND gate is connected to a level conversion unit, the other input of the first AND gate is connected to a gating module, and the output of the first AND gate is connected to the D flip-flops. One input of the second AND gate is connected to the gating module, the other input of the second AND gate is connected to the on-chip clock signal generation module, and the output of the second AND gate is connected to the clock signal port of each D flip-flop.

7. The I / O pin multiplexing circuit according to claim 1, characterized in that, The control word encoding module includes a voltage divider unit, a comparison unit, and an encoding unit. One input terminal of the comparison unit is connected to the ESD module, and the other input terminal of the comparison unit is connected to the output terminal of the voltage divider unit. The comparison result of the comparison unit is output to the encoding unit for encoding to output the control word.

8. An I / O pin multiplexing control method, applied to the I / O pin multiplexing circuit according to any one of claims 1-7, characterized in that, include: If the on-chip control signal is detected to be low, the first enable signal is high, and the second enable signal is low, the IO pin is controlled to work in control word encoding mode through the gating module and the control word encoding module; If the chip is powered on and the on-chip control signal is detected to be high, the first enable signal to be low, and the second enable signal to be high, the IO pins will be controlled to operate in digital signal input mode through the gating module and the digital signal input module.

9. A chip, characterized in that, It includes a chip core and an I / O pin multiplexing circuit as described in any one of claims 1-7.

10. An electronic device, characterized in that, It includes a device body and an I / O pin multiplexing circuit as described in any one of claims 1-7 or a chip as described in claim 9, disposed on the device body.

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