Multi-core processor on-chip network address mapping method, device, processor and medium

Abstract

The present invention provides a multi-core processor on-chip network address mapping method, device, processor and medium, relating to the field of processor technology. The method obtains the address of a shared on-chip static random access memory access request issued by a processor core; based on the master node number field in the address, a new master node number is generated through logical decentralized mapping, and the new master node number is used to dynamically allocate access requests of consecutive addresses to different routing path directions; based on the new master node number, a routing path is established between the processor core and the target master node in the address, and the access request is routed to the target master node based on the routing path. The present invention can use different routing paths for SRAM accesses of consecutive on-chip addresses, thereby reducing on-chip network congestion, achieving on-chip network traffic load balancing, and improving the performance of the multi-core processor.

Description

Technical Field

[0001] The present invention relates to the technical field of computer processors, and in particular to a method, device, processor and medium for mapping network addresses on a multi-core processor chip. Background Art

[0002] Chip multiprocessors (CMPs), also known as multi-core processors, will integrate an increasing number of processor cores, reaching 8, 16, 32, 64, 128, or even more. In addition to general-purpose CPU (central processing unit) cores, multi-core processors can also include AI (artificial intelligence) processor cores, GPU (graphics processing unit) cores, DSP (digital signal processing) cores, DPU (data processing unit) cores, cryptographic accelerators (CACs), and stream processors (SPUs). Together, these cores form the heterogeneous cores of a multi-core processor, further enhancing data flow processing capabilities based on enhanced control flow. The cores of a multi-core processor are interconnected using a network on chip (NoC). In related technologies, the addresses of shared on-chip static random-access memory (SRAM) are mapped continuously, meaning that consecutive address segments are managed by the same home node. Because program access is temporally and spatially local, consecutive address requests are transmitted along the same routing path, causing uneven on-chip network traffic and resulting in network congestion, impacting the performance of multi-core processors. Summary of the Invention

[0003] The present invention provides a multi-core processor on-chip network address mapping method, device, processor and medium, which are used to solve the defect that continuous address requests in the traditional multi-core processor on-chip network address mapping method will be transmitted along the same routing path, causing unbalanced on-chip network traffic and leading to on-chip network congestion.

[0004] The present invention provides a multi-core processor on-chip network address mapping method, comprising:

[0005] obtaining an address of a shared on-chip static random access memory access request issued by a processor core;

[0006] Based on the primary node number field in the address, a new primary node number is generated through logical scatter mapping, wherein the new primary node number is used to dynamically allocate access requests of consecutive addresses to different routing path directions;

[0007] Based on the new master node number, a routing path is established between the processor core and the target master node in the address, and the access request is routed to the target master node based on the routing path.

[0008] According to the multi-core processor on-chip network address mapping method provided by the present invention, generating a new primary node number through logical decentralized mapping based on the primary node number field in the address includes:

[0009] Reverse the address bit sequence of the master node number field to generate the new master node number;

[0010] The reverse operation of the address bit sequence is specifically: reversing the high-to-low order of the master node number field to the low-to-high order, and using the reversed address bits as the code of the new master node number.

[0011] According to the multi-core processor on-chip network address mapping method provided by the present invention, generating a new primary node number through logical decentralized mapping based on the primary node number field in the address includes:

[0012] Perform an XOR operation on the master node number field and a preset hash value to generate the new master node number;

[0013] The preset hash value is a binary number that is neither all 0 nor all 1, and the number of bits of the hash value is the same as the number of bits of the master node number field;

[0014] The XOR operation is a bitwise logical XOR operation to map continuous master node number fields into non-continuous new master node numbers.

[0015] According to the multi-core processor on-chip network address mapping method provided by the present invention, establishing a routing path between the processor core and the target master node in the address based on the new master node number includes:

[0016] Based on the on-chip network topology, starting from the processor core, the shortest path first algorithm is used to dynamically calculate the optimal path to the target master node;

[0017] A complete routing path including each hop routing node is generated according to the optimal path.

[0018] According to the multi-core processor on-chip network address mapping method provided by the present invention, the shortest path first algorithm is used to dynamically calculate the optimal path to the target master node, including:

[0019] For bidirectional ring topology, the number of hops in the clockwise and counterclockwise directions is compared, and the direction with fewer hops is selected as the next hop direction; for mesh topology, the XY dimension sequential routing algorithm is used to determine the next hop master node.

[0020] The present invention also provides a multi-core processor on-chip network address mapping device, comprising:

[0021] An acquisition module, configured to acquire an address of a shared on-chip static random access memory access request issued by a processor core;

[0022] a mapping module, configured to generate a new primary node number through logical decentralized mapping based on the primary node number field in the address, wherein the new primary node number is used to dynamically allocate access requests of consecutive addresses to different routing path directions;

[0023] A routing module is used to establish a routing path between the processor core and the target master node in the address based on the new master node number, and to route the access request to the target master node based on the routing path.

[0024] According to the multi-core processor on-chip network address mapping device provided by the present invention, the mapping module includes a reverse mapping unit, and the reverse mapping unit is used to:

[0025] Reverse the address bit sequence of the master node number field to generate the new master node number;

[0026] The reverse operation of the address bit sequence is specifically: reversing the high-to-low order of the master node number field to the low-to-high order, and using the reversed address bits as the code of the new master node number.

[0027] According to the multi-core processor on-chip network address mapping device provided by the present invention, the mapping module includes a hash XOR mapping unit, and the hash XOR mapping unit is used to:

[0028] Perform an XOR operation on the master node number field and a preset hash value to generate the new master node number;

[0029] Among them, the preset hash value is a binary number that is neither all 0 nor all 1, and its number of bits is the same as the number of bits of the master node number field; the XOR operation is a bit-by-bit logical XOR operation to map continuous master node number fields into non-continuous new master node numbers.

[0030] The present invention further provides a multi-core processor, comprising: implementing any of the above-mentioned methods for on-chip network address mapping for a multi-core processor when the multi-core processor executes a program.

[0031] The present invention also provides a non-transitory readable storage medium, which stores computer-readable instructions. The computer-readable instructions can be executed by a computer having one or more processors to enable the processor to execute the multi-core processor on-chip network address mapping method as described in any one of the above items.

[0032] The multi-core processor on-chip network address mapping method, device, processor and medium provided by the present invention obtain the address of a shared on-chip static random access memory access request issued by a processor core; based on the master node number field in the address, a new master node number is generated through logical decentralized mapping, and the new master node number is used to dynamically allocate access requests for consecutive addresses to different routing path directions; based on the new master node number, a routing path is established between the processor core and the target master node in the address, and the access request is routed to the target master node based on the routing path. Different routing paths can be used for SRAM access to consecutive on-chip addresses, thereby reducing on-chip network congestion, achieving on-chip network traffic load balancing, and improving the performance of the multi-core processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is a flow chart of a multi-core processor on-chip network address mapping method provided by an embodiment of the present invention;

[0035] Figure 2 This is a multi-core processor architecture diagram with a traditional continuous address mapping dual-ring topology;

[0036] Figure 3 This is a diagram of a multi-core processor architecture with a dual-ring topology and reverse address mapping provided by an embodiment of the present invention;

[0037] Figure 4 This is a diagram of a multi-core processor architecture with a dual-ring topology and XOR address mapping provided by an embodiment of the present invention;

[0038] Figure 5 This is a diagram of a multi-core processor architecture with a dual-ring topology provided by an embodiment of the present invention;

[0039] Figure 6 This is a diagram of a multi-core processor architecture of a Mesh topology provided by an embodiment of the present invention;

[0040] Figure 7This is a diagram showing the internal structure of a network-on-chip routing node provided by an embodiment of the present invention;

[0041] Figure 8 This is a diagram of a multi-core general-purpose processor architecture with a dual-ring topology provided by an embodiment of the present invention;

[0042] Figure 9 This is a diagram of a multi-core general-purpose processor architecture with a dual-ring topology and reverse address mapping provided by an embodiment of the present invention;

[0043] Figure 10 It is a functional structural diagram of an on-chip network address mapping device for a multi-core processor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0045] Figure 1 The flowchart of the multi-core processor on-chip network address mapping method provided by the embodiment of the present invention is as follows: Figure 1 As shown, the multi-core processor on-chip network address mapping method provided by the embodiment of the present invention includes:

[0046] Step 101: Obtain the address of a shared on-chip static random access memory access request issued by a processor core;

[0047] Step 102: Based on the primary node number field in the address, a new primary node number is generated through logical distributed mapping, where the new primary node number is used to dynamically allocate access requests for consecutive addresses to different routing path directions.

[0048] Step 103: Based on the new master node number, establish a routing path between the processor core and the target master node in the address, and route the access request to the target master node based on the routing path.

[0049] Traditional shared on-chip SRAM addresses use a continuous mapping scheme, meaning that consecutive address segments are managed by the same master node. Because program accesses are temporally and spatially local, consecutive address requests are transmitted along the same routing path, causing uneven on-chip network traffic and resulting in network congestion, impacting the performance of multi-core processors.

[0050] On-chip SRAM includes cache or scratch-pad memory (SPM). Each SRAM block has a fixed home node. In a multi-core on-chip network architecture, SRAM is shared by all processor cores and uniformly addressed. When SRAM is shared, each SRAM block has a fixed home node. In traditional on-chip network address mapping methods, SRAM addresses are mapped in a continuous manner. For example, for a multi-core processor with an 8-master node on-chip network, SRAM row 0 is on master node 0, SRAM row 1 is on master node 1, SRAM row 2 is on master node 2, SRAM row 3 is on master node 3, SRAM row 4 is on master node 4, SRAM row 5 is on master node 5, SRAM row 6 is on master node 6, SRAM row 7 is on master node 7, SRAM row 8 is on master node 0, SRAM row 9 is on master node 1, and so on.

[0051] The data access addresses of the processor core to the SRAM are generally continuous. Since the SRAM addresses managed by the master node in the prior art are arranged continuously according to the master node number, the address managed by the master node is taken from the consecutive bits of the processor core access address. Taking the dual-ring topology on-chip network as an example, in a multi-core processor on-chip network with 8 master nodes, the master node number is 3 bits (8 master nodes, , so the address corresponding to the master node is 3 bits); the size of each SRAM row is 512 bits ( bit, i.e. byte), so the internal address of the master node is 6 bits; the access address is 40 bits. Then address [5:0] is the internal address of the master node, that is, the address within the SRAM row, indicating which specific byte of the SRAM row. Address [8:6] represents the master node number (abbreviated as HN number), which indicates which master node (Home node) it corresponds to, and is also the low bit of the SRAM row address. The routing node number and the master node number are as follows Figure 2 As shown in the figure, consecutive addresses in a dual-ring on-chip network (NOC) will follow the same routing direction. For example, when master node 0 accesses SRAM row address [8:6] = 010 (binary 010, corresponding to decimal 2), the SRAM access request is directed to master node 2. The subsequent SRAM access request, at consecutive SRAM row address [8:6] = 011 (binary 011, corresponding to decimal 3), will access master node 3. The access routing path for the processor core connected to routing node 0 to master node 2 is routing node 0 → routing node 1 → routing node 2. The access routing path for the processor core connected to routing node 0 to master node 3 is routing node 0 → routing node 1 → routing node 2 → routing node 3. These two access requests are routed in the same direction, causing congestion on the paths from routing node 0 to routing node 1 and routing node 1 to routing node 2, resulting in unbalanced NOC traffic.

[0052] In particular, the routing node number and the master node number are not necessarily the same. A routing node can connect to one master node or multiple master nodes. A routing node can connect to one processor core or multiple processor cores.

[0053] The on-chip network address mapping method for a multi-core processor provided by an embodiment of the present invention obtains the address of a shared on-chip static random access memory access request issued by a processor core; based on the master node number field in the address, a new master node number is generated through logical decentralized mapping, and the new master node number is used to dynamically allocate access requests for consecutive addresses to different routing path directions; based on the new master node number, a routing path is established between the processor core and the target master node in the address, and the access request is routed to the target master node based on the routing path. Different routing paths can be used for SRAM access to consecutive on-chip addresses, thereby reducing on-chip network congestion, achieving on-chip network traffic load balancing, and improving the performance of the multi-core processor.

[0054] Based on any of the above embodiments, generating a new master node number through logical scatter mapping based on the master node number field in the address includes:

[0055] Reverse the address bit sequence of the master node number field to generate the new master node number;

[0056] The reverse operation of the address bit sequence is specifically: reversing the high-to-low order of the master node number field to the low-to-high order, and using the reversed address bits as the code of the new master node number.

[0057] The embodiment of the present invention remaps the SRAM address managed by the on-chip network Home master node, reverses the address bits that identify the Home master node number, uses the reversed address bits as the master node (Home node) number, and reverses the address bits {8,7,6} (address bits from 6 to 8, address bit 6 is the lowest bit, address bit 8 is the highest bit) to {6,7,8} (address bits from 8 to 6, that is, address bit 8 becomes the lowest bit, reversed in sequence, address bit 6 is the highest bit). The mapping relationship between the master node number and the managed SRAM address bits is transformed into that shown in Table 1. The multi-core processor architecture diagram of the dual-ring topology after re-address mapping is shown in Figure 1. Figure 3As shown. After reverse remapping, the processor core connected to routing node 0 accesses SRAM row address [8:6] = 010 (binary 010, corresponding to decimal 2) with reverse address mapping, and the SRAM access request corresponds to master node 2 (binary 010). The subsequent SRAM access request at the consecutive SRAM row address [8:6] = 011 (binary 011, corresponding to decimal 3) is reversed, and will access master node 6 (binary 110). The access routing path for the processor core connected to routing node 0 to master node 2 is routing node 0 → routing node 1 → routing node 2, and the access routing path for the processor core connected to routing node 0 to master node 6 is routing node 0 → routing node 7 → routing node 6. The two access requests are routed in different directions. This facilitates traffic balancing across all links in the on-chip network, avoids congestion in the on-chip network, and achieves bandwidth balancing. Furthermore, the on-chip network address mapping method of the present invention achieves master node address remapping by simply reversing the address without performing any additional complex operations, and does not introduce additional hardware implementation costs.

[0058] Table 1 Reverse remapping relationship of on-chip network addresses

[0059]

[0060] In some embodiments of the present invention, generating a new master node number through logical scatter mapping based on the master node number field in the address includes:

[0061] Perform an XOR operation on the master node number field and a preset hash value to generate the new master node number;

[0062] The preset hash value is a binary number that is neither all 0 nor all 1, and the number of bits of the hash value is the same as the number of bits of the master node number field;

[0063] The XOR operation is a bitwise logical XOR operation to map continuous master node number fields into non-continuous new master node numbers.

[0064] The embodiment of the present invention performs address remapping through hashing or other methods. The hashing method can XOR a binary number of the address bits of a home node, and if the XOR number is not all 0 or all 1, the access addresses of consecutive home nodes are disrupted.

[0065] In the embodiment of the present invention, the preset hash value is a binary number 110. It should be noted that the present invention does not limit the XOR hash value, and those skilled in the art can dynamically adjust the setting according to the network load status.

[0066] For example, using the address mapping method of XORing the binary number 110, the mapping relationship between the master node number and the managed SRAM address bits is transformed into the one shown in Table 2. After XOR remapping, for master node 0 accessing SRAM row address [8:6] = 011 (corresponding to decimal 3), the address XOR mapping will cause the SRAM access request to be mapped to master node 5 (011 XORing 110 equals binary 101). The subsequent SRAM access request at the consecutive SRAM row address [8:6] = 100 (corresponding to decimal 4) will be mapped to master node 2 (100 XORing 110 equals binary 010). The access routing path for the processor core connected to routing node 0 for SRAM row address [8:6] = 3 (binary 011) is routing node 0 → routing node 7 → routing node 6 → routing node 5. The access routing path for the processor core connected to routing node 0 for SRAM row address [8:6] = 4 (binary 100) is routing node 0 → routing node 1 → routing node 2. The two access requests will be routed in two different directions, such as Figure 4 shown.

[0067] Table 2 XOR remapping relationship of on-chip network addresses

[0068]

[0069] Based on any of the foregoing embodiments, establishing a routing path between the processor core and the target master node in the address based on the new master node number includes:

[0070] Step 201: Based on the on-chip network topology, starting from the processor core, the shortest path first algorithm is used to dynamically calculate the optimal path to the target master node. For a bidirectional ring topology, the number of hops in the clockwise and counterclockwise directions is compared, and the direction with the fewer hops is selected as the next hop direction. For a mesh topology, an XY dimensional sequential routing algorithm is used to determine the next hop routing node.

[0071] Step 202: Generate a complete routing path including all hop routing nodes according to the optimal path.

[0072] like Figure 5 and Figure 6 The following are examples of the multi-core processor architecture diagram of the present invention. Figure 5 It is a multi-core processor with 8 routing nodes and a master node (Home node), and the on-chip network has a dual-ring topology. Figure 6 It is a multi-core processor with 16 routing nodes and a master node (Home node), and the on-chip network has a Mesh topology.

[0073] like Figure 7Figure 2 shows the internal structure of a NoC routing node. A NoC routing node consists of an input buffer, which caches incoming data packets from all directions. An address determination module stores address window information, which indicates the specific directions to which the addresses of different incoming data packets are routed, either to adjacent routing nodes or the local home node. The address determination module determines the routing direction based on the home node to which the destination address of the incoming data packet belongs, and then outputs the data packets in the input buffer to the corresponding output direction. Data packets from all directions destined for the same home node are arbitrated by the arbitration module, which selects the input data packet for output. Upon receiving an input enable signal, the input buffer releases the space occupied by the corresponding already-output input data packet. For a routing node, if multiple data packets are destined for the same direction, they must be queued for output. Furthermore, if multiple data packets enter a routing node, the input buffer will fill up, preventing it from accepting new input data packets. Therefore, ensuring load balancing and reducing congestion within the NoC are crucial for improving processor performance.

[0074] Taking a multi-core general-purpose processor as an example, Figure 8 As shown in the figure, the processor core of a multi-core general-purpose processor includes a processor core execution unit and a multi-level cache hierarchy. The on-chip network routing node is responsible for transmitting requests from the processor core to the master node (Home node). The SRAM managed by the master node (Home node) of a multi-core general-purpose processor is a cache, including a system-level cache (System Level Cache) and a directory. The system-level cache, also known as the last-level cache (LLC), is uniformly addressed, and each cache block has a fixed master node (Home node). Under the multi-level cache hierarchy and on-chip network architecture, the system-level cache is shared by all processor cores and uniformly addressed. Cache consistency is maintained between multiple cores within a multi-core processor. In the case of shared last-level cache, each cache block has a fixed master node (Home node) as a level for consistency maintenance. Each master node (Home node) maintains a directory that records which processor cores' caches each cache block in the system-level cache owns, as well as its status in the processor core cache. After reverse address mapping, as shown in the following figure: Figure 9 shown.

[0075] like Figure 9 In the multi-core general-purpose processor shown, the multi-core processor includes 8 processor cores, 8 master nodes, and the master node number is 3 bits (8 master nodes, ), each cache line is 512 bits in size ( bit, i.e. byte), the master node internal address is 6 bits, and the access physical address is 40 bits. Address [5:0] is the master node internal address, i.e., the cache line address, indicating the specific byte in the cache line. Address [8:6] represents the master node address (HN number), indicating which master node (home node) this address corresponds to, and is also the low-order bit of the cache line address. The physical address (paddr) of data block A accessed by the processor core connected to routing node 0 is paddr0: 0x00802d7850 (hexadecimal, corresponding to binary: 0000 0000 1000 0000 0010 1101 0111 1000 0101 0000). The corresponding master node address binary 001 (decimal 1) is reverse-mapped to binary 100 (decimal 4), indicating master node 1. The routing path is routing node 0 → routing node 1. Next, the physical address (paddr) of data block B accessed by this processor core is paddr1: 0x00802d7880 (hexadecimal, corresponding to binary: 0000 0000 1000 0000 0010 1101 01111000 1000 0000). The corresponding master node address, binary 010 (decimal 2), is reverse-mapped to binary 101 (decimal 5), indicating master node 5. The routing path is routing node 0 → routing node 7 → routing node 6 → routing node 5. This shifts the two access requests from the same path to different directions, achieving traffic balance across all links in the on-chip network and improving processor performance without increasing hardware overhead.

[0076] The multi-core processor on-chip network address mapping method provided by the embodiment of the present invention dynamically allocates access requests for consecutive addresses in the multi-core processor to different routing paths through logically distributed mapping methods such as address bit reversal and hash XOR methods, significantly improving on-chip network traffic balance, reducing communication latency, and increasing the overall processor throughput. It requires no hardware overhead, is compatible with various topologies such as dual-ring and mesh, and supports linear expansion of larger-scale systems. It effectively solves the network congestion problem caused by traditional continuous address mapping and provides an efficient and reliable multi-core communication foundation for scenarios such as high-performance computing and AI acceleration.

[0077] The multi-core processor on-chip network address mapping device provided by the present invention is described below. The multi-core processor on-chip network address mapping device described below and the multi-core processor on-chip network address mapping method described above can be referenced to each other.

[0078] Figure 10 A schematic diagram of the structure of a multi-core processor on-chip network address mapping device provided by an embodiment of the present invention is shown in FIG. Figure 10 As shown, the multi-core processor on-chip network address mapping device provided by the embodiment of the present invention includes:

[0079] An acquisition module 1001 is configured to acquire an address of a shared on-chip static random access memory access request issued by a processor core;

[0080] A mapping module 1002 is configured to generate a new primary node number through logical distributed mapping based on the primary node number field in the address, wherein the new primary node number is used to dynamically allocate access requests for consecutive addresses to different routing path directions;

[0081] The routing module 1003 is configured to establish a routing path between the processor core and the target master node in the address based on the new master node number, and route the access request to the target master node based on the routing path.

[0082] In an example of the present invention, the mapping module includes a reverse mapping unit, and the reverse mapping unit is configured to:

[0083] Reverse the address bit sequence of the master node number field to generate the new master node number;

[0084] The reverse operation of the address bit sequence is specifically: reversing the high-to-low order of the master node number field to the low-to-high order, and using the reversed address bits as the code of the new master node number.

[0085] In an example of the present invention, the mapping module includes a hash XOR mapping unit, and the hash XOR mapping unit is used to:

[0086] Perform an XOR operation on the master node number field and a preset hash value to generate the new master node number;

[0087] Among them, the preset hash value is a binary number that is neither all 0 nor all 1, and its number of bits is the same as the number of bits of the master node number field; the XOR operation is a bit-by-bit logical XOR operation to map continuous master node number fields into non-continuous new master node numbers.

[0088] An embodiment of the present invention provides an on-chip network address mapping device for a multi-core processor, which obtains the address of a shared on-chip static random access memory access request issued by a processor core; generates a new master node number through logical decentralized mapping based on the master node number field in the address, and the new master node number is used to dynamically allocate access requests for consecutive addresses to different routing path directions; establishes a routing path between the processor core and the target master node in the address based on the new master node number, and routes the access request to the target master node based on the routing path. Different routing paths can be used for SRAM access to consecutive on-chip addresses, thereby reducing on-chip network congestion, achieving on-chip network traffic load balancing, and improving the performance of the multi-core processor.

[0089] An embodiment of the present invention also provides a multi-core processor, comprising: when the multi-core processor executes a program, implementing a multi-core processor on-chip network address mapping method as described in any one of the above items, the method comprising: obtaining the address of a shared on-chip static random access memory access request issued by the processor core; based on the master node number field in the address, generating a new master node number through logical decentralized mapping, the new master node number is used to dynamically allocate access requests for consecutive addresses to different routing path directions; based on the new master node number, establishing a routing path between the processor core and the target master node in the address, and routing the access request to the target master node based on the routing path.

[0090] An embodiment of the present invention also provides a non-transitory readable storage medium, which stores computer-readable instructions. The computer-readable instructions can be executed by a computer having one or more processors to enable the processor to execute a multi-core processor on-chip network address mapping method as described in any one of the above items, the method comprising: obtaining the address of a shared on-chip static random access memory access request issued by a processor core; based on the master node number field in the address, generating a new master node number through logical decentralized mapping, the new master node number being used to dynamically allocate access requests for consecutive addresses to different routing path directions; based on the new master node number, establishing a routing path between the processor core and the target master node in the address, and routing the access request to the target master node based on the routing path.

[0091] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0092] Through the description of the above embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the relevant technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A multi-core processor on-chip network address mapping method, characterized in that: include: obtaining an address of a shared on-chip static random access memory access request issued by a processor core; Based on the primary node number field in the address, a new primary node number is generated through logical scatter mapping, wherein the new primary node number is used to dynamically allocate access requests of consecutive addresses to different routing path directions; establishing a routing path between the processor core and the target master node in the address based on the new master node number, and routing the access request to the target master node based on the routing path; The generating a new master node number through logical scatter mapping based on the master node number field in the address includes: Reverse the address bit sequence of the master node number field to generate the new master node number; The reverse operation of the address bit sequence is specifically as follows: reversing the high-to-low order of the master node number field to a low-to-high order, and using the reversed address bits as the code of the new master node number; and / or, The generating a new master node number through logical scatter mapping based on the master node number field in the address includes: Perform an XOR operation on the master node number field and a preset hash value to generate the new master node number; The preset hash value is a binary number that is neither all 0 nor all 1, and the number of bits of the hash value is the same as the number of bits of the master node number field; The XOR operation is a bitwise logical XOR operation to map continuous master node number fields into non-continuous new master node numbers.

2. The multi-core processor on-chip network address mapping method according to claim 1, characterized in that: The establishing a routing path between the processor core and the target master node in the address based on the new master node number includes: Based on the on-chip network topology, starting from the processor core, the shortest path first algorithm is used to dynamically calculate the optimal path to the target master node; A complete routing path including each hop routing node is generated according to the optimal path.

3. The multi-core processor on-chip network address mapping method according to claim 2, characterized in that: The method of dynamically calculating the optimal path to the target master node using the shortest path first algorithm includes: For bidirectional ring topology, the number of hops in the clockwise and counterclockwise directions is compared, and the direction with fewer hops is selected as the next hop direction; for mesh topology, the XY dimension sequential routing algorithm is used to determine the next hop routing node.

4. A multi-core processor on-chip network address mapping device, characterized in that: include: An acquisition module, configured to acquire an address of a shared on-chip static random access memory access request issued by a processor core; a mapping module, configured to generate a new primary node number through logical decentralized mapping based on the primary node number field in the address, wherein the new primary node number is used to dynamically allocate access requests of consecutive addresses to different routing path directions; A routing module for establishing a routing path between the processor core and the target master node in the address based on the new master node number, and routing the access request to the target master node based on the routing path; The mapping module includes a reverse mapping unit, and the reverse mapping unit is configured to: Reverse the address bit sequence of the master node number field to generate the new master node number; Among them, the reverse operation of the address bit order is specifically: reversing the high-to-low order of the master node number field to a low-to-high order, and using the reversed address bits as the encoding of the new master node number; The mapping module includes a hash XOR mapping unit, and the hash XOR mapping unit is used to: Perform an XOR operation on the master node number field and a preset hash value to generate the new master node number; Among them, the preset hash value is a binary number that is neither all 0 nor all 1, and its number of bits is the same as the number of bits of the master node number field; the XOR operation is a bit-by-bit logical XOR operation to map continuous master node number fields into non-continuous new master node numbers.

5. A multi-core processor, characterized in that: include: When the multi-core processor executes the program, the multi-core processor on-chip network address mapping method according to any one of claims 1 to 3 is implemented.

6. A non-transitory readable storage medium, characterized in that: The non-transitory readable storage medium stores computer-readable instructions, which can be executed by a computer having one or more processors to enable the processor to perform the multi-core processor on-chip network address mapping method according to any one of claims 1 to 3.

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