Chip screening method and system based on artificial bee colony algorithm

Abstract

The invention discloses a chip screening method and system based on an artificial bee colony algorithm. The method comprises the steps that firstly, n to-be-processed chips and parameter information of the to-be-processed chips are acquired; then determining the parallel connection number m of the to-be-processed chips; and finally, based on the parameter information of the to-be-processed chips, determining the sorting information of the n to-be-processed chips by using an artificial bee colony algorithm, and sequentially screening m parallel chips according to the sorting information, so that the parameter difference between the parallel chips can be reduced, and the phenomenon of current junction temperature imbalance caused by the chip difference can be effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor chips, and particularly relates to a chip screening method and system based on an artificial bee colony algorithm. Background Art

[0002] Semiconductors are widely used in the field of power electronics due to their superior high power density and high efficiency characteristics. However, when multiple semiconductor chips operate in parallel, due to differences in device parameters, internal parasitic characteristics, and temperature distributions, it is easy to cause uneven current distribution, which in turn leads to problems such as uneven junction temperature, overheating, and device aging, affecting the stability and reliability of the module. Therefore, how to reduce current imbalance and temperature differences to improve the performance and lifespan of the chip system has become a technical problem that urgently needs to be solved. Summary of the Invention

[0003] The object of the present invention is to provide a chip screening method and system based on an artificial bee colony algorithm to solve the deficiencies in the prior art. It proposes a chip screening strategy based on an artificial bee colony algorithm, which can obtain the sorting information of the chips to be processed and sequentially screen several parallel chips according to the sorting information, thereby reducing the parameter differences between the parallel chips and effectively reducing the uneven current and junction temperature caused by chip differences.

[0004] An embodiment of the present application provides a chip screening method based on an artificial bee colony algorithm, and the method includes: Obtain n chips to be processed and the parameter information of the chips to be processed; Determine the number of parallel chips m to be processed; Based on the parameter information of the chips to be processed, use the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially screen m parallel chips according to the sorting information.

[0005] Optionally, the step of using the artificial bee colony algorithm based on the parameter information of the chips to be processed to determine the sorting information of the n chips to be processed and sequentially screen m parallel chips according to the sorting information includes: Step 1: Initialize the position of the worker bee's honey source based on the parameter information of the chips to be processed, where the position of the worker bee's honey source corresponds to the initial sorting of the chips to be processed; Step 2: Calculate the fitness value corresponding to the position of the worker bee's honey source according to the fitness function, obtain the neighborhood solution and the fitness value corresponding to the neighborhood solution; where the neighborhood solution is used to update the position of the worker bee's honey source; Step 3: Determine the position of the observing bee according to the comparison result of the fitness value corresponding to the current position of the worker bee's honey source and the fitness value corresponding to the updated position of the worker bee's honey source; where the observing bee is determined according to the preset observing bee position probability formula; Step 4: In response to the change in the fitness value of the worker bee's food source position being less than a preset threshold for a preset number of times, a new set of worker bee's food source positions is randomly generated by scout bees, and Steps 2 and 3 are repeatedly executed until a preset end condition is reached, so as to output the sorting information of n chips to be processed, and m parallel chips are sequentially screened according to the sorting information.

[0006] Optionally, the fitness function is determined according to the sum of variances of the parameter information of the chips to be processed in each parallel group; and, When the number n of chips to be processed can divide the number m of parallel chips to be processed, the fitness function is defined as:

[0007] Wherein, represents the parameter information of the j-th chip in the i-th group, represents the mean value of the parameters of the i-th chip.

[0008] Optionally, when the number n of chips to be processed cannot divide the number m of parallel chips to be processed, the fitness function is defined as:

[0009] Wherein, .

[0010] Optionally, the probability formula of the preset observation bee position is expressed as:

[0011] Wherein, represents the probability of the observation bee position, represents the fitness of the i-th worker bee position, and N represents the total number of worker bees.

[0012] Optionally, calculating the fitness value corresponding to the worker bee's food source position according to the fitness function, obtaining the neighborhood solution and the fitness value corresponding to the neighborhood solution includes: Performing sub-interval exchange and reverse order crossover operations according to the fitness function and the worker bee's food source position to generate a neighborhood solution.

[0013] Optionally, the chips to be processed include power semiconductor chips.

[0014] Another embodiment of the present application provides a chip screening system based on an artificial bee colony algorithm, and the system includes: An acquisition module, configured to acquire n chips to be processed and the parameter information of the chips to be processed; A first determination module, configured to determine the number m of parallel chips to be processed; A second determination module, configured to determine the sorting information of the n to-be-processed chips by using an artificial bee colony algorithm based on the parameter information of the to-be-processed chips, and sequentially screen m parallel chips according to the sorting information.

[0015] Another embodiment of the present application provides a storage medium, in which a computer program is stored, and the computer program is configured to implement the method described in any one of the above when running.

[0016] Another embodiment of the present application provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to implement the method described in any one of the above.

[0017] Compared with the prior art, the present application first obtains n to-be-processed chips and the parameter information of the to-be-processed chips; then determines the number m of parallel chips of the to-be-processed chips; and finally determines the sorting information of the n to-be-processed chips by using an artificial bee colony algorithm based on the parameter information of the to-be-processed chips, and sequentially screen m parallel chips according to the sorting information, so as to reduce the parameter differences between the parallel chips and effectively reduce the phenomenon of uneven current junction temperature caused by chip differences. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a hardware structure block diagram of a computer terminal for a chip screening method based on an artificial bee colony algorithm provided by an embodiment of the present invention; Figure 2 It is a schematic flowchart of a chip screening method based on an artificial bee colony algorithm provided by an embodiment of the present invention; Figure 3 It is a schematic flowchart of using an artificial bee colony algorithm to determine the sorting information of to-be-processed chips and sequentially screen a plurality of parallel chips according to the sorting information provided by an embodiment of the present invention; Figure 4 It is a schematic structural diagram of a chip screening system based on an artificial bee colony algorithm provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be construed as limiting the present invention.

[0020] An embodiment of the present invention first provides a chip screening method based on an artificial bee colony algorithm. This method can be applied to an electronic device, such as a computer terminal, specifically, such as a general computer, a tablet, etc.

[0021] The following takes running on a computer terminal as an example to describe it in detail. Figure 1The following is a hardware structure block diagram of a computer terminal for a chip screening method based on an artificial bee colony algorithm provided by an embodiment of the present invention. As Figure 1 shown, the computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the memory may include a non-volatile storage medium and an internal memory.

[0022] The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, and when the program instructions are executed, the processor can execute any chip screening method based on an artificial bee colony algorithm.

[0023] The processor is used to provide computing and control capabilities to support the operation of the entire computer device.

[0024] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor, the processor can execute any chip screening method based on an artificial bee colony algorithm.

[0025] The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art can understand that Figure 1 the structure shown in

[0026] is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0027] See Figure 2 , Figure 2 which is a schematic flowchart of a chip screening method based on an artificial bee colony algorithm provided by an embodiment of the present invention, and may include the following steps: S201: Obtain n chips to be processed and parameter information of the chips to be processed.

[0028] S202: Determine the number m of parallel chips to be processed.

[0029] Specifically, first obtain the number n of chips to be processed. Starting from the first chip to be processed, read the device parameters of the chip. The screening method in this application mainly solves the problem of uneven current sharing among parallel chips. The parameter information of the chips with more prominent effects can include the threshold voltage Vth, transconductance gfs, on-resistance Rds, etc. Other parameters can also be selected according to actual experimental requirements, and the selected parameters can also include any one or more of the above. Then, initially determine m parallel chips to be processed with better current sharing effect through a preset screening strategy.

[0030] It should be noted that the purpose of this application is to achieve current sharing among parallel chips to be processed. Among them, n can be used to represent the total number of an existing set of chips to be processed, from which m chips that can achieve current sharing are selected, and m can be determined according to actual needs.

[0031] S203: Based on the parameter information of the chips to be processed, use the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially screen m parallel chips according to the sorting information.

[0032] Specifically, refer to Figure 3 , Figure 3 which is a flow chart showing a method for using the artificial bee colony algorithm to determine the sorting information of chips to be processed and sequentially screen several parallel chips provided by an embodiment of the present invention. First, define a fitness function to quantify the parameter differences between chips, then initialize the nectar source positions of N worker bees, calculate the fitness values of each nectar source, and generate neighborhood solutions; update the nectar source positions of worker bees and the positions of observing bees; the scout bee monitors whether there is no improvement in the nectar source positions of worker bees to determine whether to generate new nectar source positions; finally, check whether the termination condition is met. If so, output the optimal solution, and the sorting information of the n chips to be processed can be determined and m parallel chips can be sequentially screened according to the sorting information; otherwise, return to re - execute the above steps until the preset stop condition is reached.

[0033] It should be noted that N is the number of worker bees set according to actual needs. Among them, each worker bee will have a corresponding nectar source position, and the nectar source position of the worker bee can be understood as the label sorting of the n chips to be processed.

[0034] Exemplarily, the step of determining the sorting information of the n chips to be processed based on the parameter information of the chips to be processed and using the artificial bee colony algorithm and sequentially screening m parallel chips according to the sorting information may include: Step 1: Based on the parameter information of the chips to be processed, initialize the nectar source positions of the worker bees, where the nectar source positions of the worker bees correspond to the initial sorting of the chips to be processed.

[0035] Specifically, the sorting of the chips to be processed is used as the position of the nectar sources known to the worker bees. For example, randomly generate the initial positions of N worker bees, and each nectar source position represents a possible sorting method.

[0036] Step 2: According to the fitness function, calculate the fitness values corresponding to the nectar source positions of the worker bees, obtain the neighborhood solutions and the fitness values corresponding to the neighborhood solutions; wherein, the neighborhood solutions are used to update the nectar source positions of the worker bees.

[0037] Specifically, according to the fitness function and the nectar source positions of the worker bees, perform sub-interval exchange and reverse order crossover operations to generate neighborhood solutions. Among them, the neighborhood solution is a new string of nectar source positions, which only makes a small change to the sorting of the chips. That is, some small perturbations can be made to the chip sorting initialized by the worker bees to obtain some new nectar source positions to get the neighborhood solutions. Sub-interval exchange is to swap two small parts of a sorting, and reverse order means reversing the order. Since n may not be divisible by the parallel number m with a remainder, the situation of parallel chips will change after reverse order. It should be noted that there are more methods to meet the requirements of obtaining the above neighborhood solutions, which are not limited here.

[0038] Among them, the fitness function is determined according to the sum of variances of the parameter information of the chips to be processed in each parallel group; and when the number n of chips to be processed can be divisible by the parallel number m of the chips to be processed, the fitness function can be defined as:

[0039] Among them, represents the parameter information of the j-th chip in the i-th group, represents the mean value of the parameters of the i-th chip.

[0040] When the number n of chips to be processed cannot be divisible by the parallel number m of the chips to be processed, the fitness function can be defined as:

[0041] Among them, .

[0042] Step 3: According to the comparison result of the fitness value corresponding to the current nectar source position of the worker bee and the fitness value corresponding to the updated nectar source position of the worker bee, determine the position of the observing bee; wherein, the observing bee is determined according to the preset observing bee position probability formula.

[0043] Specifically, the fitness value corresponding to the current forager bee's nectar source location and the fitness value corresponding to the updated forager bee's nectar source location are calculated and compared, and the location with better fitness is used to update the forager bee's nectar source location. Among them, the observing bees store the nectar source locations of the forager bees. If there is a better nectar source location, it will be updated; otherwise, it remains unchanged. When the number of iterations ends, the sorting result is output. The basis for the observing bees to select is that the higher the fitness of the forager bee, the greater the probability of being selected, so as to guide the search for subsequent optimal solutions.

[0044] Exemplarily, the preset observing bee location probability formula can be expressed as:

[0045] Wherein, represents the observing bee location probability, represents the fitness of the i-th forager bee location, and N represents the total number of forager bees.

[0046] Step 4: In response to the change in the fitness value of the forager bee's nectar source location being less than the preset threshold within the preset number of times, a new set of forager bee's nectar source locations is randomly generated by the scout bees, and steps 2 and 3 are repeatedly executed until the preset end condition is reached, so as to output the sorting information of n chips to be processed, and m parallel chips are sequentially screened according to the sorting information.

[0047] Specifically, if the update of the forager bee's nectar source location has not been improved after a certain number of times, this nectar source location will be considered "exhausted", and the scout bees will randomly generate a new set of nectar source locations for the forager bees; the task of the scout bees is to explore new areas to avoid falling into local optimal solutions. The operation of updating the observing bee locations of the forager bees is repeatedly performed until the preset end condition is reached; the preset end condition can be reaching the maximum number of iterations, the convergence of the fitness value, etc. When the algorithm stops, the global optimal observing bee location and its corresponding optimal solution are output to output the final grouping result, that is, the sorting information of n chips to be processed is output, and m parallel chips are sequentially screened according to the sorting information.

[0048] It should be noted that the chips to be processed may include power semiconductor chips. A power semiconductor chip is an element that converts power through high-speed switching and is mainly used for controlling and converting power supply power. Since it can withstand high voltage and large current, it is called a "power" semiconductor. Its main functions include supplying, controlling, and converting power and electricity, and are suitable for the processing of high voltage and large current. It is not only used in general household appliances, but also widely used in fields such as electric vehicle (EV) motors and batteries, and solar power generation.

[0049] The artificial bee colony algorithm in this application is a swarm intelligence optimization algorithm inspired by the foraging behavior of bees. The bee colony conducts global optimization through exploration (searching for new food sources), exploitation (optimizing existing solutions), and abandonment (eliminating inferior solutions). It is applicable to continuous optimization problems and has good search capabilities in high-dimensional spaces. The artificial bee colony algorithm can be applied to continuous optimization problems, has strong search capabilities, is easy to escape from local optima, and has low computational complexity.

[0050] The present invention realizes the global optimization of chip screening by introducing the artificial bee colony algorithm, and has the following remarkable advantages: Efficient global search ability: By adopting a swarm intelligence optimization mechanism and through the collaborative mode of worker bee exploration, observer bee exploitation, and scout bee elimination, it can quickly locate the optimal solution in the high-dimensional parameter space, effectively avoiding the defect that traditional local search methods are prone to falling into local optima, and ensuring the global optimality of the screening results.

[0051] Low-complexity parallel processing: By simulating the division of labor and cooperation of bees, the algorithm naturally supports parallel computing. While maintaining a high search efficiency, it significantly reduces the computational complexity. For large-scale chip parameter optimization problems, it can complete the sorting optimization of multiple groups of parallel chips in a short time, improving the feasibility of engineering applications.

[0052] Adaptive parameter difference compensation: By defining a fitness function based on parameter variance, the algorithm can quantitatively evaluate the current-sharing effect of different sorting schemes. Combining neighborhood search strategies such as sub-interval exchange and reverse order crossover, it can dynamically adjust the chip arrangement and combination, minimizing the parameter differences within the parallel group to the greatest extent, thereby suppressing the phenomena of uneven current distribution and unbalanced junction temperature.

[0053] Robustness and scalability: The algorithm is not sensitive to initial conditions and can adapt to different scales of chip screening scenarios. When the number of chips to be processed n cannot be divided evenly by the number of parallel connections m, it can still minimize the parameter variance through an adaptive grouping strategy (such as the remainder k processing mechanism), ensuring the stable operation of the system under complex conditions.

[0054] Enhanced engineering practicality: Through the random initialization mechanism of scout bees, the algorithm can effectively jump out of local extrema, avoiding screening failures caused by parameter measurement errors or process fluctuations. This feature significantly improves the reliability of the screening results and provides a powerful tool for the high-reliability design of power semiconductor modules.

[0055] The synergistic effect of the above advantages enables the present invention to make a breakthrough in reducing the discreteness of chip parameters and optimizing the parallel current-sharing effect, and has higher optimization accuracy and engineering practicality than traditional screening methods.

[0056] Compared with the prior art, the present application first obtains n chips to be processed and the parameter information of the chips to be processed; then determines the number m of parallel-connected chips to be processed; and finally, based on the parameter information of the chips to be processed, uses the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially screens m parallel-connected chips according to the sorting information, so as to reduce the parameter differences between the parallel-connected chips and effectively reduce the uneven current junction temperature phenomenon caused by chip differences.

[0057] Another embodiment of the present application provides a chip screening system based on the artificial bee colony algorithm, as Figure 4 shown in the structural schematic diagram of a chip screening system based on the artificial bee colony algorithm. The system includes: An acquisition module 401, configured to acquire n chips to be processed and the parameter information of the chips to be processed; A first determination module 402, configured to determine the number m of parallel-connected chips to be processed; A second determination module 403, configured to determine the sorting information of the n chips to be processed based on the parameter information of the chips to be processed by using the artificial bee colony algorithm, and sequentially screen m parallel-connected chips according to the sorting information.

[0058] Compared with the prior art, the present application first obtains n chips to be processed and the parameter information of the chips to be processed; then determines the number m of parallel-connected chips to be processed; and finally, based on the parameter information of the chips to be processed, uses the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially screens m parallel-connected chips according to the sorting information, so as to reduce the parameter differences between the parallel-connected chips and effectively reduce the uneven current junction temperature phenomenon caused by chip differences.

[0059] The embodiment of the present invention also provides a storage medium, in which a computer program is stored, and the computer program is configured to implement the steps in the above method embodiment when running.

[0060] Specifically, in this embodiment, the above storage medium may be configured to store a computer program for executing the following steps: S201: Acquire n chips to be processed and the parameter information of the chips to be processed; S202: Determine the number m of parallel-connected chips to be processed; S203: Based on the parameter information of the chips to be processed, use the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially screen m parallel-connected chips according to the sorting information.

[0061] Specifically, in this embodiment, the above storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0062] Compared with the prior art, the present application first obtains n chips to be processed and parameter information of the chips to be processed; then determines the number of parallel-connected chips m to be processed; and finally, based on the parameter information of the chips to be processed, uses the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially selects m parallel-connected chips according to the sorting information, so as to reduce the parameter differences between the parallel-connected chips and effectively reduce the uneven current junction temperature phenomenon caused by chip differences.

[0063] The embodiment of the present invention also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in the above method embodiment.

[0064] Specifically, the above electronic device may further include a transmission device and an input / output device. Among them, the transmission device is connected to the above processor, and the input / output device is connected to the above processor.

[0065] Specifically, in this embodiment, the above processor may be configured to execute the following steps through a computer program: S201: Obtain n chips to be processed and parameter information of the chips to be processed; S202: Determine the number of parallel-connected chips m to be processed; S203: Based on the parameter information of the chips to be processed, use the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially select m parallel-connected chips according to the sorting information.

[0066] Compared with the prior art, the present application first obtains n chips to be processed and parameter information of the chips to be processed; then determines the number of parallel-connected chips m to be processed; and finally, based on the parameter information of the chips to be processed, uses the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially selects m parallel-connected chips according to the sorting information, so as to reduce the parameter differences between the parallel-connected chips and effectively reduce the uneven current junction temperature phenomenon caused by chip differences.

[0067] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should understand that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0068] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0069] In several embodiments provided by the present invention, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical or other forms.

[0070] The units described as separate components above may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0071] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0072] If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned memory includes: various media that can store program codes, such as USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), mobile hard disks, magnetic disks, or optical discs.

[0073] The embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A chip screening method based on the artificial bee colony algorithm, characterized in that The method includes: Obtaining n chips to be processed and parameter information of the chips to be processed; Determining the parallel connection number m of the chips to be processed; Based on the parameter information of the chips to be processed, using the artificial bee colony algorithm, determining the sorting information of the n chips to be processed, and sequentially screening m parallel-connected chips according to the sorting information.

2. The method according to claim 1, wherein The step of, based on the parameter information of the chips to be processed, using the artificial bee colony algorithm, determining the sorting information of the n chips to be processed, and sequentially screening m parallel-connected chips according to the sorting information, includes: Step 1: Based on the parameter information of the chips to be processed, initializing the position of the employed bee's food source, where the position of the employed bee's food source corresponds to the initial sorting of the chips to be processed; Step 2: According to the fitness function, calculating the fitness value corresponding to the position of the employed bee's food source, obtaining the neighborhood solution and the fitness value corresponding to the neighborhood solution; wherein, the neighborhood solution is used to update the position of the employed bee's food source; Step 3: According to the comparison result of the fitness value corresponding to the current position of the employed bee's food source and the fitness value corresponding to the updated position of the employed bee's food source, determining the position of the observing bee; wherein, the observing bee is determined according to the preset observing bee position probability formula; Step 4: In response to the change in the fitness value of the position of the employed bee's food source being less than the preset threshold within the preset number of times, randomly generating a new set of positions of the employed bee's food source by the scout bee, and repeatedly executing Step 2 and Step 3 until the preset end condition is reached, so as to output the sorting information of the n chips to be processed, and sequentially screening m parallel-connected chips according to the sorting information.

3. The method according to claim 2, wherein The fitness function is determined according to the sum of the variances of the parameter information of the chips to be processed within each parallel group; and, When the number n of chips to be processed can divide the parallel connection number m of the chips to be processed evenly, the fitness function is defined as: Among them, represents the parameter information of the j-th chip in the i-th group, represents the average value of the parameters of the i-th chip.

4. The method according to claim 3, wherein When the number n of chips to be processed cannot divide the parallel connection number m of the chips to be processed evenly, the fitness function is defined as: Among them, .

5. The method according to claim 4, characterized in that, The preset observing bee position probability formula is expressed as: Among them, represents the probability of the position of the observed bee, represents the fitness of the position of the i-th worker bee, represents the total number of worker bees.

6. The method according to claim 5, wherein The step of, according to the fitness function, calculating the fitness value corresponding to the position of the employed bee's food source, obtaining the neighborhood solution and the fitness value corresponding to the neighborhood solution, includes: According to the fitness function and the position of the employed bee's food source, performing sub-interval exchange and reverse order crossover operations to generate a neighborhood solution.

7. The method according to any one of claims 1 to 6, characterized in that The chips to be processed include power semiconductor chips.

8. A chip screening system based on the artificial bee colony algorithm, characterized in that, The system includes: An obtaining module, configured to obtain n chips to be processed and parameter information of the chips to be processed; A first determining module, configured to determine the parallel connection number m of the chips to be processed; A second determining module, configured to, based on the parameter information of the chips to be processed, use the artificial bee colony algorithm to determine the sorting information of the n chips to be processed, and sequentially screen m parallel-connected chips according to the sorting information.

9. A storage medium, characterized in that, The computer program is stored in the storage medium, wherein the computer program is configured to implement the method according to any one of claims 1 to 7 when running.

10. An electronic device, comprising a memory and a processor, characterized in that, The computer program is stored in the memory, and the processor is configured to run the computer program to implement the method according to any one of claims 1 to 7.

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