A hybrid simulation method, electronic device and storage medium for the same interface

Abstract

The present invention relates to the field of chip design technology, and in particular to a hybrid simulation method, electronic device, and storage medium for the same interface. A verification platform allocates independent and non-overlapping address segments to each DMA module; the verification platform determines whether the current destination address is within the address segment, and if so, determines the operation OP to which the current data corresponding to the current destination address belongs. i For DMA operation, enter the non-joint simulation mode; wherein the non-joint simulation mode is used to compare the OP in the second verification model i Final replication results and first validation model in OP i The final copy results are identical; if not within the allocated address range, the system enters joint simulation mode. This mode compares the current data entry corresponding to the current destination address in the second verification model with the current data entry in the first verification model. This avoids the problem of increased code size due to synchronization, significantly reduces the amount of comparison computation, and shortens the development cycle.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a hybrid simulation method, electronic equipment and storage medium for the same interface. Background Art

[0002] With the continuous advancement of integrated circuit technology, control modules are becoming increasingly complex, placing higher demands on interface synchronization for the coordinated operation of their internal modules. When verifying control modules, co-simulation (COSIM) is often required to verify the synchronization logic of the same interface. For the direct memory access (DMA) module within the control module, since it uses the same interface as other components for data input and output, this places strict synchronization requirements on the reference model (Cmodel) and the RTL model used for verification.

[0003] Specifically, the Cmodel and RTL models must precisely synchronize every operation to accurately simulate actual operation and detect potential issues. The Cmodel operates at the software level, primarily focusing on the implementation of system functionality. Its operation relies on computer resources such as the processor and is unconstrained by physical factors such as wiring delays and gate delays in hardware circuits. RTL, on the other hand, describes the specific implementation of hardware circuits. Signal transmission and logic gate operations within the hardware circuits incur delays, which slow down data processing. Therefore, the Cmodel's data processing speed is faster than the RTL. When the RTL completes copying a piece of data, it promptly compares it with the Cmodel's data. If the two match, the copy operation is successful; otherwise, an error is reported. In practice, multiple DMA modules exist within the control module, and the DMA module and other modules share the same interface. This can lead to multiple modules competing for the same interface, meaning that the data on the same interface includes both DMA data and data from other modules, intertwining data from different modules. In this case, current verification requires that every operation on the same interface in the Cmodel and RTL be fully synchronized, resulting in a very large Cmodel codebase. Furthermore, in this case, the DMA verification logic uses the verification logic of other modules, requiring verification of whether the current data is DMA data. This slows the verification process and, in turn, increases the development cycle. Therefore, a method that can shorten the development cycle without increasing the Cmodel codebase is urgently needed. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention adopts a technical solution: a hybrid simulation method for the same interface, the method comprising the following steps:

[0005] S100: The verification platform allocates independent and non-overlapping address segments to each DMA module.

[0006] S200 , obtaining a first verification model and a second verification model, wherein the first verification model is a functional model of a chip to be tested, and the second verification model is a hardware model of the same chip to be tested.

[0007] S300, when the verification platform sends a DMA operation request req to the first verification model and the second verification model respectively, the req carries the stimulus stim, the source address Saddr, the destination address Daddr and the copied data length size; wherein, the DMA operation request is used to copy the data of the Saddr to the Daddr under the action of the stim.

[0008] S400, the verification platform determines that the second verification model is in the i-th interface interface i The current destination address Daddr i Is it within the address segment? If it is within the allocated address segment, determine the Daddr i The operation OP to which the current data belongs i For DMA operation, enter the non-joint simulation mode; wherein, the non-joint simulation mode is used to compare the OP in the second verification model i The final replication results and the first validation model described in OP i The final copy result is the same; if it is not in the allocated address segment, enter the joint simulation mode; wherein the joint simulation mode is used to compare the Daddr in the second verification model i Whether the corresponding current record data is the same as the current record data in the first verification model.

[0009] In addition, the present invention also provides a non-transitory computer-readable storage medium, which stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by a processor to implement the above method.

[0010] In addition, the present invention also provides an electronic device including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0011] The present invention has at least the following beneficial effects:

[0012] The present invention provides a hybrid simulation method, electronic device and storage medium for the same interface. The method allocates an independent and non-overlapping address segment to each DMA module through a verification platform. If the current address is within the allocated address segment, it is determined to be a DMA operation, and the result of the DMA operation is compared when the current DMA operation is completed; otherwise, the result is compared when each data is completed. The problem of increasing the amount of code due to synchronization is avoided, and the amount of comparison calculation is greatly reduced by comparing the DMA operation results, thereby accelerating the verification process and shortening the development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a hybrid simulation method for the same interface provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0017] See also Figure 1 , which shows a hybrid simulation method of the same interface, the method comprising the following steps:

[0018] S100: The verification platform allocates independent and non-overlapping address segments to each DMA module.

[0019] The verification platform is used for chip design verification. Numerous test cases are written based on the chip design specifications and then run on the verification platform to verify the correct implementation of the chip's various functions. The verification platform generates various stimulus signals, which are input into the verification model of the chip design to be verified. The platform also monitors the output response to determine whether it meets expectations.

[0020] The Direct Memory Access (DMA) module enables external devices to transfer data directly to and from memory, bypassing the CPU. DMA operations essentially transfer data from one memory location (source address) to another (destination address).

[0021] In one embodiment, when there are M DMA modules in the chip to be tested, in S100, the M DMA modules {DMA1, DMA2, ..., DMA j ,…,DMA M} address segment allocation, where DMA j For the jth DMA module, the value of j ranges from 1 to M, and also includes:

[0022] S110, obtain the address segment size to be allocated for each DMA module, which is recorded as {offset1, offset2, ..., offset j ,…,offset M}, offset j DMA j The address segment size;

[0023] S120, maintaining a free address space list, wherein the free address space list records information of all available continuous free address segments in the system, each free address segment being represented by a starting address and a length;

[0024] S130, traverse the free address space list to find whether there is a continuous free address segment whose length is sufficient to accommodate the total address segment size required by the M DMA modules, where the total address segment size offset_total=offset1+offset2+...offset j …+offset M ;

[0025] S131, if a continuous free address segment with a length not less than offset_total is found in the free address space list, set the starting address of the continuous free address segment as start_addr, and allocate address segments to the M DMA modules in sequence, where j Allocate from start_addr+∑ i=1 j-1 offset i Start with length offset jAfter the allocation is completed, the free address space list is updated, the allocated address segment is removed from the free address space list, if there is a remaining free address segment after allocation, then update its starting address and length information.

[0026] S132: If no continuous free address segments of sufficient length are found, a greedy algorithm is used to allocate space for the address segments of multiple DMA modules to reduce fragmentation. The specific steps are as follows:

[0027] S1321, sort the M DMA modules from large to small according to the size of the address segment to be allocated, and obtain a new sequential DMA S1 ,DMA S2 , …,DMA SM , where offset S1 ≥offset S2 ≥…≥offset SM ; Select the free address segment with the smallest starting address from the free address space list, set its starting address to cur_start_addr and its length to cur_len;

[0028] S1322, try to allocate address segments to the sorted DMA modules in sequence: For the first DMA module DMA S1 , if cur_len ≥ offset S1 , it will start from cur_start_addr and the length will be offset S1 The address segment is assigned to DMA S1 , update cur_start_addr=cur_start_addr+offset S1 ,cur_len=cur_len-offset S1 For the kth new sequence of DMA module DMA Sk , if cur_len ≥ offset Sk , then it will continue from cur_start_addr and the length will be offset Sk The address segment is assigned to DMA Sk , and similarly update cur_start_addr and cur_len; otherwise, stop allocating in the current free address segment, select the next free address segment with the smallest starting address from the free address space list, and repeat the above allocation process. Each time an address segment allocation is completed, update the free address space list, remove the allocated free address segment, or update the starting address and length information of the remaining free address segments.

[0029] S1323, repeat step S1322 until all DMA modules have completed the allocation attempts.

[0030] The address segment allocation method provided in steps S110-130 can reasonably allocate address segments to M DMA modules under different address space conditions, thereby achieving the purpose of allocating multiple DMA address segments to a continuous space to reduce fragmentation. It should be noted that other address segment allocation methods also fall within the scope of protection of the present invention.

[0031] S200 , obtaining a first verification model and a second verification model, wherein the first verification model is a functional model of a chip to be tested, and the second verification model is a hardware model of the same chip to be tested.

[0032] The first verification model and the second verification model are different verification models of the same chip to be tested, and therefore both have the same interface and the same input stimulus.

[0033] In one embodiment, the first verification model is a Cmodel model, a SystemC model, a Python model, or a gate-level netlist verification model, etc. Other types of verification models also fall within the protection scope of the present invention.

[0034] In one embodiment, the second verification model is RTL (Register Transfer Level model) or VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language model). Other types of register transfer level verification modules fall within the scope of protection of the present invention.

[0035] S300, when the verification platform sends a DMA operation request req to the first verification model and the second verification model respectively, the req carries the stimulus stim, the source address Saddr, the destination address Daddr and the copied data length size; wherein, the DMA operation request is used to copy the data of the Saddr to the Daddr under the action of the stim.

[0036] Among them, stimulus is a combination of signals used to control DMA operation behavior, including clock signals, enable signals, control signals, etc., which are used to simulate different working scenarios and conditions and drive the DMA module to operate as expected.

[0037] The source address is the address where the DMA operation reads data, which is an address in the memory or peripheral device.

[0038] The destination address is the address where the DMA operation writes data, and is also an address in the memory or peripheral device.

[0039] The data length is the amount of data to be copied by the DMA operation.

[0040] In one embodiment, the DMA operation request req is used to request to copy data from one area of ​​the memory to another area, or to request to transfer data in the peripheral device to the memory, or to request to transfer data in the memory to the peripheral device. Other types of DMA operation requests also fall within the scope of protection of the present invention.

[0041] S400, the verification platform determines that the second verification model is in the i-th interface interface i The current destination address Daddr i Is it within the address segment? If it is within the allocated address segment, determine the Daddr i The operation OP to which the current data belongs i For DMA operation, enter the non-joint simulation mode; wherein, the non-joint simulation mode is used to compare the OP in the second verification model i The final replication results and the first validation model described in OP i The final copy result is the same; if it is not in the allocated address segment, enter the joint simulation mode; wherein the joint simulation mode is used to compare the Daddr in the second verification model i Whether the corresponding current record data is the same as the current record data in the first verification model.

[0042] In one embodiment, when the address segments allocated by all DMA modules are allocated to a continuous free address segment, S400 further includes determining whether the Daddr i Is it within the address range? i Compared with the dedicated address segment, when Dadr i When falling into the dedicated address segment, determine Daddr i within the address segment.

[0043] In one embodiment, when all DMA modules are not allocated to a continuous free address segment, S400 further includes determining the Daddr i Is it within the address range? i Compare with the multiple address segments allocated by all DMA modules respectively. i When it falls into one of the address segments, determine Daddr i within the address segment.

[0044] Each DMA operation includes multiple data. Assume that when a DMA operation includes U-pieces of data, when all the U-pieces of data are completed, the DMA operation is completed.

[0045] It should be noted that for DMA operations, the final copy result of each DMA operation is compared in non-joint simulation mode; for non-DMA operations, each data set is compared for identity in joint simulation mode. Therefore, by using non-joint simulation mode to verify the correctness of DMA operations, not only can the code size increase caused by synchronizing DMA operations between the first and second verification models be avoided while ensuring that other verification processes in the system are completely unaffected, but it also eliminates the need for frequent comparisons of intermediate copy processes for correctness, significantly reducing the computational complexity of these comparisons.

[0046] In summary, the present invention provides a hybrid simulation method for the same interface, which allocates independent and non-overlapping address segments to each DMA module through a verification platform. If the current address is within the allocated address segment, it is determined to be a DMA operation, and the results of the DMA operation are compared when the current DMA operation is completed; otherwise, the results are compared when each data is completed. This avoids the problem of increasing the amount of code due to synchronization, and greatly reduces the amount of comparison calculations by comparing the DMA operation results, thereby accelerating the verification process and shortening the development cycle.

[0047] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0048] An embodiment of the present invention further provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0049] An embodiment of the present invention further provides a computer program product comprising program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0050] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0051] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A hybrid simulation method for the same interface, characterized in that: The method comprises the following steps: S100, verifying that the platform allocates independent and non-overlapping address segments to each DMA module; S200, obtaining a first verification model and a second verification model, wherein the first verification model is a functional model of a chip to be tested, and the second verification model is a hardware model of the same chip to be tested; S300, when the verification platform sends a DMA operation request req to the first verification model and the second verification model respectively, the req carries a stimulus stim, a source address Saddr, a destination address Daddr, and a copied data length size; wherein the DMA operation request is used to copy the data of the Saddr to the Daddr under the action of the stim; S400, the verification platform determines that the second verification model is in the i-th interface interface i The current destination address Daddr i Is it within the address segment? If it is within the allocated address segment, determine the Daddr i The operation OP to which the current data belongs i For DMA operation, enter the non-joint simulation mode; wherein, the non-joint simulation mode is used to compare the OP in the second verification model i The final replication results and the first validation model described in OP i The final copy result is the same; if it is not in the allocated address segment, enter the joint simulation mode; wherein the joint simulation mode is used to compare the Daddr in the second verification model i Whether the corresponding current record data is the same as the current record data in the first verification model.

2. The method according to claim 1, characterized in that When the address segments allocated by all DMA modules are allocated to a continuous free address segment, S400 also includes judging the Daddr i Is it within the address range? i Compared with the address segment, when Dadr i When it falls into the address segment, determine Daddr i within the address segment.

3. The method according to claim 1, characterized in that When all DMA modules are not allocated to a continuous free address segment, S400 also includes determining the Daddr i Is it within the address range? i Compare with the multiple address segments allocated by all DMA modules respectively. i When it falls into one of the address segments, determine Daddr i within the address segment.

4. The method according to claim 1, wherein When there are M DMA modules in the chip to be tested, the M DMA modules {DMA1, DMA2, ..., DMA j ,…,DMA M } address segment allocation, where DMA j For the jth DMA module, the value of j ranges from 1 to M, and also includes: S110, obtain the address segment size to be allocated for each DMA module, which is recorded as {offset1, offset2, ..., offset j ,…,offset M }, offset j DMA j The address segment size; S120, maintaining a free address space list, wherein the free address space list records information of all available continuous free address segments in the system, each free address segment being represented by a starting address and a length; S130, traverse the free address space list to find whether there is a continuous free address segment whose length is sufficient to accommodate the total address segment size required by the M DMA modules, where the total address segment size offset_total=offset1+offset2+...offset j …+offset M ; S131, if a continuous free address segment with a length not less than offset_total is found in the free address space list, set the starting address of the continuous free address segment as start_addr, and allocate address segments to the M DMA modules in sequence, where j Allocate from start_addr+∑ i=1 j-1 offset i Start with length offset j After the allocation is completed, the free address space list is updated, the allocated address segment is removed from the free address space list, if there is a remaining free address segment after allocation, then update its starting address and length information.

5. The method according to claim 4, characterized in that The S130 also includes: S132: If no continuous idle address segments of sufficient length are found, a greedy algorithm is used to allocate space for the address segments of multiple DMA modules.

6. The method according to claim 5, characterized in that The S132 also includes: S1321, sort the M DMA modules from large to small according to the size of the address segment to be allocated, and obtain a new sequential DMA S1 ,DMA S2 , …,DMA SM , the size of the address segment to be allocated is offset S1 ≥offset S2 ≥…≥offset SM ; Select the free address segment with the smallest starting address from the free address space list, set its starting address to cur_start_addr and its length to cur_len; S1322, try to allocate address segments to the sorted DMA modules in sequence: For the first DMA module DMA S1 , if cur_len ≥ offset S1 , it will start from cur_start_addr and the length will be offset S1 The address segment is assigned to DMA S1 , update cur_start_addr=cur_start_addr+offset S1 ,cur_len=cur_len-offset S1 ; For the kth new sequence DMA module DMA Sk , if cur_len ≥ offset Sk , then it will continue from cur_start_addr and the length will be offset Sk The address segment is assigned to DMA Sk , and update cur_start_addr and cur_len in the same way; otherwise, stop the allocation attempt in the current free address segment, select the next free address segment with the smallest starting address from the free address space list, and repeat the above allocation process; each time an address segment allocation is completed, update the free address space list, remove the allocated free address segment, or update the starting address and length information of the remaining free address segments; S1323, repeat step S1322 until all DMA modules have completed the allocation attempts.

7. The method according to claim 1, characterized in that The first verification model is a Cmodel model, and the second verification model is an RTL model.

8. The method according to claim 1, characterized in that The req is used to request to copy data from one area of ​​the memory to another area, or to request to transfer data in the peripheral device to the memory, or to request to transfer data in the memory to the peripheral device.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by a processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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