2.5 D integrated circuit test scheduling optimization method based on constrained differential evolution algorithm

Abstract

The invention discloses a 2.5 D integrated circuit test scheduling optimization method based on a constrained differential evolution algorithm, belongs to the field of integrated circuit test optimization, and aims to solve the problems of complex solution, low precision and low speed of the existing test scheduling method. The method comprises the following steps: step 1, establishing a 2.5 D integrated circuit test scheduling model under power consumption constraint; 2, obtaining related parameters of 2.5 D integrated circuit test scheduling, designing a discrete coding and decoding strategy, and setting initialization parameters of a constraint differential evolution algorithm; 3, performing iterative evolution on the initial population by using an improved constraint differential evolution algorithm to generate a new solution; 4, updating the population and control parameters; and 5, judging a stop condition, and outputting an optimal solution.

Description

Technical Field

[0001] The present invention relates to a method for optimizing the test scheduling of 2.5D integrated circuits based on a constrained differential evolution algorithm, belonging to the field of integrated circuit test optimization. Background Art

[0002] Integrated circuits are the foundation and support of the information age and play a key role in fields such as the Internet of Things, cloud computing, artificial intelligence, and 5G communication. With the development of integrated circuit packaging technology, 2.5D integrated circuits using through-silicon via technology have become a hot area of concern in the semiconductor industry. 2.5D integrated circuits integrate different types of IP cores and wafers with different functions on a passive silicon interposer, and achieve interconnection between wafers and between wafers and the substrate through the interposer, which can effectively improve the integration scale of the circuit, but at the same time bring greater difficulties to the testing process.

[0003] The structured testability design of integrated circuits mainly includes scan design testing and built-in self-test (BIST). Scan testing converts the sequential circuits in the circuit into combinational circuits, and the test vectors are input from the input end of the scan chain and the test responses are output from the output end of the scan chain by an automatic test equipment. In this method, the test rate of the integrated circuit is limited by the test equipment, and high-performance test equipment will increase the test cost. BIST includes test circuits inside the chip, and only by inputting the corresponding control signals can the comparison result between the actual output response and the expected response be obtained, getting rid of the dependence on expensive test equipment, but it sacrifices a certain fault coverage rate and is generally used in the testing of memory circuits. Since 2.5D integrated circuits can stack more wafers of different types and functions, they have a large number of optional test scheduling schemes, and there are differences in the cost overhead of different test schemes. At the same time, in order to shorten the test time, wafers usually need to be tested in parallel, but excessive power consumption will cause chip damage, so a test scheduling strategy with power consumption constraints needs to be considered.

[0004] Currently, the integrated circuit test scheduling problem is mainly solved by traditional mathematical programming methods or heuristic optimization algorithms, but there are still drawbacks in terms of solving efficiency and solving accuracy. Traditional mathematical programming methods require an accurate test scheduling model and require a large amount of computing time to solve complex large-scale test scheduling problems; while existing heuristic algorithms lack the ability to handle constraints in the process of solving the 2.5D integrated circuit test scheduling problem with power consumption constraints, and are prone to falling into local optima and unable to obtain satisfactory results due to the influence of algorithm parameter settings and search strategies.

[0005] In summary, 2.5D integrated circuits use the interposer technology based on through-silicon vias to effectively improve the integration density and scale of wafers, but at the same time, it also brings new challenges to testing. In the post-bonding test of wafers and interposers, multiple BIST test architectures are usually used to perform parallel tests on the wafers on the interposer. However, this will increase the hardware overhead, and at the same time, the power consumption constraints under parallel testing need to be considered. It is very difficult to solve such problems with traditional mathematical programming methods. Summary of the Invention

[0006] To solve the problems of complex solution, low accuracy, and slow speed of existing test scheduling methods, the present invention provides an optimization method for 2.5D integrated circuit test scheduling based on a constrained differential evolution algorithm.

[0007] The optimization method for 2.5D integrated circuit test scheduling based on the constrained differential evolution algorithm of the present invention includes the following steps:

[0008] Step 1: Establish a test scheduling model for 2.5D integrated circuits under power consumption constraints;

[0009] Step 2: Obtain the parameters related to 2.5D integrated circuit test scheduling, design a discrete encoding and decoding strategy, and set the initialization parameters of the constrained differential evolution algorithm;

[0010] Step 3: Use the improved constrained differential evolution algorithm to iteratively evolve the initial population to generate new solutions;

[0011] Step 4: Update the population and control parameters;

[0012] Step 5: Judge the stop condition and output the optimal solution.

[0013] Preferably, the model in Step 1 is:

[0014] Assume that a 2.5D integrated circuit with d wafers stacked on a passive silicon interposer is to be tested. The wafers to be tested are divided into n test chains. Different test chains are independent of each other and can be tested simultaneously, but the wafers on the same test chain must be serially tested in sequence, and the total power consumed by the test at any time needs to meet the maximum power consumption constraint P max ;

[0015] According to the optimization objective and the maximum power consumption constraint, the optimization function of this model is determined as:

[0016]

[0017] In the formula, F is the comprehensive cost of 2.5D integrated circuit testing, a is the testing cost per unit time of the integrated circuit, b is the hardware cost of implementing a test chain in the integrated circuit, m j is the number of wafers on the jth test chain, is the test time of the j-th test chain; where is expressed as:

[0018]

[0019] In the formula, TL i represents the test length of the i-th wafer, f represents the frequency of the test clock, and y ijl is a binary variable. If the i-th wafer is in the l-th position of the j-th test chain, then y ijl is 1, otherwise it is 0;

[0020] P i represents the test power of the i-th wafer;

[0021] δ i (t) represents whether the i-th wafer is being tested at time t. If it is being tested, it is 1, otherwise it is 0;

[0022] T j(l-1) represents the time when the (l - 1)-th wafer on the j-th test chain is tested. T jl represents the time when the l-th wafer on the j-th test chain is tested, and it satisfies that the start test time T of the j-th test chain j0 = 0.

[0023] Preferably, the constraint violation level G is obtained according to the following formula:

[0024]

[0025] Preferably, the specific process of step two includes:

[0026] Step 21: Determine the number d of wafers to be tested, the maximum allowable test power consumption P max , the maximum number of evaluations FES of the algorithm max , the population size NP, and the parameter storage size H. Initialize the scaling factor parameter archive MF h and the crossover rate parameter archive MCR h as vectors of length H with element values of 0.5, where h ∈ {1, 2, 3};

[0027] Step 22: Randomly generate an initial population P of d dimensions with NP individuals within (0, d) 0 = {x1, x2,..., x NP}, where each individual x r = {x r,1 , x r,2 ,..., x r,s ,..., x r,d}, r ∈ {1, 2,..., NP} represents a test scheduling scheme, and each individual has d dimensions;

[0028] Step 23. Design a discrete encoding and decoding strategy to encode and map the individuals in the population into test scheduling schemes. First, sequentially number each dimension of the individual to represent the serial number of the wafer to be tested. Then, sort the values of each dimension in the individual in ascending order, and the dimension numbers will change positions accordingly. Round up each dimension of the individual. If the rounded-up values are the same, it means that the wafers corresponding to the dimension numbers are on the same test chain, and the arrangement order of the wafers on the same test chain is the arrangement order of the corresponding dimension numbers.

[0029] Step 24. Evaluate the test scheduling scheme represented by each individual in the initial population, and calculate the objective function value F and the constraint violation level G of the population.

[0030] Preferably, the specific process of step three includes:

[0031] Step 31. Uniformly divide the population into an elite sub-population EP, an intermediate sub-population MP, and a disadvantaged sub-population IP according to the individual performance.

[0032] Step 32. Perform differential mutation and crossover operations to generate new solutions.

[0033] Step 33. Evaluate the new solutions. The newly generated population is denoted as Pn. Decode the newly generated trial vectors, and calculate the objective function value Fn and the constraint violation Gn corresponding to the trial vectors in the new population.

[0034] Preferably, the specific process of step four is:

[0035] Step 41. Normalize the objective function value and the constraint violation level.

[0036] Use {F, Fn} to represent the union of the objective function values of the original population and the new population. The following formula is used to normalize the objective function value F(x r corresponding to the individual x in the original population r ) to obtain the corresponding normalized objective function value F_nor r :

[0037]

[0038] where θ is a number between (10 -8 , 10 -5 );

[0039] The following formula is used to normalize the objective function value Fn(x r corresponding to the individual x in the new population r ) to obtain the corresponding normalized objective function value Fn_nor r :

[0040]

[0041] Use {G, Gn} to represent the union of the constraint violation levels of the original population and the new population. The following formula is used to normalize the constraint violation level G(x r corresponding to the individual x in the original population to obtain the corresponding normalized objective function value G_nor r ) as follows: r :

[0042]

[0043] The following formula is used to normalize the constraint violation level Gn(x r corresponding to the individual x in the new population to obtain the corresponding normalized objective function value Gn_nor r ) as follows: r :

[0044]

[0045] Step 42: Update the individuals in the population; use flag r to mark whether the r-th individual in the population uses the experimental vector to replace the original individual. If it is replaced, it is 1; if it is retained, it is 0. Use FR to represent the proportion of solutions that satisfy the constraint conditions in the current population. The expression formula of flag r is as follows:

[0046]

[0047] Step 43: Update the control parameters; record the crossover rate SCR h and the scaling factor SF h of the sub-population successfully entering the next generation. Update the parameter archive according to the following formula:

[0048]

[0049] In the formula, g is the population iteration number, and v is the serial number of the parameter archive. When v > H, reset v to 1 to overwrite the archive. When the SCR h and SF h corresponding to the new population are empty, the parameter archive will not be updated. MCR h,v,g+1 represents the updated value of the (g + 1)-th population iteration of the v-th element in the crossover rate parameter archive MCR h , and MF h,v,g+1 represents the updated value of the (g + 1)-th population iteration of the v-th element in the scaling factor parameter archive MF h ;

[0050] mean WA (SCR h ) represents the weighted average of SCR h , meanWL (SF h ) represents the Lehmer mean of SF h and is calculated according to the following formula:

[0051]

[0052] In the formula, SCR h,k represents the k-th success parameter in SCR h , and SF h,k represents the k-th success parameter in SF h ;

[0053] w k represents the weight value of the k-th success parameter and is calculated according to the following formula:

[0054]

[0055] In the formula, Δf k and Δf m respectively represent the fitness improvement values brought by the k-th and m-th success parameters, and Δf k

[0056] is calculated according to the following formula:

[0057] Δf k = |Fn_nor k - F_nor k + Gn_nor k - G_nor k |

[0058] In the formula, Fn_nor k represents the normalized objective function value of the k-th successful individual in the new population, F_nor k represents the normalized objective function value of the k-th successful individual in the original population, Gn_nor k represents the normalized constraint violation level of the k-th successful individual in the new population, and G_nor k represents the normalized constraint violation level of the k-th successful individual in the original population.

[0059] Preferably, the specific process of step five is: repeat steps three and four until the maximum number of evaluations FES max is satisfied, and output the optimal solution obtained by the algorithm and the corresponding test scheduling scheme and cost.

[0060] Advantages of the present invention: The present invention designs an improved constrained differential evolution algorithm and a discrete encoding and decoding strategy, which can efficiently solve the test scheduling optimization problem of 2.5D integrated circuits under power consumption constraints, obtain an excellent test scheduling scheme to improve the test efficiency of integrated circuits, and thus reduce the comprehensive test cost. Specifically, it includes:

[0061] (1) The differential evolution algorithm is an intelligent optimization algorithm with a simple structure and high search efficiency. The present invention uses an improved differential evolution algorithm to introduce a new constraint handling method, which can well solve the constrained optimization problem, and has the advantages of simple implementation, strong robustness, and high solution efficiency compared with traditional mathematical programming methods.

[0062] (2) Using the improved constrained differential evolution algorithm and discrete encoding and decoding strategy can efficiently solve the test scheduling problem of 2.5D integrated circuits under power consumption constraints, obtain an ideal test scheduling scheme, thereby improving the test efficiency of 2.5D integrated circuits and reducing the test hardware consumption and time cost. Description of the Drawings

[0063] Figure 1 is a schematic diagram of the test scheduling of 2.5D integrated circuits under power consumption constraints;

[0064] Figure 2 is a schematic diagram of the individual encoding and decoding process;

[0065] Figure 3 is a flowchart of the 2.5D integrated circuit test scheduling method based on the constrained differential evolution algorithm of the present invention. Detailed Embodiments

[0066] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the scope of protection of the present invention.

[0067] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0068] Next, the present invention will be further described in conjunction with the accompanying drawings and specific embodiments, but it is not a limitation of the present invention.

[0069] Detailed Embodiment 1: Next, in conjunction with Figures 1 to 3 This embodiment is described. The 2.5D integrated circuit test scheduling optimization method based on the constrained differential evolution algorithm described in this embodiment includes the following steps:

[0070] Step 1: Establish a test scheduling model for 2.5D integrated circuits under power consumption constraints;

[0071] Step 2: Obtain the relevant parameters of the 2.5D integrated circuit test scheduling, design a discrete encoding and decoding strategy, and set the initialization parameters of the constrained differential evolution algorithm;

[0072] Step 3: Use the improved constrained differential evolution algorithm to iteratively evolve the initial population to generate new solutions;

[0073] Step 4: Update the population and control parameters;

[0074] Step 5: Judge the stop condition and output the optimal solution.

[0075] The model described in Step 1 is:

[0076] (1) Model definition: Assume that a 2.5D integrated circuit with d wafers stacked on a passive silicon interposer is tested. The wafers to be tested are divided into n test chains. Different test chains are independent of each other and can be tested simultaneously, but the wafers on the same test chain must be serially tested in sequence, and the total power consumed during the test at any time needs to satisfy the maximum power consumption constraint P max ; as Figure 1 shown in the schematic diagram of the 2.5D integrated circuit test scheduling under power consumption constraint.

[0077] (2) Construct the objective function: The optimization objective of the 2.5D integrated circuit test scheduling model is to minimize the test hardware overhead and test time cost, and its objective function is expressed as:

[0078]

[0079] In the formula, a is the test cost per unit time of the integrated circuit, b is the hardware cost of implementing a test chain in the integrated circuit, is the test time of the jth test chain, and the comprehensive test cost of the 2.5D integrated circuit is the sum of the hardware overhead and the time overhead. Among them can be expressed as:

[0080]

[0081] In the formula, TL i represents the test length of the ith wafer, f represents the frequency of the test clock, m j is the number of wafers on the jth test chain, y ijl is a binary variable. If the ith wafer is in the lth position of the jth test chain, then y ijl is 1, otherwise it is 0.

[0082] (3) Calculate the constraint violation: The main constraint of the 2.5D integrated circuit test scheduling model is the power consumption constraint. Use P i to represent the test power of the ith wafer, then its constraint violation level can be expressed as:

[0083]

[0084] As can be seen from the test scheduling model, the total power of parallel tests at any time cannot exceed the maximum power consumption constraint. In formula (3), δ i (t) represents whether the i-th wafer is being tested at time t. If it is being tested, it is 1; otherwise, it is 0.

[0085] T j(l-1) represents the time when the (l - 1)-th wafer on the j-th test chain is tested, and T jl represents the time when the l-th wafer on the j-th test chain is tested, and it satisfies that the start time T j0 of the j-th test chain is 0.

[0086] In summary, according to the optimization objective and the maximum power consumption constraint, the optimization function of this model is determined as:

[0087]

[0088] The specific process of step two includes:

[0089] Step 21: Determine the number d of wafers to be tested, the maximum allowable test power consumption P max , the maximum number of evaluations FES of the algorithm max , the population size NP, and the parameter storage size H. Initialize the scaling factor parameter archive MF h and the crossover rate parameter archive MCR h as vectors of length H with element values of 0.5, where h ∈ {1, 2, 3};

[0090] Step 22: Randomly generate an initial population P 0 of dimension d with NP individuals within (0, d), where P NP = {x1, x2, …, x r}, and each individual x r,1 = {x r,2 , x r,s , …, x r,d}, r ∈ {1, 2, …, NP} represents a test scheduling scheme, and each individual has d dimensions;

[0091] Step 23: Design a discrete encoding and decoding strategy to encode the individuals in the population and map them to test scheduling schemes. First, sequentially number each dimension of the individual to represent the serial number of the wafer to be tested. Then, sort the values of each dimension in the individual in ascending order, and the dimension numbers change positions accordingly. Round up each dimension of the individual. If the rounded-up values are the same, it means that the wafers corresponding to the dimension numbers are on the same test chain, and the arrangement order of the wafers on the same test chain is the arrangement order of the corresponding dimension numbers. Figure 2 shows the schematic diagram of the encoding and decoding process of the individual.

[0092] Step 24: Evaluate the test scheduling scheme represented by each individual in the initial population, and calculate the objective function value F (total test cost) and constraint violation level G (level exceeding the power consumption constraint) of the population.

[0093] The specific process of Step 3 includes:

[0094] Step 31: Uniformly divide the population into an elite sub-population EP, an intermediate sub-population MP, and a disadvantaged sub-population IP according to individual performance;

[0095] Division principle: Divide the sub-population according to individual performance. The solution that satisfies the power consumption constraint, i.e., G = 0, is called a feasible solution, otherwise it is called an infeasible solution. Sort the individuals in the population according to the following rules: 1) Feasible solutions are superior to infeasible solutions; 2) When all are feasible solutions, the solution with a smaller objective function value is dominant; 3) When all are infeasible solutions, the solution with a smaller constraint violation degree is dominant. The sorting value of individual r in the obtained population is denoted as rank c (r), and at the same time sort the individuals in the population in ascending order according to the objective function value, and the obtained sorting value is denoted as rank f (r). Assume that the proportion of feasible solutions in the population is FR. The relative performance of individuals in the population can be obtained by weighting the above sorting values:

[0096] RANK(r) = (1 - FR) × rank c (r) + FR × rank f (r) (5)

[0097] Individuals with smaller overall sorting values are considered to have better performance. The population is uniformly divided into three sub-populations according to the overall sorting value RANK(r): the elite sub-population EP, the intermediate sub-population MP, and the disadvantaged sub-population IP.

[0098] Step 32: Perform differential mutation and crossover operations to generate new solutions;

[0099] The present invention uses a variety of mutation strategies to update the individuals in the population to balance the exploitation and exploration capabilities of the population. The following mutation operations are respectively performed on the divided sub-populations:

[0100]

[0101] It can be seen from formula (6) that different sub-populations adopt mutation strategies with different characteristics and different control parameters at the same time, so as to balance the exploitation and exploration of the population. Where x r1 , x r2 , x r3 are randomly selected individuals from the population, x re is a randomly selected individual from the elite sub-population, x best is the individual with the best overall sorting value in the population, xpbest Randomly select individuals from the top p×100% in the population, where p is 0.11. F h Randomly generated from a Cauchy distribution with a mean of μF h and a variance of 0.1, that is, F h = randc(μF h , 0.1); CR h Randomly generated from a Gaussian distribution with a mean of μCR h and a variance of 0.1, that is, CR h = randn(μCR h , 0.1), where h ∈ {1, 2, 3}. μF h and μCR h are randomly selected from different parameter archives MF h and MCR h respectively. The target vector x r and the mutant vector v r generate a trial vector u r through a crossover operation. Use s rand to represent a randomly selected dimension. The crossover operation can be expressed as follows:

[0102]

[0103] Step 33: Evaluate the new solution; the newly generated population is denoted as Pn. Decode the newly generated trial vectors and calculate the objective function values Fn and constraint violations Gn corresponding to the trial vectors in the new population.

[0104] The specific process of Step 4 is as follows:

[0105] Step 41: Normalize the objective function value and the constraint violation level;

[0106] Use {F, Fn} to represent the union of the objective functions of the original population and the new population. The following formula is used to normalize the objective function value F(x r ) corresponding to the individual x r in the original population to obtain the corresponding normalized objective function value F_nor r :

[0107]

[0108] where θ is a number between (10 -8 , 10 -5 ). Set θ as a very small positive number to avoid a zero denominator;

[0109] The following formula is used to normalize the objective function value Fn(x r ) corresponding to the individual x r)Normalize to obtain the corresponding normalized objective function value Fn_nor r :

[0110]

[0111] Use {G, Gn} to represent the union of the constraint violation levels of the original population and the new population. The following formula is used to normalize the constraint violation level G(x r corresponding to the individual x in the original population r ) to obtain the corresponding normalized objective function value G_nor r :

[0112]

[0113] The following formula is used to normalize the constraint violation level Gn(x r corresponding to the individual x in the new population r ) to obtain the corresponding normalized objective function value Gn_nor r :

[0114]

[0115] Step 42: Update the individuals in the population; Use flag r to mark whether the r-th individual in the population uses the experimental vector to replace the original individual. If it is replaced, it is 1; if it is retained, it is 0. Use FR to represent the proportion of solutions that satisfy the constraint conditions in the current population. The expression formula of flag r is as follows:

[0116]

[0117] Step 43: Update the control parameters; Record the crossover rate SCR h and the scaling factor SF h of the subpopulation successfully entering the next generation, and update the parameter archive according to the following formula:

[0118]

[0119] In the formula, g is the population iteration number, v is the serial number of the parameter archive. When v > H, reset v to 1 to overwrite the archive. When the SCR h and SF h corresponding to the new population are empty, the parameter archive will not be updated. MCR h,v,g+1 represents the updated value of the (g + 1)-th population iteration of the v-th element in the crossover rate parameter archive MCR h , and MF h,v,g+1 represents the updated value of the (g + 1)-th population iteration of the v-th element in the scaling factor parameter archive MF h ;

[0120] In Formulas (13) and (14), mean WA (SCR h ) represents the weighted average of SCR h , and mean WL (SF h ) represents the Lehmer mean of SF h , and is calculated as follows:

[0121]

[0122] Wherein, SCR h,k represents the k-th success parameter in SCR h , and SF h,k represents the k-th success parameter in SF h ;

[0123] w k represents the weight value of the k-th success parameter, and is calculated as follows:

[0124]

[0125] Wherein, Δf k and Δf m respectively represent the fitness improvement values brought by the k-th and m-th success parameters, and the calculation methods of the two variables are the same, wherein Δf k is calculated as follows:

[0126] Δf k =|Fn_nor k -F_nor k +Gn_nor k -G_nor k | (18)

[0127] Wherein, Fn_nor k represents the normalized objective function value of the k-th successful individual in the new population, F_nor k represents the normalized objective function value of the k-th successful individual in the original population, Gn_nor k represents the normalized constraint violation level of the k-th successful individual in the new population, and G_nor k represents the normalized constraint violation level of the k-th successful individual in the original population.

[0128] The sum of the fitness improvement values brought by all the success parameters in SCR h is Formula (17) calculates the proportion of the fitness improvement value brought by the k-th success parameter.

[0129] Step 5: Determine the stopping condition and output the optimal solution. Repeat Steps 3 and 4 until the maximum number of function evaluations FES is satisfied max , and output the optimal solution obtained by the algorithm, the corresponding test scheduling scheme, and the cost.

[0130] Through the above steps, an ideal test scheduling scheme for the 2.5D integrated circuit test scheduling model under power consumption constraints and the corresponding test cost can be obtained. Decision-makers can adopt this scheduling scheme to improve test efficiency and reduce the comprehensive test cost. Figure 3 The flowchart of the 2.5D integrated circuit test scheduling method based on the constrained differential evolution algorithm is shown.

[0131] Although the present invention has been described herein with reference to particular embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Accordingly, it should be understood that numerous modifications may be made to the exemplary embodiments, and other arrangements may be designed, provided they do not depart from the spirit and scope of the invention as defined by the appended claims. It should be understood that the features described in the different dependent claims and in the present description may be combined in a manner different from that described in the original claims. It should also be understood that the features described in connection with a particular embodiment may be used in other described embodiments.

Claims

1. A 2.5D integrated circuit test scheduling optimization method based on a constrained differential evolution algorithm, characterized in that, The method includes the following steps: Step 1: Establish a 2.5D integrated circuit test scheduling model under power consumption constraints; Step 2: Obtain parameters related to 2.5D integrated circuit test scheduling, design a discrete encoding and decoding strategy, and set the initial parameters of the constrained differential evolution algorithm; Step 3: Use the improved constrained differential evolution algorithm to iteratively evolve the initial population to generate new solutions; Step 4: Update the population and control parameters; Step 5: Judge the stop condition and output the optimal solution.

2. The 2.5D integrated circuit test scheduling optimization method based on the constrained differential evolution algorithm according to claim 1, wherein The model described in Step 1 is: Suppose a 2.5D integrated circuit with d wafers stacked on a passive silicon interposer is tested. The wafers to be tested are partitioned into n test chains. Different test chains can be tested independently and simultaneously, but the wafers on the same test chain must be tested serially in sequence, and the total power consumed during testing at any given time needs to satisfy the maximum power consumption constraint P max ; According to the optimization objective and the maximum power consumption constraint, the optimization function of this model is determined as: In the formula, F is the comprehensive cost of 2.5D integrated circuit testing, a is the testing cost of the integrated circuit per unit time, b is the hardware cost of implementing a test chain in the integrated circuit, m j is the number of wafers on the j-th test chain, is the testing time of the j-th test chain; among which is expressed as: where TL i represents the test length of the i-th wafer, f represents the frequency of the test clock, and y ijl is a binary variable, and y is 1 if the i-th wafer is in the l-th position of the j-th test chain, otherwise it is 0; ijl ​ P i represents the test power of the i-th wafer; δ i (t) indicates whether the i-th wafer is being tested at time t. If it is being tested, it is 1; otherwise, it is 0. T j(l-1) represents the time when the (l - 1)-th wafer on the j-th test chain is tested, T jl represents the time when the l-th wafer on the j-th test chain is tested, and the starting time T of the j-th test chain j0 = 0.

3. The 2.5D integrated circuit test scheduling optimization method based on the constrained differential evolution algorithm according to claim 2, wherein The constraint violation level G is obtained according to the following formula:

4. The 2.5D integrated circuit test scheduling optimization method based on the constrained differential evolution algorithm according to claim 3, wherein The specific process of Step 2 includes: Step 21: Determine the number d of wafers to be measured and the maximum allowable test power consumption P max , the maximum number of evaluations FES of the algorithm max , the population size NP and the parameter storage size H, and initialize the scaling factor parameter archive MF of the sub-population h and the crossover rate parameter archive MCR h as a vector of length H with element values of 0.5, where h ∈ {1, 2, 3}; Step 22: Randomly generate an initial population $P$ of $NP$ individuals in $(0, d)$ with $d$ dimensions 0 = {x1, x2, …, x NP}, where each individual $x$ r = {x r,1 , x r,2 , …, x r,s , …, x r,d}, $r \in \{1, 2, \ldots, NP\}$ represents a test scheduling scheme, and each individual has $d$ dimensions; Step 23: Design a discrete encoding and decoding strategy to encode and map the individuals in the population into a test scheduling scheme; First, number each dimension of the individual in sequence to represent the serial number of the wafer to be tested; Then, sort the values of each dimension in the individual in ascending order, and the dimension numbers change positions accordingly; Round up each dimension of the individual. If the rounded-up values are the same, it means that the wafers corresponding to the dimension numbers are in the same test chain, and the arrangement order of the wafers on the same test chain is the arrangement order of the corresponding dimension numbers; Step 24: Evaluate the test scheduling scheme represented by each individual in the initial population, and calculate the objective function value F and the constraint violation level G of the population.

5. The 2.5D integrated circuit test scheduling optimization method based on the constrained differential evolution algorithm according to claim 4, wherein The specific process of Step 3 includes: Step 31: Uniformly divide the population into: an elite sub-population EP, an intermediate sub-population MP, and a disadvantaged sub-population IP according to the individual performance; Step 32: Perform differential mutation and crossover operations to generate new solutions; Step 33: Evaluate the new solutions; The newly generated population is denoted as Pn. Decode the newly generated trial vectors, and calculate the objective function value Fn and the constraint violation Gn corresponding to the trial vectors in the new population.

6. The 2.5D integrated circuit test scheduling optimization method based on the constrained differential evolution algorithm according to claim 5, characterized in that The specific process of Step 4 is: Step 41: Normalize the objective function value and the constraint violation level; Use {F, Fn} to represent the union of the objective functions of the original population and the new population, and use the following formula to normalize the objective function value F(x r corresponding to the individual x in the original population r ) to obtain the corresponding normalized objective function value F_nor r : where θ is a number between (10 -8 , 10 -5 ); The following formula is used to calculate the individual x in the new population r The corresponding objective function value Fn(x r ) is normalized to obtain the corresponding normalized objective function value Fn_nor r : Use {G, Gn} to represent the union of the constraint violation levels of the original population and the new population. The following formula is used to normalize the constraint violation level G(x r ) corresponding to the individual x in the original population to obtain the corresponding normalized objective function value G_nor r : r : The constraint violation level Gn(x r corresponding to the individual x in the new population is normalized to obtain the corresponding normalized objective function value Gn_nor r ) r : Step 42: Update the individuals in the population; use flag r Mark whether the r-th individual in the population replaces the original individual with the experimental vector. If it is replaced, it is 1; if it is retained, it is 0. Use FR to represent the proportion of solutions that meet the constraint conditions in the current population. The expression formula of flag r is as follows: Step 43: Update control parameters; record the crossover rate SCR and the scaling factor SF h h of the subpopulation successfully entering the next generation, and update the parameter archive according to the following formula: h and the scaling factor SF h , according to the following formula to update the parameter archive: where g is the population iteration number, v is the serial number of the parameter archive. When v > H, v is reset to 1 to overwrite the archive. When the SCR h and SF h of the new population are empty, the parameter archive will not be updated. MCR h,v,g+1 represents the updated value of the (g + 1)-th population iteration of the v-th element in the crossover rate parameter archive MCR h . MF h,v,g+1 represents the updated value of the (g + 1)-th population iteration of the v-th element in the scaling factor parameter archive MF h ; mean WA (SCR h ) represents the weighted average of SCR h , and mean WL (SF h ) represents the Lehmer mean of SF h , and is calculated according to the following formula: where SCR h,k represents the k-th success parameter in SCR h , and SF h,k represents the k-th success parameter in SF h ; w k represents the weight value of the k-th successful parameter and is calculated by the following formula: where Δf k and Δf m represent the fitness improvement values brought by the k-th and m-th successful parameters respectively, and Δf k is calculated according to the following formula: Δf k = |Fn_nor k - F_nor k + Gn_nor k - G_nor k | where Fn_nor k represents the normalized objective function value of the k-th successful individual in the new population, and F_nor k represents the normalized objective function value of the k-th successful individual in the original population, and Gn_nor k represents the normalized constraint violation level of the k-th successful individual in the new population, and G_nor k represents the normalized constraint violation level of the k-th successful individual in the original population.

7. The 2.5D integrated circuit test scheduling optimization method based on the constrained differential evolution algorithm according to claim 1, characterized in that The specific process of Step 5 is as follows: Repeat Step 3 and Step 4 until the maximum number of evaluations FES is satisfied max , and output the optimal solution obtained by the algorithm, the corresponding test scheduling scheme, and the cost.

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