Winding path generation method and device, electronic equipment and storage medium
By generating an undirected graph and inserting registers, the winding path between BEs in large system-level chips is automatically generated, which solves the problem of low manual design efficiency, improves generation efficiency and rationality, and reduces development difficulty.
Patent Information
- Application Number
- CN202510382765.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-08-01
AI Technical Summary
In large system-level chips, due to the large number of BEs and the complex symmetry relationship of multiplexing, professional engineers have a large workload to manually design the winding path, resulting in low generation efficiency and high difficulty.
By generating an undirected graph based on the chip design diagram, the reference path is determined based on the weight of the edges, and registers are inserted into the analog circuit of the target BE, and the winding path is automatically generated. Taking into account the connection difficulty between BE and physical implementation conditions, the winding path is optimized.
It reduces the workload of winding path generation, improves efficiency, shortens the development cycle, reduces the difficulty of chip development, and has higher rationality and realization of the generated winding paths.
Smart Images
Figure CN120409414A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip design, and in particular, to a method, device, electronic device, and storage medium for generating a routing path. Background Art
[0002] In various scenarios, the performance requirements for chips are getting higher and higher, and the application of large system-on-chip (SoC) is increasing. Among them, a large SoC generally includes multiple subsystems, and each subsystem includes multiple backends (BEs). A BE is a hardware with a certain physical shape and is used to implement a set function.
[0003] In related technologies, signal transmission across BEs is often achieved through feedthrough, that is, the signal is directly transmitted to other BEs through the inside of the BE. For example, if BE1 needs to be connected to BE3 but is blocked by BE2 in the middle, at this time, a feedthrough line can be arranged inside BE2. In this way, the signal sent by BE1 can be directly transmitted to BE3 based on the feedthrough line inside BE2 without detouring outside BE2. In this way, the wiring path can be shortened and wiring resources can be saved.
[0004] Currently, generally, professional engineers manually design the routing paths between BEs. When the chip area is large and there are many BEs included, the workload of professional engineers is large and the time required is long, resulting in low efficiency in generating routing paths. Summary of the Invention
[0005] The purpose of the embodiments of the present invention is to provide a method, device, electronic device, and storage medium for generating a routing path to improve the efficiency of generating the routing path. The specific technical solutions are as follows:
[0006] In a first aspect, an embodiment of the present application provides a method for generating a routing path, the method including:
[0007] Obtaining an undirected graph of subsystems in the chip generated based on a chip design diagram, where nodes in the undirected graph represent: the backends (BEs) included in the subsystem and virtual BEs corresponding to adjacent subsystems, and edges in the undirected graph represent: the BEs represented by the connected nodes are adjacent;
[0008] Determining a reference path between two nodes in each pair of nodes based on set weights of each edge in the undirected graph, where the weight of an edge represents: the difficulty of feedthrough between the BEs represented by the connected nodes;
[0009] Determining a first pair of BEs with an interface connection relationship according to the design code of the chip;
[0010] Generate a detoured path with registers inserted in the analog circuit of the target BE based on the first reference path between the first node pairs corresponding to the first BEs, where the target BE is the BE represented by the nodes through which the first reference path passes.
[0011] In one embodiment of the present application, the method further includes:
[0012] Determine whether the detoured path meets the physical implementation conditions;
[0013] If yes, determine the detoured path as the final detoured path of the subsystem;
[0014] Otherwise, obtain the adjusted undirected graph of the subsystem, and return to the step of determining the reference path between the two nodes in each pair of nodes based on the set weights of the edges in the undirected graph.
[0015] In one embodiment of the present application, the physical implementation conditions include at least one of the following:
[0016] The area of the analog circuit of the target BE after inserting the registers is less than or equal to the set area; [[ID=2...]]
[0017] The number of detoured paths passing through the target BE is less than or equal to the set number;
[0018] Signals can be transmitted in the detoured path according to the set timing.
[0019] In one embodiment of the present application, insert registers in the analog circuit of the target BE in the following manner:
[0020] Determine the register information of the target BE according to the set timing of the signals in the detoured path to be generated, where the register information includes: register type and register quantity;
[0021] Insert registers in the analog circuit of the target BE according to the register information.
[0022] In one embodiment of the present application, the chip includes multiple subsystems. After determining the detoured paths of each subsystem in the chip, the method further includes:
[0023] Generate the detoured paths between each subsystem based on the first position of the first BE and the second position of the second BE included in each subsystem, where the first BE is the BE in the subsystem for receiving the input signals from the adjacent subsystem, and the second BE is the BE in the subsystem for outputting signals to the adjacent subsystem;
[0024] Generate the detoured path of the chip based on the detoured paths of each subsystem and the detoured paths between each subsystem.
[0025] In one embodiment of the present application, among the multiple subsystems, there is a subsystem that prohibits wire winding, and the wire winding paths between the subsystems wind around the subsystem that prohibits wire winding in a set direction.
[0026] In one embodiment of the present application, the set weight of an edge is set based on at least one of the following factors:
[0027] The distance between the BEs represented by the nodes connected by the edge;
[0028] The relative positional relationship between the BEs represented by the nodes connected by the edge;
[0029] The relative position of the BEs represented by the nodes connected by the edge in the subsystem.
[0030] In one embodiment of the present application, the reference path between two nodes in each pair of nodes is: the path with the minimum sum of the weights of the included edges.
[0031] In a second aspect, an embodiment of the present application provides a wire winding path generation device, and the device includes:
[0032] An undirected graph acquisition module, configured to acquire an undirected graph of the subsystems in the chip generated based on the chip design diagram, where the nodes in the undirected graph represent: the backend BEs included in the subsystems and the virtual BEs corresponding to adjacent subsystems, and the edges in the undirected graph represent: the BEs represented by the connected nodes are adjacent;
[0033] A reference path determination module, configured to determine the reference path between two nodes in each pair of nodes based on the set weights of the edges in the undirected graph, where the weight of an edge represents: the wire winding difficulty between the BEs represented by the nodes connected by the edge;
[0034] A connection relationship determination module, configured to determine a first pair of BEs with an interface connection relationship according to the design code of the chip;
[0035] A first wire winding path generation module, configured to generate a wire winding path with a register inserted in the analog circuit of the target BE based on the first reference path between the first pair of nodes corresponding to the first pair of BEs, where the target BE is: the BE represented by the node passed by the first reference path.
[0036] In one embodiment of the present application, the device further includes:
[0037] A condition judgment module, configured to judge whether the wire winding path meets the physical implementation condition. If so, trigger the path determination module; otherwise, trigger the return module;
[0038] The path determination module is configured to determine the wire winding path as the final wire winding path of the subsystem;
[0039] The return module is configured to obtain the undirected graph after the subsystem is adjusted, and trigger the reference path determination module.
[0040] In one embodiment of the present application, the physical implementation conditions include at least one of the following:
[0041] The area of the analog circuit of the target BE after inserting the register is less than or equal to the set area; the number of routing paths passing through the target BE is less than or equal to the set number; signals can be transmitted in the routing paths according to the set timing.
[0042] In one embodiment of the present application, registers are inserted into the analog circuit of the target BE in the following manner:
[0043] According to the set timing of the signals in the to-be-generated routing paths, determine the register information of the target BE, where the register information includes: register type and register quantity; insert registers into the analog circuit of the target BE according to the register information.
[0044] In one embodiment of the present application, the chip includes multiple subsystems. After determining the routing paths of each subsystem in the chip, the apparatus further includes:
[0045] A second routing path generation module, configured to generate routing paths between each subsystem based on the first position of the first BE and the second position of the second BE included in each subsystem, where the first BE is the BE in the subsystem for receiving input signals from adjacent subsystems, and the second BE is the BE in the subsystem for outputting signals to adjacent subsystems; generate the routing paths of the chip based on the routing paths of each subsystem and the routing paths between each subsystem.
[0046] In one embodiment of the present application, among the multiple subsystems, there is a subsystem that prohibits routing, and the routing paths between each subsystem bypass the subsystem that prohibits routing in a set direction.
[0047] In one embodiment of the present application, the set weight of the edge is set based on at least one of the following factors:
[0048] The distance between the BEs represented by the nodes connected by the edge; the relative positional relationship between the BEs represented by the nodes connected by the edge; the relative position of the BEs represented by the nodes connected by the edge in the subsystem.
[0049] In one embodiment of the present application, the reference path between two nodes in each pair of nodes is: the path with the minimum sum of the weights of the included edges.
[0050] In a third aspect, an embodiment of the present application provides an electronic device, including:
[0051] A memory for storing a computer program;
[0052] A processor for implementing the method described in the first aspect when executing the program stored in the memory.
[0053] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, including:
[0054] A memory for storing a computer program;
[0055] A processor for implementing the method described in the first aspect when executing the program stored in the memory.
[0056] In a fifth aspect, an embodiment of the present application further provides a computer program product containing instructions, which when running on a computer, causes the computer to execute the method described in the first aspect.
[0057] As can be seen from the above, by applying the solution provided by the embodiment of the present application, an electronic device can obtain an undirected graph representing the adjacent relationship between the BEs included in the subsystem and the virtual BEs of the adjacent subsystems based on the chip design diagram, and determine the reference path between two nodes in each pair of nodes according to the weights of the edges in the undirected graph; then, after determining the first pair of BEs with an interface connection relationship, a detour path with registers inserted in the analog circuit of the target BE can be generated according to the first reference path between the first pair of nodes corresponding to the first pair of BEs. It can be seen that in the solution provided by the embodiment of the present application, the electronic device can analyze the chip design diagram to autonomously generate the detour path between the BEs included in the subsystems in the chip, without the need for professional engineers to manually design the detour path, reducing the workload, improving the generation efficiency of the detour path, and thus reducing the development difficulty and development cycle of the chip and improving the overall development efficiency of the chip.
[0058] In addition, the weight of the edge in the undirected graph represents the connection difficulty between the BEs. In this way, when generating the detour path based on the undirected graph, the connection difficulty between the BEs is also considered, so that a detour path with a lower connection difficulty between the BEs can be generated, which is beneficial to reducing the physical implementation difficulty and improving the rationality and feasibility of the generated detour path.
[0059] Of course, it is not necessary for any product or method implementing the present invention to achieve all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS
[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.
[0061] Figure 1 Schematic diagram of the first subsystem provided by the embodiment of the present application;
[0062] Figure 2 Schematic diagram of a BE provided by the embodiment of the present application;
[0063] Figure 3 Flow schematic diagram of the first wire routing path generation method provided by the embodiment of the present application;
[0064] Figure 4 Schematic diagram of an undirected graph extraction scenario provided by the embodiment of the present application;
[0065] Figure 5 Schematic diagram of an undirected graph provided by the embodiment of the present application;
[0066] Figure 6 Flow schematic diagram of the second wire routing path generation method provided by the embodiment of the present application;
[0067] Figure 7 Schematic diagram of a wire routing path adjustment process provided by the embodiment of the present application;
[0068] Figure 8 Flow schematic diagram of the third wire routing path generation method provided by the embodiment of the present application;
[0069] Figure 9 Schematic diagram of the second subsystem provided by the embodiment of the present application;
[0070] Figure 10 Schematic diagram of an inter-subsystem wire routing path provided by the embodiment of the present application;
[0071] Figure 11 Schematic diagram of the first register circuit provided by the embodiment of the present application;
[0072] Figure 12 Schematic diagram of the second register circuit provided by the embodiment of the present application;
[0073] Figure 13 Schematic diagram of the structure of a wire routing path generation device provided by the embodiment of the present application;
[0074] Figure 14 Schematic diagram of the structure of an electronic device provided by the embodiment of the present application. Detailed implementation manners
[0075] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art based on this application belong to the scope of protection of the present invention.
[0076] First, the execution subject of the solution provided in the embodiments of this application will be described.
[0077] The execution subject of the solution provided in the embodiments of this application is: any electronic device with functions such as data processing and storage, such as a personal computer, a server, etc.
[0078] Next, some concepts to be involved in the embodiments of this application will be introduced.
[0079] 1. Subsystem (subsys)
[0080] The structure of a large-scale SoC is relatively complex. For the convenience of design and testing, the SoC is generally divided into multiple subsystems, and these multiple subsystems cooperate to implement the design functions of the SoC.
[0081] The following will be Figure 1 more intuitively introduced through Figure 1 which shows the subsystems included in the system-on-chip. It can be seen that a total of 9 subsystems, namely subsystem 0 - subsystem 8, are included in one SoC.
[0082] 2. BE
[0083] Similarly, each subsystem can include multiple BEs, and these multiple BEs cooperate to implement the design functions of a subsystem.
[0084] The following will be Figure 2 more intuitively introduced through Figure 2 As shown, a total of 18 BEs, namely BE0 - BE17, are included in one subsystem.
[0085] The application scenario of the embodiments of this application is: the scenario of generating the routing path inside the chip.
[0086] In the related art, professional engineers manually design the routing paths between BEs. When the chip area is large and there are many BEs included, the workload of professional engineers is large and the time required is long.
[0087] Moreover, when the subsystems in the chip have a multiplexing symmetry relationship, the difficulty for professional engineers to design the routing paths is higher and the workload is greater. First, the above-mentioned multiplexing symmetry relationship will be described below.
[0088] The above-mentioned multiplexing symmetry relationship means that: the subsystem structures are the same and centrosymmetric about the midpoint of the SoC. Among them, the same subsystem structure means that: the BEs included in the subsystem are the same and the layout of the BEs is the same.
[0089] Still taking Figure 1 as an example, assuming that Figure 1 in the SoC shown, the structures of subsystem 0 and subsystem 1 are the same and centrosymmetric about the midpoint of the SoC, then it can be said that subsystem 0 and subsystem 1 have a multiplexing symmetry relationship; similarly, assuming that the structures of subsystem 2 and subsystem 3 are the same and centrosymmetric about the midpoint of the SoC, then it can be said that subsystem 2 and subsystem 3 have a multiplexing symmetry relationship.
[0090] It can be seen that the subsystem structures with multiplexing symmetry relationships are the same. However, according to actual design requirements, the BE connection relationships within the subsystems are often different. In this way, professional engineers need to plan different routing paths in subsystems with the same structure, which further increases the difficulty of generating routing paths and results in a low generation efficiency of routing paths.
[0091] In view of the above situation, the embodiments of the present application provide a routing path generation scheme, aiming to improve the generation efficiency of routing paths, especially for complex chips.
[0092] Next, in combination with the flowchart, the routing path generation scheme provided by the embodiments of the present application will be introduced in detail.
[0093] Refer to Figure 3 , which is a schematic flowchart of the first routing path generation method provided by the embodiments of the present application. The above method includes the following steps S301 to S304.
[0094] Step S301: Obtain an undirected graph of the subsystems in the chip generated based on the chip design drawing.
[0095] In this step, an undirected graph of any subsystem in the chip can be obtained, and then a routing path for the subsystem can be generated based on the undirected graph.
[0096] In the above undirected graph, the nodes (vertices) represent: the BEs included in the subsystem and the virtual BEs corresponding to the adjacent subsystems, and the edges (edges) in the undirected graph represent: the BEs represented by the connected nodes are adjacent.
[0097] Among them, the subsystem and its adjacent subsystems are both functional modules at the subsystem level. In this step, the adjacent subsystems are abstracted as functional modules at the BE level in the undirected graph. Therefore, the adjacent subsystems can also be called virtual BEs.
[0098] Next, in combination with Figure 4 、 Figure 5, a more intuitive introduction to the above-mentioned undirected graph is given.
[0099] For example, refer to Figure 4 , Figure 4 In it, the solid rectangle represents the BE included in the subsystem, the dashed rectangle represents the virtual BE corresponding to the adjacent subsystem of the subsystem, the circle represents the node, the solid line represents the edge between the nodes corresponding to two adjacent BEs, and the dashed line represents the edge between the BE and the node corresponding to the adjacent virtual BE. In this way, taking the BEs included in the subsystem and the virtual BEs corresponding to the adjacent subsystems as nodes and establishing edges between the nodes corresponding to the adjacent BEs, the Figure 5 shown undirected graph can be obtained. Figure 5 The meanings of the circle, dashed line, and solid line in Figure 4 are the same. It can be seen that a node in the undirected graph represents a BE or a virtual BE. If there is an edge between two nodes, it means that the two BEs represented by the two nodes are adjacent. On the contrary, if there is no edge between two nodes, it means that the two BEs represented by the two nodes are not adjacent.
[0100] Specifically, the undirected graph of the subsystem can be obtained in the following way.
[0101] In one implementation, according to the chip design diagram, the undirected graph of the subsystem is generated.
[0102] As mentioned above, taking the BEs included in the subsystem and the virtual BEs corresponding to the adjacent subsystems as nodes and establishing edges between the nodes corresponding to the adjacent BEs, the undirected graph of the subsystem can be obtained.
[0103] It should be noted that for the edges between the BEs included in the subsystem, the adjacent BEs can be determined according to the relative position relationship of the BEs in the subsystem recorded in the chip design diagram (floorplan), and edges are established between the nodes representing the adjacent BEs; for the edges between the BEs included in the subsystem and the virtual BEs corresponding to the adjacent subsystems, the BEs in the subsystem adjacent to the adjacent subsystems can be first determined from the chip design diagram, and then edges are established between the nodes representing the determined BEs and the nodes representing the virtual BEs.
[0104] In another implementation, the pre-generated undirected graph of the subsystem can be loaded from the set storage location. That is, the undirected graph of the subsystem can be pre-generated according to the chip design diagram, so this step can directly obtain it. The generation method of the undirected graph is the same as the previous implementation, and will not be elaborated here.
[0105] Step S302: Based on the set weights of the edges in the undirected graph, determine the reference path between the two nodes in each pair of nodes.
[0106] For the sake of simplicity of description, in the following parts of the description, the edges between the nodes representing BEs are simply referred to as the edges between BEs.
[0107] Characterization of the weight of an edge: The winding difficulty between the BEs represented by the nodes connected by the edge. Specifically, for the edge between two adjacent BEs in a subsystem, the weight of the edge represents the winding difficulty between the two adjacent BEs; for the edge between one BE in a subsystem and the virtual BE of an adjacent subsystem, the weight of the edge represents the winding difficulty between the BE in the subsystem and the BE in the adjacent subsystem.
[0108] Among them, the winding difficulty between BEs can be evaluated from multiple dimensions such as the distance between BEs and the relative positions of BEs in the subsystem, and then the weight of the edge can be set according to the evaluated winding difficulty. For example, a higher weight can be set for the edge between BEs with a relatively large distance, and a higher weight can be set for the edge between a BE and a virtual BE. The embodiments of the present application do not limit the specific weight setting method. For the factors considered when setting the weight of the edge, refer to the introduction of subsequent embodiments, which will not be elaborated here for the time being.
[0109] In one embodiment of the present application, for an isolated node representing an isolated BE without adjacent BEs, an edge can be established between the isolated node and other nodes, and the weight of the edge can be set to a default relatively high value.
[0110] Each of the above pairs of nodes refers to: a pair of nodes composed of any two nodes included in an undirected graph.
[0111] Specifically, the following method can be adopted to determine the reference path between the two nodes in each pair of nodes.
[0112] In one implementation manner, for the two nodes included in each pair of nodes, a path with the minimum sum of the weights of the included edges can be determined as the reference path between the two nodes.
[0113] In this case, the determined reference path is essentially: the path with the lowest connection difficulty between the BEs represented by the two nodes, which can also be called the optimal path between the two nodes, so that the connection difficulty of the BEs in the winding path is as low as possible, that is, the implementation difficulty of the winding path is reduced.
[0114] For example, algorithms such as the depth-first algorithm, Dijkstra algorithm, A* algorithm, etc. can be used to determine a path with the minimum sum of the weights of the included edges as the reference path between the two nodes.
[0115] In another implementation manner, for the two nodes included in each pair of nodes, a path with the sum of the weights of the included edges less than or equal to a set threshold can be determined as the reference path between the two nodes.
[0116] The reference path determined in this case is essentially: a path where the connection difficulty between BEs represented by two nodes meets the set requirements.
[0117] For example, for each path existing between two nodes, the sum of the weights of the edges included in the path can be calculated in sequence, and it can be judged whether the obtained sum of weights is less than or equal to the set threshold. If so, this path is determined as the reference path between the two nodes; otherwise, continue to traverse the next path to calculate the sum of weights until a path with a sum of weights less than or equal to the set threshold is determined. Of course, if no path with a sum of weights less than or equal to the set threshold is determined after all paths have been traversed, the path with the smallest sum of weights can be used as the reference path between the two nodes.
[0118] Step S303: Determine the first pair of BEs with interface connection relationships according to the design code of the chip.
[0119] In the foregoing steps, the reference path between each pair of nodes is determined, that is, the path between each pair of BEs is obtained. However, the actual connection relationship between BEs is determined according to the design requirements, and there is not necessarily an actual interface connection relationship between each pair of BEs.
[0120] For example, for BE1 included in subsystem 0, BE1 may have an interface connection relationship with BE2 - BE5 and no interface connection relationship with the remaining BEs.
[0121] In this step, it is aimed to determine the pair of BEs with actual interface connection relationships based on the design code of the chip.
[0122] Specifically, the design code of the chip, such as the Register Transfer Level (RTL) code, can be obtained first, and then chip design code analysis tools such as verdi are used to parse the design code to obtain the interface connection relationship between BEs, that is, the first pair of BEs with interface connection relationships is obtained.
[0123] Step S304: Generate a detour path with registers inserted in the analog circuit of the target BE based on the first reference path between the first pair of nodes corresponding to the first pair of BEs.
[0124] The above-mentioned target BE is: the BE represented by the node passed by the first reference path. Inserting a register in the analog circuit of the BE means inserting a register in the signal transmission path.
[0125] Specifically, a detour line can be generated in the analog circuit of the target BE passed by the first reference path, and a register can be inserted in the target BE to obtain the detour path.
[0126] The signal transmitted in the routing path can be called a feedthrough signal. When the feedthrough signal is transmitted in the chip, propagation delay will be generated due to factors such as wire resistance, capacitance, and logic gates. When the feedthrough signal needs to penetrate multiple BEs, the delays will accumulate, resulting in the feedthrough signal being unable to reach the destination stably within one clock cycle. In view of this, registers can be inserted into the BEs to divide the propagation path of the feedthrough signal into multiple short paths, shortening the delay of each path to within one clock cycle to ensure normal signal timing. Among them, inserting registers in the feedthrough signal transmission path can be called pipelining.
[0127] Specifically, according to different feedthrough signals, the number and type of registers inserted into the BEs are different. For details, please refer to the introduction in the following embodiments, which will not be elaborated here for the time being.
[0128] As can be seen from the above, by applying the solution provided in the embodiments of the present application, the electronic device can obtain an undirected graph representing the adjacent relationship between the BEs included in the subsystem and the virtual BEs of the adjacent subsystems based on the chip design diagram, and determine the reference path between the two nodes in each pair of nodes according to the weights of the edges in the undirected graph; then, after determining the first pair of BEs with an interface connection relationship, a routing path with registers inserted into the analog circuit of the target BE can be generated according to the first reference path between the first pair of nodes corresponding to the first pair of BEs. It can be seen that in the solution provided in the embodiments of the present application, the electronic device can autonomously generate the routing path between the BEs included in the subsystem in the chip by analyzing the chip design diagram, without the need for professional engineers to manually design the routing path, reducing the workload, improving the generation efficiency of the routing path, and thus reducing the development difficulty and development cycle of the chip and improving the overall development efficiency of the chip.
[0129] In addition, the weight of the edge in the undirected graph represents the connection difficulty between the BEs. In this way, when generating the routing path based on the undirected graph, the connection difficulty between the BEs is also considered, so that a routing path with a lower connection difficulty between the BEs can be generated, which is beneficial to reducing the physical implementation difficulty and improving the rationality and feasibility of the generated routing path.
[0130] Next, the factors considered when setting the weight mentioned in the foregoing Figure 3 step S302 will be introduced.
[0131] In one embodiment of the present application, the set weight of the edge is set based on at least one of the following factors:
[0132] Factor 1: The distance between the BEs represented by the nodes connected by the edge.
[0133] Specifically, the weight of an edge can be inversely proportional to the distance between the BEs represented by the nodes connected by the edge.
[0134] For example, the greater the distance between the BEs, the greater the weight of the edge between the nodes representing the BEs; conversely, the smaller the distance between the BEs, the smaller the weight of the edge between the nodes representing the BEs.
[0135] Factor 2: The relative positional relationship between the BEs represented by the nodes connected by the edge.
[0136] Specifically, first, according to the relative positional relationship between the BEs represented by the nodes connected by the edge, determine the distribution direction of the BEs represented by the nodes connected by the edge, and then determine the weight of the edge according to the distribution direction. Among them, the corresponding relationship between the distribution direction and the weight can be preset.
[0137] For example, if it is determined according to the relative positional relationship between the BEs that the BEs are distributed in the horizontal direction, the weight of the edge is determined as a smaller weight value; conversely, if it is determined according to the relative positional relationship between the BEs that the BEs are distributed in the vertical direction, the weight of the edge is determined as a larger weight value.
[0138] Factor 3: The relative position of the BEs represented by the nodes connected by the edge in the subsystem.
[0139] For example, if the BE is at the edge of the subsystem and there is an edge between this BE and the virtual BE corresponding to other subsystems, the weight of this edge can be determined as a larger weight value.
[0140] In this way, various possible factors that may affect the wiring difficulty between BEs can be comprehensively considered, and then the weight of the edge between BEs can be determined more reasonably according to the above factors.
[0141] In an embodiment of the present application, registers can be inserted into the analog circuit of the target BE in the following manner:
[0142] According to the set timing of the signal in the to-be-generated wiring path, determine the register information of the target BE, and then insert registers into the analog circuit of the target BE according to the register information. The above register information includes: register type and register quantity, where the register quantity can also be referred to as the number of beats.
[0143] Specifically, the type of feedthrough signal passing through each BE can be determined according to the timing of the signal, and then the register quantity can be determined according to different feedthrough signal types in the following manner:
[0144] Type 1: Signals with beats through feedthrough
[0145] If the feedthrough signal is a signal that passes through the feedthrough and beats, the delay of the feedthrough signal in the BE can be determined based on the size of the BE, etc. Based on the above delay, the number of registers inserted into the BE can be determined.
[0146] Type 2: Signals that pass through the feedthrough without beating
[0147] This type of signal is generally a signal with a tight timing. For this type of signal, registers may not be inserted.
[0148] Type 3: Signals that do not pass through the feedthrough
[0149] This type of signal is generally a static signal or a low-speed signal and does not pass through the inside of the BE. For this type of signal, registers may not be inserted.
[0150] Type 4: Feedthrough signals with special beating logic inserted
[0151] For this type of signal, the number of registers inserted into the BE can be determined according to specific design requirements.
[0152] For the type of register inserted into the BE, it can be determined according to actual needs. For example, for different BEs, determine that the type of register inserted into the BE is a register with a counting function or a register without a counting function. The specific method is not limited in the embodiments of the present application. Among them, a register without a counting function may have a certain impact on the performance of the existing design. For a register with a counting function, refer to the subsequent examples for illustration.
[0153] In this way, by inserting registers into the analog circuit of the target BE, the signal can be transmitted in the detour path according to the set timing, ensuring the stability and convergence of the timing, and making the detour path not affect the normal transmission of the signal.
[0154] In Figure 3 Based on the shown embodiment, after generating the detour path of the subsystem in the chip, it is also possible to determine whether the generated detour path can be physically implemented, and adjust the detour path in the case where it is determined that it is difficult to physically implement. In view of the above situation, the embodiments of the present application provide a second method for generating a detour path.
[0155] See Figure 6 , which is a schematic flowchart of the second method for generating a detour path provided by the embodiments of the present application. The above method includes the following steps S601-step S607.
[0156] Step S601: Obtain an undirected graph of the subsystem in the chip generated based on the chip design diagram.
[0157] Step S602: Based on the set weights of the edges in the undirected graph, determine the reference path between two nodes in each pair of nodes.
[0158] Step S603: According to the design code of the chip, determine the first BE pair with an interface connection relationship.
[0159] Step S604: Based on the first reference path between the first node pair corresponding to the first BE pair, generate a detour path with a register inserted in the analog circuit of the target BE.
[0160] The above Step S601 - Step S604 is the same as Step S301 - Step S304 in the foregoing Figure 3 illustrated embodiment, and will not be elaborated here.
[0161] Step S605: Determine whether the detour path meets the physical implementation conditions. If yes, execute Step S606; otherwise, execute Step S607.
[0162] In this step, the physical implementation conditions may include: any conditions that ensure the detour path can be actually implemented in the process. The embodiments of the present application do not limit this.
[0163] The following is an introduction by way of example. In an embodiment of the present application, the physical implementation conditions may include at least one of the following:
[0164] Condition 1: The area of the analog circuit of the target BE after inserting the register is less than or equal to the set area.
[0165] Specifically, since the register has a certain area, after inserting the register into the target BE, the area of the analog circuit of the target BE will increase, and the area of the BE needs to meet certain size requirements. Therefore, it is necessary to ensure that the area of the analog circuit of the target BE after inserting the register is less than or equal to the set area.
[0166] Condition 2: The number of detour paths passing through the target BE is less than or equal to the set number.
[0167] Similarly, since the area of the analog circuit of the target BE is limited, to prevent too many detour paths passing through the target BE from causing the area of the target BE to be too large and the detour paths therein to be too dense, it is necessary to ensure that the number of detour paths passing through the target BE is less than or equal to the set number.
[0168] Condition 3: The signal can be transmitted in the detour path according to the set timing.
[0169] In this embodiment, the physical implementation conditions of the routing path include conditions in multiple dimensions such as the analog circuit area of the BE, the number of routing paths passing through the BE, and the signal timing. Based on the conditions in the above-mentioned multiple dimensions, more comprehensive information can be considered when determining whether the routing path can be physically implemented, improving the accuracy of the determination.
[0170] Step S606: Determine the routing path as the final routing path of the subsystem.
[0171] If the routing path meets the physical implementation conditions, no additional adjustment is required, and the routing path is directly determined as the final routing path of the subsystem.
[0172] Step S607: Obtain the undirected graph of the subsystem after adjustment, and return to step S602.
[0173] If the routing path does not meet the physical implementation conditions, it indicates that the routing path generated this time does not meet the requirements and needs to be adjusted. Therefore, the undirected graph of the subsystem after adjustment can be obtained, and the previous steps can be returned to re-plan the routing path.
[0174] Among them, when obtaining the undirected graph of the subsystem after adjustment, the adjusted chip design drawing can be obtained first, and the undirected graph of the subsystem can be regenerated according to the adjusted chip design drawing; or the undirected graph of the subsystem after adjustment can be directly obtained.
[0175] As can be seen from the above, in this embodiment, whether the routing path can be physically implemented is used as the judgment criterion, and the routing path that does not meet the requirements is iteratively adjusted until the requirements are met, so that a routing path that is convenient for physical implementation can be obtained, reducing the difficulty of subsequent routing path layout.
[0176] Next, through Figure 7 , a specific process of iteratively adjusting the routing path will be introduced by way of example.
[0177] See Figure 7 , which is a schematic diagram of a routing path generation process provided by an embodiment of the present application. The above process includes the following steps S701 - step S708:
[0178] Step S701: Obtain a chip design drawing (floorplan).
[0179] Step S702: Extract the undirected graph of the subsystem and generate an adjacency matrix.
[0180] Step S703: Generate a feedthrough path.
[0181] In the above steps S701 - step S703, the undirected graph of the subsystem is obtained according to the chip design drawing, and based on the undirected graph, a reference path between two nodes in each pair of nodes is generated.
[0182] Step S704: Manually adjust the feedthrough path.
[0183] In this step, professional engineers can manually design or adjust some reference paths according to experience and / or actual scenario requirements.
[0184] Step S705: Obtain the design code without feedthrough.
[0185] Step S706: Determine the connection relationship between BEs.
[0186] Step S707: Generate the feedthrough circuit for each BE.
[0187] In the above steps S705 - S707, according to the design code of the chip, the routing path between the first pair of BEs with interface connection relationship is determined, and registers are inserted into the analog circuits of each target BE through which the routing path passes according to requirements, to obtain the feedthrough circuit of each target BE.
[0188] Then, the wireless diagram and routing path can be adjusted based on the number of lines. That is, if it is determined that the number of routing paths (wire number) passing through the target BE does not meet the physical implementation conditions, step S702 can be returned to adjust the undirected graph, so as to regenerate the routing path based on the adjusted floorplan; or step S704 can be returned to manually adjust a specific routing path.
[0189] Step S708: Integrate the feedthrough circuit.
[0190] In this step, the feedthrough circuits of each BE can be integrated, and then the circuit area is counted and the signal timing is determined. Based on the integrated circuit area and signal timing, the floorplan and routing path are adjusted if necessary. That is, if it is determined that the routing path does not meet the physical implementation conditions according to the circuit area and signal timing, step S701 can be returned to adjust the floorplan based on the circuit area and signal timing, so as to obtain a new floorplan and regenerate the routing path based on the new floorplan; or step S704 can be returned to adjust a specific routing path.
[0191] In an embodiment of the present application, for a chip including multiple subsystems, after determining the routing paths of each subsystem in the chip, the routing paths between each subsystem can also be generated. In view of the above situation, the third routing path generation method is provided in the embodiment of the present application.
[0192] See Figure 8, which is a schematic flowchart of the third wire routing path generation method provided by the embodiments of the present application. The above method includes the following steps S801 - step S806.
[0193] Step S801: Obtain an undirected graph of subsystems in a chip generated based on a chip design diagram.
[0194] Step S802: Based on the set weights of each edge in the undirected graph, determine the reference path between two nodes in each pair of nodes.
[0195] Step S803: According to the design code of the chip, determine the first BE pair with an interface connection relationship.
[0196] Step S804: Based on the first reference path between the first node pair corresponding to the first BE pair, generate a wire routing path with a register inserted in the analog circuit of the target BE.
[0197] The above steps S801 - step S804 are the same as steps S301 - step S304 in the foregoing Figure 3 illustrated embodiments and will not be elaborated here.
[0198] Step S805: Based on the first position of the first BE and the second position of the second BE included in each subsystem, generate a wire routing path between each subsystem.
[0199] The foregoing steps generate a wire routing path for the BE inside the subsystem, which can be understood as the wire routing path of the first hierarchy.
[0200] In this step, from the perspective of the subsystem, a wire routing path of the second hierarchy is generated, that is, a wire routing path between subsystems. Refer to Figure 9 , Figure 9 in which each rectangle represents subsystem 0 - subsystem 4. It can be seen that in this step, the subsystem is degenerated into a node in the wire routing path, and the adjacent relationship of the subsystems is used as the edge of the node.
[0201] Among them, the first BE is the BE in the subsystem for receiving input signals from adjacent subsystems, and the second BE is the BE in the subsystem for outputting signals to adjacent subsystems.
[0202] Specifically, the first BE of each subsystem can be connected to the second BE of its adjacent subsystem, and the second BE of each subsystem can be connected to the first BE of its adjacent subsystem to obtain a wire routing path between each subsystem.
[0203] In an embodiment of the present application, in the case where there is a subsystem that prohibits wire routing among multiple subsystems, the wire routing path between each subsystem bypasses the subsystem that prohibits wire routing in a set direction.
[0204] The above setting direction can be clockwise or counterclockwise, and the embodiments of the present application do not limit this.
[0205] See Figure 10 , Figure 10 In, each rectangle represents a subsystem. Among them, it is assumed that subsystem 0 and subsystem 1 have a multiplexing symmetry relationship, subsystem 2 and subsystem 3 have a multiplexing symmetry relationship, and the middle subsystem 4 is a subsystem where wire winding is prohibited. If the setting direction is clockwise, the wire winding path between each subsystem can be the path shown as A→D→B→C. Among them, the number of beats of inserting BE in the wire winding path can be determined based on the size of the subsystem, which will not be elaborated here.
[0206] In this way, it is possible to achieve the connection between subsystems based on the wire winding path, and at the same time avoid the wire winding path passing through the subsystem where wire winding is prohibited, improving the rationality of the wire winding path.
[0207] Step S806: Generate the wire winding path of the chip based on the wire winding paths of each subsystem and the wire winding paths between each subsystem.
[0208] In this step, the wire winding path at the BE level and the wire winding path at the subsystem level can be integrated and interconnected to obtain the wire winding path of the entire chip.
[0209] In this embodiment, first consider the BE level to generate the wire winding path between BEs in the subsystem, and then consider the subsystem level to generate the wire winding path between subsystems. Through the wire winding design of the two levels, the generation process of the wire winding path is simplified, and the generation efficiency of the wire winding path is further improved.
[0210] Next, a register circuit with a counting function mentioned above will be introduced.
[0211] See Figure 11 , such a register circuit has a First In First Out (FIFO) unit. Figure 11 In, the largest rectangle represents the register circuit, the rectangles included in the largest matrix represent the units in the register circuit, the First In First Out FIFO depth (F_DEPTH) represents the number of data items that the FIFO unit can store, the number of samples (NUMOFSAMPLE) represents the number of data items to be sent, the maximum count value (MAX_CRED) represents the maximum number of data items that can be sent, the input idle (free) signal (fit_income_free) is used to indicate whether the upstream module can input data to itself; the output free signal (out_fit_free) is a signal sent by the downstream module, indicating whether data can be output to the downstream module; the signal input represents the input signal of the upstream module, and the signal output represents the output signal to the downstream module.
[0212] Specifically, every time the upstream module sends a piece of data, the FIFO unit in the downstream module receives and temporarily stores it; every time a piece of data is processed, the downstream module returns a count signal (free = 1) to notify the upstream module that it can continue to send.
[0213] In this way, under normal circumstances, the upstream module can receive one clock signal and send one piece of data, so the number of data stored in the downstream module will not exceed the FIFO depth.
[0214] Moreover, when the count (cntr) threshold of the upstream module is aligned with the FIFO depth of the downstream module, it will not be affected by feedthrough.
[0215] Figure 12 Scenarios of multiple register circuits used in combination are shown. Among them, the upstream module maintains a counter to record the amount of data that can be sent. The initial value is equal to the FIFO depth of the downstream module. Every time a piece of data is sent, the counter is decremented by 1. Every time a count signal is received, the counter is incremented by 1. When the counter is 0, the upstream module stops sending. In this way, through the register circuit between the upstream module and the downstream module, data overflow in the downstream module can be avoided.
[0216] As can be seen from the foregoing, the solution provided in the embodiments of the present application can support the routing evaluation in the early stage of feedthrough design, especially support the feedthrough design of large chips and symmetric structures; in addition, support the overall routing design that distinguishes between direct connection and feedthrough; support the feedthrough design for special signal routing planning; support the feedthrough design with and without credit; support the feedthrough routing mode for BE internal and subsystem top-level allocation; support the feedthrough routing mode for SoC top-level and subsystem top-level allocation. It can be seen that the solution provided in the embodiments of the present application provides an automated design and generation method for feedthrough in complex large chips, improving the development efficiency of the chip and shortening the development cycle.
[0217] In the technical solution of the present application, operations such as the acquisition, storage, use, processing, transmission, provision, and disclosure of user personal information are all carried out under the condition of obtaining user authorization.
[0218] Corresponding to the above-mentioned routing path generation method, the embodiments of the present application also provide a routing path generation device.
[0219] See Figure 13 , which is a schematic structural diagram of a routing path generation device provided in the embodiments of the present application. The above device includes the following modules:
[0220] An undirected graph obtaining module 1301, configured to obtain an undirected graph of subsystems in the chip generated based on a chip design diagram, where nodes in the undirected graph represent: a backend BE included in the subsystem and a virtual BE corresponding to an adjacent subsystem, and edges in the undirected graph represent: the BEs represented by the connected nodes are adjacent;
[0221] A reference path determining module 1302, configured to determine a reference path between two nodes in each pair of nodes based on set weights of edges in the undirected graph, where the weight of an edge represents: the routing difficulty between the BEs represented by the nodes connected by the edge;
[0222] A connection relationship determining module 1303, configured to determine a first pair of BEs with an interface connection relationship according to the design code of the chip;
[0223] A first routing path generating module 1304, configured to generate a routing path with a register inserted in a simulation circuit of a target BE based on a first reference path between a first pair of nodes corresponding to the first pair of BEs, where the target BE is: the BE represented by the node passed by the first reference path.
[0224] As can be seen from the above, by applying the solution provided in the embodiments of the present application, an electronic device can obtain an undirected graph representing the adjacent relationship between the BEs included in the subsystem and the virtual BEs of adjacent subsystems based on a chip design diagram, and determine a reference path between two nodes in each pair of nodes according to the weights of the edges in the undirected graph; then, after determining a first pair of BEs with an interface connection relationship, a routing path with a register inserted in a simulation circuit of a target BE can be generated according to the first reference path between the first pair of nodes corresponding to the first pair of BEs. It can be seen that in the solution provided in the embodiments of the present application, the electronic device can analyze the chip design diagram to autonomously generate a routing path between the BEs included in the subsystems in the chip, without the need for a professional engineer to manually design the routing path, reducing the workload, improving the generation efficiency of the routing path, thereby reducing the development difficulty and development cycle of the chip, and improving the overall development efficiency of the chip.
[0225] In addition, the weight of an edge in the undirected graph represents the connection difficulty between BEs. In this way, when generating a routing path based on the undirected graph, the connection difficulty between BEs is also considered, so that a routing path with a lower connection difficulty between BEs can be generated, which is beneficial to reducing the physical implementation difficulty and improving the rationality and feasibility of the generated routing path.
[0226] In an embodiment of the present application, the device further includes:
[0227] A condition judgment module, configured to judge whether the routing path meets the physical implementation condition. If yes, trigger a path determination module; otherwise, trigger a return module;
[0228] The path determination module is configured to determine the routing path as the final routing path of the subsystem;
[0229] The return module is configured to obtain the undirected graph after the adjustment of the subsystem, and trigger the reference path determination module 1302.
[0230] As can be seen from the above, in this embodiment, whether the routing path can be physically implemented is used as the judgment criterion, and the routing path that does not meet the requirements is iteratively adjusted until the requirements are met, so that a routing path that is convenient for physical implementation can be obtained, reducing the difficulty of subsequent routing path layout.
[0231] In one embodiment of the present application, the physical implementation conditions include at least one of the following:
[0232] After inserting the register, the area of the analog circuit of the target BE is less than or equal to the set area; the number of routing paths passing through the target BE is less than or equal to the set number; the signal can be transmitted in the routing path according to the set timing.
[0233] In this embodiment, the physical implementation conditions of the routing path include conditions in multiple dimensions such as the area of the analog circuit of the BE, the number of routing paths passing through the BE, and the timing of the signal. Based on the conditions in the above multiple dimensions, more comprehensive information can be considered when judging whether the routing path can be physically implemented, improving the accuracy of the judgment.
[0234] In one embodiment of the present application, the register is inserted into the analog circuit of the target BE in the following manner:
[0235] According to the set timing of the signal in the routing path to be generated, the register information of the target BE is determined, where the register information includes: register type and register quantity; according to the register information, a register is inserted into the analog circuit of the target BE.
[0236] In this way, by inserting a register into the analog circuit of the target BE, the signal can be transmitted in the routing path according to the set timing, ensuring the stability and convergence of the timing, and preventing the routing path from affecting the normal transmission of the signal.
[0237] In one embodiment of the present application, the chip includes multiple subsystems. After determining the routing paths of each subsystem in the chip, the apparatus further includes:
[0238] The second routing path generation module is configured to generate routing paths between each subsystem based on the first positions of the first BEs included in each subsystem and the second positions of the second BEs, where the first BE is the BE in the subsystem for receiving input signals from adjacent subsystems, and the second BE is the BE in the subsystem for outputting signals to adjacent subsystems; generate the routing path of the chip based on the routing paths of each subsystem and the routing paths between each subsystem.
[0239] In this embodiment, first consider the BE level, generate the routing paths between the BEs in the subsystem, and then consider the subsystem level, generate the routing paths between the subsystems. Through the routing design of two levels, the generation process of the routing path is simplified, and the generation efficiency of the routing path is further improved.
[0240] In an embodiment of the present application, among the multiple subsystems, there is a subsystem that prohibits routing, and the routing paths between each subsystem bypass the subsystem that prohibits routing in a set direction.
[0241] In this way, it is possible to achieve connectivity between subsystems based on the routing path and avoid the routing path passing through the subsystem that prohibits routing, improving the rationality of the routing path.
[0242] In an embodiment of the present application, the set weight of the edge is set based on at least one of the following factors:
[0243] The distance between the BEs represented by the nodes connected by the edge; the relative positional relationship between the BEs represented by the nodes connected by the edge; the relative position of the BEs represented by the nodes connected by the edge in the subsystem.
[0244] In this way, it is possible to comprehensively consider the above various factors that may affect the routing difficulty between BEs, and then be able to more reasonably determine the weight of the edge between BEs according to the above factors.
[0245] In an embodiment of the present application, the reference path between two nodes in each pair of nodes is: the path with the smallest sum of the weights of the included edges.
[0246] In this case, the determined reference path is essentially: the path with the lowest connection difficulty between the BEs represented by the two nodes, which can also be called the optimal path between the two nodes, making the connection difficulty of the BEs in the routing path as low as possible, that is, reducing the implementation difficulty of the routing path.
[0247] Corresponding to the above routing path generation method, the embodiments of the present application also provide an electronic device, a computer-readable storage medium, and a computer program.
[0248] The embodiments of the present application provide an electronic device, such as Figure 14 shown, including:
[0249] A memory 1401 for storing a computer program;
[0250] A processor 1402, which, when executing the program stored in the memory 1401, implements the aforementioned winding path generation method.
[0251] Moreover, the above electronic device may further include a communication bus and / or a communication interface, and the processor 1402, the communication interface, and the memory 1401 complete communication with each other through the communication bus.
[0252] The communication bus mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.
[0253] The communication interface is used for communication between the above electronic device and other devices.
[0254] The memory may include a Random Access Memory (RAM), or may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.
[0255] The above processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
[0256] In another embodiment provided by the present application, there is also provided a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the aforementioned winding path generation methods are implemented.
[0257] In yet another embodiment provided by the present application, a computer program product containing instructions is further provided. When it runs on a computer, it causes the computer to execute any one of the circuit path generation methods in the above embodiments.
[0258] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from a website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a solid-state disk (SSD), etc.
[0259] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including the element.
[0260] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments of the device, electronic device, and storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference can be made to the corresponding descriptions in the method embodiments.
[0261] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.
Claims
1. A method for generating a winding path, characterized in that, The method includes: Obtaining an undirected graph of the subsystems in the chip generated based on the chip design diagram, where the nodes in the undirected graph represent: the back ends (BEs) included in the subsystem and the virtual BEs corresponding to adjacent subsystems, and the edges in the undirected graph represent: the BEs represented by the connected nodes are adjacent; Based on the set weights of the edges in the undirected graph, determining a reference path between two nodes in each pair of nodes, where the weight of an edge represents: the routing difficulty between the BEs represented by the nodes connected by the edge; According to the design code of the chip, determining a first pair of BEs with an interface connection relationship; Based on the first reference path between the first pair of nodes corresponding to the first pair of BEs, generating a routing path with registers inserted in the analog circuit of the target BE, where the target BE is: the BE represented by the node through which the first reference path passes.
2. The method according to claim 1, characterized in that The method further includes: Judging whether the routing path meets the physical implementation conditions; If so, determining the routing path as the final routing path of the subsystem; Otherwise, obtaining an adjusted undirected graph of the subsystem, and returning to the step of determining a reference path between two nodes in each pair of nodes based on the set weights of the edges in the undirected graph.
3. The method according to claim 2, wherein The physical implementation conditions include at least one of the following: The area of the analog circuit of the target BE after inserting the register is less than or equal to the set area; The number of routing paths passing through the target BE is less than or equal to the set number; Signals can be transmitted in the routing path according to the set timing.
4. The method according to claim 1, characterized in that, Inserting registers in the analog circuit of the target BE in the following manner: According to the set timing of the signals in the to-be-generated routing path, determining the register information of the target BE, where the register information includes: register type and register quantity; Inserting registers in the analog circuit of the target BE according to the register information.
5. The method according to claim 1, wherein The chip includes multiple subsystems. After determining the routing paths of each subsystem in the chip, the method further includes: Based on the first position of the first BE and the second position of the second BE included in each subsystem, generating a routing path between each subsystem, where the first BE is: the BE in the subsystem for receiving input signals from adjacent subsystems, and the second BE is: the BE in the subsystem for outputting signals to adjacent subsystems; Based on the routing paths of each subsystem and the routing paths between each subsystem, generating the routing path of the chip.
6. The method according to claim 5, wherein Among the multiple subsystems, there are subsystems where routing is prohibited, and the routing paths between each subsystem bypass the subsystems where routing is prohibited in a set direction.
7. The method according to any one of claims 1-6, characterized in that The set weight of an edge is set based on at least one of the following factors: The distance between the BEs represented by the nodes connected by the edge; The relative positional relationship between the BEs represented by the nodes connected by the edge; The relative position of the BEs represented by the nodes connected by the edge in the subsystem.
8. According to the method according to any one of claims 1-6, characterized in that The reference path between two nodes in each pair of nodes is: the path with the minimum sum of the weights of the included edges.
9. A wiring path generation device, characterized in that, The device includes: An undirected graph acquisition module, configured to acquire an undirected graph of subsystems in the chip generated based on a chip design diagram, wherein nodes in the undirected graph represent: a back end (BE) included in the subsystem and a virtual BE corresponding to an adjacent subsystem, and edges in the undirected graph represent: the BEs represented by the connected nodes are adjacent; A reference path determination module, configured to determine a reference path between two nodes in each pair of nodes based on set weights of edges in the undirected graph, wherein the weight of an edge represents: the routing difficulty between the BEs represented by the nodes connected by the edge; A connection relationship determination module, configured to determine a first pair of BEs having an interface connection relationship according to design code of the chip; A first routing path generation module, configured to generate a routing path with a register inserted in a simulation circuit of a target BE based on a first reference path between a first pair of nodes corresponding to the first pair of BEs, wherein the target BE is: the BE represented by a node through which the first reference path passes; 10. An electronic device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to implement the method according to any one of claims 1-8 when executing the program stored on the memory.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1-8 is implemented.