Generative adversarial network circuit based on memristor

Abstract

The invention discloses a generative adversarial network circuit based on a memristor. The method is formed by combining nine generators and a discriminator. Wherein each path of generator consists of a sampling module, a weight adjustment module, a neuron module, an activation function module, a signal selection module and a subtraction module; the discriminator is composed of a signal selection module, a weight adjustment module, a neuron module, a sampling module, an activation function module and a subtraction module. The nine noise signals Vin1-Vin9 and the real image signal xn are connected to the nine generators, the discriminator is connected with the output signals Vout1-Vout9 of the nine generators and is also connected with the real image signal xn, the discriminator calculates the error between the output image and the real image and returns the error to the generators, so that the generators are guided to optimally generate the image, and the image quality is improved. And the image signal is closer to a real image signal. The memristor array is used for building a generative adversarial network circuit, and some simple images can be preliminarily generated.

Description

Technical Field

[0001] The present invention relates to the field of neural network circuit design based on memristors, and particularly to a generative adversarial network circuit based on memristors. Background Art

[0002] The concept of memristors was first proposed by the Chinese-American scientist Chua Shao-Tang in 1971. When studying the relationship between current, voltage, charge, and magnetic flux, he speculated that in addition to resistors, capacitors, and inductors, there should exist a device that can represent the relationship between charge and magnetic flux, which is the memristor.

[0003] The remarkable characteristic of memristors lies in the plasticity of the resistance value, that is, under the excitation of an external electric field, the resistance value of the memristor can change significantly, and the change in the direction of the electric field will directly cause the resistance value to change in the opposite direction.

[0004] Memristors also have a threshold characteristic. The threshold characteristic of memristors refers to the fact that in the resistance switching phenomenon of memristors, there is a specific voltage or current threshold. When the applied voltage or current exceeds this threshold, the resistance state of the memristor will change abruptly.

[0005] As a new type of memory device, memristors have the advantages of fast operation speed, low power consumption, high integration density, and resistance plasticity. These characteristics make memristors have the potential in aspects such as simulating biological synaptic plasticity in brain-like computing.

[0006] Generative Adversarial Networks (GAN) is a well-known complex neural network model. Its operation requires a large amount of computing resources and depends on a large amount of training data. This requirement makes the deployment of generative adversarial networks on edge devices supported by traditional microprocessor hardware slow and challenging.

[0007] The training process of generative adversarial networks involves adversarial training of the generator and the discriminator. The generator tries to "deceive" the discriminator into thinking that the generated fake data is real data; while the discriminator tries its best to identify true and false data.

[0008] Based on the resistance plasticity and threshold characteristics of memristors, the present invention proposes a generative adversarial network circuit based on memristors. Different from previous studies that implemented generative adversarial networks through software algorithms, the present invention realizes the hardware acceleration of generative adversarial networks through a memristor array and improves the training efficiency, which provides a certain reference for the hardware implementation of generative adversarial network circuits. Summary of the Invention

[0009] The present invention proposes a memristor-based generative adversarial network circuit, which uses the resistance plasticity and threshold characteristics of the new two-port device memristor to build a generative adversarial network circuit, and can initially generate some simple images through the resistance plasticity of the memristor.

[0010] The entire generative adversarial network circuit consists of nine generators and one discriminator. For generator n, n = 1, 2, 3, …, 9, where n is the generator number. The generator is composed of a generator input sampling module, a generator weight adjustment module, a generator neuron module, a generator sampling module, a generator activation function module, a generator signal selection module, and a generator subtraction module. The discriminator is composed of a discriminator signal selection module, a discriminator weight adjustment module, a discriminator neuron module, a discriminator sampling module, a discriminator activation function module, and a discriminator subtraction module.

[0011] The connection relationship of the generators is as follows. Each generator consists of nine generator input sampling modules, nine generator weight adjustment modules, one generator neuron module, one generator sampling module, one generator activation function module, one generator signal selection module, and one generator subtraction module. For the first two numbers n, m before the subscript of each component in the generator input sampling module and the generator weight adjustment module, the first number n represents the generator number where it is located, and the second number m represents the corresponding m-th generator input sampling module and generator weight adjustment module number in the generator n, where m = 1, 2, 3, …, 9. Taking m = 1 as an example below, the connection relationship of the generator input sampling module and the generator weight adjustment module is described. That is, for the first generator input sampling module of the n-th generator, this module consists of a sample and hold circuit Q n1 , a capacitor C n1 , a positive voltage source, and a negative voltage source. Among them, the positive and negative voltage sources are connected to the positive and negative voltage source terminals of the sample and hold circuit to provide the operating voltage for the sample and hold circuit; the capacitor C n1 is connected to the capacitor terminal of the sample and hold circuit Q n1 to store the voltage sampled by the sample and hold circuit; the noise signal V in1 is connected to the input terminal of the sample and hold circuit; the clock signal T1 is connected to the clock terminal of the sample and hold circuit to control the operating state of the sample and hold circuit; the output terminal of the sample and hold circuit is connected to the generator weight adjustment module; the generator weight adjustment module consists of an operational amplifier GA n1 , a multiplier MT n1 , an adder SUM n1 , a resistor R n11 - R n12 , and a voltage-controlled switch S n11 - S n12components, where the subscript n of the component represents the generator number as n, n = 1, 2, 3, …, 9, and the second subscript 1 represents the m = 1st input signal V in the nth generator in1 is connected; the sample and hold circuit Q n1 One of the output terminals is connected to the voltage-controlled switch S n12 at the input terminal, and the other is connected to the multiplier MT n1 ; the multiplier MT n1 Another input terminal is connected to the input signal V cpn , and the output terminal of the multiplier is connected to the operational amplifier GA n1 ; the operational amplifier GA n1 The output terminal is connected to the input terminal of the voltage-controlled switch S n11 ; the control terminal of the voltage-controlled switch S n11 is connected to the clock signal T2, and one end of the output terminal is connected to the resistor R n11 , and at the same time connected to the input terminal of the adder SUM n1 , the other end of the resistor R n11 is grounded; the output terminal of the voltage-controlled switch S n12 is also connected to the adder SUM n1 , and at the same time connected to one end of the resistor R n12 , the other end of the resistor R n12 is grounded, and the clock control terminal of the voltage-controlled switch S n12 is connected to the clock control signal T3; the output terminal of the adder SUM n1 is connected to the synapse in the generator neuron module. For other generator input sampling modules and generator weight adjustment modules in the generator where m is not 1, the internal components are connected in the same way as when m = 1. For the generator n, its generator neuron module consists of the memristor MR nm1 -MR nm2 , the operational amplifier GA n_1 -GA n_3 and the resistor R n1 -R n6 components, where m = 1, 2, 3, …, 9; the positive pole of the memristor MR n11 is connected to the negative pole of the memristor MR n12 to jointly form a memristive synapse. For other memristive synapses where m is not 1, the connection method is exactly the same as that of the memristive synapse when m = 1; the output terminal of the adder SUM n1 is connected to the connection point between MR n11 and MR n12 , the negative pole of the memristor MR nm1 is connected to one end of the resistor R n1 , and at the same time connected to the inverting input terminal of the operational amplifier GA n_1 , the resistor Rn1 The other end is connected to the output terminal of the operational amplifier GA n_1 and is also connected to one end of the resistor R n3 ; One end of the memristor MR nm2 is connected to one end of the resistor R n2 and is also connected to the inverting input terminal of the operational amplifier GA n_2 ; The other end of the resistor R n2 is connected to the output terminal of the operational amplifier GA n_2 ; The inverting input terminal and the non-inverting input terminal of the operational amplifier GA n_1 and GA n_2 are both grounded; The output terminal of the operational amplifier GA n_1 is also connected to one end of the resistor R n3 ; One end of the resistor R n3 is connected to one end of the resistor R n5 and is also connected to the inverting input terminal of the operational amplifier GA n_3 ; The other end of the resistor R n5 is connected to the output terminal of the operational amplifier GA n_3 ; The output terminal of the operational amplifier GA n_2 is connected to the resistor R n4 ; One end of the resistor R n4 is connected to the inverting input terminal of the operational amplifier GA n_3 ; The non-inverting input terminal of the operational amplifier GA n_3 is connected to the resistor R n6 ; The other end of the resistor R n6 is grounded. The generator sampling module consists of a sample and hold circuit Q n , a capacitor C n and positive and negative voltage sources; The positive and negative voltage sources are connected to the power supply terminal of the sample and hold circuit Q n to provide the operating voltage for the sample and hold circuit Q n ; The capacitor C n is connected to the capacitor terminal of the sample and hold circuit to hold the voltage signal sampled by the sample and hold circuit; The clock signal T3 is connected to the control terminal of Q n to control the operating state of the sample and hold circuit, and the output terminal of the sample and hold circuit is connected to the generator activation function module. The generator activation function module consists of positive and negative voltage sources, PMOS transistors M n1 -M n2 and NMOS transistors M n3 -M n4 ; The output terminal of the sample and hold circuit Q n is connected to the gates of the PMOS transistor M n1 and the NMOS transistor M n3 ; The source of the PMOS transistor M n1 is connected to the positive voltage, and the drain is connected to the NMOS transistor M n3is connected to the drain of NMOS transistor M n3 The gate is connected to the sample and hold circuit Q n The output terminal, and the source is connected to the negative voltage. M n3 The drain of and M n1 The drains of are simultaneously connected to the gate of PMOS transistor M n2 And the gate of NMOS transistor M n4 Are connected together. M n2 The source is connected to the positive voltage. M n4 The source is connected to the negative voltage. M n2 Is connected to the drain of M n4 The signal at this point is denoted as V outn , V outn Is also connected to the generator subtraction module. The generator subtraction module consists of operational amplifier GA n_4 -GA n_5 , voltage-controlled switch S n3 -S n5 , resistor R dn1 -R dn9 And adder SUM sn2 Composed. V outn Is connected to one end of resistor R dn1 At the same time, the other end of resistor R dn1 Is connected to the inverting input terminal of operational amplifier GA n_4 And resistor R dn2 The other end of resistor R dn2 Is connected to the output terminal of operational amplifier GA n_4 The non-inverting input terminal of operational amplifier GA n_4 Is connected to resistor R dn4 The other end of resistor R dn4 Is grounded. Resistor R dn3 Is also connected to the non-inverting input terminal of operational amplifier GA n_4 The output terminal of operational amplifier GA n_4 Is connected to the input terminal of voltage-controlled switch S n3 , S n3 The output terminal is connected to resistor R dn5 , R dn5 The other end is grounded. R dn5 The part connected to S n3 The output signal is denoted as V cpn , S n3 The control terminal is connected to the output terminal of adder SUM sn2 The input terminals of adder SUM sn2 Are respectively connected to the output terminals of voltage-controlled switches S n4 And S n5 , S n4 The output terminal is also connected to resistor R dn8is connected, while the resistor R dn8 has the other end grounded, and the output end of the voltage-controlled switch S n5 is also connected to the resistor R dn9 ; while the resistor R dn9 has the other end grounded; the non-inverting input end of the operational amplifier GA n_5 is grounded, and the output end is connected to the input end and the control end of the voltage-controlled switch S n4 , and is also connected to the resistor R dn7 ; the other end of the resistor R dn7 is connected to the inverting input end of GA n_5 ; one end of the resistor R dn6 is connected to the inverting input end of GA n_5 , while this end is connected to the resistor R dn7 , and the other end is connected to the voltage V cp , and is also connected to the control end and the input end of the voltage-controlled switch S n5 . The output signal of the generator signal selection module is connected to the generator subtraction module, that is, the output end of the adder SUM sn1 is connected to one end of the resistor R dn3 ; for the generator signal selection module, it consists of the voltage-controlled switch S n1 - S n2 , the resistor R sn1 - R sn2 and the adder SUM sn1 ; the control end of the voltage-controlled switch S n1 is connected to the clock signal T c1 , the input end is connected to the real image signal x n , the output end of the voltage-controlled switch S n1 is connected to the resistor R sn2 , and is also connected to the input end of the adder SUM sn1 ; the input end of the voltage-controlled switch S n2 is connected to the constant voltage V c , the control end is connected to the clock signal T c2 , the output end of S n2 is connected to the resistor R sn1 , and is also connected to the adder SUM sn1 , and the other end of the resistor R sn1 is grounded.

[0012] The working principle of the generator in the generative adversarial network circuit is described below. Each generator consists of nine generator input sampling modules, nine generator weight adjustment modules, one generator neuron module, one generator sampling module, one generator activation function module, one generator subtraction module, and one generator signal selection module. The entire circuit can be divided into two stages from the start of learning to the end of learning. In the first 0 - 0.13 seconds, it is the discriminator learning period, and in the period of 0.13 - 0.25 seconds, it is the generator learning period. These two cycles are composed of small cycles of 10 milliseconds each. In each small cycle, the first 5 milliseconds is the signal input period, and the last 5 milliseconds is the weight adjustment period. For the generator input sampling module and the generator weight adjustment module, taking the connection of the first input signal, that is, m = 1, as an example, the working principle of the generator input sampling module is described as follows. The noise signal V in1 is input into the sample and hold circuit Q n1 . When the clock signal T1 is at a high level, the sample and hold circuit Q n1 samples and stores the sampled voltage in the capacitor C n1 . When the clock signal T1 is at a low level, the sample and hold circuit Q n1 stops sampling, and the sampled signal at the output terminal is transmitted to the generator weight adjustment module. For the generator weight adjustment module, its working principle is described as follows. The clock signals T2 and T3 in the generator weight adjustment module are a pair of inverted signals. During the signal input period, the clock signal T2 is at a low level and T3 is at a high level; during the weight adjustment period, the clock signal T2 is at a high level and T3 is at a low level. During the signal input period, the sampled signal can be input into the adder SUM n12 through the voltage - controlled switch S n1 , and is input into the memristive synapse of the generator neuron module. At this time, the voltage - controlled switch S n11 is closed, and the weight adjustment signal from the operational amplifier GA n1 cannot be input into the adder. During the weight adjustment period, the clock signal T2 is at a high level and T3 is at a low level. At this time, the voltage - controlled switch S n11 is opened, S n12 is closed, and the weight adjustment signal can be input into the memristive synapse of the generator neuron module through the adder SUM n1 . For the generator neuron module, the working principle is as follows: The positive pole of the memristor MR 1m1 is connected to the negative pole of MR 1m2 , where m = 1, 2, 3, …, 9, jointly forming a memristive synapse. The voltage signal output from the negative pole of the memristor MR 1m1 passes through the voltage amplifier composed of the resistor R n1 and the operational amplifier GA n_1 . After amplification, it is input into the resistor R n3 -Rn6 and operational amplifier GA n_3 In the subtraction circuit composed of, as an input signal of the subtraction circuit; similarly, from the memristor MR 1m2 The voltage signal output from the positive pole is input to the voltage amplifier composed of resistor R n2 and operational amplifier GA n_2 After amplification, it is input to the subtraction circuit as another input signal of the subtraction circuit; the two signals connected to resistor R n3 and resistor R n4 After subtraction, the output voltage of the generator neuron module is obtained. For the generator sampling module, it is composed of the sample and hold circuit Q n , positive and negative voltage sources, and capacitor C n . The working principle of the generator sampling module is as follows. The signal from the generator neuron module is input to the sampling terminal of the sample and hold circuit Q n . When T3 is at a high level, the sample and hold circuit Q n will sample the output signal from the operational amplifier GA n_3 . When T3 is at a low level, Q n will not sample the signal but will hold the previous sampling result; during the signal input period, T3 is at a high level, and at this time the sample and hold circuit Q n will sample; during the weight adjustment period, T3 is at a low level, and at this time the sample and hold circuit Q n will not sample the input signal and still maintains the level output during the signal input period. For the generator activation function module, this module is composed of NMOS transistors M n1 -M n2 and PMOS transistors M n3 -M n4 . The output signal of the generator activation function module is denoted as V outn . For the generator subtraction module, the working principle is as follows: V outn is input to the subtraction circuit composed of resistor R dn1 -R dn4 and operational amplifier GA n_4 . After subtracting V outn from the output signal from the generator signal selection module, it is input to the input terminal of the voltage-controlled switch S n3 . The control terminal of S n3 is connected to the output terminal of the adder SUM sn2 . Resistor R dn6 -R dn9 , voltage-controlled switch S n4 -S n5 , operational amplifier GA n_3 and adder SUM sn2 together constitute an absolute value circuit, whose function is to find Vcp The absolute value, when V cp When the input voltage of n3 is not 0, the absolute value circuit outputs a positive voltage. At this time, the voltage-controlled switch S n3 conducts, and the output voltage of the operational amplifier can cause the voltage-controlled switch S n_4 to open. The output signal from the operational amplifier GA n3 can be output through the voltage-controlled switch S cpn . The output voltage signal is denoted as V c1 . For the generator signal selection module, the working principle is as follows: when the clock signal T c2 is at a high level and T n1 is at a low level, at this time the voltage-controlled switch S n is turned on, and the pixel signal x n1 corresponding to the real image signal can be input into the adder SUM sn1 through the voltage-controlled switch S c1 and serves as one of the input voltages of the subtraction circuit in the generator subtraction module; when T c2 is at a low level and T n is at a high level, x n1 cannot pass through the voltage-controlled switch S c , while the reference voltage signal V n2 can be input into the adder SUM sn1 through the voltage-controlled switch S c1 and serves as the input of the subtraction circuit in the generator subtraction module. During 0 - 0.13 seconds, that is, during the discriminator learning period, T c2 is at a low level and T c1 is at a high level; during 0.13 - 0.25 seconds, that is, during the generator learning period, T c2 is at a high level and T

[0013] The connection relationship of the discriminator is as follows. The generative adversarial network circuit proposed by the present invention has only one discriminator, which is composed of nine discriminator signal selection modules, nine discriminator weight adjustment modules, one discriminator neuron module, one discriminator sampling module, one discriminator activation function module, and one discriminator subtraction module. For the subscripts of the components in the discriminator signal selection module and the discriminator weight adjustment module, the first subscript d represents the position in the discriminator, the second subscript n represents the module number, where n = 1, 2, 3, …, 9, and the third subscript represents the component number. For the discriminator signal selection module and the discriminator weight adjustment module, the following will be described by taking the connection to one path of the generator 1 as an example, that is, the second subscript n of the component is 1. The discriminator signal selection module consists of the voltage-controlled switches S d11 -S d12 , resistors R d11 -R d12and adder SUM d11 is composed of voltage - controlled switch S d11 The input terminal is connected to the output signal V of generator 1 out1 The control terminal is connected to clock signal T c2 S d11 The output terminal is connected to one end of resistor R d11 One end of resistor R d11 The other end is grounded; The output terminal of S d11 is also connected to the input terminal of adder SUM d11 The real - image signal x1 is connected to the input terminal of voltage - controlled switch S d12 The voltage - controlled switch S d12 The control terminal is connected to clock signal T c1 The output terminal is connected to the input terminal of adder SUM d11 and is also connected to one end of resistor R d12 One end of resistor R d12 The other end is grounded. The discriminator weight - adjustment module is composed of operational amplifier DA d1 , voltage - controlled switch S d13 - S d14 , resistor R d13 - R d14 , multiplier MT d1 and adder SUM d12 The output terminal of adder SUM d11 is connected to the input terminal of multiplier MT d1 and the input terminal of voltage - controlled switch S d13 The output terminal of MT d1 is connected to the non - inverting input terminal of operational amplifier DA d1 The inverting input terminal of DA is grounded, and the output terminal of DA d1 is connected to the input terminal of voltage - controlled switch S d1 The output terminal of S d14 is connected to one end of resistor R d14 One end of resistor R d14 The other end is grounded. The output terminal of voltage - controlled switch S d14 is also connected to the input terminal of adder SUM d14 The control terminal of S d12 is connected to clock signal T2; The control terminal of voltage - controlled switch S d14 is connected to clock signal T3, and the output terminal of S d13 is connected to the input terminal of adder SUM d13 and is also connected to resistor R d12 One end of resistor R d13 The other end is grounded. For the discriminator neuron module, the connection relationship is as follows. The discriminator neuron module is composed of memristor MR d13 - MR n1 - MR n2, operational amplifiers DA1 - DA3 and resistor R d1 -R d6 are composed, where n = 1, 2, 3, …, 9; among them, memristor MR n1 's positive pole is connected to the negative pole of MR n2 to jointly form a memristive synapse; the output terminal of adder SUM d12 is connected to the connection point of two memristors MR 11 -MR 12 . The negative pole of memristor MR n1 is connected to the inverting input terminal of operational amplifier DA1, and is also connected to resistor R d1 , the other end of resistor R d1 is connected to the output terminal of operational amplifier DA1, and the non-inverting input terminal of operational amplifier DA1 is grounded; the positive pole of memristor MR n2 is connected to the inverting input terminal of operational amplifier DA2, and is also connected to resistor R d2 , the other end of the resistor is connected to the output terminal of operational amplifier DA2, and the non-inverting input terminal of operational amplifier DA2 is grounded; the output terminal of operational amplifier DA1 is connected to resistor R d3 , the other end of resistor R d3 is connected to one end of resistor R d5 and the inverting input terminal of operational amplifier DA3, the output terminal of operational amplifier DA2 is connected to resistor R d4 , and at the same time the other end of resistor R d4 is connected to the inverting input terminal of operational amplifier DA3, and is also connected to one end of resistor R d5 , the other end of resistor R d5 is connected to the output terminal of operational amplifier DA3, the non-inverting input terminal of operational amplifier DA3 is connected to resistor R d6 , and at the same time resistor R d6The other end is grounded. For the discriminator sampling module, the connection relationship is as follows: The discriminator sampling module consists of a sample and hold circuit DQ, a capacitor DC, and positive and negative voltage sources. The output terminal of the operational amplifier DA3 is connected to the input terminal of the sample and hold circuit DQ. The capacitor DC is connected to the capacitor terminal of the sample and hold circuit DQ. The positive and negative power supplies are connected to the positive and negative power supply terminals of the sample and hold circuit, used to provide the working power supply for the sample and hold circuit. The control terminal of the sample and hold circuit DQ is connected to the clock signal T3. The discriminator activation function module consists of NMOS transistors DM1 - DM2, PMOS transistors DM3 - DM4, and positive and negative voltage sources. The connection relationship is as follows: The output terminal of the sample and hold circuit is connected to the gates of the PMOS transistor DM1 and the NMOS transistor DM3. The source of the PMOS transistor is connected to the positive voltage source, and the drain is connected to the drain of the NMOS transistor DM3. The source of DM3 is connected to the negative voltage source. The drains of DM1 and DM3 are simultaneously connected to the gates of DM2 and DM4. The source of DM2 is connected to the positive voltage source, the drain of DM2 is connected to the drain of DM4, and the source of DM4 is connected to the negative power supply. The discriminator subtraction module consists of a resistor R ds1 -R ds6 , an operational amplifier DA4, a reference voltage V tg , a voltage - controlled switch S d1 -S d2 , and an adder SUM s . The connection relationship of the discriminator subtraction module is as follows: The drains of DM4 and DM2 are connected to one end of the resistor R ds1 . The other end of the resistor R ds1 is connected to the inverting input terminal of the operational amplifier DA4 and is also connected to one end of the resistor R ds3 . The other end of the resistor R ds3 is connected to the output terminal of the operational amplifier DA4. The reference voltage V tg is connected to the resistor R ds2 . The other end of the resistor R ds2 is connected to the non - inverting input terminal of the operational amplifier DA4 and is also connected to one end of the resistor R ds4 . The other end of the resistor R ds4 is grounded. The signal at the output terminal of the operational amplifier DA4 is denoted as the voltage V cp . V cp is connected to the input terminal of the voltage - controlled switch S d1 . The control terminal of the voltage - controlled switch S d1 is connected to the clock signal T c1 . The output terminal of S d1 is connected to one end of the resistor R ds5 and is also connected to the input terminal of the adder SUM s . The other end of the resistor R ds5 is grounded. The input terminal of the voltage - controlled switch S d2 is grounded, and the output terminal is connected to the resistor Rds6 is connected, and at the same time is connected to the input terminal of the adder SUM s while the other end of the resistor R is grounded, and the control terminal of the voltage-controlled switch S ds6 is connected to the clock signal T d2 while the output signal of the adder SUM c2 is connected to the input terminal of the discriminator weight adjustment module MT s The working principle of the discriminator is as follows. The period from 0 to 0.13 seconds is the discriminator learning period, and the period from 0.13 to 0.25 seconds is the generator learning period; during the discriminator learning period, only the discriminator learns the real image signal. The working principles of each module are as follows: For the discriminator signal selection module, during the discriminator learning period, at this time T dn is at a high level, T

[0014] is at a low level, the voltage-controlled switch S c1 is turned on, S c2 is turned off, and the real image signal x dn2 can be input into the discriminator weight adjustment module through the voltage-controlled switch S dn1 and the adder SUM n where n = 1, 2, 3, …, 9. During the generator learning period, T dn2 is at a low level, T dn1 is at a high level, at this time the voltage-controlled switch S c1 is turned off, S c2 is turned on, and at this time the output signal from the generator n can be input into the discriminator weight adjustment module through the voltage-controlled switch S dn2 and the adder SUM dn1 For the discriminator weight adjustment module, during the weight adjustment period, T2 is at a high level and T3 is at a low level. At this time, the voltage-controlled switch S dn1 is turned on, S dn1 is turned off, and the adjustment signal from the operational amplifier DA dn4 can be input into the memristive synapse through the voltage-controlled switch S dn3 and the adder SUM d1 ; during the signal input period, T2 is at a low level and T3 is at a high level. At this time, the voltage-controlled switch S dn4 is turned off, S dn2 is turned on, and the signal from the adder SUM dn4 can be input into the memristive synapse through the voltage-controlled switch S dn3 and the adder SUM dn1 For the discriminator neuron module, the working principle is as follows: The voltage from the previous stage is weighted and summed. The resistor R dn3 and the operational amplifier DA1 together constitute a voltage amplifier. Similarly, the resistor R dn2 and the operational amplifier DA1 together constitute a voltage amplifier. Similarly, the resistor R d1 and the operational amplifier DA1 together constitute a voltage amplifierd2 The AND operational amplifier DA2 also forms a voltage amplifier. The amplified voltages on both sides are then input into a subtraction circuit composed of resistors R d3 -R d6 and the operational amplifier DA3. After subtraction, the output of the entire discriminator neuron circuit can be obtained. For the discriminator sampling module, its working principle is as follows: When T3 is at a high level, the sample and hold circuit DQ samples the voltage signal from the output terminal of the operational amplifier DA3 and stores the sampled voltage in the capacitor DC. When T3 is at a low level, the sample and hold circuit DQ holds the previously sampled voltage and outputs it. For the discriminator activation function module, its working principle is as shown in the appendix Figure 4 . The signal from the discriminator sampling module is processed by the activation function. The positive and negative voltage sources in the activation function module are +1V and -1V respectively. Therefore, the output of the discriminator activation function module is a voltage between +1V and -1V, and its input-output mapping relationship is as shown in the appendix Figure 4 . For the discriminator subtraction module, its working principle is as follows: During the discriminator learning period, T c1 is at a high level and T c2 is at a low level. At this time, the voltage-controlled switch S d1 is turned on and S d2 [[ID=|17]]is turned off. V cp can be input into the multiplier MT d1 of the discriminator weight adjustment module through the voltage-controlled switch S s and the adder SUM dn and participate in the adjustment of the memristive synaptic weight of the discriminator itself. During the generator learning period, T c1 is at a low level and T c2 is at a high level. At this time, the voltage-controlled switch S d1 is turned off and S d2 is turned on. The grounded 0V signal can be input into the multiplier MT d2 of the discriminator weight adjustment module through the voltage-controlled switch S s and the adder SUM dn . At this time, the discriminator weight adjustment module will no longer adjust the memristive synapses in the discriminator neuron module. Description of the Drawings

[0015] Figure 1 is a circuit structure diagram of a memristor-based generative adversarial network proposed

[0016] Figure 2 is a schematic diagram of the generator

[0017] Figure 3 is a schematic diagram of the discriminator

[0018] Figure 4It is a mapping relationship diagram of the input and output of the generator activation function module or the discriminator activation function module.

[0019] Figure 5 It is a schematic diagram of each clock signal in the generative adversarial network circuit.

[0020] Figure 6 It is a schematic diagram of the noise signal after sampling.

[0021] Figure 7 It is a schematic diagram of the output voltage and the target voltage of the first generator.

[0022] Figure 8 It is a schematic diagram of the output voltage and the target voltage of the third generator.

[0023] Figure 9 It is a schematic diagram of the real image signal and the finally generated image of the generator. Specific implementation mode

[0024] The present invention proposes a generative adversarial network circuit based on memristors, which uses the resistance plasticity and threshold characteristics of the novel two-port device memristors to build a generative adversarial network circuit, and can initially generate some simple images through the resistance plasticity of the memristors.

[0025] Appendix Figure 1 It is a schematic diagram of the connection mode of the generative adversarial network circuit. The whole circuit consists of nine generators and one discriminator; each generator consists of a generator input sampling module, a generator weight adjustment module, a generator neuron module, a generator sampling module, a generator activation function module, a generator signal selection module and a generator subtraction module; the discriminator consists of a discriminator signal selection module, a discriminator weight adjustment module, a discriminator neuron module, a discriminator sampling module, a discriminator activation function module and a discriminator subtraction module.

[0026] Appendix Figure 2Schematic diagram of the generator. Each generator consists of nine generator input sampling modules, nine generator weight adjustment modules, one generator neuron module, one generator sampling module, one generator activation function module, one generator signal selection module, and one generator subtraction module. For generator n, where n = 1, 2, 3, …, 9 and n is the generator number. For each component in the generator input sampling module and the generator weight adjustment module, the first two numbers n and m before the subscript represent the generator number where it is located, and the second number m represents the corresponding number of the m-th generator input sampling module and generator weight adjustment module in generator n, where m = 1, 2, 3, …, 9. Here, taking m = 1 as an example, the connection relationship between the generator input sampling module and the generator weight adjustment module is described. That is, for the first generator input sampling module of the n-th generator, this module consists of a sample and hold circuit Q n1 , capacitor C n1 , a positive voltage source, and a negative voltage source. Among them, the positive and negative voltage sources are connected to the positive and negative voltage source terminals of the sample and hold circuit, and capacitor C n1 is connected to the capacitor terminal of the sample and hold circuit Q n1 . The noise signal V in1 is connected to the input terminal of the sample and hold circuit. The clock signal T1 is connected to the clock terminal of the sample and hold circuit, and the output terminal of the sample and hold circuit is connected to the generator weight adjustment module. The generator weight adjustment module consists of an operational amplifier GA n1 , a multiplier MT n1 , an adder SUM n1 , resistors R n11 -R n12 , and voltage-controlled switches S n11 -S n12 . Among them, the subscript n of the component represents that the generator number where it is located is n, where n = 1, 2, 3, …, 9, and the second subscript 1 represents the connection with the first-path input signal V in1 in the n-th generator. One path of the output terminal of the sample and hold circuit Q n1 is connected to the input terminal of the voltage-controlled switch S n12 , and the other path is connected to the multiplier MT n1 . The other input terminal of the multiplier MT n1 is connected to the input signal V cpn . The output terminal of the multiplier is connected to the operational amplifier GA n1 . The output terminal of the operational amplifier GA n1 is connected to the input terminal of the voltage-controlled switch S n11 . The control terminal of the voltage-controlled switch S n11 is connected to the clock signal T2, and one end of the output terminal is connected to the resistor R n11 , and at the same time, it is connected to the adder SUM n1The input terminal of resistor R n11 The other end is grounded; the voltage-controlled switch S n12 The output terminal is also connected to the adder SUM n1 Meanwhile, it is connected to resistor R n12 One end of resistor R n12 The other end is grounded; the voltage-controlled switch S n12 The clock control terminal is connected to the clock control signal T3; the output terminal of the adder SUM n1 Is connected to the synapse in the generator neuron module. For other generator input sampling modules and generator weight adjustment modules in the generator where m is not 1, the internal components are connected in the same way as when m = 1. For generator n, its generator neuron module consists of memristors MR nm1 -MR nm2 The operational amplifier GA n_1 -GA n_3 And resistor R n1 -R n6 Where m = 1, 2, 3, …, 9; the positive pole of memristor MR n11 Is connected to the negative pole of memristor MR n12 To form a memristive synapse together. For other memristive synapses where m is not 1, the connection method is exactly the same as that of the memristive synapse when m = 1; the output terminal of the adder SUM n1 Is connected to the connection point between MR n11 And MR n12 The negative pole of memristor MR nm1 Is connected to one end of resistor R n1 Meanwhile, it is connected to the inverting input terminal of the operational amplifier GA n_1 One end of resistor R n1 The other end is connected to the output terminal of the operational amplifier GA n_1 Meanwhile, it is connected to one end of resistor R n3 The positive pole of memristor MR nm2 Is connected to one end of resistor R n2 Meanwhile, it is connected to the inverting input terminal of the operational amplifier GA n_2 One end of resistor R n2 The other end is connected to the output terminal of the operational amplifier GA n_2 The in-phase input terminals of operational amplifiers GA n_1 And GA n_2 Are both grounded. The output terminal of the operational amplifier GA n_1 Is also connected to one end of resistor R n3 One end of resistor R n3 The other end is connected to resistor R n5 And is connected to the inverting input terminal of the operational amplifier GA n_3 One end of resistor R n5The other end is connected to the operational amplifier GA n_3 at its output terminal; the output terminal of the operational amplifier GA n_2 is connected to the resistor R n4 ; meanwhile, the other end of the resistor R n4 is connected to the inverting input terminal of the operational amplifier GA n_3 ; the non-inverting input terminal of the operational amplifier GA n_3 is connected to the resistor R n6 ; the other end of the resistor R n6 is grounded. The generator sampling module consists of a sample and hold circuit Q n , a capacitor C n and positive and negative voltage sources; the positive and negative voltage sources are connected to the power supply terminal of the sample and hold circuit Q n , the capacitor C n is connected to the capacitor terminal of the sample and hold circuit, the clock signal T3 is connected to the control terminal of Q n , and the output terminal of the sample and hold circuit is connected to the generator activation function module. The generator activation function module consists of positive and negative voltage sources, PMOS transistors M n1 -M n2 and NMOS transistors M n3 -M n4 ; the output terminal of the sample and hold circuit Q n is connected to the gates of the PMOS transistor M n1 and the NMOS transistor M n3 ; the source of the PMOS transistor M n1 is connected to the positive voltage, the drain is connected to the drain of the NMOS transistor M n3 ; the gate of the NMOS transistor M n3 is connected to the output terminal of the sample and hold circuit Q n , the source is connected to the negative voltage, the drains of M n3 and M n1 are simultaneously connected to the gates of the PMOS transistor M n2 and the NMOS transistor M n4 and tied together; the source of M n2 is connected to the positive voltage, the source of M n4 is connected to the negative voltage, the drains of M n2 and M n4 are connected, and the signal there is denoted as V outn , and V outn is also connected to the generator subtraction module. The generator subtraction module consists of operational amplifiers GA n_4 -GA n_5 , voltage-controlled switches S n3 -S n5 , resistors R dn1 -R dn9 and an adder SUM sn2 ; V outn is connected to the resistor Rdn1 is connected to one end, while resistor R dn1 's other end is connected to the inverting input terminal of operational amplifier GA n_4 and resistor R dn2 are connected. The other end of resistor R dn2 is connected to the output terminal of operational amplifier GA n_4 . The non-inverting input terminal of operational amplifier GA n_4 is connected to resistor R dn4 . The other end of resistor R dn4 is grounded. Resistor R dn3 is also connected to the non-inverting input terminal of operational amplifier GA n_4 ; The output terminal of operational amplifier GA n_4 is connected to the input terminal of voltage-controlled switch S n3 . The output terminal of S n3 is connected to resistor R dn5 . The other end of R dn5 is grounded. The part of R dn5 connected to S n3 outputs a signal denoted as V cpn . The control terminal of S n3 is connected to the output terminal of adder SUM sn2 . The input terminals of adder SUM sn2 are respectively connected to the output terminals of voltage-controlled switches S n4 and S n5 . The output terminal of S n4 is also connected to resistor R dn8 . At the same time, the other end of resistor R dn8 is grounded. The output terminal of voltage-controlled switch S n5 is also connected to resistor R dn9 . At the same time, the other end of resistor R dn9 is grounded; The non-inverting input terminal of operational amplifier GA n_5 is grounded. The output terminal is connected to the input terminal and the control terminal of voltage-controlled switch S n4 , and is also connected to resistor R dn7 ; The other end of resistor R dn7 is connected to the inverting input terminal of GA n_5 ; One end of resistor R dn6 is connected to the inverting input terminal of GA n_5 . At the same time, this end is connected to resistor R dn7 . The other end is connected to voltage V cp , and is also connected to the control terminal and the input terminal of voltage-controlled switch S n5 . The output signal of the generator signal selection module is connected to the generator subtraction module, that is, through the output terminal of adder SUM sn1 is connected to one end of resistor R dn3 . For the generator signal selection module, it consists of voltage-controlled switch Sn1 -S n2 and resistor R sn1 -R sn2 and adder SUM sn1 are composed; the control terminal of voltage-controlled switch S n1 is connected to clock signal T c1 and the input terminal is connected to real image signal x n ; the output terminal of voltage-controlled switch S n1 is connected to resistor R sn2 and is also connected to the input terminal of adder SUM sn1 ; the input terminal of voltage-controlled switch S n2 is connected to constant voltage V c and the control terminal is connected to clock signal T c2 ; the output terminal of S n2 is connected to resistor R sn1 and is also connected to adder SUM sn1 ; the other end of resistor R sn1 is grounded.

[0027] Attached Figure 3 is a schematic diagram of the discriminator, and the connection relationship of the discriminator is as follows. The generative adversarial network circuit proposed by the present invention has only one discriminator, and this discriminator is composed of nine discriminator signal selection modules, nine discriminator weight adjustment modules, one discriminator neuron module, one discriminator sampling module, one discriminator activation function module, and one discriminator subtraction module. For the subscripts of the components in the discriminator signal selection module and the discriminator weight adjustment module, the first subscript d represents the position in the discriminator, the second subscript n represents the module number, where n = 1, 2, 3, …, 9, and the third subscript represents the component number. For the discriminator signal selection module and the discriminator weight adjustment module, the following will be described by taking the connection of one path of generator 1 as an example, that is, the second subscript n of the component is 1. The discriminator signal selection module is composed of voltage-controlled switch S d11 -S d12 , resistor R d11 -R d12 and adder SUM d11 ; the input terminal of voltage-controlled switch S d11 is connected to the output signal V out1 of generator 1, the control terminal is connected to clock signal T c2 , the output terminal of S d11 is connected to one end of resistor R d11 , and the other end of resistor R d11 is grounded; the output terminal of S d11 is also connected to the input terminal of adder SUM d11 ; real image signal x1 is connected to the input terminal of voltage-controlled switch S d12 ​d12 The control terminal is connected to the clock signal T c1 The output terminal is connected to the input terminal of the adder SUM d11 and is also connected to one end of the resistor R d12 One end of the resistor R d12 The other end is grounded. The discriminator weight adjustment module consists of an operational amplifier DA d1 , a voltage-controlled switch S d13 -S d14 , a resistor R d13 -R d14 , a multiplier MT d1 and an adder SUM d12 The output terminal of the adder SUM d11 is connected to the input terminal of the multiplier MT d1 and the input terminal of the voltage-controlled switch S d13 The output terminal of MT d1 is connected to the non-inverting input terminal of the operational amplifier DA d1 The inverting input terminal of DA is grounded d1 The output terminal of DA is connected to the input terminal of the voltage-controlled switch S d1 The output terminal of S is connected to one end of the resistor R d14 One end of the resistor R d14 is connected to the other end which is grounded d14 The output terminal of the voltage-controlled switch S d14 is also connected to the input terminal of the adder SUM d12 The control terminal of S is connected to the clock signal T2 d14 The control terminal of the voltage-controlled switch S d13 is connected to the clock signal T3 d13 The output terminal of S is connected to the input terminal of the adder SUM d12 and is also connected to the resistor R d13 One end of the resistor R d13 is connected to the other end which is grounded n1 For the discriminator neuron module, the connection relationship is as follows; the discriminator neuron module consists of a memristor MR n2 -MR d1 , operational amplifiers DA1-DA3 and a resistor R d6 -R n1 where n = 1, 2, 3,..., 9; among them, the positive pole of the memristor MR n2 is connected to the negative pole of MR d12 to jointly form a memristive synapse 11 The output terminal of the adder SUM 12 is connected to the connection point of the two memristors MR n1 -MR d1 The negative pole of the memristor MR is connected to the inverting input terminal of the operational amplifier DA1 and is also connected to the resistor R d1is connected to resistor R d1 The other end is connected to the output terminal of operational amplifier DA1, and the non-inverting input terminal of operational amplifier DA1 is grounded; the memristor MR n2 The positive electrode is connected to the inverting input terminal of operational amplifier DA2, and at the same time is connected to resistor R d2 is connected. The other end of the resistor is connected to the output terminal of operational amplifier DA2, and the non-inverting input terminal of operational amplifier DA2 is grounded; the output terminal of operational amplifier DA1 is connected to resistor R d3 is connected, resistor R d3 The other end is connected to resistor R d5 One end is also connected to the inverting input terminal of operational amplifier DA3. The output terminal of operational amplifier DA2 is connected to resistor R d4 is connected. At the same time, the other end of resistor R d4 is connected to the inverting input terminal of operational amplifier DA3, and at the same time is connected to one end of resistor R d5 is connected. The other end of resistor R d5 is connected to the output terminal of operational amplifier DA3. The non-inverting input terminal of operational amplifier DA3 is connected to resistor R d6 is connected. At the same time, the other end of resistor R d6 is grounded at the other end. For the discriminator sampling module, the connection relationship is as follows: The discriminator sampling module consists of a sample and hold circuit DQ, a capacitor DC, and positive and negative voltage sources. The output terminal of operational amplifier DA3 is connected to the input terminal of the sample and hold circuit DQ. The capacitor DC is connected to the capacitor terminal of the sample and hold circuit DQ. The positive and negative power supplies are connected to the positive and negative power supply terminals of the sample and hold circuit. The control terminal of the sample and hold circuit DQ is connected to the clock signal T3. The discriminator activation function module consists of NMOS transistors DM1 - DM2, PMOS transistors DM3 - DM4, and positive and negative voltage sources. The connection relationship is as follows: The output terminal of the sample and hold circuit is connected to the gates of PMOS transistor DM1 and NMOS transistor DM3. The source of the PMOS transistor is connected to the positive voltage source, and the drain is connected to the drain of NMOS transistor DM3. The source of DM3 is connected to the negative voltage source. The drains of DM1 and DM3 are simultaneously connected to the gates of DM2 and DM4. The source of DM2 is connected to the positive voltage source. The drain of DM2 is connected to the drain of DM4. The source of DM4 is connected to the negative power supply. The discriminator subtraction module consists of resistors R ds1 -R ds6 , operational amplifier DA4, reference voltage V tg , voltage-controlled switch S d1 -S d2 and adder SUM s is composed. The connection relationship of the discriminator subtraction module is as follows: The drains of DM4 and DM2 are connected to one end of resistor R ds1 . The other end of resistor R ds1 is connected to the inverting input terminal of operational amplifier DA4, and at the same time is connected to resistor Rds3 is connected to one end of resistor R ds3 and the other end is connected to the output terminal of operational amplifier DA4. The reference voltage V tg is connected to resistor R ds2 and the other end of resistor R ds2 is connected to the non-inverting input terminal of operational amplifier DA4 and is also connected to one end of resistor R ds4 and the other end of resistor R ds4 is grounded. The signal at the output terminal of operational amplifier DA4 is denoted as voltage V cp , V cp is connected to the input terminal of voltage-controlled switch S d1 . The control terminal of voltage-controlled switch S d1 is connected to clock signal T c1 . The output terminal of S d1 is connected to one end of resistor R ds5 and is also connected to the input terminal of adder SUM s . The other end of resistor R ds5 is grounded. The input terminal of voltage-controlled switch S d2 is grounded and the output terminal is connected to resistor R ds6 and is also connected to the input terminal of adder SUM s . The other end of resistor R ds6 is grounded. The control terminal of voltage-controlled switch S d2 is connected to clock signal T c2 . The output signal of adder SUM s is connected to the input terminal of discriminator weight adjustment module MT dn .

[0028] Appendix Figure 4 is the mapping relationship diagram of the input and output in the generator activation function module and the discriminator activation function module, reflecting the voltage input-output mapping relationship of these two modules.

[0029] Appendix Figure 5 is the waveform diagram of all clock signals in the generative adversarial network circuit; T c1 is high level within 0 - 0.13 seconds and low level within 0.13 - 0.25 seconds; T c2 is low level within 0 - 0.13 seconds and high level within 0.13 - 0.25 seconds; The period of T1 is 10 milliseconds, the first 2 milliseconds are high level, and the rest are low level; The period of T2 is 10 milliseconds, the first 5 milliseconds are low level, and the last 5 milliseconds are high level; The period of T3 is 10 milliseconds, the first 5 milliseconds are high level, and the last 5 milliseconds are low level.

[0030] Appendix Figure 6 is the schematic diagram of the noise signal after sampling. After the noise signal is sampled by the generator input sampling module, a random input signal is generated.

[0031] Appendix Figure 7 is the output voltage V of the first generator out1 and the target voltage V rd1 Schematic diagram. The learning target of the first generator is a high level of 0.6V. During the discriminator learning period from 0 to 0.13 seconds, the first generator learns the intermediate value between the highest level and the lowest level of the real image signal. After 0.13 seconds, the learning voltage of the first generator is the high level of 0.6V, and at this time, the output voltage of the first generator converges to 0.6V.

[0032] Appendix Figure 8 is the output voltage V of the third generator out3 and the target voltage V rd3 Schematic diagram. The learning target of the third generator is a low level of 0.1V. During the discriminator learning period from 0 to 0.13 seconds, the third generator learns the intermediate value between the highest level and the lowest level of the real image signal. After 0.13 seconds, the learning voltage of the third generator is the low level of 0.1V, and at this time, the output voltage of the third generator converges to 0.1V.

[0033] Appendix Figure 9 is a schematic diagram of the real image signal and the finally generated image of the generator. This image shows the corresponding relationship between each generator and the real image pixel points. The real image signal is a 3*3 binary image. Figure 9 (b) is the real image signal Figure 9 (c) is the generated image signal output by the generator after learning.

Claims

1. A memristor-based generative adversarial network circuit, characterized in that, It is jointly composed of nine generators and one discriminator; among them, each generator consists of a generator input sampling module, a generator weight adjustment module, a generator neuron module, a generator sampling module, a generator activation function module, a generator signal selection module, and a generator subtraction module; the discriminator consists of a discriminator signal selection module, a discriminator weight adjustment module, a discriminator neuron module, a discriminator sampling module, a discriminator activation function module, and a discriminator subtraction module; nine noise signals V in1 -V in9 and the real image signal x n are connected to the nine generators. In addition to connecting to the output signals V out1 -V out9 of the nine generators, the discriminator is also connected to the real image signal x n The discriminator calculates the error between the output image and the real image and returns it to the generator, thereby guiding the generator to optimize the generated image to make it closer to the real image signal.

2. The memristor-based generative adversarial network circuit according to claim 1, wherein Each generator consists of nine generator input sampling modules, nine generator weight adjustment modules, one generator neuron module, one generator sampling module, one generator activation function module, one generator signal selection module, and one generator subtraction module; for generator n, where n = 1, 2, 3, …, 9 and n is the generator number; for each component in the generator input sampling module and the generator weight adjustment module, the first two numbers n and m before the subscript represent the generator number where it is located, and the second number m represents the corresponding m-th generator input sampling module and generator weight adjustment module number in generator n, where m = 1, 2, 3, …, 9; below, taking m = 1 as an example, the connection relationship of the generator input sampling module and the generator weight adjustment module is described, that is, for the first generator input sampling module of the n-th generator, this module consists of a sample and hold circuit Q n1 , a capacitor C n1 , a positive voltage source, and a negative voltage source; among them, the positive and negative voltage sources are connected to the positive and negative voltage source terminals of the sample and hold circuit, and the capacitor C n1 is connected to the capacitor terminal of the sample and hold circuit Q n1 , and the noise signal V in1 is connected to the input terminal of the sample and hold circuit; the clock signal T1 is connected to the clock terminal of the sample and hold circuit, and the output terminal of the sample and hold circuit is connected to the generator weight adjustment module; the generator weight adjustment module consists of an operational amplifier GA n1 , a multiplier MT n1 , an adder SUM n1 , a resistor R n11 - R n12 , and a voltage-controlled switch S n11 - S n12 ; among them, the subscript n of the component represents that the generator number where it is located is n, n = 1, 2, 3, …, 9, and the second subscript 1 represents the connection to the first path of input signal V in1 in the n-th generator; one path of the output terminal of the sample and hold circuit Q n1 is connected to the input terminal of the voltage-controlled switch S n12 , and the other path is connected to the multiplier MT n1 ; another input terminal of the multiplier MT n1 is connected to the input signal V cpn , the output terminal of the multiplier is connected to the operational amplifier GA n1 , and the output terminal of the operational amplifier GA n1 is connected to the input terminal of the voltage-controlled switch S n11 ; the control terminal of the voltage-controlled switch S n11 is connected to the clock signal T2, and one end of the output terminal is connected to the resistor R n11 , and is also connected to the adder SUM n1 The input terminal of, resistor R n11 The other end is grounded; voltage-controlled switch S n12 The output terminal is also connected to the adder SUM n1 In, and at the same time with resistor R n12 One end is connected, resistor R n12 The other end is grounded; voltage-controlled switch S n12 The clock control terminal is connected to the clock control signal T3; adder SUM n1 The output terminal is connected to the synapse in the generator neuron module; for other generator input sampling modules and generator weight adjustment modules in the generator where m is not 1, the internal components are connected in the same way as when m is 1; for generator n, its generator neuron module consists of memristor MR nm1 -MR nm2 、operational amplifier GA n_1 -GA n_3 And resistor R n1 -R n6 Composed of, where m = 1, 2, 3, …, 9; the positive pole of memristor MR n11 Is connected to the negative pole of memristor MR n12 To jointly form a memristive synapse. For other memristive synapses where m is not 1, the connection method is exactly the same as that of the memristive synapse when m = 1; the output terminal of adder SUM n1 Is connected to the connection point between MR n11 And MR n12 The negative pole of memristor MR nm1 Is connected to one end of resistor R n1 And at the same time to the inverting input terminal of operational amplifier GA n_1 One end of resistor R n1 The other end is connected to the output terminal of operational amplifier GA n_1 And at the same time to one end of resistor R n3 The positive pole of memristor MR nm2 Is connected to one end of resistor R n2 And at the same time to the inverting input terminal of operational amplifier GA n_2 One end of resistor R n2 The other end is connected to the output terminal of operational amplifier GA n_2 The non-inverting input terminals of operational amplifier GA n_1 And GA n_2 Are both grounded. The output terminal of operational amplifier GA n_1 Is also connected to one end of resistor R n3 One end of resistor R n3 The other end is connected to resistor R n5 And at the same time to the inverting input terminal of operational amplifier GA n_3 One end of resistor R n5 The other end is connected to the operational amplifier GA n_3 at its output terminal; the output terminal of the operational amplifier GA n_2 is connected to the resistor R n4 ; at the same time, the other end of the resistor R n4 is connected to the inverting input terminal of the operational amplifier GA n_3 ; the non-inverting input terminal of the operational amplifier GA n_3 is connected to the resistor R n6 ; the other end of the resistor R n6 is grounded; the generator sampling module consists of a sample and hold circuit Q n , a capacitor C n and positive and negative voltage sources; the positive and negative voltage sources are connected to the power supply terminal of the sample and hold circuit Q n ; the capacitor C n is connected to the capacitor terminal of the sample and hold circuit; the clock signal T3 is connected to the control terminal of Q n ; the output terminal of the sample and hold circuit is connected to the generator activation function module; the generator activation function module consists of positive and negative voltage sources, PMOS transistors M n1 -M n2 and NMOS transistors M n3 -M n4 ; the output terminal of the sample and hold circuit Q n is connected to the gates of the PMOS transistor M n1 and the NMOS transistor M n3 ; the source of the PMOS transistor M n1 is connected to the positive voltage, and the drain is connected to the drain of the NMOS transistor M n3 ; the gate of the NMOS transistor M n3 is connected to the output terminal of the sample and hold circuit Q n ; the source is connected to the negative voltage; the drains of M n3 and M n1 are simultaneously connected to the gates of the PMOS transistor M n2 and the NMOS transistor M n4 and are connected together; the source of M n2 is connected to the positive voltage, the source of M n4 is connected to the negative voltage; M n2 is connected to M n4 at its drain, and the signal at this point is denoted as V outn ; V outn is also connected to the generator subtraction module; the generator subtraction module consists of operational amplifiers GA n_4 -GA n_5 , voltage-controlled switches S n3 -S n5 , resistors R dn1 -R dn9 and an adder SUM sn2 ; V outn is connected to the resistor R dn1 is connected to one end, while resistor R dn1 's other end is connected to the inverting input terminal of operational amplifier GA n_4 and resistor R dn2 are connected. The other end of resistor R dn2 is connected to the output terminal of operational amplifier GA n_4 . The non-inverting input terminal of operational amplifier GA n_4 is connected to resistor R dn4 . The other end of resistor R dn4 is grounded. Resistor R dn3 is also connected to the non-inverting input terminal of operational amplifier GA n_4 ; The output terminal of operational amplifier GA n_4 is connected to the input terminal of voltage-controlled switch S n3 . The output terminal of S n3 is connected to resistor R dn5 . The other end of R dn5 is grounded. The part of R dn5 connected to S n3 outputs a signal denoted as V cpn . The control terminal of S n3 is connected to the output terminal of adder SUM sn2 . The input terminals of adder SUM sn2 are respectively connected to the output terminals of voltage-controlled switches S n4 and S n5 . The output terminal of S n4 is also connected to resistor R dn8 . At the same time, the other end of resistor R dn8 is grounded. The output terminal of voltage-controlled switch S n5 is also connected to resistor R dn9 . At the same time, the other end of resistor R dn9 is grounded; The non-inverting input terminal of operational amplifier GA n_5 is grounded. The output terminal is connected to the input terminal and the control terminal of voltage-controlled switch S n4 , and is also connected to resistor R dn7 ; The other end of resistor R dn7 is connected to the inverting input terminal of GA n_5 ; One end of resistor R dn6 is connected to the inverting input terminal of GA n_5 . At the same time, this end is connected to resistor R dn7 . The other end is connected to voltage V cp , and is also connected to the control terminal and the input terminal of voltage-controlled switch S n5 ; The output signal of the generator signal selection module is connected to the generator subtraction module, that is, through the output terminal of adder SUM sn1 is connected to one end of resistor R dn3 ; For the generator signal selection module, it consists of voltage-controlled switch S n1 -S n2 , resistor R sn1 -R sn2 and adder SUM sn1 are composed; the control terminal of the voltage-controlled switch S n1 is connected to the clock signal T c1 , the input terminal is connected to the real image signal x n , the output terminal of the voltage-controlled switch S n1 is connected to the resistor R sn2 , and at the same time is connected to the input terminal of the adder SUM sn1 ; the input terminal of the voltage-controlled switch S n2 is connected to the constant voltage V c , the control terminal is connected to the clock signal T c2 , the output terminal of S n2 is connected to the resistor R sn1 , and at the same time is connected to the adder SUM sn1 , the other end of the resistor R sn1 is grounded.

3. The generative adversarial network circuit based on a memristor according to claim 1, wherein The discriminator consists of nine discriminator signal selection modules, nine discriminator weight adjustment modules, one discriminator neuron module, one discriminator sampling module, one discriminator activation function module, and one discriminator subtraction module; for the subscripts of the components in the discriminator signal selection module and the discriminator weight adjustment module, the first subscript d represents the position in the discriminator, the second subscript n represents the module number, where n = 1, 2, 3, …, 9, and the third subscript represents the component number; for the discriminator signal selection module and the discriminator weight adjustment module, the following will be described by taking the connection of Generator 1 as an example, that is, the second subscript n of the component is 1; the discriminator signal selection module consists of a voltage-controlled switch S d11 -S d12 、a resistor R d11 -R d12 and an adder SUM d11 ; the input end of the voltage-controlled switch S d11 is connected to the output signal V out1 of Generator 1, and the control end is connected to the clock signal T c2 ; the output end of S d11 is connected to one end of the resistor R d11 , and the other end of the resistor R d11 is grounded; the output end of S d11 is also connected to the input end of the adder SUM d11 ; the real image signal x1 is connected to the input end of the voltage-controlled switch S d12 , the control end of the voltage-controlled switch S d12 is connected to the clock signal T c1 , the output end is connected to the input end of the adder SUM d11 , and is also connected to one end of the resistor R d12 , and the other end of the resistor R d12 is grounded; the discriminator weight adjustment module consists of an operational amplifier DA d1 , a voltage-controlled switch S d13 -S d14 , a resistor R d13 -R d14 , a multiplier MT d1 and an adder SUM d12 ; the output end of the adder SUM d11 is connected to the input end of the multiplier MT d1 and the input end of the voltage-controlled switch S d13 , the output end of MT d1 is connected to the non-inverting input end of the operational amplifier DA d1 , the inverting input end of DA d1 is grounded, the output end of DA d1 is connected to the input end of the voltage-controlled switch S d14 , and the output end of S d14 is connected to the resistor R d14 is connected to resistor R d14 with the other end grounded, and voltage-controlled switch S d14 The output end is also connected to the input end of adder SUM d12 ; the control end of S d14 is connected to clock signal T2; the control end of voltage-controlled switch S d13 is connected to clock signal T3, and the output end of S d13 is connected to the input end of adder SUM d12 and is also connected to resistor R d13 is connected to resistor R d13 For the discriminator neuron module, the connection relationship is as follows; the discriminator neuron module consists of memristor MR n1 -MR n2 , operational amplifiers DA1-DA3 and resistor R d1 -R d6 where n = 1, 2, 3, …, 9; among them, the positive pole of memristor MR n1 is connected to the negative pole of MR n2 to jointly form a memristive synapse; the output end of adder SUM d12 is connected to the connection point of two memristors MR 11 -MR 12 ; the negative pole of memristor MR n1 is connected to the inverting input end of operational amplifier DA1 and is also connected to resistor R d1 is connected to resistor R d1 with the other end connected to the output end of operational amplifier DA1, and the non-inverting input end of operational amplifier DA1 is grounded; the positive pole of memristor MR n2 is connected to the inverting input end of operational amplifier DA2 and is also connected to resistor R d2 ; the other end of the resistor is connected to the output end of operational amplifier DA2, and the non-inverting input end of operational amplifier DA2 is grounded; the output end of operational amplifier DA1 is connected to resistor R d3 is connected to resistor R d3 with the other end connected to one end of resistor R d5 and the inverting input end of operational amplifier DA3, and the output end of operational amplifier DA2 is connected to resistor R d4 and at the same time the other end of resistor R d4 is connected to the inverting input end of operational amplifier DA3 and is also connected to one end of resistor R d5 is connected to resistor R d5 with the other end connected to the output end of operational amplifier DA3, and the non-inverting input end of operational amplifier DA3 is connected to resistor R d6 and at the same time resistor R d6 The other end is grounded; for the discriminator sampling module, the connection relationship is as follows: the discriminator sampling module consists of a sample and hold circuit DQ, a capacitor DC, and positive and negative voltage sources. The output terminal of the operational amplifier DA3 is connected to the input terminal of the sample and hold circuit DQ, the capacitor DC is connected to the capacitor terminal of the sample and hold circuit DQ, the positive and negative power supplies are connected to the positive and negative power supply terminals of the sample and hold circuit, and the control terminal of the sample and hold circuit DQ is connected to the clock signal T3; the discriminator activation function module consists of NMOS transistors DM1 - DM2, PMOS transistors DM3 - DM4, and positive and negative voltage sources. The connection relationship is as follows: the output terminal of the sample and hold circuit is connected to the gates of PMOS transistor DM1 and NMOS transistor DM3. The source of the PMOS transistor is connected to the positive voltage source, the drain is connected to the drain of NMOS transistor DM3, the source of DM3 is connected to the negative voltage source, the drains of DM1 and DM3 are simultaneously connected to the gates of DM2 and DM4, the source of DM2 is connected to the positive voltage source, the drain of DM2 is connected to the drain of DM4, and the source of DM4 is connected to the negative power supply; the discriminator subtraction module consists of resistors R ds1 -R ds6 , operational amplifier DA4, reference voltage V tg , voltage - controlled switch S d1 -S d2 , and adder SUM s . The connection relationship of the discriminator subtraction module is as follows: the drains of DM4 and DM2 are connected to one end of resistor R ds1 . The other end of resistor R ds1 is connected to the inverting input terminal of operational amplifier DA4 and is also connected to one end of resistor R ds3 . The other end of resistor R ds3 is connected to the output terminal of operational amplifier DA4. The reference voltage V tg is connected to resistor R ds2 . The other end of resistor R ds2 is connected to the non - inverting input terminal of operational amplifier DA4 and is also connected to one end of resistor R ds4 . The other end of resistor R ds4 is grounded. The signal at the output terminal of operational amplifier DA4 is denoted as voltage V cp . V cp is connected to the input terminal of voltage - controlled switch S d1 [[ID=�6]]. The control terminal of voltage - controlled switch S d1 is connected to the clock signal T c1 . The output terminal of S d1 is connected to one end of resistor R ds5 and is also connected to the input terminal of adder SUM s . The other end of resistor R ds5 is grounded. The input terminal of voltage - controlled switch S d2 is grounded, and the output terminal is connected to resistor R ds6 is connected, and at the same time is connected to the input terminal of the adder SUM s ; the resistor R ds6 has the other end grounded, and the control terminal of the voltage-controlled switch S d2 is connected to the clock signal T c2 ; the output signal of the adder SUM s is connected to the input terminal of the discriminator weight adjustment module MT dn .

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