Implementation method of quantum circuit weaving

Abstract

The present application discloses a method for implementing quantum circuit weaving. The method includes: compiling the obtained initial quantum circuit to determine the first quantum circuit, which includes a single-bit quantum gate and a two-bit quantum gate. Then, based on the first quantum circuit, the second quantum circuit and the target two-bit quantum gate information are determined. Finally, based on the target two-bit quantum gate information, the target single-bit quantum gate operation set is determined to achieve quantum circuit weaving. In this way, by compiling the initial quantum circuit into a first quantum circuit containing only single-bit quantum gates and two-bit quantum gates, the interference of the complex quantum gate structure on subsequent operations is eliminated. And by generating a target single-bit quantum gate operation set equivalent to the target two-bit quantum gate and merging and simplifying repeated operations, the sampling overhead of the quantum hardware is significantly reduced.

Description

Technical Field

[0001] The present application relates to the field of quantum computing, and more specifically, to a method for implementing quantum circuit weaving. Background Art

[0002] Based on the unique physical properties of qubits, such as quantum superposition and entanglement, quantum computing demonstrates significant theoretical advantages over classical computing paradigms when addressing specific complex problems. Quantum circuits are the tools of quantum computing, transforming abstract quantum algorithms into executable sequences of physical operations. However, when dealing with medium- and larger-scale quantum circuits, the scale of the circuits often exceeds the performance of the quantum computing hardware, resulting in execution anomalies and impacting the user experience. Summary of the Invention

[0003] The present application provides a method for implementing quantum circuit weaving.

[0004] The present application provides a method for implementing quantum circuit braiding, the method comprising:

[0005] Compiling the obtained initial quantum circuit to determine a first quantum circuit, where the first quantum circuit includes a single-bit quantum gate and a two-bit quantum gate;

[0006] Determining information of a second quantum circuit and a target two-bit quantum gate according to the first quantum circuit;

[0007] According to the target two-bit quantum gate information, a target single-bit quantum gate operation set is determined to realize the quantum circuit braiding.

[0008] In this way, the computer device compiles and processes the acquired initial quantum circuit to determine the first quantum circuit, which includes a single-bit quantum gate and a two-bit quantum gate. Next, the computer device determines the second quantum circuit and the target two-bit quantum gate information based on the first quantum circuit. Finally, the computer device determines the target single-bit quantum gate operation set based on the target two-bit quantum gate information to achieve quantum circuit weaving. In this way, by compiling the initial quantum circuit into a first quantum circuit containing only single-bit quantum gates and two-bit quantum gates, the interference of the complex quantum gate structure on subsequent operations is eliminated. In addition, by generating a target single-bit quantum gate operation set equivalent to the target two-bit quantum gate and merging and simplifying repeated operations, the sampling overhead of the quantum hardware is significantly reduced.

[0009] In some embodiments, determining the second quantum circuit and target two-bit quantum gate information based on the first quantum circuit includes:

[0010] Based on hardware performance, splitting the first quantum circuit to determine the second quantum circuit;

[0011] The target two-bit quantum gate information is determined according to the second quantum circuit, where the target two-bit quantum gate information includes the cut target two-bit quantum gate and position information of the target two-bit quantum gate in the first quantum circuit.

[0012] In this way, based on hardware performance, the computer device splits the first quantum circuit and determines the second quantum circuit. Next, based on the second quantum circuit, the computer device determines the target two-bit quantum gate information. This target two-bit quantum gate information includes the split target two-bit quantum gate and its location within the first quantum circuit. In this way, by splitting the first quantum circuit based on hardware performance, a first quantum circuit that cannot be correctly executed due to hardware performance is converted into multiple executable second quantum circuits, allowing complex tasks to be run in stages.

[0013] In some embodiments, determining the second quantum circuit and target two-bit quantum gate information based on the first quantum circuit includes:

[0014] Splitting the first quantum circuit based on a preset splitting algorithm to determine the second quantum circuit;

[0015] The target two-bit quantum gate information is determined according to the second quantum circuit, where the target two-bit quantum gate information includes the cut target two-bit quantum gate and position information of the target two-bit quantum gate in the first quantum circuit.

[0016] In this way, based on a preset splitting algorithm, the computer device splits the first quantum circuit and determines the second quantum circuit. Next, the computer device determines the target two-bit quantum gate information based on the second quantum circuit. This target two-bit quantum gate information includes the target two-bit quantum gate to be split and its location within the first quantum circuit. In this way, the preset splitting algorithm automatically divides the first quantum circuit into second quantum circuits that meet the hardware scale, eliminating the need for manual grouping. Furthermore, the preset algorithm adjusts the splitting strategy based on the hardware's connectivity, ensuring that the quantum gates within the second quantum circuit meet the hardware's physical connectivity constraints.

[0017] In some embodiments, the target two-bit quantum gate information includes a cut target two-bit quantum gate, and determining the target single-bit quantum gate operation set based on the target two-bit quantum gate information includes:

[0018] performing an equivalent disassembly of the target two-bit quantum gate to determine an initial single-bit quantum gate operation set, wherein the initial single-bit quantum gate operation set includes an initial single-bit quantum gate operation, a weight corresponding to the initial single-bit quantum gate operation, and a mapping relationship between the initial single-bit quantum gate operation and the second quantum circuit;

[0019] The initial single-bit quantum gate operation set is merged to determine the target single-bit quantum gate operation set.

[0020] In this way, the computer device equivalently disassembles the target two-bit quantum gate to determine an initial set of single-bit quantum gate operations. This initial set of single-bit quantum gate operations includes the initial single-bit quantum gate operation, the weight corresponding to the initial single-bit quantum gate operation, and the mapping relationship between the initial single-bit quantum gate operation and the second quantum circuit. The computer device then merges the initial set of single-bit quantum gate operations to determine the target set of single-bit quantum gate operations. This equivalent disassembly ensures the correctness of the quantum computation and facilitates the subsequent restoration of the first quantum circuit. Furthermore, this merging process reduces the number of quantum circuits that the quantum hardware needs to execute, thereby reducing hardware execution overhead and improving quantum simulation efficiency.

[0021] In certain embodiments, the method further comprises:

[0022] A target measurement result is determined according to the second quantum circuit and the target single-bit quantum gate operation set.

[0023] In this way, the computer device determines the target measurement result based on the second quantum circuit and the target set of single-bit quantum gate operations. This combines the target set of single-bit quantum gate operations obtained through quantum hardware execution with the second quantum circuit to obtain the target measurement result, improving hardware execution efficiency while preventing loss of quantum circuit information.

[0024] In some embodiments, determining a target measurement result based on the second quantum circuit and the target single-bit quantum gate operation set includes:

[0025] determining a first measurement result according to the second quantum circuit and the initial single-bit quantum gate operation;

[0026] Determining a complete operation result corresponding to the initial single-bit quantum gate operation according to the first measurement result;

[0027] The target measurement result is determined according to the complete operation result and the weight corresponding to the initial single-bit quantum gate operation.

[0028] In this way, the computer device determines the first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation. Next, based on the first measurement result, the computer device determines the complete operation result corresponding to the initial single-bit quantum gate operation. Finally, the computer device determines the target measurement result based on the complete operation result and the weight corresponding to the initial single-bit quantum gate operation. In this way, through mathematical derivation and weight superposition, the calculation results of the original initial quantum circuit can be efficiently reproduced without losing any quantum information, breaking through the scale limitations of existing quantum hardware and ensuring the efficiency and accuracy of the actual execution of large-scale quantum circuits.

[0029] In some embodiments, determining a first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation includes:

[0030] determining a target sub-circuit variant according to the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship;

[0031] According to the target sub-line variant, a first measurement result corresponding to the target sub-line variant is determined.

[0032] In this way, the computer device determines the target subcircuit variant based on the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship. Next, the computer device determines the first measurement result corresponding to the target subcircuit variant based on the target subcircuit variant. In this way, through the combined effect of the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship, quantum state evolution deviations caused by operational mapping errors are avoided, ensuring the physical feasibility and logical correctness of the target subcircuit variant.

[0033] In some embodiments, determining a target sub-circuit variant according to the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship includes:

[0034] According to the mapping relationship, the initial single-bit quantum gate operation and the second quantum circuit are spliced ​​to determine the target sub-circuit variant.

[0035] In this way, the computer device splices the initial single-bit quantum gate operation and the second quantum circuit according to the mapping relationship to determine the target sub-circuit variant. In this way, the mapping-driven splicing process ensures the accuracy of the target sub-circuit variant generation.

[0036] In some embodiments, determining, based on the first measurement result, a complete operation result corresponding to the initial single-bit quantum gate operation includes:

[0037] A complete operation result corresponding to the initial single-bit quantum gate operation is determined according to the mapping relationship and the first measurement result.

[0038] In this way, the computer device determines the complete operation result corresponding to the initial single-bit quantum gate operation based on the mapping relationship and the first measurement result. In this way, the combination of measurement results driven by the mapping relationship achieves a systematic integration of local measurement results into the complete operation result.

[0039] In some embodiments, the target two-bit quantum gate information includes position information of the target two-bit quantum gate in the first quantum circuit, and determining the target measurement result based on the complete operation result and the weight corresponding to the initial single-bit quantum gate operation includes:

[0040] multiplying the complete operation result by a weight corresponding to the initial single-bit quantum gate operation to determine a temporary processing result;

[0041] The target measurement result is determined according to the temporary processing result and the position information.

[0042] In this way, the computer multiplies the complete operation result by the weight corresponding to the initial single-bit quantum gate operation to determine a temporary processing result. The computer then determines the target measurement result based on the temporary processing result and the position information. In this way, by associating the weight distribution with the position information, a precise mapping is achieved between the fragmented target subcircuit variant measurement results and the original initial quantum circuit global result.

[0043] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0045] Figure 1 This is one of the flow charts of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0046] Figure 2 Schematic diagram of the structure of quantum circuit C according to an embodiment of the present application;

[0047] Figure 3 This is the second flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0048] FIG4( a ) is a schematic structural diagram of a second quantum circuit C2 - 1 according to an embodiment of the present application;

[0049] FIG4( b ) is a schematic structural diagram of a second quantum circuit C2 - 2 according to an embodiment of the present application;

[0050] FIG4( c ) is a schematic structural diagram of a second quantum circuit C2 - 3 according to an embodiment of the present application;

[0051] FIG4( d ) is a schematic structural diagram of a second quantum circuit C2 - 4 according to an embodiment of the present application;

[0052] Figure 4(e) is a schematic structural diagram of a second quantum circuit C2-5 according to an embodiment of the present application;

[0053] FIG5( a ) is a schematic structural diagram of a second quantum circuit C3 - 1 according to an embodiment of the present application;

[0054] FIG5( b ) is a schematic structural diagram of a second quantum circuit C3 - 2 according to an embodiment of the present application;

[0055] FIG5( c ) is a schematic structural diagram of a second quantum circuit C3 - 3 according to an embodiment of the present application;

[0056] FIG5( d ) is a schematic structural diagram of a second quantum circuit C3 - 4 according to an embodiment of the present application;

[0057] Figure 5(e) is a schematic structural diagram of a second quantum circuit C3-5 according to an embodiment of the present application;

[0058] Figure 6 This is the third flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0059] Figure 7 This is the fourth flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0060] Figure 8 This is the fifth flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0061] Figure 9 This is the sixth flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0062] Figure 10 This is the seventh flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0063] Figure 11 This is the eighth flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0064] Figure 12 This is the ninth flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0065] Figure 13 This is the tenth flow chart of the method for implementing quantum circuit braiding according to the embodiment of the present application;

[0066] Figure 14 Schematic diagram of the structure of the quantum circuit D according to the embodiment of the present application;

[0067] FIG15( a ) is a schematic diagram of one of the target sub-circuit variants according to an embodiment of the present application;

[0068] FIG15( b ) is a second schematic structural diagram of a target sub-circuit variant according to an embodiment of the present application;

[0069] FIG15( c ) is a third structural diagram of a target sub-circuit variant according to an embodiment of the present application. DETAILED DESCRIPTION

[0070] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and should not be understood as limiting the embodiments of the present application.

[0071] Based on the unique physical properties of quantum bits - quantum superposition and quantum entanglement, quantum computing has shown significant theoretical advantages over classical computing paradigms in dealing with specific complex problems. Unlike classical bits that can only represent two discrete states, 0 or 1, a single quantum bit can be in and The entanglement between multiple quantum bits can form a high-dimensional correlated state, which makes quantum computing have a natural parallel information processing capability. For example, the Shor algorithm uses quantum Fourier transform and superposition to complete the decomposition of large integers in polynomial time, which requires exponential time for classical algorithms, directly threatening the existing RSA encryption system; the Grover algorithm uses quantum search amplitude amplification technology to improve the search efficiency of unsorted databases to 100% of the classical algorithm. times (N is the database size). These characteristics make quantum computing show great potential in fields such as cryptography, combinatorial optimization, and quantum chemistry simulation.

[0072] In related technologies, quantum circuits are an important tool for quantum computing. They can convert abstract quantum algorithms into executable sequences of physical operations. Just as the circuit schematics in classical computers guide the work of electronic components, quantum circuits specify in detail the steps of preparing, operating, and measuring quantum bits.

[0073] However, when processing medium-sized and larger quantum circuits, the scale of the quantum circuit often exceeds the performance of quantum computing hardware. Currently, the development of quantum computing hardware faces numerous bottlenecks. The bit count has only reached a few hundred bits, and due to noise such as decoherence, current hardware only supports quantum circuits of a few dozen bits. When the size of the quantum circuit to be executed exceeds this limit, it can lead to abnormal execution, such as increased errors in the calculation results and significantly increased execution times, severely impacting the user experience.

[0074] Based on the above questions, please refer to Figure 1 , an embodiment of the present application provides a method for implementing quantum circuit weaving, the method comprising:

[0075] 01: Compile the obtained initial quantum circuit and determine the first quantum circuit;

[0076] 02: Based on the first quantum circuit, determine the second quantum circuit and the target two-bit quantum gate information;

[0077] 03: Based on the target two-bit quantum gate information, determine the target single-bit quantum gate operation set to achieve quantum circuit weaving.

[0078] The present application also provides a computer device comprising a memory and a processor. The method for implementing quantum circuit braiding in the present application can be implemented by the computer device in the present application. Specifically, the memory stores a computer program, and the processor is configured to compile and process the acquired initial quantum circuit to determine a first quantum circuit. Based on the first quantum circuit, a second quantum circuit and target two-bit quantum gate information are determined. Furthermore, based on the target two-bit quantum gate information, a target single-bit quantum gate operation set is determined to implement quantum circuit braiding.

[0079] The embodiments of the present application also provide a quantum circuit braiding device. The implementation method of the quantum circuit braiding of the embodiments of the present application can be implemented by the quantum circuit braiding device of the embodiments of the present application. Specifically, the quantum circuit simulation device includes a determination module. The determination module is configured to compile and process the acquired initial quantum circuit to determine a first quantum circuit. Based on the first quantum circuit, the second quantum circuit and target two-bit quantum gate information are determined. Furthermore, based on the target two-bit quantum gate information, a target single-bit quantum gate operation set is determined to implement quantum circuit braiding.

[0080] Specifically, quantum circuit weaving (QCW) refers to a quantum circuit optimization or compilation technique that achieves equivalent transformations of quantum circuits by reorganizing, decomposing, or mapping quantum gate operations (especially two-bit gates) to adapt to specific quantum computing hardware architectures (such as restricted qubit connection topologies), reduce gate operation errors, or lower computational complexity. Quantum circuit weaving uses mathematical transformations (such as unitary matrix decomposition) to convert the original quantum circuit into a gate sequence executable by quantum computing hardware. For example, a two-bit quantum gate can be decomposed into a combination of single-bit quantum gates and CNOT gates, or the gate order can be adjusted to avoid qubit interactions across large distances.

[0081] The initial quantum circuit refers to the original, unstandardized quantum circuit, which is directly generated by an abstract quantum algorithm and may contain quantum gate operations that are not supported by quantum computing hardware or two-bit gates with too large a span.

[0082] Quantum circuits are tools for quantum computing, used to transform abstract quantum algorithms into sequences of physical operations executable on quantum computing hardware. Essentially, they are graphical models that describe the evolution of quantum bits (qubits), similar to logic circuits in classical computers, but operating on qubits that exhibit quantum superposition and entanglement.

[0083] Qubit refers to the basic unit of quantum circuit and is the carrier of quantum information. 、 and its superposition state.

[0084] Quantum gates refer to the basic operating units in quantum computing. They are mathematical operations that perform specific transformations on the state of quantum bits. In essence, they are unitary transformations acting on quantum states, satisfying reversibility and probability conservation. They are used to construct quantum circuits to realize the logical functions of quantum algorithms.

[0085] The first quantum circuit is a standardized quantum circuit obtained by compiling the initial quantum circuit. It contains only single-bit and two-bit quantum gates that can be directly executed by quantum hardware. This first quantum circuit can serve as standardized input for subsequent two-bit quantum gate optimization, simplifying the decomposition process of complex quantum gates. The goal of the compilation process is to decompose high-order quantum gates or gates unsupported by the hardware into a set of basic gates that can be operated by the hardware. For example, a three-bit Toffoli gate (CCNOT gate) can be compiled into a combination of multiple single-bit and two-bit CNOT gates.

[0086] Single-bit quantum gates act on a single quantum bit, such as the Pauli gate (X gate, Y gate, Z gate), Hadamard gate (H gate) and phase gate (S gate, T gate), etc., and are used to control the phase or superposition of the quantum state.

[0087] Two-bit quantum gates act on two quantum bits, such as the CNOT gate (controlled NOT gate), CZ gate (controlled Z gate), SWAP gate, etc., to achieve entanglement or correlation between quantum bits.

[0088] A second quantum circuit is a collection of subcircuits derived from further processing of the first quantum circuit. All of these second quantum circuits, when combined in their original order, form the first quantum circuit. This second quantum circuit is smaller in scale (fewer qubits and gates) and can be directly executed on existing quantum computing hardware.

[0089] The target two-bit quantum gate information refers to the characteristic information set of the cut two-bit quantum gate extracted during the first quantum circuit processing.

[0090] The target single-bit quantum gate operation set refers to the single-bit quantum gate combination and related information used to replace the original two-bit quantum gate after cutting the target two-bit quantum gate.

[0091] First, the computer device compiles the obtained initial quantum circuit and converts the abstract initial quantum circuit into a first quantum circuit that only includes single-bit quantum gates and two-bit quantum gates.

[0092] Subsequently, the computer equipment analyzes the first quantum circuit, identifies the target two-bit quantum gate that needs to be cut, and disassembles the first quantum circuit to determine the information of the second quantum circuit and the target two-bit quantum gate.

[0093] Finally, the target single-bit quantum gate operation set is determined based on the target two-bit quantum gate information.

[0094] The following uses quantum circuit C as an example to illustrate the implementation method of quantum circuit weaving provided by the embodiment of this application. Figure 2 , Figure 2 This is a circuit diagram of quantum circuit C, which includes quantum bits acting on The H gate acts on the quantum bit and quantum bits CNOT gate.

[0095] First, quantum circuit C is compiled to determine the first quantum circuit C1. It can be seen that quantum circuit C originally only includes single-bit quantum gates and two-bit quantum gates, so the first quantum circuit C1 remains unchanged.

[0096] Next, the first quantum circuit C1 is split into two parts based on the dotted line, namely the quantum bit Split into the first part, quantum bits Split into the second part. Then, the first part is the second quantum circuit (C2-1) to (C2-5), the second part is the second quantum circuit (C3-1) to (C3-5), and the target two-bit quantum gate information includes the cut CNOT gate.

[0097] Then, the computer device determines the target single-bit quantum gate operation set equivalent to the CNOT gate based on the target two-bit quantum gate information. and .

[0098] Finally, the computer device realizes quantum circuit weaving based on the target single-bit quantum gate operation set.

[0099] In summary, in the implementation method of quantum circuit weaving provided by the embodiment of the present application, the computer device compiles and processes the obtained initial quantum circuit to determine the first quantum circuit, which includes a single-bit quantum gate and a two-bit quantum gate. Then, the computer device determines the second quantum circuit and the target two-bit quantum gate information based on the first quantum circuit. Finally, the computer device determines the target single-bit quantum gate operation set based on the target two-bit quantum gate information to achieve quantum circuit weaving. In this way, by compiling the initial quantum circuit into a first quantum circuit containing only single-bit quantum gates and two-bit quantum gates, the interference of the complex quantum gate structure on subsequent operations is eliminated. And by generating a target single-bit quantum gate operation set equivalent to the target two-bit quantum gate and merging and simplifying repeated operations, the sampling overhead of the quantum hardware is significantly reduced.

[0100] See also Figure 3 In some embodiments, step 02 (determining the second quantum circuit and target two-bit quantum gate information based on the first quantum circuit) includes:

[0101] 021: Based on hardware performance, split the first quantum circuit and determine the second quantum circuit;

[0102] 022: Based on the second quantum circuit, determine the target two-bit quantum gate information.

[0103] In certain embodiments, the determination module is further configured to split the first quantum circuit based on hardware performance to determine a second quantum circuit, and determine target two-bit quantum gate information based on the second quantum circuit.

[0104] In certain embodiments, the processor is further configured to split the first quantum circuit based on hardware performance to determine a second quantum circuit, and determine target two-bit quantum gate information based on the second quantum circuit.

[0105] Specifically, splitting is a crucial step in quantum circuit weaving technology. In certain implementations, this process can be based on the performance limitations of current quantum computing hardware (e.g., number of bits, coherence time, gate operation errors, etc.), splitting a first quantum circuit into multiple second quantum circuits that can independently run on the quantum computing hardware. This process involves disconnecting key connections (two-bit gates) in the first quantum circuit, reducing the size of individual quantum circuits and adapting them to the performance capabilities of the quantum computing hardware.

[0106] Hardware performance limitations include qubit count limits, quantum gate count limits, and quantum gate operation errors. The qubit count limit refers to the fact that a quantum computer's qubit count is approximately 50-1000, but due to decoherence, this only supports stable execution of quantum circuits with a scale of tens of qubits. The quantum gate count limit refers to the fact that the coherence time (the time a qubit maintains its quantum state) of a qubit is limited (typically microseconds). If a quantum circuit has too many quantum gates, the execution time may exceed the coherence time, resulting in large errors in the result. Quantum gate operation error refers to the error rate of a two-qubit gate, which accumulates as the number of gates increases.

[0107] The target two-bit quantum gate information is key during the splitting process. It includes the two-bit gate itself and its location within the first quantum circuit. This information provides precise positioning of the "cutting point" for the splitting operation and provides a basis for subsequently replacing the two-bit gate with a single-bit gate.

[0108] The target two-bit quantum gate to be cut is a two-bit gate (such as a key CNOT gate) selected from the first quantum circuit. These two-bit quantum gates are usually "bridges" connecting different second quantum circuits. After cutting, the original circuit can be divided into independent sub-circuits.

[0109] The position information refers to the specific position of the target two-bit quantum gate in the first quantum circuit, for example, and quantum bits .

[0110] Continuing with the above example, please refer to Figures 4(a)-4(e) and 5(a)-5(e). Figures 4(a)-4(e) are schematic diagrams of the structures of the second quantum circuits (C2-1) to (C2-5), and Figures 5(a)-5(e) are schematic diagrams of the structures of the second quantum circuits (C3-1) to (C3-5). The first quantum circuit C1 is disassembled into two parts, that is, the quantum bit Split into the first part, quantum bits Split into the second part. Then, the first part includes the second quantum circuit (C2-1) to (C2-5), the second part is the second quantum circuit (C3-1) to (C3-5), and the target two-bit quantum gate information includes the cut CNOT gate and position information "acting on the quantum bit and quantum bits ”.

[0111] In this way, based on hardware performance, the computer device splits the first quantum circuit and determines the second quantum circuit. Next, based on the second quantum circuit, the computer device determines the target two-bit quantum gate information. This target two-bit quantum gate information includes the split target two-bit quantum gate and its location within the first quantum circuit. In this way, by splitting the first quantum circuit based on hardware performance, a first quantum circuit that cannot be correctly executed due to hardware performance is converted into multiple executable second quantum circuits, allowing complex tasks to be run in stages.

[0112] See also Figure 6 In some embodiments, step 02 (determining the second quantum circuit and target two-bit quantum gate information based on the first quantum circuit) includes:

[0113] 023: Based on the preset splitting algorithm, the first quantum circuit is split and the second quantum circuit is determined;

[0114] 024: Determine the target two-bit quantum gate information based on the second quantum circuit.

[0115] In certain embodiments, the determination module is further configured to split the first quantum circuit based on a preset splitting algorithm to determine a second quantum circuit, and to determine target two-bit quantum gate information based on the second quantum circuit.

[0116] In certain embodiments, the processor is further configured to split the first quantum circuit based on a preset splitting algorithm to determine a second quantum circuit, and to determine target two-bit quantum gate information based on the second quantum circuit.

[0117] Specifically, the splitting process is an important step in quantum circuit braiding technology. In certain embodiments, the splitting process can use a preset splitting algorithm to split the first quantum circuit into multiple second quantum circuits that can be independently run on quantum computing hardware.

[0118] The preset splitting algorithm refers to a regularized method in quantum circuit weaving technology that guides how to split the first quantum circuit into sub-circuits (second quantum circuits) that can run on existing quantum hardware.

[0119] Splitting using a preset splitting algorithm and splitting based on hardware performance are two different strategies for quantum circuits. Splitting based on hardware performance requires manual configuration of the relevant parameters of the quantum computing hardware and is primarily limited by the physical capabilities of the quantum hardware, ensuring that the second quantum circuit can be executed on the hardware. Splitting using a preset splitting algorithm typically involves the algorithm executing automatically without human intervention, with preset mathematical optimization objectives or rules to ensure optimal splitting quality. Splitting based on hardware performance is preferred when precise adaptation to specific hardware is required (such as temporarily using a device with a faulty bit), when manual optimization of critical quantum paths is required (such as preserving a portion of entangled states), or when the circuit scale is small. Splitting based on a preset splitting algorithm is preferred when faced with large-scale, complex circuits, when batch processing tasks are required, or when dynamic adaptation to different hardware topologies is required (such as multi-machine support on a quantum cloud platform).

[0120] It should be noted that splitting processing using a preset splitting algorithm and splitting processing based on hardware performance are not mutually exclusive. In practical applications, they are usually used in combination. For example, the initial splitting plan is first generated using a preset algorithm, and then manually fine-tuned according to the real-time performance of the hardware (such as the current number of available bits) to balance efficiency and hardware adaptability.

[0121] In this way, based on a preset splitting algorithm, the computer device splits the first quantum circuit and determines the second quantum circuit. Next, the computer device determines the target two-bit quantum gate information based on the second quantum circuit. This target two-bit quantum gate information includes the target two-bit quantum gate to be split and its location within the first quantum circuit. In this way, the preset splitting algorithm automatically divides the first quantum circuit into second quantum circuits that meet the hardware scale, eliminating the need for manual grouping. Furthermore, the preset algorithm adjusts the splitting strategy based on the hardware's connectivity, ensuring that the quantum gates within the second quantum circuit meet the hardware's physical connectivity constraints.

[0122] See also Figure 7 In some embodiments, the target two-bit quantum gate information includes a target two-bit quantum gate to be cut. Step 03 (determining a target single-bit quantum gate operation set based on the target two-bit quantum gate information) includes:

[0123] 031: Equivalently disassemble the target two-bit quantum gate and determine the initial single-bit quantum gate operation set;

[0124] 032: Merge the initial single-bit quantum gate operation set to determine the target single-bit quantum gate operation set.

[0125] In certain embodiments, the determination module is configured to perform an equivalent decomposition of the target two-bit quantum gate to determine an initial set of single-bit quantum gate operations, and to merge the initial set of single-bit quantum gate operations to determine a target set of single-bit quantum gate operations.

[0126] In certain embodiments, the processor is further configured to perform an equivalent decomposition of the target two-bit quantum gate to determine an initial set of single-bit quantum gate operations, and to merge the initial set of single-bit quantum gate operations to determine a target set of single-bit quantum gate operations.

[0127] Specifically, equivalent disassembly refers to the process of disassembling the target two-bit quantum gate (such as CNOT, CZ gate, etc.) into a combination of single-bit quantum gate operations through mathematical transformations or quantum gate identities, so that the overall effect of this set of single-bit operations is completely equivalent to the original two-bit gate. The purpose is to replace the cut two-bit gate with a single-bit gate, splitting the original circuit into sub-circuits (second quantum circuits) that can be executed on hardware, while retaining the relevant information of the original circuit so that the results can be reconstructed through classical calculations later. For example, The two-bit gate can be disassembled into ,in, The corresponding weight is , The corresponding weight is , The corresponding weight is , The corresponding weight is , The corresponding weight is , The corresponding weight is .

[0128] The initial single-bit quantum gate operation set refers to the preliminary result after equivalent decomposition, which includes all the single-bit gate operations generated by decomposition and their supporting information. The initial single-bit quantum gate operation set includes the initial single-bit quantum gate operation, the weight corresponding to the initial single-bit quantum gate operation, and the mapping relationship between the initial single-bit quantum gate operation and the second quantum circuit. Among them, the initial single-bit quantum gate operation refers to the single-bit gate sequence generated after decomposing the two-bit gate, such as , each operation acts only on a single qubit and can be directly executed by quantum hardware. The weight corresponding to the initial single-bit quantum gate operation Refers to a complex or real number that quantifies the contribution of the operation to the effect of the original two-bit gate. The mapping relationship between the initial single-bit quantum gate operation and the second quantum circuit refers to the corresponding relationship between each single-bit gate operation and the cut sub-circuit (second quantum circuit), such as, Acting on the second quantum circuit (C2-1) to (C2-5), Acts on the second quantum circuit (C3-1) to (C3-5).

[0129] The target single-bit quantum gate operation set is the optimized result of merging the initial single-bit quantum gate operation set. By merging repeated or equivalent single-bit gate operations, the number of secondary quantum circuits and hardware sampling overhead are reduced while preserving the computational information of the original circuit. Because the initial single-bit quantum gate operation set may contain a large number of repeated operations, these repeated operations will lead to a surge in the number of sub-circuits. The hardware will need to run the same sub-circuits multiple times, increasing execution costs. Therefore, merging the initial single-bit quantum gate operation set is necessary.

[0130] Continuing with the above example, the computer device performs equivalent disassembly processing on the target two-bit quantum gate CNOT gate and determines the initial single-bit quantum gate operation set equivalent to the CNOT gate. ,in, The corresponding weight is 0.5, The corresponding weight is 0.5, The corresponding weight is 0.5, The corresponding weight is -0.5, The corresponding weight is 0.5, The corresponding weight is 0.5. And, Acting on the second quantum circuits (C2-1) to (C2-5) respectively (corresponding to Figure 4 (a) - Figure 4 (e)), Acting on the second quantum circuits (C3-1) to (C3-5) respectively (corresponding to Figure 5 (a) - Figure 5 (e)). It should be noted that, Indicates first application The door is then measured.

[0131] Next, the initial single-bit quantum gate operation set is merged to determine the target single-bit quantum gate operation set. and , and the corresponding weights and mapping relationship between the initial single-bit quantum gate operation and the second quantum circuit.

[0132] In this way, the computer device equivalently disassembles the target two-bit quantum gate to determine an initial set of single-bit quantum gate operations. This initial set of single-bit quantum gate operations includes the initial single-bit quantum gate operation, the weight corresponding to the initial single-bit quantum gate operation, and the mapping relationship between the initial single-bit quantum gate operation and the second quantum circuit. The computer device then merges the initial set of single-bit quantum gate operations to determine the target set of single-bit quantum gate operations. This equivalent disassembly ensures the correctness of the quantum computation and facilitates the subsequent restoration of the first quantum circuit. Furthermore, this merging process reduces the number of quantum circuits that the quantum hardware needs to execute, thereby reducing hardware execution overhead and improving quantum simulation efficiency.

[0133] See also Figure 8 In certain embodiments, the method further comprises:

[0134] 04: Determine the target measurement result based on the second quantum circuit and the target single-bit quantum gate operation set.

[0135] In some embodiments, the determination module is further configured to determine a target measurement result based on the second quantum circuit and the target single-bit quantum gate operation set.

[0136] In some embodiments, the processor is further configured to determine a target measurement result based on the second quantum circuit and the target single-bit quantum gate operation set.

[0137] Specifically, the target measurement result refers to the measurement result equivalent to the original initial quantum circuit, which is obtained by running the second quantum circuit through quantum hardware and combining the weights in the target single-bit quantum gate operation set.

[0138] The computer device runs the second quantum circuit and the single-bit quantum gates in the target single-bit quantum gate operation set through quantum hardware, and combines classical weighted calculations to reorganize the split local results into the target measurement results.

[0139] In this way, the computer device determines the target measurement result based on the second quantum circuit and the target set of single-bit quantum gate operations. This combines the target set of single-bit quantum gate operations obtained through quantum hardware execution with the second quantum circuit to obtain the target measurement result, improving hardware execution efficiency while preventing loss of quantum circuit information.

[0140] See also Figure 9 In some embodiments, step 04 (determining a target measurement result based on the second quantum circuit and the target single-bit quantum gate operation set) includes:

[0141] 041: Determine a first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation;

[0142] 042: Determine, based on the first measurement result, a complete operation result corresponding to the initial single-bit quantum gate operation;

[0143] 043: Determine the target measurement result based on the complete operation result and the weight corresponding to the initial single-bit quantum gate operation.

[0144] In some embodiments, the determination module is further configured to determine a first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation; determine a complete operation result corresponding to the initial single-bit quantum gate operation based on the first measurement result; and determine a target measurement result based on the complete operation result and a weight corresponding to the initial single-bit quantum gate operation.

[0145] In some embodiments, the processor is further configured to determine a first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation; determine a complete operation result corresponding to the initial single-bit quantum gate operation based on the first measurement result; and determine a target measurement result based on the complete operation result and a weight corresponding to the initial single-bit quantum gate operation.

[0146] Specifically, the first measurement result refers to the original probability distribution corresponding to each initial single-bit quantum gate operation in the target single-bit quantum gate operation set, determined by actually running and measuring the second quantum circuit obtained through quantum hardware. For example, using the six groups of initial single-bit quantum gate operations in the CNOT gate decomposition as an example, there are a total of ten first measurement results. Please refer to Figure 4(a), which shows the data obtained after running the quantum circuit shown in Figure 4(a) as one of the first measurement results.

[0147] The complete operation result is the set of the first measurement results corresponding to all initial single-bit gate operations, that is, the measurement results covering all possible single-bit operation combinations, ensuring that the calculation results of the original quantum circuit can be fully restored after weighted recombination. Taking the 6 groups of initial single-bit quantum gate operations disassembled by the CNOT gate as an example, the complete operation result includes a set of 6 elements, namely The corresponding measurement results.

[0148] First, each initial single-bit gate operation is applied to the subcircuit, running the hardware and measuring to obtain the original probability distribution corresponding to each operation. Next, all first measurement results are aggregated into a single set to ensure coverage of all initial operations. Finally, through classical calculation, each probability distribution in the complete operation result is multiplied by the weight (squared modulus) of the corresponding initial operation and then summed to obtain the equivalent measurement result of the original circuit.

[0149] In this way, the computer device determines the first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation. Next, based on the first measurement result, the computer device determines the complete operation result corresponding to the initial single-bit quantum gate operation. Finally, the computer device determines the target measurement result based on the complete operation result and the weight corresponding to the initial single-bit quantum gate operation. In this way, through mathematical derivation and weight superposition, the calculation results of the original initial quantum circuit can be efficiently reproduced without losing any quantum information, breaking through the scale limitations of existing quantum hardware and ensuring the efficiency and accuracy of the actual execution of large-scale quantum circuits.

[0150] See also Figure 10 In some embodiments, step 041 (determining a first measurement result based on the second quantum circuit and the initial single-bit quantum gate operation) includes:

[0151] 0411: Determine the target sub-circuit variant based on the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship;

[0152] 0412: Determine, according to the target sub-line variant, a first measurement result corresponding to the target sub-line variant.

[0153] In some embodiments, the determination module is further configured to determine a target subcircuit variant based on the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship, and determine a first measurement result corresponding to the target subcircuit variant based on the target subcircuit variant.

[0154] In some embodiments, the processor is further configured to determine a target subcircuit variant based on the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship, and determine a first measurement result corresponding to the target subcircuit variant based on the target subcircuit variant.

[0155] Specifically, the target subcircuit variant refers to the executable subcircuit version generated by modifying the second quantum circuit (original subcircuit) according to the initial single-bit quantum gate operation in the quantum circuit weaving technology. That is, the initial single-bit gate operation is injected into the second quantum circuit to generate multiple variants (subcircuits with different operation versions). Each variant needs to run independently on the quantum hardware, and finally restore the computational output of the original circuit through weighted recombination of the measurement results. For example, please refer to Figure 4 (a)-Figure 4 (e), Figure 4 (a)-Figure 4 (e) is Add the first part of the quantum circuit (i.e. quantum bit ) is the target sub-circuit variant obtained after .

[0156] After determining the target subcircuit variant, quantum measurement data (first measurement result) is obtained by running the generated subcircuit variant, providing an experimental basis for subsequent result reconstruction.

[0157] In this way, the computer device determines the target subcircuit variant based on the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship. Next, the computer device determines the first measurement result corresponding to the target subcircuit variant based on the target subcircuit variant. In this way, through the combined effect of the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship, quantum state evolution deviations caused by operational mapping errors are avoided, ensuring the physical feasibility and logical correctness of the target subcircuit variant.

[0158] See also Figure 11 In some embodiments, step 0411 (determining a target subcircuit variant based on the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship) includes:

[0159] 04111: Based on the mapping relationship, the initial single-bit quantum gate operation and the second quantum circuit are spliced ​​to determine the target sub-circuit variant.

[0160] In some embodiments, the determination module is further configured to perform a splicing process on the initial single-bit quantum gate operation and the second quantum circuit according to the mapping relationship to determine a target sub-circuit variant.

[0161] In some embodiments, the processor is further configured to perform a splicing process on the initial single-bit quantum gate operation and the second quantum circuit according to the mapping relationship to determine a target sub-circuit variant.

[0162] Specifically, taking quantum circuit C as an example, quantum circuit C includes The H gate acts on the quantum bit and quantum bits After splitting the quantum circuit C, two second quantum circuits C2 and C3 are generated. The second quantum circuit C2 includes quantum bits and acting on quantum bits All operations in (excluding CNOT gates), the second quantum circuit C3 includes quantum bits and acting on quantum bits All operations in (excluding CNOT gates).

[0163] Then, the initial single-bit quantum gate operation is obtained by disassembling and merging the CNOT gate. , respectively add the second quantum circuit C2 to obtain the corresponding target sub-circuit variant. According to the initial single-bit quantum gate operation obtained by disassembling and merging the CNOT gate , respectively adding the second quantum circuit C3 to obtain the corresponding target sub-circuit variant. Among them, the mapping relationship is used to determine the correspondence between the initial single-bit quantum gate operation and the second quantum circuit, that is, to determine which second quantum circuit the initial single-bit quantum gate operation should be spliced ​​with.

[0164] In this way, the computer device splices the initial single-bit quantum gate operation and the second quantum circuit according to the mapping relationship to determine the target sub-circuit variant. In this way, the mapping-driven splicing process ensures the accuracy of the target sub-circuit variant generation.

[0165] See also Figure 12 In some embodiments, step 042 (determining, based on the first measurement result, a complete operation result corresponding to the initial single-bit quantum gate operation) includes:

[0166] 0421: Determine a complete operation result corresponding to the initial single-bit quantum gate operation according to the mapping relationship and the first measurement result.

[0167] In some embodiments, the confirmation module is further configured to determine a complete operation result corresponding to the initial single-bit quantum gate operation based on the mapping relationship and the first measurement result.

[0168] In some embodiments, the processor is further configured to determine a complete operation result corresponding to the initial single-bit quantum gate operation based on the mapping relationship and the first measurement result.

[0169] Specifically, the mapping relationship refers to the correspondence between the initial single-bit quantum gate operation and the second quantum circuit. This mapping relationship can bind the first measurement result of the quantum hardware to the theoretical initial single-bit gate operation one by one, forming a complete data set covering all operations, ensuring that no information is missed when the original circuit results are subsequently reconstructed. For example, if the initial single-bit gate operation set is {initial single-bit quantum gate operation 1, initial single-bit quantum gate operation 2, …, initial single-bit quantum gate operation n}, and the corresponding first measurement results are {result 1; result 2; …; result n}, then the complete operation results can be expressed as: {operation 1: result 1; operation 2: result 2; …; operation n: result n}.

[0170] Continuing with the above example, if the second quantum circuit C2 The first measurement result of the corresponding target subcircuit variant is M1, and the second quantum circuit C2 The first measurement result of the corresponding target subcircuit variant is M2, and the second quantum circuit C2 The first measurement result of the corresponding target subcircuit variant is M3, and the second quantum circuit C2 The first measurement result of the corresponding target subcircuit variant is M4, and the second quantum circuit C2 The first measurement result of the corresponding target subcircuit variant is M5. The first measurement result of the corresponding target subcircuit variant is M6, and the second quantum circuit C3 The first measurement result of the corresponding target subcircuit variant is M7, and the second quantum circuit C3 The first measurement result of the corresponding target subcircuit variant is M8, and the second quantum circuit C3 The first measurement result of the corresponding target subcircuit variant is M9, and the second quantum circuit C3 The first measurement result of the corresponding target sub-line variant is M10.

[0171] Then, according to the mapping relationship, the complete operation results include Results 、 Results 、 Results 、 Results 、 Results 、 Results .

[0172] In this way, the computer device determines the complete operation result corresponding to the initial single-bit quantum gate operation based on the mapping relationship and the first measurement result. In this way, the combination of measurement results driven by the mapping relationship achieves a systematic integration of local measurement results into the complete operation result.

[0173] See also Figure 13 In some embodiments, the target two-bit quantum gate information includes position information of the target two-bit quantum gate in the first quantum circuit. Step 043 (determining the target measurement result based on the complete operation result and the weight corresponding to the initial single-bit quantum gate operation) includes:

[0174] 0431: Multiply the complete operation result and the weight corresponding to the initial single-bit quantum gate operation to determine the temporary processing result;

[0175] 0432: Determine the target measurement result based on the temporary processing result and position information.

[0176] In some embodiments, the determination module is further configured to multiply the complete operation result by the weight corresponding to the initial single-bit quantum gate operation to determine a temporary processing result, and to determine a target measurement result based on the temporary processing result and the position information.

[0177] In some embodiments, the processor is further configured to multiply the complete operation result by the weight corresponding to the initial single-bit quantum gate operation to determine a temporary processing result, and to determine a target measurement result based on the temporary processing result and the position information.

[0178] Specifically, the temporary processing result is the product of each complete operation result and the square of the corresponding weight modulus, reflecting the contribution of each initial operation to the original line result.

[0179] Positional information determines how interim processing results are integrated. If the target two-bit quantum gate is located at the end of the original quantum circuit (i.e., its function is the final operation), the target measurement result is the weighted sum of all interim processing results (since no subsequent operations affect it). If the target two-bit quantum gate is located at the end or middle of the original quantum circuit, the quantum state evolution of the preceding and following operations must be considered, potentially requiring temporal convolution or state updates of the interim processing results.

[0180] Continuing with the above example, according to Results 、 Results 、 Results 、 Results 、 Results 、 Results , and the weights corresponding to the above complete operation results {0.5, 0.5, 0.5, -0.5, 0.5, -0.5}, determine the temporary processing results.

[0181] Then, all temporary processing results are summed up to determine the target measurement result. And according to the position information, the integration method of the temporary processing results is determined.

[0182] In this way, the computer multiplies the complete operation result by the weight corresponding to the initial single-bit quantum gate operation to determine a temporary processing result. The computer then determines the target measurement result based on the temporary processing result and the position information. In this way, by associating the weight distribution with the position information, a precise mapping is achieved between the fragmented target subcircuit variant measurement results and the original initial quantum circuit global result.

[0183] The following is a complete example to illustrate the implementation method of the above quantum circuit weaving. Figure 14 , Figure 14 This is a schematic diagram of the structure of quantum circuit D, which includes the quantum bits and quantum bits The process is as follows: First, check whether the quantum circuit D has been compiled into a form with only single-bit gates and two-bit gates. If the compilation is not complete, recompile the quantum circuit D into a form with only single-bit gates and two-bit gates. If the compilation is complete, it will be decomposed into two parts according to the dotted line. The first part includes the quantum bit and quantum bits and the quantum bits in the original circuit and quantum bits All operations, the second part includes quantum bits and quantum bits and the quantum bits in the original circuit and quantum bits All operations of . In this decomposition, the quantum bit and quantum bits The two CNOT gates in between will be cut.

[0184] Next, a set of single-bit quantum gate operations is used to replace the two-bit quantum gates that were cut, generating an equivalent set of single-bit quantum gate operations and corresponding weights. After the two CNOT gates are cut, the two parts of the sub-circuit will each generate 6^2=36 initial single-bit quantum gate operations.

[0185] Then, the 36 initial single-bit quantum gate operations are merged and simplified, that is, the repeated initial single-bit quantum gate operations are merged and simplified to obtain 5^2=25 non-repeating initial single-bit quantum gate operations (that is, the target single-bit quantum gate operation set).

[0186] Subsequently, these non-repeating initial single-bit quantum gate operations are spliced ​​with the corresponding second quantum circuit to determine the target subcircuit variant. Please refer to Figures 15(a)-15(c). Figure 15(a) shows the first subcircuit variant, the second subcircuit variant, and the 25th subcircuit variant. The dotted box shows the single-bit quantum operation used to replace the two CNOTs.

[0187] Then, these sub-circuit variants are respectively run on hardware to collect measurement results (ie, first measurement results).

[0188] Then, the complete quantum operation is restored to the inner product set of 36 complete variants (i.e., the complete operation result).

[0189] Finally, the original line properties are restored by combining weight calculation, that is, the local results of the sub-lines are reorganized through classical calculation to restore the global properties of the original line.

[0190] The present application also provides a computer-readable storage medium containing a computer program. When the computer program is executed by one or more processors, the one or more processors execute the method of the present application.

[0191] It is understood that a computer program includes computer program code. The computer program code may be in source code form, object code form, executable file, or some intermediate form. Computer-readable storage media may include any entity or device capable of carrying computer program code, recording media, USB flash drives, removable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution media.

[0192] In the description of this specification, the descriptions with reference to the terms "particularly", "further", "particularly", "understandably", etc. are intended to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms are not intended to refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0193] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0194] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for realizing quantum circuit braiding, characterized in that: The method comprises: Compiling the obtained initial quantum circuit to determine a first quantum circuit, where the first quantum circuit only includes a single-bit quantum gate and a two-bit quantum gate; Splitting the first quantum circuit to determine a second quantum circuit; Determining target two-bit quantum gate information according to the second quantum circuit, where the target two-bit quantum gate information includes the cut target two-bit quantum gate and position information of the target two-bit quantum gate in the first quantum circuit; performing an equivalent disassembly of the target two-bit quantum gate to determine an initial single-bit quantum gate operation set, wherein the initial single-bit quantum gate operation set includes an initial single-bit quantum gate operation, a weight corresponding to the initial single-bit quantum gate operation, and a mapping relationship between the initial single-bit quantum gate operation and the second quantum circuit; The initial single-bit quantum gate operation set is merged to determine the target single-bit quantum gate operation set.

2. The method according to claim 1, characterized in that The splitting of the first quantum circuit to determine the second quantum circuit includes: Based on hardware performance, the first quantum circuit is split and processed to determine the second quantum circuit.

3. The method according to claim 1, characterized in that The splitting of the first quantum circuit to determine the second quantum circuit includes: Based on a preset splitting algorithm, the first quantum circuit is split to determine the second quantum circuit.

4. The method according to claim 1, wherein The method further comprises: A target measurement result is determined according to the second quantum circuit and the target single-bit quantum gate operation set.

5. The method according to claim 4, characterized in that Determining a target measurement result according to the second quantum circuit and the target single-bit quantum gate operation set includes: determining a first measurement result according to the second quantum circuit and the initial single-bit quantum gate operation; Determining a complete operation result corresponding to the initial single-bit quantum gate operation according to the first measurement result; The target measurement result is determined according to the complete operation result and the weight corresponding to the initial single-bit quantum gate operation.

6. The method according to claim 5, characterized in that Determining a first measurement result according to the second quantum circuit and the initial single-bit quantum gate operation includes: determining a target sub-circuit variant according to the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship; According to the target sub-line variant, a first measurement result corresponding to the target sub-line variant is determined.

7. The method according to claim 6, characterized in that The determining of a target sub-circuit variant according to the initial single-bit quantum gate operation, the second quantum circuit, and the mapping relationship includes: According to the mapping relationship, the initial single-bit quantum gate operation and the second quantum circuit are spliced ​​to determine the target sub-circuit variant.

8. The method according to claim 5, characterized in that Determining, based on the first measurement result, a complete operation result corresponding to the initial single-bit quantum gate operation includes: A complete operation result corresponding to the initial single-bit quantum gate operation is determined according to the mapping relationship and the first measurement result.

9. The method according to claim 5, characterized in that Determining the target measurement result according to the complete operation result and the weight corresponding to the initial single-bit quantum gate operation includes: multiplying the complete operation result by a weight corresponding to the initial single-bit quantum gate operation to determine a temporary processing result; The target measurement result is determined according to the temporary processing result and the position information.

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