Display device

Abstract

The invention relates to a display device. The display device includes a substrate on which is disposed a display panel configured to display an image corresponding to image data, a data driver configured to apply a plurality of data signals corresponding to the image data to the display panel, a level shifter configured to change a voltage level of the image data, and a first pad; a controller is disposed on the control substrate, the controller is configured to output image data to the level shifter, and the control substrate is attached to the substrate in a vertical direction through the first pad.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefits of Korean Patent Application No. 10 - 2024 - 0014225, filed with the Korean Intellectual Property Office on January 30, 2024, and Korean Patent Application No. 10 - 2024 - 0047266, filed with the Korean Intellectual Property Office on April 8, 2024. The entire disclosure of the Korean patent applications is incorporated herein by reference. Technical field

[0003] Aspects of some embodiments of the present disclosure relate to a display device. Background art

[0004] With the development of information technology, the importance of display devices that provide a connection medium between users and information is emerging. Accordingly, the use of display devices such as liquid crystal display devices, organic light - emitting display devices, and inorganic light - emitting display devices is increasing.

[0005] A display device may include a display panel on which an image is displayed and a controller that controls the display panel. Various methods may be provided for connecting a substrate on which the display panel is disposed and a substrate on which the controller is disposed.

[0006] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the invention

[0007] Aspects of some embodiments of the present disclosure include a display device including a substrate on which a display panel is disposed and a substrate on which a controller is disposed.

[0008] According to some embodiments of the present disclosure, the display device includes a substrate and a control substrate. On the substrate, there are provided: a display panel that displays an image corresponding to image data; a data driver that applies a plurality of data signals corresponding to the image data to the display panel; a level shifter that changes the voltage level of the image data; and a first pad. On the control substrate, there is a controller that outputs the image data to the level shifter, and the control substrate is attached to the substrate in a vertical direction through the first pad.

[0009] According to some embodiments, the data driver and the level shifter may be configured as one integrated circuit.

[0010] According to some embodiments, a gate driver that applies a plurality of gate signals to the display panel may further be provided on the substrate.

[0011] According to some embodiments, the substrate may include a display area in which a display panel is positioned, and a non-display area in which a first pad, a data driver, a gate driver, and a level shifter are positioned.

[0012] According to some embodiments, the first pad, the level shifter, and the data driver may be on a first side surface of the display panel, the gate driver may be on a second side surface of the display panel, and the first side surface and the second side surface may be perpendicular to each other.

[0013] According to some embodiments, the first pad, the level shifter, and the gate driver may be on a first side surface of the display panel, the data driver may be on a second side surface of the display panel, and the first side surface and the second side surface may be perpendicular to each other.

[0014] According to some embodiments, the gate driver may include a first sub-gate driver and a second sub-gate driver. The first pad, the level shifter, and the first sub-gate driver may be on the first side surface, the data driver may be on the second side surface, the second sub-gate driver may be on a third side surface of the display panel, the second side surface and the third side surface may be perpendicular to each other, and the first side surface and the third side surface may be parallel to each other.

[0015] According to some embodiments, the data driver may include a sampling latch and a holding latch, and image data may be output to the display panel in this order through the level shifter, the sampling latch, and the holding latch.

[0016] According to some embodiments, the image data output from the controller to the level shifter may be a digital signal.

[0017] According to some embodiments, the control substrate may be formed as a silicon wafer substrate.

[0018] According to some embodiments of the present disclosure, a display device includes a substrate and a control substrate. A display panel for displaying an image corresponding to image data and a first pad on a first side surface of the display panel are provided on the substrate; a data driver and a controller are provided on the control substrate. The data driver applies a plurality of data signals corresponding to the image data to the display panel, and the controller outputs the image data to the data driver. Among them, the control substrate is attached to the substrate in the vertical direction through the first pad. A gate driver is further provided on the substrate, and the gate driver is on a second side surface of the display panel, and the first side surface and the second side surface are perpendicular to each other.

[0019] According to some embodiments, the control substrate may be formed as a silicon wafer substrate.

[0020] According to some embodiments, the controller and the data driver may be configured as an integrated circuit.

[0021] According to some embodiments, a gate driver may apply a plurality of gate signals to a display panel.

[0022] According to some embodiments, a substrate may include a display area in which a display panel is positioned, and a non-display area in which a first pad and a gate driver are positioned.

[0023] According to some embodiments, a level shifter may be further provided on the substrate, a data driver may include a sampling latch and a holding latch, and image data may be output to the display panel through the sampling latch, the holding latch, and the level shifter in this order.

[0024] According to some embodiments of the present disclosure, a display device includes a substrate, a control circuit board, and a connection circuit board. A display panel and a data driver are provided on the substrate. The display panel displays an image corresponding to image data, and the data driver applies a plurality of data signals corresponding to the image data to the display panel. A controller that outputs the image data to the data driver is provided on the control circuit board. The connection circuit board connects the substrate and the control circuit board.

[0025] According to some embodiments, a first pad may be further provided on the substrate, a second pad may be further provided on the control circuit board, and one end of the connection circuit board may be connected to the first pad, and the other end of the connection circuit board may be connected to the second pad.

[0026] According to some embodiments, the control circuit board may be formed as a silicon wafer substrate.

[0027] According to some embodiments, the control circuit board may be a printed circuit board, and the connection circuit board may be a flexible circuit board.

[0028] In a display device according to some embodiments of the present disclosure, the design freedom can be relatively improved, and the power consumption can be relatively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A block diagram of a display device according to some embodiments is shown.

[0030] Figure 2 Shown is Figure 1 a top view of an embodiment of a display panel of

[0031] Figure 3 Shown is Figure 2 an exploded perspective view of a part of a display panel of

[0032] Figure 4 A block diagram showing a connection relationship between a substrate and a controller according to some embodiments is shown.

[0033] Figure 5 shows the Figure 4 top view of an embodiment of

[0034] Figure 6 shows the Figure 4 cross-sectional view of an embodiment of

[0035] Figure 7 block diagram showing the connection relationship between a substrate and a controller according to some embodiments.

[0036] Figure 8 shows the Figure 7 top view of an embodiment of

[0037] Figure 9 shows the Figure 7 cross-sectional view of an embodiment of

[0038] Figure 10 block diagram showing the connection relationship between a substrate and a controller according to some embodiments.

[0039] Figure 11 shows the Figure 10 top view of an embodiment of

[0040] Figure 12 shows the Figure 10 cross-sectional view of an embodiment of

[0041] Figure 13 block diagram showing the connection relationship between a substrate and a controller according to some embodiments.

[0042] Figure 14 shows the Figure 13 cross-sectional view of an embodiment of

[0043] Figure 15 block diagram showing the connection relationship between a substrate and a controller according to some embodiments.

[0044] Figure 16 shows the Figure 15 cross-sectional view of an embodiment of

[0045] Figure 17 block diagram of a display system according to some embodiments.

[0046] Figure 18 shows the Figure 17 three-dimensional view of an application example of a display system of

[0047] Figure 19 shows Figure 18 head-mounted display device worn by a user of Detailed Embodiments

[0048] In the following, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The following description is intended to provide only sufficient disclosure to enable an understanding of the operation of the present invention, and any other disclosure is omitted to avoid obscuring the scope of the present invention. In addition, the inventive concept may be implemented in different forms and is not limited to the embodiments set forth herein. The embodiments described herein are provided so that the technical concept of the present invention is described in sufficient detail for those skilled in the art to easily practice the present invention.

[0049] Throughout the specification, when an element is described as "connected" to another element, this includes not only "directly connected" but also "indirectly connected" by another device therebetween. The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the scope of the present invention. Throughout the specification, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as, by way of example, XYZ, XY, YZ, and XZ). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Although terms such as "first" and "second" may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Thus, without departing from the teachings of the present disclosure, the first component discussed below may be referred to as the second component.

[0051] For descriptive purposes, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein, and thereby describe the relationship of one element or feature to another (other) element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device during use, operation, and / or manufacturing. For example, if the device in the figures is flipped, an element or feature described as "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an upper and a lower orientation. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thereby, the spatial relative descriptors used herein will be interpreted accordingly.

[0052] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As a result, deviations from the shapes as illustrated due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments disclosed herein should not be construed as being limited to the shapes of particular regions shown, but rather include deviations in shapes resulting from, for example, manufacturing. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to be limiting.

[0053] Figure 1 A block diagram of a display device according to some embodiments is shown.

[0054] Reference Figure 1 , the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0055] The display panel 110 includes sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through first gate lines GL1 to m-th gate lines GLm. The sub-pixels SP may be connected to the data driver 130 through first data lines DL1 to n-th data lines DLn.

[0056] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Thus, the sub-pixels SP may respectively generate light of a specific color such as red, green, blue, cyan, magenta, yellow, etc. Two or more of the sub-pixels SP may configure one pixel PXL. For example, as Figure 1 shown, three sub-pixels SP may configure one pixel PXL.

[0057] The gate driver 120 is connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 can output gate signals to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. According to some embodiments, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting gate signals synchronously with the timing of applying data signals, and the like.

[0058] In some embodiments, the first emission control lines EL1 to the m-th emission control lines ELm connected to the sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to the m-th emission control lines ELm, and the emission control driver may operate under the control of the controller 150.

[0059] The gate driver 120 may be located on one side of the display panel 110. However, the embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and these drivers may be located on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. As described above, according to embodiments, the gate driver 120 may be arranged around the display panel 110 in various forms.

[0060] The data driver 130 is connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. According to some embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0061] The data driver 130 may use the voltage from the voltage generator 140 to apply data signals having gray-scale voltages corresponding to the image data DATA to the first data line DL1 to the n-th data line DLn. When a gate signal is applied to each of the first gate line GL1 to the m-th gate line GLm, data signals corresponding to the image data DATA may be applied to the data lines DL1 to DLm. Accordingly, the corresponding sub-pixels SP may generate light corresponding to the data signals. Thus, an image is displayed on the display panel 110.

[0062] According to some embodiments, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0063] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and supply the generated voltages to components of the display device 100. For example, the voltage generator 140 can be configured to generate a plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0064] The voltage generator 140 can generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first power supply voltage VDD and second power supply voltage VSS can be supplied to the sub-pixel SP. The first power supply voltage VDD can have a relatively high voltage level, and the second power supply voltage VSS can have a voltage level lower than that of the first power supply voltage VDD. According to some embodiments, the first power supply voltage VDD or the second power supply voltage VSS can be provided by an external device of the display device 100.

[0065] In addition, the voltage generator 140 can generate various voltages. For example, the voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing the electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a reference voltage (e.g., a set or predetermined reference voltage) can be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 can generate the reference voltage.

[0066] The controller 150 controls various operations of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from the outside. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0067] The controller 150 can convert the input image data IMG into a form suitable for the display device 100 or the display panel 110 to output image data DATA. According to some embodiments, the controller 150 can output the image data DATA by adjusting the input image data IMG to be suitable for the sub-pixels SP of the row unit.

[0068] Two or more of the data driver 130, the voltage generator 140, and the controller 150 can be configured as one integrated circuit.

[0069] According to some embodiments, the controller 150 can be configured as one integrated circuit and located on a printed circuit board (PCB). This will be described in more detail later with reference to Figures 4 to 6 for a more detailed description.

[0070] According to some embodiments, the data driver 130 and the controller 150 may be configured as an integrated circuit and located on a control substrate. In this case, the data driver 130 and the controller 150 may be functionally separated components within an integrated circuit. This will be described in more detail later with reference to Figures 7 to 9 for a more detailed description.

[0071] According to some embodiments, the controller 150 may be configured as an integrated circuit and located on a control substrate. This will be described in more detail later with reference to Figures 10 to 16 for a more detailed description.

[0072] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense the ambient temperature and generate temperature data TEP representative of the sensed temperature.

[0073] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. According to some embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power supply voltage VDD and the second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0074] Figure 2 Shows a top view of a Figure 1 display panel according to some embodiments.

[0075] Referring to Figure 2 , the display panel DP (which is an example of the Figure 1 display panel 110) may include a display area DA and a non-display area NDA. The display panel DP displays an image at the display area DA. The non-display area NDA is arranged around the display area DA (for example, at the periphery of the display area DA or outside the position occupied by the display area DA).

[0076] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0077] When the display panel DP is used as a display screen of a head-mounted display (HMD), virtual reality (VR) device, mixed reality (MR) device, or augmented reality (AR) device, the display panel DP may be positioned very close to the user's eyes. In this case, sub-pixels SP with relatively high integration are required. To increase the integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP may be formed on the substrate SUB that is a silicon substrate. The display device 100 including the display panel DP having the substrate SUB that is a silicon substrate (see Figure 1) may be referred to as an OLED on silicon (OLEDoS) display device.

[0078] Sub-pixels SP are located in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix format along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a shape. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0079] Two or more of the plurality of sub-pixels SP may configure one pixel PXL.

[0080] The components for controlling the sub-pixels SP may be located in the non-display area NDA on the substrate SUB. For example, wirings (such as Figure 1 the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn) connected to the sub-pixels SP may be located in the non-display area NDA.

[0081] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, and temperature sensor 160 in Figure 1 may be integrated in the non-display area NDA of the display panel DP. According to some embodiments, Figure 1 the gate driver 120 may be mounted on the display panel DP and may be located in the non-display area NDA. According to some embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. According to some embodiments, the temperature sensor 160 may be located in the non-display area NDA to detect the temperature of the display panel DP.

[0082] The pads PD are located in the non-display area NDA on the substrate SUB. The pads PD may be electrically connected to the sub-pixels SP through wirings. For example, the pads PD may be connected to the sub-pixels SP through the first data lines DL1 to the n-th data lines DLn.

[0083] The pads PD may connect the display panel DP to other components of the display device 100 (see Figure 1 ). According to some embodiments, the voltages and signals required for the operation of the components included in the display panel DP may be provided from Figure 1 the controller 150 through the pads PD. For example, the first data lines DL1 to the n-th data lines DLn may be connected to the control substrate or printed circuit board on which the controller 150 is mounted through the pads PD.

[0084] According to some embodiments, the display area DA may have various shapes. The display area DA may have a closed-loop shape including sides with straight lines and / or curves. For example, the display area DA may have shapes such as a polygonal shape, a circular shape, a semi-circular shape, and an elliptical shape.

[0085] According to some embodiments, the display panel DP may have a flat display surface. According to some embodiments, the display panel DP may have a display surface that is at least partially rounded. According to some embodiments, the display panel DP may be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB may include materials having flexible properties.

[0086] Figure 3 A partial exploded perspective view of the Figure 2 display panel is shown. In Figure 3 , for clear and concise description, a portion of the display panel DP corresponding to Figure 2 two of the pixels PXL1 and PXL2 among the pixels PXL of

[0087] is schematically shown. The portion of the display panel DP corresponding to the remaining pixels may be configured similarly. Figure 2 and Figure 3 , each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiments are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or two sub-pixels.

[0088] In Figure 3 , the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are shown as having a quadrilateral shape and the same size when viewed in a third direction DR3 (e.g., in a plan view) intersecting the first direction DR1 and the second direction DR2. However, the embodiments are not limited thereto. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be modified to have various shapes.

[0089] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical function layer OFL, an outer coating OC, and a cover window CW.

[0090] According to some embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium.

[0091] The substrate SUB can be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. According to some embodiments, the substrate SUB can include a glass substrate. In other embodiments, the substrate SUB can include a polyimide (PI) substrate.

[0092] The pixel circuit layer PCL is located on the substrate SUB. The pixel circuit layer PCL can include an insulating layer and conductive patterns located between the insulating layers. The conductive patterns of the pixel circuit layer PCL can be used as at least some of circuit elements, wirings, etc.

[0093] The conductive patterns can include copper, but the embodiments are not limited thereto.

[0094] The circuit elements can include sub-pixel circuits for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The sub-pixel circuits can include transistors and one or more capacitors. Each transistor can include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. According to some embodiments, when the substrate SUB is provided as a silicon substrate, the semiconductor portion can be included in the substrate SUB, and the gate electrode can be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. According to some embodiments, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode can be included in the pixel circuit layer PCL. Each capacitor can include electrodes spaced apart from each other. For example, each capacitor can include electrodes spaced apart from each other in a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor can include electrodes spaced apart from each other in a third direction DR3, with an insulating layer therebetween.

[0095] The wirings of the pixel circuit layer PCL can include signal lines connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, such as gate lines, light emission control lines, and data lines. The wirings can further include wirings providing Figure 1 the first power supply voltage VDD. In addition, the wirings can also include wirings providing Figure 1 the second power supply voltage VSS.

[0096] The light-emitting element layer LDL can include an anode electrode AE, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0097] The anode electrode AE can be located on the pixel circuit layer PCL. The anode electrode AE can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE can include an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0098] The pixel defining layer PDL is located on the anode electrode AE. The pixel defining layer PDL may include openings OP that expose portions of each of the anode electrodes AE. The openings OP of the pixel defining layer PDL may be understood as corresponding to the light emitting regions of the first to third sub-pixels SP1 to SP3, respectively.

[0099] According to some embodiments, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). According to some embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0100] The light emitting structure EMS may be located on the anode electrode AE exposed by the openings OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0101] According to some embodiments, the light emitting structure EMS may fill the openings OP of the pixel defining layer PDL and may be disposed entirely on the upper portion of the pixel defining layer PDL. In other words, the light emitting structure EMS may extend across the first to third sub-pixels SP1 to SP3. In this case, at least some of the functional layers in the light emitting structure EMS may be disconnected or bent at the boundaries between the first to third sub-pixels SP1 to SP3. However, the embodiments are not limited thereto. For example, the portions of the light emitting structure EMS corresponding to the first to third sub-pixels SP1 to SP3 are separated from each other, and each of them may be located in the openings OP of the pixel defining layer PDL.

[0102] The cathode electrode CE may be located on the light emitting structure EMS. The cathode electrode CE may extend across the first to third sub-pixels SP1 to SP3. Accordingly, the cathode electrode CE may be provided as a common electrode for the first to third sub-pixels SP1 to SP3.

[0103] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be made of a metal material or a transparent conductive material to have a relatively thin thickness. According to some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. According to some embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited thereto.

[0104] One of the anode electrodes AE, the portion of the light-emitting structure EMS overlapping with the anode electrode AE, and the portion of the cathode electrode CE overlapping with the anode electrode AE can be understood as configuring a light-emitting element. In other words, each of the light-emitting elements in the first sub-pixel SP1 to the third sub-pixel SP3 can include an anode electrode AE, the portion of the light-emitting structure EMS overlapping with the one anode electrode AE, and the portion of the cathode electrode CE overlapping with the one anode electrode AE. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE are transported to the light-emitting layer of the light-emitting structure EMS to form excitons, and when the excitons transition from the excited state to the ground state, light can be generated. The brightness of the light can be determined according to the amount of current flowing through the light-emitting layer. According to the configuration of the light-emitting layer, the wavelength range of the generated light can be determined.

[0105] The encapsulation layer TFE is located on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent or reduce the penetration of contaminants such as oxygen and / or moisture into the light-emitting element layer LDL. According to some embodiments, the encapsulation layer TFE can include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film can include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ). For example, the organic film can include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene. However, the materials of the organic film and the inorganic film of the encapsulation layer TFE are not limited thereto.

[0106] The encapsulation layer TFE can also include a thin film containing aluminum oxide (AlO x ) to relatively improve the encapsulation efficiency of the encapsulation layer TFE. The thin film containing aluminum oxide can be located on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0107] The thin film containing aluminum oxide can be formed by atomic layer deposition (ALD). However, the embodiments are not limited thereto. The encapsulation layer TFE can also include a thin film made of at least one of various materials suitable for relatively improving the encapsulation efficiency.

[0108] The optical function layer OFL is located on the encapsulation layer TFE. The optical function layer OFL can include a color filter layer CFL and a lens array LA.

[0109] The color filter layer CFL is located between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to selectively output light in a wavelength range corresponding to each sub-pixel or light of a corresponding color by filtering the light emitted from the light-emitting structure EMS. The color filter layer CFL includes color filters CF respectively corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, and each of the color filters CF can allow light within the wavelength range corresponding to the sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 can allow red light to pass through, the color filter corresponding to the second sub-pixel SP2 can allow green light to pass through, and the color filter corresponding to the third sub-pixel SP3 can allow blue light to pass through. At least some of the color filters CF can be omitted according to the light emitted from the light-emitting structure EMS of each sub-pixel.

[0110] The lens array LA is located on the color filter layer CFL. The lens array LA can include lenses LS respectively corresponding to the first sub-pixel SP1 to the third sub-pixel SP3. Each of the lenses LS can relatively improve the light output efficiency by outputting the light emitted from the light-emitting structure EMS in an expected path. The lens array LA can have a relatively high refractive index. For example, the lens array LA can have a refractive index higher than that of the outer coating OC. According to some embodiments, the lens LS can include an organic material. According to some embodiments, the lens LS can include an acrylic material. However, the material of the lens LS is not limited thereto.

[0111] According to some embodiments, at least some of the color filters CF in the color filter layer CFL and at least some of the lenses LS in the lens array LA may be shifted in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2, compared to the openings OP of the pixel defining layer PDL. Specifically, in the central region of the display area DA, when viewed in the third direction DR3 (e.g., in a plan view), the centers of the color filters CF and the centers of the lenses LS may be aligned with or overlap the centers of the corresponding openings OP of the pixel defining layer PDL. For example, in the central region of the display area DA, the openings OP of the pixel defining layer PDL may completely overlap the corresponding color filters CF of the color filter layer CFL and the corresponding lenses LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3 (e.g., in a plan view), the centers of the color filters CF and the centers of the lenses LS may be shifted in the plane direction from the centers of the corresponding openings OP of the pixel defining layer PDL. For example, in the region of the display area DA adjacent to the non-display area NDA, the openings OP of the pixel defining layer PDL may partially overlap the corresponding color filters CF of the color filter layer CFL and the corresponding lenses LS of the lens array LA. Thus, at the center of the display area DA, the light emitted from the light emitting structure EMS can be effectively output in the normal direction of the display surface. The light emitted from the light emitting structure EMS outside the display area DA can be effectively output in a direction inclined at an angle (e.g., a set or predetermined angle) with respect to the normal direction of the display surface.

[0112] The outer coating OC may be located on the lens array LA. The outer coating OC may cover the optical functional layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting its underlying layers from foreign substances such as dust and moisture. For example, the outer coating OC may include at least one of an inorganic insulating film and an organic insulating film. For example, the outer coating OC may include an epoxy resin, but the embodiments are not limited thereto. The outer coating OC may have a lower refractive index than the lens array LA.

[0113] The cover window CW may be located on the outer coating OC. The cover window CW is configured to protect its underlying layers. The cover window CW may have a higher refractive index than the outer coating OC. The cover window CW may include glass, but the embodiments are not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect the components located below it. According to some embodiments, the cover window CW may be omitted.

[0114] Figure 4 A block diagram showing the connection relationship between a substrate and a controller according to some embodiments is shown.

[0115] Reference Figure 4, the controller 150 may be located on the control circuit board CP, and the display panel 110, the gate driver 120, and the data driver 130 may be located on Figure 2 the substrate SUB described in

[0116] Figure 4 The display panel 110, the gate driver 120, the data driver 130, and the controller 150 are similar to Figure 1 the display panel 110, the gate driver 120, the data driver 130, and the controller 150 thereof, so redundant descriptions thereof are omitted.

[0117] The controller 150 may convert the input image data IMG to be suitable for the display panel 110 to generate image data DATA.

[0118] The controller 150 may output the image data DATA to the data driver 130 through an interface. For example, the controller 150 may output the image data DATA to the data driver 130 through a low-voltage differential signaling (LVDS) interface.

[0119] Figure 5 shows Figure 4 a top view of an embodiment of

[0120] Referring to Figure 5 , the control circuit board CP and the substrate SUB connected by the connection circuit board FC are shown. For ease of illustration, the connection relationships among the display panel 110, the gate driver 120, and the data driver 130 are omitted.

[0121] A first pad PD1 may also be provided on the control circuit board CP. A second pad PD2 may also be provided on the substrate SUB. The second pad PD2 may be Figure 2 some of the pads PD in

[0122] Referring to Figure 2 , the display panel 110 may be located in the display area DA of the substrate SUB, and the second pad PD2, the gate driver 120, and the data driver 130 may be located in the non-display area NDA of the substrate SUB.

[0123] The control circuit board CP and the substrate SUB may be connected by the connection circuit board FC. According to some embodiments, the control circuit board CP may be a printed circuit board, and the connection circuit board FC may be a flexible circuit board. In addition, according to some embodiments, the control circuit board CP may be formed of a silicon wafer substrate.

[0124] One end of the connection circuit board FC can be connected to the first pad PD1, and the other end of the connection circuit board FC can be connected to the second pad PD2. According to some embodiments, the connection circuit board FC may include a plurality of wirings. One end of each of the plurality of wirings can be connected to the first pad PD1, and the other end of each of the plurality of wirings can be connected to the second pad PD2.

[0125] The controller 150 can output the image data DATA to the substrate SUB through the wirings included in the connection circuit board FC.

[0126] Figure 6 Illustrated is Figure 4 a cross-sectional view of an embodiment of.

[0127] Refer to Figure 6 , which shows the control circuit board CP and the substrate SUB connected through the connection circuit board FC.

[0128] The display panel 110, the gate driver 120, and the data driver 130 can be located on the substrate SUB. According to some embodiments, the gate driver 120 and the data driver 130 can be configured as separate integrated circuits and can be located on the substrate SUB. For ease of illustration, the display panel 110 and the gate driver 120 are shown as being configured as one circuit, but the gate driver 120 can be located on one side of the display panel 110.

[0129] The controller 150 can be located on the control circuit board CP. According to some embodiments, the controller 150 can be configured as an integrated circuit located on the control circuit board CP.

[0130] In addition, the first pad PD1 can be located on the control circuit board CP, and the second pad PD2 can be located on the substrate SUB. The first pad PD1 can be connected to one end of the connection circuit board FC, and the second pad PD2 can be connected to the other end of the connection circuit board FC.

[0131] Figure 7 Illustrated is a block diagram showing the connection relationship between the substrate and the controller according to some embodiments.

[0132] Refer to Figure 7 , the data driver 130 and the controller 150 can be located on the control substrate SC, and the display panel 110 and the gate driver 120 can be located on Figure 2 the substrate SUB described in.

[0133] Figure 7 The display panel 110, the gate driver 120, the data driver 130, and the controller 150 of are similar to Figure 1a display panel 110, a gate driver 120, a data driver 130, and a controller 150, and thus some redundant descriptions thereof can be omitted.

[0134] According to some embodiments, the substrate SUB and the control substrate SC may include a silicon wafer substrate formed using a semiconductor process. The control substrate SC may include a semiconductor material suitable for forming circuit elements. The control substrate SC may be manufactured in the form of a single chip formed from a silicon wafer substrate.

[0135] When the controller 150 and the data driver 130 are located on one substrate, the controller 150 may output image data DATA to the data driver 130 without a separate interface. In this case, the signal output from the data driver 130 to the display panel 110 may be an analog signal.

[0136] According to some embodiments, the substrate SUB may further include a plurality of demultiplexers. The demultiplexers may be located between the data driver 130 and the display panel 110. The demultiplexers may output the signal output from the data driver 130 to a plurality of data lines through one channel.

[0137] Since the interface for the controller 150 to output image data DATA to the data driver 130 is omitted, the power consumption for driving the interface can be relatively reduced.

[0138] However, when the controller 150 and the data driver 130 are located on one control substrate SC, the degree of freedom in designing the control substrate SC may be relatively reduced. For example, since the control substrate SC is manufactured in consideration of the layout structure of the data driver 130 and the display panel 110, the degree of freedom in designing the control substrate SC may be relatively reduced.

[0139] Even when the design or process for the controller 150 is modified, since the entire control substrate SC must be remanufactured instead of only remanufacturing the controller 150, the production cost of the control substrate SC may increase.

[0140] In addition, when the voltages of the power used by the controller 150 and the data driver 130 are different, the production cost of the control substrate SC may increase because processes for separately developing the controller 150 and the data driver 130 are required.

[0141] Figure 8 shows Figure 7 a top view of an embodiment of

[0142] Refer to Figure 8 , a control substrate SC attached to the substrate SUB is shown. For ease of illustration, the connection relationship between the display panel 110 and the gate driver 120 is omitted.

[0143] A second pad PD2 and a third pad PD3 may also be provided on the substrate SUB. The second pad PD2 and the third pad PD3 may be some of the pads PD Figure 2 . The substrate SUB may be connected to an external substrate such as a flexible printed circuit board through the second pad PD2. The substrate SUB may be connected to the control substrate SC through the third pad PD3. That is, the control substrate SC may be attached to the substrate SUB in a third direction DR3 (vertical direction) through the third pad PD3.

[0144] Reference Figure 2 , the display panel 110 may be located in the display area DA of the substrate SUB, and the second pad PD2, the third pad PD3, and the gate driver 120 may be located in the non-display area NDA of the substrate SUB.

[0145] According to some embodiments, the third pad PD3 may be located on a first side surface of the display panel 110, and the gate driver 120 may be located on a second side surface of the display panel 110. The first side surface and the second side surface may be perpendicular to each other. Herein, a component "on" a side surface of the display panel not only may mean that the component is "directly on" the side surface of the display panel, but also may mean that the component "faces" / "is adjacent to" the side surface of the display panel when there are other components therebetween.

[0146] For example, when observed in the third direction DR3 (e.g., in a plan view), the third pad PD3 and the display panel 110 may be positioned along a first direction DR1, and the display panel 110 and the gate driver 120 may be arranged along a second direction DR2.

[0147] According to some embodiments, when the substrate SUB further includes a plurality of demultiplexers, when observed in the third direction DR3 (e.g., in a plan view), the third pad PD3, the demultiplexer, and the display panel 110 may be arranged along the first direction DR1.

[0148] Although Figure 8 the data driver 130 and the controller 150 are shown configured as separate integrated circuits, the present disclosure is not limited thereto, and they may be configured as one integrated circuit and located on the control substrate SC.

[0149] Figure 9 is shown Figure 7 a cross-sectional view of an embodiment.

[0150] Reference Figure 9 , a control substrate SC and a substrate SUB connected through the third pad PD3 are shown.

[0151] The display panel 110 and the gate driver 120 may be located on the substrate SUB. For ease of illustration, the display panel 110 and the gate driver 120 are shown configured as one circuit, but the gate driver 120 may be located on one side of the display panel 110.

[0152] The data driver 130 and the controller 150 may be located on the control substrate SC. According to some embodiments, the data driver 130 and the controller 150 may be configured as a single integrated circuit, or may be configured as separate integrated circuits and located on the control substrate SC.

[0153] In addition, the second pad PD2 and the third pad PD3 may be located on the substrate SUB. The substrate SUB may be connected to another substrate through the second pad PD2 and the connection circuit board FC. The substrate SUB may be connected to the control substrate SC through the third pad PD3.

[0154] Figure 10 A block diagram showing the connection relationship between the substrate and the controller according to some embodiments is shown.

[0155] Reference Figure 10 , the controller 150 may be located on the control substrate SC, and the display panel 110, the gate driver 120, and the data driver 130 may be located Figure 2 on the substrate SUB described in

[0156] Figure 10 The display panel 110, the gate driver 120, the data driver 130, and the controller 150 of Figure 1 are similar to the display panel 110, the gate driver 120, the data driver 130, and the controller 150 of

[0157] According to some embodiments, the substrate SUB and the control substrate SC may be formed of a silicon wafer substrate formed using a semiconductor process.

[0158] When the controller 150 and the data driver 130 are arranged on separate substrates, the degree of freedom in designing the control substrate SC can be increased. For example, when manufacturing the control substrate SC without considering the layout structure of the data driver 130 and the display panel 110, the degree of freedom in designing the control substrate SC can be increased.

[0159] In addition, even if the voltages of the power used by the controller 150 and the data driver 130 are different, only the process for developing the controller 150 is required, and the process for developing the data driver 130 is not required. Therefore, the production cost of the control substrate SC can be relatively reduced.

[0160] In addition, by attaching the control substrate SC to the substrate SUB, the controller 150 can output the image data DATA to the data driver 130 without a separate interface. Therefore, since the interface for the controller 150 to output the image data DATA to the data driver 130 is omitted, the power consumption for driving the interface can be relatively reduced. In this case, the image data DATA can be a digital signal.

[0161] According to some embodiments, the controller 150 and the data driver 130 can transmit and receive the image data DATA through serialization and deserialization. For example, the controller 150 can generate a matrix (or object) by deserializing the image data DATA. The controller 150 can output the matrix to the data driver 130. The data driver 130 can serialize the received matrix and output it to the display panel 110. Through serialization and deserialization, the controller 150 can even output the image data DATA to the data driver 130 at a lower speed than before. Therefore, the power consumed for transmitting and receiving the image data DATA can be relatively reduced.

[0162] According to some embodiments, the substrate SUB may further include a plurality of demultiplexers. The demultiplexer may be located between the data driver 130 and the display panel 110. The demultiplexer can output the signal output from the data driver 130 to a plurality of data lines through one channel.

[0163] Figure 11 Shows Figure 10 a top view of an embodiment of

[0164] Refer to Figure 11 , a control substrate SC attached to the substrate SUB is shown. For ease of illustration, the connection relationships between the display panel 110, the gate driver 120, and the data driver 130 are omitted.

[0165] Because Figure 11 the substrate SUB and the control substrate SC of Figure 10 are similar to the substrate SUB and the control substrate SC of

[0166] Some redundant descriptions thereof can be omitted. Figure 2Some of the pads PD. The substrate SUB can be connected to an external substrate such as a flexible printed circuit board through the second pad PD2. The substrate SUB can be connected to the control substrate SC through the third pad PD3. That is, the control substrate SC can be attached to the substrate SUB in the third direction DR3 through the third pad PD3. For example, the substrate SUB and the control substrate SC can be attached using a ball grid array (BGA) method. However, the present disclosure is not limited thereto, and the substrate SUB and the control substrate SC can be attached by a through-silicon via (TSV) or a hybrid bonding process.

[0167] Reference Figure 2 , the display panel 110 can be located in the display area DA of the substrate SUB, and the second pad PD2, the third pad PD3, the gate driver 120, and the data driver 130 can be located in the non-display area NDA of the substrate SUB.

[0168] According to some embodiments, the third pad PD3 and the data driver 130 can be located on the first side surface of the display panel 110, and the gate driver 120 can be located on the second side surface of the display panel 110. The first side surface and the second side surface can be perpendicular to each other.

[0169] For example, when observed in the third direction DR3 (e.g., in a plan view), the third pad PD3, the data driver 130, and the display panel 110 can be arranged along the first direction DR1, and the display panel 110 and the gate driver 120 can be arranged along the second direction DR2.

[0170] According to some embodiments, when the substrate SUB further includes a plurality of demultiplexers, when observed in the third direction DR3 (e.g., in a plan view), the third pad PD3, the data driver 130, the demultiplexer, and the display panel 110 can be arranged along the first direction DR1.

[0171] According to some embodiments, the third pad PD3 and the gate driver 120 can be located on the first side surface of the display panel 110, and the data driver 130 can be located on the second side surface of the display panel 110.

[0172] For example, when observed in the third direction DR3 (e.g., in a plan view), the third pad PD3, the gate driver 120, and the display panel 110 can be arranged along the first direction DR1, and the display panel 110 and the data driver 130 can be arranged along the second direction DR2.

[0173] The controller 150 may be configured as an integrated circuit located on the control substrate SC. However, the present disclosure is not limited thereto, and an external processor that outputs input image data IMG and a control signal CTRL to the controller 150 and the controller 150 may be arranged together on the control substrate SC.

[0174] Reference Figure 11 , the control substrate SC is shown to be located between the second pad PD2 and the data driver 130, but the present disclosure is not limited thereto, and it may be located on at least one of the first to fourth side surfaces of the display panel 110. The first side surface and the third side surface may be parallel to each other, and the second side surface and the fourth side surface may be parallel to each other.

[0175] In addition, according to some embodiments, the control substrate SC may be located on the first side surface and the second side surface at the same time, on the third side surface and the fourth side surface at the same time, on the first side surface and the third side surface at the same time, or on the second side surface and the fourth side surface at the same time.

[0176] Figure 12 Is shown Figure 10 A cross-sectional view of an embodiment of

[0177] Reference Figure 12 , a control substrate SC and a substrate SUB connected through a third pad PD3 are shown.

[0178] Because Figure 12 The substrate SUB and the control substrate SC of Figure 10 are similar to the substrate SUB and the control substrate SC of

[0179] The display panel 110, the gate driver 120, and the data driver 130 may be located on the substrate SUB. According to some embodiments, the gate driver 120 and the data driver 130 may be configured as separate integrated circuits and may be located on the substrate SUB. For ease of illustration, the display panel 110 and the gate driver 120 are shown as being configured as one circuit, but the gate driver 120 may be located on one side of the display panel 110.

[0180] The controller 150 may be located on the control substrate SC.

[0181] In addition, the second pad PD2 and the third pad PD3 may be located on the substrate SUB. The substrate SUB may be connected to another substrate through the second pad PD2 and the connection circuit board FC. The substrate SUB may be connected to the control substrate SC through the third pad PD3.

[0182] Figure 13 A block diagram showing the connection relationship between a substrate and a controller according to some embodiments is shown.

[0183] Reference Figure 13 ,the controller 150 may be located on the control substrate SC, and the display panel 110, the gate driver 120, the data driver 130, and the level shifter 131 may be located on Figure 2 the substrate SUB described in. Reference Figure 2 ,the display panel 110 may be located in the display area DA of the substrate SUB, and the gate driver 120, the data driver 130, and the level shifter 131 may be located in the non-display area NDA of the substrate SUB.

[0184] Figure 13 The display panel 110, the gate driver 120, the data driver 130, and the controller 150 of Figure 10 are similar to the display panel 110, the gate driver 120, the data driver 130, and the controller 150 of

[0185] ,so some of their redundant descriptions may be omitted.

[0186] The data driver 130 and the level shifter 131 may be configured as an integrated circuit. The controller 150 may output the image data DATA to the level shifter 131.

[0187] More specifically, the data driver 130 may include a shift register, a sampling latch, and a holding latch.

[0188] The level shifter 131 may change the voltage levels of the image data DATA and the data control signal DCS received from the controller 150 and output them to the shift register and the sampling latch. The shift register may generate a sampling signal based on the data control signal DCS received from the level shifter 131. The sampling latch may store the image data DATA received from the level shifter 131 in response to the sampling signal. The holding latch may store the image data DATA provided by the sampling latch.

[0189] That is, the image data DATA output from the controller 150 may be output to the display panel 110 through the level shifter 131, the sampling latch, and the holding latch in this order.

[0190] However, in an embodiment different from Figure 13 ,when the controller 150 and the data driver 130 are as Figure 7When located together on the control substrate SC as shown, the image data DATA output from the controller 150 can be output to the display panel 110 in this order through the sampling latch, the holding latch, and the level shifter 131.

[0191] In Figure 13 the level shifter 131 is described as being configured as an integrated circuit with the data driver 130, but the present disclosure is not limited thereto, and in some embodiments, the level shifter 131 and the data driver 130 can be configured as separate integrated circuits.

[0192] Figure 14 Illustrated is Figure 13 a cross-sectional view of an embodiment of

[0193] Because Figure 14 the substrate SUB and the control substrate SC of Figure 13 are similar to the substrate SUB and the control substrate SC of

[0194] the display panel 110, the gate driver 120, the data driver 130, and the level shifter 131 can be located on the substrate SUB.

[0195] According to some embodiments, the gate driver 120 and the data driver 130 can be configured as separate integrated circuits and can be located on the substrate SUB. For ease of illustration, the display panel 110 and the gate driver 120 are shown as being configured as an integrated circuit, but the gate driver 120 can be located on one side of the display panel 110.

[0196] Figure 14 the level shifter 131 in

[0197] is shown as being configured as a separate integrated circuit from the data driver 130, but the present disclosure is not limited thereto, and the level shifter 131 and the data driver 130 can be configured as an integrated circuit.

[0198] In addition, the second pad PD2 and the third pad PD3 can be located on the substrate SUB. The substrate SUB can be connected to another substrate through the second pad PD2 and the connection circuit board FC. The substrate SUB can be connected to the control substrate SC through the third pad PD3.

[0199] The controller 150 may output image data DATA to the level shifter 131 through the third pad PD3. The level shifter 131 may change the voltage level of the image data DATA output from the controller 150 and output it to the data driver 130.

[0200] Reference Figure 14 , the control substrate SC and the level shifter 131 are shown as having an overlapping structure, but in some embodiments, the control substrate SC and the level shifter 131 may not overlap.

[0201] Figure 15 A block diagram showing the connection relationship between the substrate and the controller according to some embodiments is shown.

[0202] Reference Figure 15 , a control substrate SC attached to the substrate SUB is shown.

[0203] Because Figure 15 the substrate SUB and the control substrate SC are similar to Figure 11 the substrate SUB and the control substrate SC, some redundant descriptions thereof may be omitted.

[0204] Figure 11 the gate driver 120 of Figure 15 may include Figure 15 the first gate driver 120a and the second gate driver 120b of Figure 11 . That is,

[0205] According to some embodiments, the third pad PD3 and the first gate driver 120a may be located on the first side surface of the display panel 110, the data driver 130 may be located on the second side surface of the display panel 110, and the second gate driver 120b may be located on the third side surface of the display panel 110. The first side surface and the second side surface may be perpendicular to each other, and the first side surface and the third side surface may be parallel to each other. That is, the third side surface may be the side surface of the display panel 110 opposite to the first side surface.

[0206] For example, when observed in the third direction DR3 (e.g., in a plan view), the third pad PD3, the first gate driver 120a, the display panel 110, and the second gate driver 120b may be arranged along the first direction DR1, and the display panel 110 and the data driver 130 may be arranged along the second direction DR2.

[0207] In addition, when the level shifter is configured as an integrated circuit separate from the data driver 130, the third pad PD3, the level shifter, and the first gate driver 120a may be located on a first side surface of the display panel 110, the data driver 130 may be located on a second side surface of the display panel 110, and the second gate driver 120b may be located on a third side surface of the display panel 110.

[0208] For ease of illustration, the connection relationships between the display panel 110, the first gate driver 120a, the second gate driver 120b, and the data driver 130 are omitted.

[0209] In addition, according to some embodiments, the data driver 130 may include a first sub-data driver and a second sub-data driver. For example, the first sub-data driver, the display panel 110, and the second sub-data driver may be sequentially positioned according to a second direction DR2.

[0210] Figure 15 The arrangement structures of the display panel 110, the first gate driver 120a, the second gate driver 120b, and the data driver 130 on the substrate SUB may be different from Figure 11 the arrangement structures of the display panel 110, the gate driver 120, and the data driver 130 on the substrate SUB.

[0211] More specifically, different from the arrangement where the data driver 130 and the display panel 110 are arranged along a first direction DR1 in Figure 11 , in Figure 15 , the first gate driver 120a, the display panel 110, and the second gate driver 120b may be arranged along the first direction DR1.

[0212] That is, since only the controller 150 is located on the control substrate SC separated from the substrate SUB, the degree of freedom in arranging the components of the substrate SUB (e.g., the gate driver 120 and the data driver 130) can be relatively improved. Therefore, the components of the substrate SUB can be positioned considering the signal delay caused by the gate lines or data lines.

[0213] A second pad PD2 and a third pad PD3 may also be provided on the substrate SUB. The second pad PD2 and the third pad PD3 may be Figure 2 some of the pads PD. The substrate SUB may be connected to an external substrate such as a flexible circuit board through the second pad PD2. The substrate SUB may be connected to the control substrate SC through the third pad PD3.

[0214] The controller 150 may be configured as an integrated circuit located on the control substrate SC.

[0215] Figure 16shows Figure 15 a cross-sectional view of an embodiment.

[0216] Since Figure 16 the substrate SUB and the control substrate SC of Figure 15 are similar to the substrate SUB and the control substrate SC of

[0217] The display panel 110, the first gate driver 120a, the second gate driver 120b, and the data driver 130 may be located on the substrate SUB. According to some embodiments, the first gate driver 120a, the second gate driver 120b, and the data driver 130 may be configured as separate integrated circuits and may be located on the substrate SUB. For ease of illustration, the display panel 110 and the data driver 130 are shown as being configured as one integrated circuit, but the data driver 130 may be located on one side of the display panel 110.

[0218] Figure 16 The level shifter 131 in

[0219] is shown as being configured as a separate integrated circuit from the data driver 130, but the present disclosure is not limited thereto, and the level shifter 131 and the data driver 130 may be configured as one integrated circuit.

[0220] In addition, the second pad PD2 and the third pad PD3 may be located on the substrate SUB. The substrate SUB may be connected to another substrate through the second pad PD2 and the connection circuit board FC. The substrate SUB may be connected to the control substrate SC through the third pad PD3.

[0221] The controller 150 may output the image data DATA to the level shifter 131 through the third pad PD3. The level shifter 131 may change the voltage level of the image data DATA and output it to the data driver 130.

[0222] Referring to Figure 16 , the control substrate SC and the level shifter 131 are shown as having an overlapping structure, but in some embodiments, the control substrate SC and the level shifter 131 may not overlap.

[0223] Figure 17 shows a block diagram of a display system according to some embodiments.

[0224] Referring to Figure 17, the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0225] The processor 1100 may perform various tasks and calculations. According to some embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to and control other components of the display system 1000 through a bus system.

[0226] In Figure 17 , the display system 1000 is shown as including a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1 and to the second display device 1220 through a second channel CH2.

[0227] Through the first channel CH1, the processor 1100 may transmit first image data IMG1 and a first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 may be configured similarly to the display device 100 described in reference Figure 1 . In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as the input image data IMG and the control signal CTRL respectively Figure 1 .

[0228] Through the second channel CH2, the processor 1100 may transmit second image data IMG2 and a second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 may be configured similarly to the display device 100 described in reference Figure 1 . In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as the input image data IMG and the control signal CTRL respectively Figure 1 .

[0229] The display system 1000 may include a computing system providing an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, and an ultra-mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head-mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0230] Figure 18 shows a Figure 17 stereogram of an application example of a display system.

[0231] Referring to Figure 18 , Figure 17 the display system 1000 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0232] The head-mounted display device 2000 can include a head-mounted band 2100 and a display device housing box 2200. The head-mounted band 2100 can be connected to the display device housing box 2200. The head-mounted band 2100 can include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band can be configured to surround a side portion of the user's head, and the vertical band can be configured to surround an upper portion of the user's head. However, the embodiments are not limited thereto. For example, the head-mounted band 2100 can be implemented in the form of eyeglass frames, helmets, etc.

[0233] The display device housing box 2200 can accommodate Figure 17 the first display device 1210 and the second display device 1220 of Figure 17 . The display device housing box 2200 can also accommodate

[0234] Figure 19 shows Figure 18 a head-mounted display device worn by a user.

[0235] Referring to Figure 19 , the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 are located in the head-mounted display device 2000. The head-mounted display device 2000 can also include one or more lenses LLNS and RLNS.

[0236] In the display device housing box 2200, the right-eye lens RLNS can be located between the first display panel DP1 and the user's right eye. In the display device housing box 2200, the left-eye lens LLNS can be located between the second display panel DP2 and the user's left eye.

[0237] The image output from the first display panel DP1 can be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS can refract the light from the first display panel DP1 to direct it to the user's right eye. The right-eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0238] The image output from the second display panel DP2 can be displayed to the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS can refract the light from the second display panel DP2 to direct it to the user's left eye. The left-eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0239] According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS can include an optical lens having a cross-section in the shape of a pancake. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS can include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel outputs an image corresponding to the sub-region of the multi-channel lens, and the output image can pass through the sub-region and be viewed by the user.

[0240] Although specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, embodiments in accordance with the present disclosure are not limited to the disclosed embodiments, but rather to the broader scope of the presented claims and various modifications and equivalent arrangements.

Claims

1. A display device, comprising: a substrate, on which are provided: a display panel configured to display an image corresponding to image data; a data driver configured to apply a plurality of data signals corresponding to the image data to the display panel; a level shifter configured to change the voltage level of the image data; and a first pad; and a control substrate, on which a controller is provided, the controller being configured to output the image data to the level shifter, and the control substrate being attached to the substrate in a vertical direction through the first pad.

2. The display device according to claim 1, wherein, The data driver and the level shifter are configured as an integrated circuit.

3. The display device according to claim 1, wherein, A gate driver is further provided on the substrate, the gate driver being configured to apply a plurality of gate signals to the display panel.

4. The display device according to claim 3, wherein, The substrate includes a display area in which the display panel is located, and a non-display area in which the first pad, the data driver, the gate driver, and the level shifter are located.

5. The display device according to claim 3, wherein the first pad, the level shifter, and the data driver are on a first side surface of the display panel, the gate driver is on a second side surface of the display panel, and the first side surface and the second side surface are perpendicular to each other.

6. The display device according to claim 3, wherein the first pad, the level shifter, and the gate driver are on a first side surface of the display panel, the data driver is on a second side surface of the display panel, and the first side surface and the second side surface are perpendicular to each other.

7. The display device according to claim 6, wherein the gate driver includes a first sub-gate driver and a second sub-gate driver, the first pad, the level shifter, and the first sub-gate driver are on the first side surface, the data driver is on the second side surface, the second sub-gate driver is on a third side surface of the display panel, the second side surface and the third side surface are perpendicular to each other, and the first side surface and the third side surface are parallel to each other.

8. The display device according to claim 1, wherein, The data driver includes a sampling latch and a holding latch, and the image data is output to the display panel in this order through the level shifter, the sampling latch, and the holding latch.

9. The display device according to claim 1, wherein, The image data output from the controller to the level shifter is a digital signal.

10. The display device according to claim 1, wherein, The control substrate is formed as a silicon wafer substrate.

11. A display device, comprising: a substrate, on which are provided a display panel configured to display an image corresponding to image data and a first pad on a first side surface of the display panel; and a control substrate, on which are provided a data driver and a controller, the data driver being configured to apply a plurality of data signals corresponding to the image data to the display panel, the controller being configured to output the image data to the data driver, wherein the control substrate is attached to the substrate in a vertical direction through the first pad; and A gate driver is also provided on the substrate, and the gate driver is on the second side surface of the display panel, wherein, the first side surface and the second side surface are perpendicular to each other.

12. The display device according to claim 11, wherein, the control substrate is formed as a silicon wafer substrate.

13. The display device according to claim 11, wherein, the controller and the data driver are configured as an integrated circuit.

14. The display device according to claim 11, wherein, the gate driver is configured to apply a plurality of gate signals to the display panel.

15. The display device according to claim 14, wherein, the substrate includes a display area where the display panel is located, and a non-display area where the first pad and the gate driver are located.

16. The display device according to claim 11, wherein, a level shifter is also provided on the substrate, the data driver includes a sampling latch and a holding latch, and the image data is output to the display panel in this order through the sampling latch, the holding latch, and the level shifter.

17. A display device, comprising: a substrate, on which a display panel and a data driver are provided, the display panel being configured to display an image corresponding to image data, and the data driver being configured to apply a plurality of data signals corresponding to the image data to the display panel; a control circuit board, on which a controller configured to output the image data to the data driver is provided; and a connection circuit board configured to connect the substrate and the control circuit board.

18. The display device according to claim 17, wherein, a first pad is also provided on the substrate, a second pad is also provided on the control circuit board, and one end of the connection circuit board is connected to the first pad, and the other end of the connection circuit board is connected to the second pad.

19. The display device according to claim 17, wherein, the control circuit board is formed as a silicon wafer substrate.

20. The display device according to claim 17, wherein, the control circuit board is a printed circuit board, and the connection circuit board is a flexible circuit board.

Images