Signal processor, filtering system, filter and data filtering method

Abstract

The present invention discloses a signal processor, a filtering system, a filter and a data filtering method, which are applied to the field of signal processing. After determining the first data input channel corresponding to the first data to be filtered, the scheduling circuit in the filter can transmit the first data to be filtered to the filtering circuit through the first data input channel. Then, the filtering circuit filters the first data to be filtered based on the first filtering parameter corresponding to the first data input channel to obtain a first filtering result. By matching the first data input channel for the first data to be filtered, and then matching the corresponding first filtering parameter for the first data to be filtered, different filtering parameters can be matched for different data to be filtered. Compared with the filter in the related art that adopts fixed filtering parameters, the filter of the present invention can realize personalized signal processing while meeting diverse filtering requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal processing, in particular to a signal processor, a filtering system, a filter and a data filtering method. BACKGROUND

[0002] With the development of the information age, digital signal processing technology has gradually replaced the traditional analog signal processing system in many application fields such as automatic control, aerospace, fault detection and communication. Digital filter plays an important role in the field of digital signal processing. It can filter out the clutter in the input signal by using the difference in the frequency spectrum of the input signal and other signals, so as to extract and strengthen the useful components in the signal and weaken the interference components.

[0003] In related technologies, the filtering parameters (such as filtering coefficients) used by the digital filter are usually fixed parameters, so the digital filter can only filter a single signal and cannot meet the diverse filtering needs. SUMMARY

[0004] The present application provides a signal processor, a filtering system, a filter and a data filtering method, which can solve the problem that the digital filter in related technologies can only filter a single signal and cannot meet the diverse filtering needs. The technical solution comprises:

[0005] On the one hand, a filter is provided, which comprises a scheduling circuit, a plurality of data input channels and a filtering circuit.

[0006] The scheduling circuit is configured to determine a first data input channel corresponding to first to-be-filtered data from the plurality of data input channels, and transmit the first to-be-filtered data to the first data input channel.

[0007] The first data input channel is configured to transmit the first to-be-filtered data to the filtering circuit.

[0008] The filtering circuit is configured to filter the first to-be-filtered data based on a first filtering parameter corresponding to the first data input channel to obtain a first filtering result.

[0009] Optionally, the filtering circuit comprises a plurality of filtering sub-circuits.

[0010] The first data input channel is configured to transmit the first to-be-filtered data to a first filtering sub-circuit corresponding to the first data input channel.

[0011] Optionally, the types of the plurality of filtering sub-circuits are different.

[0012] Optionally, the scheduling circuit is further configured to transmit the intermediate processing result to a second data input channel corresponding to the first data input channel in response to the cascade signal, wherein the intermediate processing result is obtained by processing the first filtering result.

[0013] The second data input channel is configured to transmit the intermediate processing result to the filtering circuit.

[0014] The filtering circuit is further configured to filter the intermediate processing result based on a second filtering parameter corresponding to the second data input channel to obtain a target filtering result.

[0015] Optionally, the filter further comprises a plurality of first post-processing circuits corresponding to the plurality of data input channels one by one.

[0016] The first target post-processing circuit corresponding to the first data input channel is configured to perform peak value holding or comparison processing on the intermediate processing result, wherein the intermediate processing result is obtained by processing the first filtering result.

[0017] Optionally, the filter further comprises a plurality of second post-processing circuits corresponding to the plurality of data input channels one by one.

[0018] The second target post-processing circuit corresponding to the first data input channel is configured to perform absolute value operation or decimation processing on the received first filtering result to obtain the intermediate processing result.

[0019] Optionally, the filter further comprises a plurality of data output channels corresponding to the plurality of data input channels one by one.

[0020] The second target post-processing circuit is further configured to transmit the intermediate processing result to a first data output channel corresponding to the first data input channel.

[0021] The first data output channel is configured to output the intermediate processing result.

[0022] Optionally, the scheduling circuit is further configured to:

[0023] If the second to-be-filtered data is received in addition to the first to-be-filtered data, a third data input channel corresponding to the second to-be-filtered data is determined from the plurality of data input channels.

[0024] If the priority of the first data input channel is higher than the priority of the third data input channel, the first to-be-filtered data is transmitted to the first data input channel.

[0025] Optionally, the scheduling circuit is further configured to:

[0026] In a case where it is determined that the first data input channel corresponding to the first to-be-filtered data is multiple, the first to-be-filtered data is transmitted to the multiple first data input channels, and the first data input channel with the highest priority is preferred.

[0027] Optionally, the filter further comprises a plurality of data storage areas, the plurality of data storage areas correspond to the plurality of data input channels one by one.

[0028] Each data storage area is configured to store intermediate data generated by the filtering circuit and / or to-be-filtered data transmitted to the corresponding data input channel.

[0029] Optionally, the filter further comprises a plurality of coefficient storage areas corresponding to the plurality of data input channels one by one.

[0030] Each coefficient storage area is configured to store a filtering parameter of the corresponding data input channel.

[0031] In another aspect, a filtering system is provided, comprising the filter described in the above aspect.

[0032] In yet another aspect, a signal processor is provided, comprising a signal input circuit and the filtering system described in the above aspect; wherein the signal input circuit is configured to transmit to-be-filtered data to the filtering system.

[0033] Optionally, the signal processor further comprises a signal receiving circuit configured to receive a result output by the filtering system.

[0034] In still another aspect, a data filtering method is provided, applied to a filtering system comprising a plurality of data input channels, the method comprising:

[0035] determining, from the plurality of data input channels, a first data input channel corresponding to first to-be-filtered data, so that the first data input channel transmits the first to-be-filtered data;

[0036] filtering the first to-be-filtered data based on a first filtering parameter corresponding to the first data input channel to obtain a first filtering result.

[0037] In summary, the embodiment of the present application provides a signal processor, a filtering system, a filter and a data filtering method. The filter is provided with multiple data input channels, and the multiple data input channels share a filtering circuit. After the scheduling circuit determines the first data input channel corresponding to the first to-be-filtered data, the first data input channel is used to transmit the first to-be-filtered data to the filtering circuit. Then, the filtering circuit filters the first to-be-filtered data based on the first filtering parameter corresponding to the first data input channel to obtain a first filtering result. By matching the first data input channel for the first to-be-filtered data, the corresponding first filtering parameter is matched for the first to-be-filtered data, so that different filtering parameters can be matched for different to-be-filtered data. Compared with the filter in the related art which uses fixed filtering parameters, the filter in the present application can meet the diversified filtering requirements and realize personalized signal processing.

[0038] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a structural schematic diagram of a filter provided by an embodiment of the present application;

[0040] Figure 2 is a timing diagram of a signal provided by an embodiment of the present application;

[0041] Figure 3 is a structural schematic diagram of another filter provided by an embodiment of the present application;

[0042] Figure 4 is a structural schematic diagram of still another filter provided by an embodiment of the present application;

[0043] Figure 5 is a schematic diagram of a coefficient storage area provided by an embodiment of the present application;

[0044] Figure 6 is a schematic diagram of a data storage area provided by an embodiment of the present application;

[0045] Figure 7 is a structural schematic diagram of a signal processor provided by an embodiment of the present application;

[0046] Figure 8 is a structural schematic diagram of another signal processor provided by an embodiment of the present application;

[0047] Figure 9 is a flowchart of a data filtering method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0048] Embodiments of the present application are described below in detail with reference to the accompanying drawings, examples of which are shown in the drawings, wherein the same or similar notations are used to represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and are not to be understood as limiting the present application.

[0049] With the development of the information age, digital signal processing technology has gradually replaced the traditional analog signal processing system in many application fields such as automatic control, aerospace, fault detection and communication. Digital filter plays an important role in the field of digital signal processing. It can filter out the clutter in the input signal by using the difference in the frequency spectrum of the input signal and other signals, so as to extract and strengthen the useful components in the signal and weaken the interference components.

[0050] In the related art, since the filter parameters (such as filter coefficients) used by the digital filter are usually fixed parameters, the digital filter can only filter a single signal, and such a digital filter has certain limitations and cannot meet the diversity of filtering requirements.

[0051] It can be understood that the order of the digital filter determines the frequency response of the digital filter. The higher the order of the digital filter, the steeper the frequency response of the digital filter, the smaller the roll-off coefficient of the corresponding digital filter, and the narrower the transition bandwidth of the corresponding digital filter. The digital filter will preserve the effective signal amplitude characteristics more completely within the cutoff frequency, and attenuate the noise outside the cutoff frequency more rapidly. At the same time, the higher the order of the digital filter, the more complex the calculation of the digital filter and the longer the time consumed.

[0052] Figure 1 is a structural schematic diagram of a filter provided by an embodiment of the present application, as shown in Figure 1 The filter includes a scheduling circuit 10, a plurality of data input channels 20 and a filter circuit 30. Figure 1 Only three data input channels 20 are shown. The filter can be a digital filter, and each data input channel 20 can be an input data register.

[0053] The scheduling circuit 10 is configured to determine a first data input channel corresponding to first to-be-filtered data A from the plurality of data input channels 20, and transmit the first to-be-filtered data A to the first data input channel.

[0054] The first data input channel is configured to transmit the first to-be-filtered data A to the filter circuit 30.

[0055] The filter circuit 30 is configured to filter the first to-be-filtered data A based on a first filter parameter corresponding to the first data input channel to obtain a first filter result. The filter parameter can include an order of a filter and / or a filter coefficient.

[0056] With reference to Figure 2 The scheduling circuit 10 can receive the initial activation signal S1 transmitted by the signal input circuit, the first to-be-filtered data A, and the first data tag Ta1 of the first to-be-filtered data A. When the initial activation signal S1 reaches a first transition edge, the scheduling circuit 10 can determine a first channel tag corresponding to the first data tag from a first correspondence between data tags and channel tags, and then determine a data input channel 20 indicated by the first channel tag as the first data input channel. The first correspondence can be pre-stored in the scheduling circuit 10. The first transition edge can be a rising edge.

[0057] The signal input circuit can be an analog-to-digital converter (ADC), for example, a delta-sigma (DS) ADC or a successive approximation register (SAR) ADC.

[0058] The filter circuit 30 can obtain a filter parameter corresponding to the first channel tag from a second correspondence between channel tags and parameters based on the first channel tag of the first data input channel, and determine the filter parameter corresponding to the first channel tag as the first filter parameter.

[0059] With reference to Figure 2 After receiving the initial activation signal S1, the first to-be-filtered data A, and the first data tag Ta1, the scheduling circuit 10 can generate an intermediate activation signal S2, and then the filter circuit 30 can filter the first to-be-filtered data A when the intermediate activation signal S2 reaches a second transition edge, that is, perform a filter processing process FP1 in the running process of the filter shown in FIG. 2. Figure 2 The second transition edge can be a falling edge.

[0060] To sum up, the embodiment of the present application provides a filter, wherein a plurality of data input channels are arranged, and the plurality of data input channels share a filter circuit, compared with each data input channel being connected with one filter circuit, the filter provided in the embodiment of the present application can optimize resource allocation, reduce system resource consumption, and improve overall performance. After the scheduling circuit determines the first data input channel corresponding to the first to-be-filtered data, the first data input channel can be used to transmit the first to-be-filtered data to the filter circuit, so that the filter circuit filters the first to-be-filtered data based on the first filter parameter corresponding to the first data input channel to obtain the first filter result. By matching the first data input channel for the first to-be-filtered data, and then matching the corresponding first filter parameter for the first to-be-filtered data, different filter parameters can be matched for different to-be-filtered data, compared with the filter in the related art adopting fixed filter parameters, the filter in the present application can meet the diversified filtering requirements and realize personalized signal processing.

[0061] The filter circuit 30 can include a plurality of filter sub-circuits. Each data input channel 20 is connected with a corresponding filter sub-circuit. The first data input channel is used to transmit the first to-be-filtered data A to the first filter sub-circuit corresponding to the first data input channel.

[0062] For example, the filter circuit 30 can include a finite impulse response (fir) filter sub-circuit and an infinite impulse response (IIR) filter sub-circuit.

[0063] For different types of to-be-filtered data, the filter can match different types of filter sub-circuits, further meeting the diversified filtering requirements and enriching the use scenarios of the filter.

[0064] In the embodiment of the present application, different data input channels can transmit different types of to-be-filtered data, by transmitting the to-be-filtered data to the filter sub-circuit corresponding to the data input channel, and determining the filter parameter corresponding to the data input channel through the second correspondence, different filter types and filter parameter switching can be realized.

[0065] Reference Figure 3 The filter can further include a first post-processing unit 40 configured to perform peak holding or comparison processing on the intermediate processing result.

[0066] The first post-processing unit 40 can include a plurality of first post-processing circuits corresponding to the plurality of data input channels 20. Each first post-processing circuit can be a peak holding circuit or a comparison circuit.

[0067] The first target post-processing circuit corresponding to the first data input channel is configured to perform peak holding or comparison processing on the intermediate processing result. The peak holding or comparison processed data is used to update the peak data in the register corresponding to the first target post-processing circuit.

[0068] The peak holding processing on the intermediate processing result can refer to performing peak holding processing on the intermediate processing result and the peak data stored in the register, and updating the peak data stored in the register to the larger one of the intermediate processing result and the peak data. The comparison processing on the intermediate processing result can refer to comparing whether the intermediate processing result is equal to the reference value stored in the comparison register corresponding to the first target post-processing circuit.

[0069] Reference Figure 2 and Figure 3 The first target post-processing circuit is further configured to output the processed result Ou1 and send an interrupt request IR. Wherein, Figure 2 The output process Ou1 in the running process shown in FIG. 5 can include the process of outputting the processed result.

[0070] Reference Figure 3 The filter can further include a second post-processing unit 50 configured to perform absolute value operation or decimation processing on the received first filtering result to obtain the intermediate processing result.

[0071] The second post-processing unit 50 can include a plurality of second post-processing circuits corresponding to the plurality of data input channels 20. Each second post-processing circuit can be an absolute value operation circuit or a decimation circuit.

[0072] The second target post-processing circuit corresponding to the first data input channel is configured to perform absolute value operation or decimation processing on the received first filtering result to obtain the intermediate processing result.

[0073] Reference Figure 3 The second post-processing unit 50 is further configured to output the intermediate processing result and send an interrupt request IR. For example, the second post-processing unit 50 is further configured to output the intermediate processing result to the first target post-processing circuit.

[0074] The second target post-processing circuit is further configured to output the intermediate processing result and send an interrupt request IR.

[0075] Optionally, the second target post-processing circuit is further configured to output the intermediate processing result to the first target post-processing circuit.

[0076] Reference Figure 3 The filter can further include a plurality of data output channels 60 corresponding to the plurality of data input channels 20, and each data output channel 60 can be an output data register.

[0077] The second post-processing unit 50 is further configured to transmit the intermediate processing result to a first data output channel corresponding to the first data input channel and send an interrupt request.

[0078] Optionally, the second target post-processing circuit is further configured to transmit the intermediate processing result to a first data output channel corresponding to the first data input channel and send an interrupt request.

[0079] The first data output channel is configured to output the intermediate processing result and send an interrupt request.

[0080] Optionally, the first data output channel is configured to output the intermediate processing result to a signal receiving circuit.

[0081] In the embodiment of the present application, the scheduling circuit 10 is further configured to transmit the intermediate processing result to a second data input channel corresponding to the first data input channel in response to the cascade signal.

[0082] The second data input channel is configured to transmit the intermediate processing result to the filter circuit 30.

[0083] The filter circuit 30 is further configured to filter the intermediate processing result based on a second filter parameter corresponding to the second data input channel to obtain a target filter result. The second filter parameter can be the same as or different from the first filter parameter.

[0084] In the embodiment of the present application, the third correspondence relationship between the first input channel label and the second input channel label is pre-stored in the scheduling circuit 10. The scheduling circuit 10 can determine the second channel label corresponding to the first channel label of the first data input channel from the third correspondence relationship in response to the cascade signal, and then determine the data input channel 20 indicated by the second channel label as the second data input channel.

[0085] The filter can perform at least one filtering on the intermediate processing result output by the second post-processing unit 50 to obtain a target filtering result. It can be understood that in the case of performing the first filtering on the intermediate processing result, the intermediate processing result is obtained by performing the absolute value operation or the decimation processing on the first filtering result by the second post-processing unit 50, and in the case of performing the Nth filtering on the intermediate processing result, the intermediate processing result is obtained by performing the absolute value operation or the decimation processing on the reference filtering result by the second post-processing unit 50, and the reference filtering result is obtained by performing the filtering on the (N-1)th intermediate processing result by the filter circuit 30. N is an integer greater than 1. Optionally, in the case of performing the Nth filtering on the intermediate processing result, the second post-processing unit 50 can also perform the accumulation processing on the reference filtering result according to the requirement to obtain the intermediate processing result.

[0086] Reference Figure 2 In response to the cascade signal, the scheduling circuit 10 can generate the intermediate activation signal S2 again, and the filter circuit 30 can perform the filtering on the intermediate processing result again when the intermediate activation signal S2 reaches the transition edge again, that is, perform the filtering process FP2 shown in FIG. 2 again. The transition edge can be a rising edge. Figure 2

[0087] The intermediate processing result output by the second post-processing unit 50 is filtered at least once as the input data of the data input channel 20, and in the case that the second filtering parameter is different from the first filtering parameter, the complex filtering structure of different types can be realized, and the stability and robustness of the filter are improved.

[0088] In the embodiment of the application, the second data input channel is used to transmit the intermediate processing result to the corresponding second filtering sub-circuit.

[0089] The second filtering sub-circuit is used to perform the filtering on the intermediate processing result based on the second filtering parameter corresponding to the second data input channel to obtain the target filtering result.

[0090] The type of the second filtering sub-circuit can be the same as or different from the type of the first filtering sub-circuit.

[0091] ​The intermediate processing result output by the second post-processing unit 50 is input to the data input channel 20 as input data and filtered at least once. Since the type of the second filter sub-circuit can be different from the type of the first filter sub-circuit, and / or the second filter parameter can be different from the first filter parameter, the multi-stage filtering processing can be implemented by using the scheme provided in the embodiment of the application. In addition, the to-be-filtered data can be gradually optimized and filtered according to requirements. The plurality of data input channels can be configured with different filters (such as low-pass, high-pass, band-pass, band-stop, etc.), and different filtering configurations are applied in each processing stage, so that the to-be-filtered data is more finely adjusted and improved in each stage, and the flexibility and precision of processing are improved. Thus, a complex filtering structure of different types is implemented, and the performance of a single filter is reduced by means of gradual filtering, thereby improving the stability and robustness of the filter.

[0092] It can be understood that, for different to-be-filtered data, the scheduling circuit 10 determines whether the intermediate processing result output by the second post-processing unit 50 needs to be filtered at least once based on the cascade signal of the data input channel corresponding to the to-be-filtered data, thereby realizing individualized signal processing.

[0093] In the embodiment of the application, the second post-processing unit 50 is further configured to perform accumulation or decimation processing on the received target filtering result to obtain a reference processing result.

[0094] The third target post-processing circuit corresponding to the second data input channel is configured to perform absolute value operation or decimation processing on the received target filtering result to obtain a reference processing result.

[0095] Optionally, the second post-processing unit 50 is further configured to transmit the reference processing result to the second data output channel corresponding to the second data input channel and send an interrupt request IR.

[0096] The third target post-processing circuit is further configured to transmit the reference processing result to the second data output channel corresponding to the second data input channel and send an interrupt request IR.

[0097] The second data output channel is configured to output the reference processing result and send an interrupt request IR. Figure 2 The output process Ou2 in the running process shown can include the process of the result after the output processing.

[0098] The second post-processing unit 50 is further configured to transmit the reference processing result to the first post-processing unit 40. The first post-processing unit 40 is further configured to perform peak value retention or comparison processing on the reference processing result and send an interrupt request.

[0099] Optionally, the third target post-processing circuit is further configured to transmit the reference processing result to a fourth target post-processing circuit corresponding to the second data input channel.

[0100] The fourth target post-processing circuit is configured to perform peak holding or comparison processing on the reference processing result and send an interrupt request.

[0101] In the embodiment of the present application, the scheduling circuit 10 is further configured to:

[0102] If the second to-be-filtered data is received in addition to the first to-be-filtered data A, a third data input channel corresponding to the second to-be-filtered data can be determined from the plurality of data input channels 20. In the case where the priority of the first data input channel is higher than the priority of the third data input channel, the first to-be-filtered data A is transmitted to the first data input channel. The priorities of the plurality of data input channels 20 can be pre-stored in the scheduling circuit 10.

[0103] By using the priority scheduling strategy, each data input channel 20 is assigned a priority, ensuring that important data input channels 20 can have priority access to the filtering circuit 30 when needed, i.e., data transmitted to a high-priority data input channel 20 is processed first, while data transmitted to a low-priority data input channel 20 needs to wait. This mechanism ensures that high-priority data input channels 20 can quickly obtain to-be-filtered data in emergency situations, thereby ensuring the real-time performance of critical data, optimizing the data processing flow, and effectively improving processing efficiency and response capability.

[0104] The scheduling circuit 10 can transmit the second to-be-filtered data to the corresponding third data input channel after filtering the first to-be-filtered data A, to filter the second to-be-filtered data.

[0105] Reference Figure 1 The first data input channel 20 among the three data input channels 20 has the highest priority, and the fourth data input channel 20 has the lowest priority.

[0106] Optionally, the scheduling circuit 10 is further configured to, in the case where a plurality of first data input channels corresponding to the first to-be-filtered data A are determined, transmit the first to-be-filtered data A to the first data input channels with the highest priority, so as to process the first to-be-filtered data A preferentially.

[0107] By transmitting the first to-be-filtered data A to the first data input channels with the highest priority, the filtering effect of the first to-be-filtered data A can be ensured to be better and more in line with user needs.

[0108] Reference Figure 4, the filter may further include: a plurality of data storage areas 701 ( Figure 3 (Three data storage areas are shown) multiple data storage areas 701 correspond one-to-one to multiple data input channels 20. Each data storage area 701 is used for at least real-time data. Real-time data may include intermediate data generated by the filtering circuit and / or data to be filtered transmitted to the corresponding data input channel.

[0109] Optionally, when the real-time data includes intermediate data generated by a filtering circuit, the filtering circuit may be a filtering sub-circuit corresponding to the data storage area. Each data storage area 701 is also used to store initialization data.

[0110] Each data storage area 701 may include an initial value buffer and / or a circular buffer, wherein the initial value buffer is used to store initialization data, the circular buffer is used to store real-time data, and the storage structure of the circular buffer is cyclic.

[0111] When the filtering subcircuit corresponding to the data input channel 20 is an FIR filtering circuit, the real-time data stored in the circular buffer corresponding to the data input channel 20 is the data to be filtered transmitted to the corresponding data input channel, and the initialization data can be the factory data.

[0112] When the filtering subcircuit corresponding to the data input channel 20 is an IIR filtering circuit, the real-time data stored in the circular buffer corresponding to the data input channel 20 is the intermediate data generated by the IIR filter, and the initialization data may be factory data.

[0113] To efficiently manage the data flow of each data input channel, the circular buffer utilizes a pointer-based data writing process, ensuring that data is stored in first-in, first-out order. When the circular buffer is full, newly written data overwrites the oldest data. The pointer is initialized to the starting address of the circular buffer, and the data writing process is managed using a write pointer. Each channel's write pointer controls the data write location. During data writing, the write pointer points to the current position in the circular buffer. Each time new data is written, the write pointer automatically advances. Once the write pointer reaches the end of the circular buffer, it automatically wraps back to the beginning of the buffer, thus implementing circular storage. This write pointer wrapping mechanism ensures continuous data storage, allowing large amounts of real-time data to be stored within limited memory space without wasting resources. This prevents overwriting valid historical data, thus avoiding the risk of memory overflow or data loss.

[0114] refer to Figure 4 The filter may further include: a plurality of coefficient storage areas 702 corresponding to the plurality of data input channels 20 , each coefficient storage area 702 being used to store filtering parameters of the corresponding data input channel 20 .

[0115] Figure 5 Schematic diagram of a coefficient storage area provided by an embodiment of the present invention, such as Figure 5 As shown, the storage areas indicated by the first address 000H to the sixth address 014H in the coefficient storage area all store filter coefficients, and the filter coefficients stored in the first address 000H include two coefficients a11 and b00.

[0116] Figure 6 Schematic diagram of a data storage area provided by an embodiment of the present invention. Figure 6 As shown, the storage address 040H to the address 07CH in the data storage area corresponds to the initial value buffer B1, and the storage address 000H to the storage address 03CH corresponds to the circular buffer B2, wherein the initial value buffer B1 and the circular buffer B2 each include n storage addresses, n is a positive integer, and the data stored in the first storage address 000H includes the low bit W1 (n-1).L and the high bit W1 (n-1).H, and the write pointer p points to the first storage address 000H.

[0117] By allocating an independent data storage area 701 and coefficient storage area 702 to each data input channel 20 and specifying a fixed memory address, cross-interference of data from different data input channels 20 can be effectively avoided.

[0118] refer to Figure 4 The filter may further include a memory control circuit 80 and a bus interface 90. The memory control circuit 80 may receive data from an external device via the bus interface 90 and store the received data in a corresponding storage area. For example, the memory control circuit 80 may receive filter coefficients corresponding to each data input channel 20 from an external device via the bus interface 90 and store the filter coefficients in the coefficient storage area corresponding to the data input channel 20.

[0119] In addition, the filter circuit 30 can obtain the filter coefficients from the coefficient storage area corresponding to the data input channel through the memory control circuit 80.

[0120] To sum up, the embodiment of the present application provides a filter, wherein a plurality of data input channels are arranged, and the plurality of data input channels share a filter circuit, and after a first data input channel corresponding to first to-be-filtered data is determined by a scheduling circuit, the first to-be-filtered data is transmitted to the filter circuit through the first data input channel, so that the filter circuit filters the first to-be-filtered data based on first filter parameters corresponding to the first data input channel to obtain a first filter result. By matching the first data input channel for the first to-be-filtered data, and then matching the corresponding first filter parameters for the first to-be-filtered data, different filter parameters can be matched for different to-be-filtered data, compared with the filter in the related art which uses fixed filter parameters, the filter in the present application can meet the diversified filtering requirements and realize personalized signal processing.

[0121] The embodiment of the present application provides a filter system, which can include the filter described in the above embodiment.

[0122] Figure 7 is a structural schematic diagram of a signal processor provided by the embodiment of the present application, as Figure 7 shown, the signal processor can include a filter system 100 and a signal input circuit 200, wherein the signal input circuit 200 is used for transmitting first to-be-filtered data A to the filter system 100.

[0123] Referring to Figure 8 , the signal processor can further include a signal receiving circuit 300, and the signal receiving circuit 300 is used for receiving a result output by the filter system 100.

[0124] Figure 9 is a flowchart of a data filtering method provided by the embodiment of the present application, and the method can be applied to a filter system, as Figure 9 shown, the method includes the following steps.

[0125] Step 901, a first data input channel corresponding to first to-be-filtered data is determined from a plurality of data input channels, so that the first data input channel transmits the first to-be-filtered data.

[0126] Step 902, the first to-be-filtered data is filtered based on first filter parameters corresponding to the first data input channel to obtain a first filter result.

[0127] Optionally, the method includes the following steps.

[0128] In response to the cascade signal, the intermediate processing result is transmitted to a second data input channel corresponding to the first data input channel, so that the second data input channel transmits the intermediate processing result to the filter circuit, wherein the intermediate processing result is obtained by processing the first filter result.

[0129] Filter the intermediate processing result to obtain a target filtering result based on a second filtering parameter corresponding to the second data input channel.

[0130] Optionally, the method comprises:

[0131] Peak value retention or comparison processing is performed on the intermediate processing result, wherein the intermediate processing result is obtained by processing the first filtering result.

[0132] Optionally, the method comprises:

[0133] Absolute value operation or decimation processing is performed on the received first filtering result to obtain the intermediate processing result.

[0134] Optionally, the method comprises:

[0135] If the second to-be-filtered data is received in addition to the first to-be-filtered data, a third data input channel corresponding to the second to-be-filtered data is determined from the plurality of data input channels.

[0136] If the priority of the first data input channel is higher than the priority of the third data input channel, the first to-be-filtered data is transmitted to the first data input channel.

[0137] Optionally, the method comprises:

[0138] If a plurality of first data input channels corresponding to the first to-be-filtered data are determined, the first to-be-filtered data is transmitted to the first data input channel with the highest priority.

[0139] In summary, the embodiment of the present application provides a data filtering method, wherein after determining the first data input channel corresponding to the first to-be-filtered data and transmitting the first to-be-filtered data from the first data input channel to the filtering circuit, the first to-be-filtered data is filtered based on the first filtering parameter corresponding to the first data input channel to obtain the first filtering result. By matching the first to-be-filtered data with the first data input channel, and then matching the first to-be-filtered data with the corresponding first filtering parameter, different filtering parameters can be matched for different to-be-filtered data, thereby meeting the diverse filtering requirements and realizing personalized signal processing.

[0140] It is to be appreciated that the above description and the examples that follow are intended to be illustrative only and that changes can be made to the description and examples without departing from the scope of the application. Note also that the use of particular brand names in the description is solely for illustration and should not be construed as an endorsement of such brands.

[0141] It should be understood that aspects of the application can be implemented in hardware, software, firmware or a combination thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, can be used: a hybrid of the technologies mentioned above, discrete logic circuitry having logic gates for implementing logic functions upon data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), or the like.

[0142] In the description of the present application, reference has been made to the use of terms such as "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" means that a particular feature, structure, material or characteristic is included in at least one embodiment or example of the present application. The illustrative examples given are not necessarily to be construed as preferred or advantageous or with the exclusion of other equally valid examples that can be particularly adapted to a given application. Furthermore, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the application to the exact construction and operation described. Accordingly, all suitable modifications and equivalents should be included within the scope of the present application.

[0143] In the description of the present application, it needs to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0144] In addition, the terms "first", "second", and the like used in the embodiments of the present application are only for the purpose of description, and cannot be understood as indicating or implying relative importance, or implicitly indicating the number of technical features referred to in the embodiments. Therefore, the features defined with "first", "second" and the like in the embodiments of the present application can be explicitly or implicitly indicated to include at least one of the features in the embodiments. In the description of the present application, the meaning of the word "plurality" is at least two or two or more, such as two, three, four, etc., unless otherwise specifically limited in the embodiments.

[0145] In the present application, unless otherwise specifically defined or limited in the embodiments, the terms "mounting", "connecting", "connecting" and "fixing" and the like appearing in the embodiments should be understood broadly, for example, the connection can be fixed connection, or detachable connection, or integral, which can be understood, or can be mechanical connection, electrical connection, etc. Of course, it can also be directly connected, or indirectly connected through an intermediate medium, or it can be the communication between two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific implementation situation.

[0146] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as a limitation on the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A filter, characterized in that: The filter includes: a scheduling circuit, a plurality of data input channels and a filtering circuit; The scheduling circuit is configured to determine a first data input channel corresponding to the first data to be filtered from the plurality of data input channels, and transmit the first data to be filtered to the first data input channel; The first data input channel is used to transmit the first data to be filtered to the filtering circuit; The filtering circuit is configured to filter the first data to be filtered based on a first filtering parameter corresponding to the first data input channel to obtain a first filtering result; The scheduling circuit is further configured to transmit, in response to a cascade signal, an intermediate processing result to a second data input channel corresponding to the first data input channel; wherein, when the intermediate processing result is filtered for the first time, the intermediate processing result is obtained by processing the first filtering result; and when the intermediate processing result is filtered for the Nth time, the intermediate processing result is obtained by processing a reference filtering result, and the reference filtering result is obtained by filtering the intermediate processing result for the N-1th time, where N is an integer greater than 1; The second data input channel is used to transmit the intermediate processing result to the filtering circuit; The filtering circuit is further configured to filter the intermediate processing result based on a second filtering parameter corresponding to the second data input channel to obtain a target filtering result.

2. The filter according to claim 1, wherein The filtering circuit includes a plurality of filtering sub-circuits; The first data input channel is used to transmit the first to-be-filtered data to a first filtering sub-circuit corresponding to the first data input channel.

3. The filter according to claim 2, characterized in that The types of the plurality of filtering sub-circuits are different from each other.

4. The filter according to claim 1, wherein The filter further includes: a plurality of first post-processing circuits corresponding one-to-one to the plurality of data input channels; The first target post-processing circuit corresponding to the first data input channel is used to perform peak hold or comparison processing on the intermediate processing result; wherein the intermediate processing result is obtained by processing the first filtering result.

5. The filter according to claim 1 or 4, characterized in that The filter further includes: a plurality of second post-processing circuits corresponding one-to-one to the plurality of data input channels; The second target post-processing circuit corresponding to the first data input channel is used to perform absolute value operation or extraction processing on the received first filtering result to obtain the intermediate processing result.

6. The filter according to claim 5, characterized in that The filter further comprises: a plurality of data output channels corresponding one-to-one to the plurality of data input channels; The second target post-processing circuit is further configured to transmit the intermediate processing result to a first data output channel corresponding to the first data input channel; The first data output channel is used to output the intermediate processing result.

7. The filter according to any one of claims 1 to 4, characterized in that: The scheduling circuit is further configured to: If second data to be filtered is received in addition to the first data to be filtered, determining a third data input channel corresponding to the second data to be filtered from the plurality of data input channels; In a case where the priority of the first data input channel is higher than the priority of the third data input channel, the first data to be filtered is transmitted to the first data input channel.

8. The filter according to any one of claims 1 to 4, characterized in that: The scheduling circuit is further configured to: When it is determined that there are multiple first data input channels corresponding to the first data to be filtered, the first data to be filtered is transmitted to the first data input channel with the highest priority among the multiple first data input channels.

9. The filter according to any one of claims 1 to 4, characterized in that: The filter further comprises: a plurality of data storage areas, wherein the plurality of data storage areas correspond one-to-one to the plurality of data input channels; Each of the data storage areas is used to store at least the intermediate data generated by the filtering circuit and / or the data to be filtered that is transmitted to the corresponding data input channel.

10. The filter according to any one of claims 1 to 4, characterized in that: The filter further comprises: a plurality of coefficient storage areas corresponding one-to-one to the plurality of data input channels; Each of the coefficient storage areas is used to store the filtering parameters of the corresponding data input channel.

11. A filtering system, characterized in that: The filter comprises the filter according to any one of claims 1 to 10.

12. A signal processor, characterized in that: The signal processor includes a signal input circuit and the filtering system according to claim 11; Wherein, the signal input circuit is used to transmit the data to be filtered to the filtering system.

13. The signal processor according to claim 12, wherein: The signal processor further includes a signal receiving circuit, which is configured to receive a result output by the filtering system.

14. A data filtering method, characterized in that: Applied to a filtering system, the filtering system includes multiple data input channels, and the method includes: Determine a first data input channel corresponding to the first data to be filtered from the plurality of data input channels, so that the first data input channel transmits the first data to be filtered; Filtering the first to-be-filtered data based on a first filtering parameter corresponding to the first data input channel to obtain a first filtering result; In response to a cascade signal, the intermediate processing result is transmitted to a second data input channel corresponding to the first data input channel, so that the second data input channel transmits the intermediate processing result; wherein, when the intermediate processing result is filtered for the first time, the intermediate processing result is obtained by processing the first filtering result; and when the intermediate processing result is filtered for the Nth time, the intermediate processing result is obtained by processing a reference filtering result, and the reference filtering result is obtained by filtering the intermediate processing result for the N-1th time, where N is an integer greater than 1; The intermediate processing result is filtered based on a second filtering parameter corresponding to the second data input channel to obtain a target filtering result.

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