Preparation method of flash memory device
By using a wet cleaning process without HF in the preparation of flash memory devices, the problems of side-pull and air gap defects of the outer wall structure are solved, and the device yield and data retention capabilities are improved.
Patent Information
- Application Number
- CN202510494879.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-18
- Publication Date
- 2025-08-01
AI Technical Summary
In the preparation process of small-size flash memory cells, the wet cleaning process containing HF results in the side dicing of the silica layer of the outer wall structure, affecting the data retention performance, and forming air gap defects during the deposition of the interlayer insulating dielectric layer, which in turn affects the device yield and conductive plug bridge.
After forming the first outer wall material layer, the gate oxide layer of the peripheral logic region is removed through a wet cleaning process without HF to avoid side digging of the outer wall structure of the storage area. Then, the HF wet cleaning is no longer used before forming the metal silicide barrier layer to ensure the integrity of the outer wall structure.
The side digging and air gap formation of the outer wall structure are avoided, the device yield is improved, and data retention capabilities and electrical performance are improved.
Smart Images
Figure CN120417385A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and particularly relates to a method for manufacturing a flash memory device. Background Art
[0002] In the traditional manufacturing process of flash memory devices, in order to form a good metal silicide contact on the substrate surface in the high-voltage MOS device region of the peripheral logic region, after forming the source and drain of the high-voltage MOS device region in the peripheral logic region and before depositing the metal silicide barrier (SAB), there is usually a wet cleaning process containing heavy hydrofluoric acid (HF) to remove the redundant gate oxide layers on both sides of the gate in the high-voltage MOS device region of the peripheral logic region.
[0003] However, in the manufacturing process of small-sized flash memory cells, the above wet cleaning process containing heavy HF will cause the following problems:
[0004] 1) The wet cleaning process containing HF will etch part of the film layer in the outer wall structure of the flash memory cell laterally. For example, it will cause the silicon dioxide layer at the bottom of the silicon nitride layer in the outer wall structure to be accidentally etched to form a lateral etch. When the lateral etch of the silicon dioxide layer in the outer wall structure is severe, it may affect the data retention performance of the flash memory device.
[0005] 2) Further, after depositing the metal silicide barrier layer, an interlayer dielectric layer needs to be deposited in the storage area later. During the deposition process of the interlayer dielectric layer, it is also easy to drill into the gap formed by the lateral etch of the silicon dioxide layer in the outer wall structure, thus forming an air gap defect.
[0006] 3) As the size of the flash memory cell is further miniaturized, the formed air gap is likely to become a bridge between conductive plugs during the contact hole filling process, which has an adverse effect on the device yield. Summary of the Invention
[0007] This application provides a method for manufacturing a flash memory device, which can solve the problem that the yield of the device is affected due to the accidental etching of part of the film layer at the bottom of the outer wall structure of the flash memory cell in the storage area to form a lateral etch.
[0008] An embodiment of this application provides a method for manufacturing a flash memory device, including:
[0009] A substrate is provided, which includes a storage area and a peripheral logic area. A pad oxide layer, a floating gate layer, an ONO layer, a control gate layer, a source line polysilicon, a tunneling oxide layer, and an inner sidewall structure are formed on the substrate of the storage area. Among them, the pad oxide layer, the floating gate layer, the ONO layer, and the control gate layer are stacked in sequence. The source line polysilicon is located in the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer and the source line polysilicon extends beyond the control gate layer by a certain height. The inner sidewall structure is located between the source line polysilicon and the stacked pad oxide layer, the floating gate layer, the ONO layer, and the control gate layer. The tunneling oxide layer is located between the source line polysilicon and the inner sidewall structure; A gate oxide layer covering the surface of the substrate and a gate polysilicon layer located on the gate oxide layer are formed on the substrate of the peripheral logic area;
[0010] A first outer sidewall material layer is formed, which covers the control gate layer, the source line polysilicon, and the inner sidewall structure of the storage area and covers the gate oxide layer and the gate polysilicon layer of the peripheral logic area;
[0011] The first outer sidewall material layer on the upper surface of the control gate layer, the upper surface of the source line polysilicon, and the upper surface of the inner sidewall structure in the storage area is removed, and the first outer sidewall material layer on the outer surface of the inner sidewall structure is retained. At the same time, the first outer sidewall material layer on the surface of the gate oxide layer and the upper surface of the gate polysilicon layer in the peripheral logic area is removed, and the first outer sidewall material layer on the outer surface of the gate polysilicon layer is retained;
[0012] The gate oxide layer on the surface of the substrate in the peripheral logic area is removed by using a first wet cleaning process;
[0013] The control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer outside the inner sidewall structure are etched away;
[0014] A second outer sidewall material layer and a third outer sidewall material layer are respectively formed. The second outer sidewall material layer covers the outer surfaces of the first outer sidewall material layer, the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer in the storage area, as well as the substrate, the inner sidewall structure, and the source line polysilicon. The second outer sidewall material layer also covers the gate polysilicon layer, the first outer sidewall material layer, and the substrate in the peripheral logic area. The third outer sidewall material layer covers the second outer sidewall material layer;
[0015] Remove the second outer sidewall material layer and the third outer sidewall material layer on the upper surface of the source line polysilicon in the storage area, the upper surface of the inner sidewall structure, and part of the substrate surface, and retain the second outer sidewall material layer and the third outer sidewall material layer on the outer surface of the first outer sidewall material layer. At the same time, remove the second outer sidewall material layer and the third outer sidewall material layer on the substrate surface of the peripheral logic area and the upper surface of the gate polysilicon layer, and retain the second outer sidewall material layer and the third outer sidewall material layer on the outer surface of the first outer sidewall material layer. Among them, the remaining first outer sidewall material layer, second outer sidewall material layer, and third outer sidewall material layer in the storage area form the outer sidewall structure of the storage area, and the remaining first outer sidewall material layer, second outer sidewall material layer, and third outer sidewall material layer in the peripheral logic area form the sidewall structure of the peripheral logic area;
[0016] By means of an ion implantation process, form a source electrode and a drain electrode respectively in the substrate on both sides of the sidewall structure of the peripheral logic area;
[0017] Perform a second wet cleaning process on the semiconductor structure after forming the source electrode and the drain electrode. Among them, the cleaning solution used in the second wet cleaning process does not contain hydrofluoric acid;
[0018] Form a metal silicide blocking layer, and the metal silicide blocking layer covers the semiconductor structure after forming the source electrode and the drain electrode.
[0019] Optionally, in the method for manufacturing the flash memory device, during the process of removing the gate oxide layer on the substrate surface of the peripheral logic area by using the first wet cleaning process, the cleaning solution used at least includes: hydrofluoric acid.
[0020] Optionally, in the method for manufacturing the flash memory device, the thickness of the gate oxide layer is 30 angstroms to 90 angstroms.
[0021] Optionally, in the method for manufacturing the flash memory device, the material of the first outer sidewall material layer is silicon nitride.
[0022] Optionally, in the method for manufacturing the flash memory device, the thickness of the first outer sidewall material layer is 130 angstroms to 150 angstroms.
[0023] Optionally, in the method for manufacturing the flash memory device, the material of the second outer sidewall material layer is silicon dioxide; the material of the third outer sidewall material layer is silicon nitride.
[0024] Optionally, in the method for manufacturing the flash memory device, the thickness of the second outer sidewall material layer is 150 angstroms to 250 angstroms.
[0025] Optionally, in the method for manufacturing the flash memory device, the thickness of the third outer sidewall material layer is 80 angstroms to 120 angstroms.
[0026] Optionally, in the method for manufacturing the flash memory device, during the process of performing a second wet cleaning process on the semiconductor structure after forming the source electrode and the drain electrode, the cleaning solution used is SC1 solution.
[0027] The technical solution of the present application has at least the following advantages:
[0028] In the method for manufacturing the flash memory device provided by the present application, after forming the first outer sidewall material layer and before forming the second outer sidewall material layer and the third outer sidewall material layer, a first wet cleaning process is adopted to remove the gate oxide layer on the surface of the substrate in the peripheral logic region. Since the self-aligned etching of the storage region has not been performed at this time, the first wet cleaning process will not laterally etch the second outer sidewall material layer at the bottom of the third outer sidewall material layer in the outer sidewall structure of the flash memory cell. In this way, it is not necessary to perform a step of using HF wet cleaning to remove the redundant gate oxide layer on both sides of the gate polysilicon layer after forming the source electrode and the drain electrode respectively and before forming the metal silicide blocking layer, avoiding the situation that the second outer sidewall material layer at the bottom of the third outer sidewall material layer in the outer sidewall structure of the flash memory cell in the storage region is accidentally etched by HF to form a lateral etch, resulting in the influence on the device yield. Thus, the situation that an air gap is formed in the interlayer insulating layer at the lateral etch position is avoided, and the situation that different conductive plugs are bridged is also avoided, improving the device yield and improving the electrical properties such as the data retention ability of the device. Description of the Drawings
[0029] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0030] Figure 1 is a flowchart of the method for manufacturing the flash memory device according to the embodiment of the present invention;
[0031] Figures 2 - 10 is a schematic diagram of the semiconductor structure in each process step of manufacturing the flash memory device according to the embodiment of the present invention;
[0032] Among them, the description of the reference numerals is as follows:
[0033] 100 - Substrate, 101 - Source line ion implantation region, 110 - Pad oxide layer, 120 - Floating gate layer, 130 - ONO layer, 140 - Control gate layer, 160 - First inner sidewall, 180 - Second inner sidewall, 190 - Tunneling oxide layer, 200 - Source line polysilicon, 210 - Protective layer, 220 - First outer sidewall material layer, 230 - Second outer sidewall material layer, 240 - Third outer sidewall material layer, 250 - Metal silicide barrier layer, 310 - Gate oxide layer, 320 - Gate polysilicon layer, 301 - Source electrode, 302 - Drain electrode. Detailed implementation manners
[0034] The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.
[0035] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.
[0036] In the description of the present application, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0037] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0038] The embodiment of the present application provides a method for manufacturing a flash memory device. Refer to Figure 1 , Figure 1 is a flowchart of the method for manufacturing a flash memory device according to the embodiment of the present invention. The method for manufacturing the flash memory device includes:
[0039] First, perform step S1: Refer to Figure 2 , Figure 2 is a schematic diagram of a semiconductor structure after forming a source line polysilicon and a gate polysilicon layer according to an embodiment of the present application. Provide a substrate 100, the substrate 100 includes a storage area and a peripheral logic area. A pad oxide layer 110, a floating gate layer 120, an ONO layer 130, a control gate layer 140, a source line polysilicon 200, a tunneling oxide layer 190, and an inner sidewall structure are formed on the substrate 100 of the storage area. Among them, the pad oxide layer 110, the floating gate layer 120, the ONO layer 130, and the control gate layer 140 are stacked in sequence. The inner sidewall structure includes: a first inner sidewall 160 and a second inner sidewall 180. The source line polysilicon 200 is located in the control gate layer 140, the ONO layer 130, the floating gate layer 120, and the pad oxide layer 110, and the source line polysilicon 200 extends beyond the control gate layer 140 by a certain height. The first inner sidewall 160 is located on the control gate layer. The second inner sidewall 180 is located between the source line polysilicon and the stacked pad oxide layer, the floating gate layer, the ONO layer, and the control gate layer, and the second inner sidewall 180 covers a part of the first inner sidewall 160 and covers the inner surfaces of the control gate layer 140 and the ONO layer 130. The tunneling oxide layer 190 is located between the source line polysilicon 200 and the second inner sidewall 180, and the tunneling oxide layer 190 covers a part of the second inner sidewall 180 and covers the inner surfaces of the ONO layer 130 and the pad oxide layer 110.
[0040] Further, in this embodiment, taking the peripheral logic area as a high-voltage MOS device area as an example, a gate oxide layer 310 covering the surface of the substrate 100 and a gate polysilicon layer 320 located on the gate oxide layer 310 are formed on the substrate 100 of the peripheral logic area.
[0041] Preferably, the thickness of the gate oxide layer 310 is 30 Å to 90 Å.
[0042] In this embodiment, the ONO layer 130 includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer stacked in sequence.
[0043] Preferably, a protective layer 210 is further formed on the top of the source line polysilicon 200, and the protective layer 210 serves to isolate the source line polysilicon 200 from the subsequent deposited film layers above it.
[0044] Preferably, a source line ion implantation region 101 is further formed in the substrate 100, and the source line ion implantation region 101 is located at the bottom of the source line polysilicon 200.
[0045] Then, perform step S2: Refer to Figure 3 ,Figure 3 FIG. Figure 3 is a schematic diagram of a semiconductor structure after forming a first sidewall material layer according to an embodiment of the present application. The first sidewall material layer 220 is formed, and the first sidewall material layer 220 covers the control gate layer 140, the protection layer 210, and the inner sidewall structure of the storage area, and covers the gate oxide layer 210 and the gate polysilicon layer 320 of the peripheral logic area.
[0046] In this embodiment, the material of the first sidewall material layer 220 is silicon nitride.
[0047] Preferably, the thickness of the first sidewall material layer 220 is 130 Å to 150 Å.
[0048] Next, step S3 is performed: Refer to Figure 4 , Figure 4 FIG. Figure 4 is a schematic diagram of a semiconductor structure after removing a part of the first sidewall material layer according to an embodiment of the present application. The first sidewall material layer 220 on the upper surface of the control gate layer 140, the upper surface of the source line polysilicon 200, and the upper surface of the inner sidewall structure in the storage area is removed, and the first sidewall material layer 220 on the outer side surface of the inner sidewall structure is retained. At the same time, the first sidewall material layer 220 on the surface of the gate oxide layer 310 and the upper surface of the gate polysilicon layer 320 in the peripheral logic area is removed, and the first sidewall material layer 220 on the outer side surface of the gate polysilicon layer 320 is retained.
[0049] In this embodiment, a dry etching process is used to etch and remove the first sidewall material layer 220 on the upper surface of the control gate layer 140, the upper surface of the source line polysilicon 200, and the upper surface of the inner sidewall structure in the storage area, and to remove the first sidewall material layer 220 on the surface of the gate oxide layer 310 and the upper surface of the gate polysilicon layer 320 in the peripheral logic area, and the first sidewall material layer 220 on the outer side surface of the gate polysilicon layer 320 is retained.
[0050] Further, step S4 is performed: Refer to Figure 5 , Figure 5 FIG. Figure 5 is a schematic diagram of a semiconductor structure after removing a part of the gate oxide layer according to an embodiment of the present application. A first wet cleaning process is used to remove the gate oxide layer 310 on the surface of the substrate 100 on both sides of the gate polysilicon layer 320 in the peripheral logic area.
[0051] It should be noted that during the process of removing the gate oxide layer on the surface of the substrate in the peripheral logic area by the first wet cleaning process, the cleaning solution used at least includes: hydrofluoric acid. The cleaning solution containing hydrofluoric acid can effectively remove the excess gate oxide layer 310 on the surface of the substrate 100 on both sides of the gate polysilicon layer 320 in the peripheral logic area.
[0052] Next, perform step S5: Refer to Figure 6 , Figure 6 is a schematic diagram of a semiconductor structure after removing a part of the gate oxide layer in an embodiment of the present application. Etch and remove the control gate layer 140, the ONO layer 130, the floating gate layer 120, and the pad oxide layer 110 outside the inner sidewall structure.
[0053] In this embodiment, a dry etching process is used to etch and remove the control gate layer 140, the ONO layer 130, the floating gate layer 120, and the pad oxide layer 110 outside the inner sidewall structure.
[0054] Further, perform step S6: Refer to Figure 7 , Figure 7 is a schematic diagram of a semiconductor structure after forming a second outer sidewall material layer and a third outer sidewall material layer in an embodiment of the present application. Form a second outer sidewall material layer 230 and a third outer sidewall material layer 240 respectively. The second outer sidewall material layer 230 covers the outer surface of the first outer sidewall material layer 220, the control gate layer 140, the ONO layer 130, the floating gate layer 120, and the pad oxide layer 110 in the storage area, as well as the protective layer 210 on the substrate 100, the inner sidewall structure, and the source line polysilicon 200. The second outer sidewall material layer 230 also covers the gate polysilicon layer 320, the first outer sidewall material layer 220, and the substrate 100 in the peripheral logic area. The third outer sidewall material layer 240 covers the second outer sidewall material layer 230.
[0055] In this embodiment, the material of the second outer sidewall material layer 230 is silicon dioxide; the material of the third outer sidewall material layer 240 is silicon nitride.
[0056] Preferably, the thickness of the second outer sidewall material layer 230 is 150 Å to 250 Å.
[0057] Further, the thickness of the third outer sidewall material layer 240 is 80 Å to 120 Å.
[0058] Next, perform step S7: Refer to Figure 8 , Figure 8It is a schematic diagram of a semiconductor structure after removing a part of the second outer wall material layer and the third outer wall material layer in an embodiment of the present application. The second outer wall material layer 230 and the third outer wall material layer 240 on the upper surface of the source line polysilicon 200, the upper surface of the inner wall structure, and a part of the surface of the substrate 100 in the storage area are removed, and the second outer wall material layer 230 and the third outer wall material layer 240 on the outer surface of the first outer wall material layer 220 are retained. At the same time, the second outer wall material layer 230 and the third outer wall material layer 240 on the surface of the substrate 100 in the peripheral logic area and the upper surface of the gate polysilicon layer 320 are removed, and the second outer wall material layer 230 and the third outer wall material layer 240 on the outer surface of the first outer wall material layer 220 are retained. The retained second outer wall material layer 230 and third outer wall material layer 240 are both L-shaped.
[0059] Among them, the remaining first outer wall material layer 220, second outer wall material layer 230, and third outer wall material layer 240 in the storage area form the outer wall structure of the storage area, and the remaining first outer wall material layer 220, second outer wall material layer 230, and third outer wall material layer 240 in the peripheral logic area form the side wall structure of the peripheral logic area.
[0060] Further, perform step S8: Refer to Figure 9 , Figure 9 It is a schematic diagram of a semiconductor structure after forming source and drain electrodes in an embodiment of the present application. By means of an ion implantation process, a source electrode 301 and a drain electrode 302 are respectively formed in the substrate on both sides of the side wall structure in the peripheral logic area.
[0061] Then, perform step S9: Perform a second wet cleaning process on the semiconductor structure after forming the source electrode 301 and the drain electrode 302 ( Figure 9 the semiconductor structure shown). Among them, the cleaning solution used in the second wet cleaning process does not contain hydrofluoric acid.
[0062] In this embodiment, during the process of performing the second wet cleaning process on the semiconductor structure after forming the source electrode 301 and the drain electrode 302, the cleaning solution used is SC1 solution. Among them, the SC1 solution is mainly composed of deionized water, hydrogen peroxide (H2O2), and ammonium hydroxide (NH4OH) mixed in a certain proportion. Among them, before forming the metal silicide blocking layer 250 in the present application, impurities on the surface of the Figure 9 semiconductor structure shown are removed by using a cleaning solution (SC1 solution) that does not contain hydrofluoric acid.
[0063] Finally, perform step S10: Refer to Figure 10 , Figure 10It is a schematic diagram of a semiconductor structure after forming a metal silicide barrier layer in an embodiment of the present application. A metal silicide barrier layer 250 is formed, and the metal silicide barrier layer 250 covers the semiconductor structure after forming the source electrode 301 and the drain electrode 302.
[0064] In the present application, after forming the first sidewall material layer and before forming the second sidewall material layer and the third sidewall material layer, a first wet cleaning process is used to remove the gate oxide layer on the substrate surface of the peripheral logic region. Since the self-aligned etching of the storage region has not been performed at this time, the first wet cleaning process will not laterally etch the second sidewall material layer at the bottom of the third sidewall material layer in the sidewall structure of the flash memory cell. In this way, it is not necessary to perform the step of using HF wet cleaning to remove the redundant gate oxide layers on both sides of the gate polysilicon layer after forming the source electrode and the drain electrode respectively and before forming the metal silicide barrier layer, avoiding the situation that the second sidewall material layer at the bottom of the third sidewall material layer in the sidewall structure of the flash memory cell in the storage region is accidentally etched by HF to form a lateral etch, resulting in the yield of the device being affected. Thus, the situation that an air gap is formed in the interlayer insulating layer at the lateral etch position is avoided, and the situation that different conductive plugs are bridged is also avoided, improving the yield of the device and improving the electrical properties such as the data retention ability of the device.
[0065] Furthermore, after forming the metal silicide barrier layer 250, the metal silicide barrier layer 250 can also be etched to expose a part of the gate polysilicon layer 320, the source electrode 301, and the drain electrode 302 in the peripheral logic region, and to expose a part of the source line polysilicon 200 in the storage region, preparing for subsequent formation of contact holes / conductive plugs. The embodiments of the present application do not make any limitations on the process steps after forming the metal silicide barrier layer 250, and can be the steps / processes of the conventional preparation process of flash memory devices.
[0066] Obviously, the above embodiments are only examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.
Claims
1. A method for manufacturing a flash memory device, characterized in that Comprising: Providing a substrate, the substrate includes a storage area and a peripheral logic area. A pad oxide layer, a floating gate layer, an ONO layer, a control gate layer, source line polysilicon, a tunneling oxide layer, and an inner sidewall structure are formed on the substrate of the storage area. Among them, the pad oxide layer, the floating gate layer, the ONO layer, and the control gate layer are stacked in sequence. The source line polysilicon is located in the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer and the source line polysilicon extends beyond the control gate layer by a certain height. The inner sidewall structure is located between the source line polysilicon and the stacked pad oxide layer, the floating gate layer, the ONO layer, and the control gate layer. The tunneling oxide layer is located between the source line polysilicon and the inner sidewall structure; A gate oxide layer covering the surface of the substrate and a gate polysilicon layer located on the gate oxide layer are formed on the substrate of the peripheral logic area; Forming a first outer sidewall material layer, the first outer sidewall material layer covers the control gate layer, the source line polysilicon, and the inner sidewall structure of the storage area and covers the gate oxide layer and the gate polysilicon layer of the peripheral logic area; Removing the first outer sidewall material layer on the upper surface of the control gate layer, the upper surface of the source line polysilicon, and the upper surface of the inner sidewall structure of the storage area, retaining the first outer sidewall material layer on the outer surface of the inner sidewall structure. At the same time, removing the first outer sidewall material layer on the surface of the gate oxide layer and the upper surface of the gate polysilicon layer of the peripheral logic area, retaining the first outer sidewall material layer on the outer surface of the gate polysilicon layer; Removing the gate oxide layer on the surface of the substrate of the peripheral logic area by using a first wet cleaning process; Etching to remove the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer outside the inner sidewall structure; Respectively forming a second outer sidewall material layer and a third outer sidewall material layer. The second outer sidewall material layer covers the outer surface of the first outer sidewall material layer, the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer of the storage area, as well as the substrate, the inner sidewall structure, and the source line polysilicon. The second outer sidewall material layer also covers the gate polysilicon layer, the first outer sidewall material layer, and the substrate of the peripheral logic area. The third outer sidewall material layer covers the second outer sidewall material layer; Remove the second outer sidewall material layer and the third outer sidewall material layer on the upper surface of the source line polysilicon in the storage area, the upper surface of the inner sidewall structure, and a part of the substrate surface, and retain the second outer sidewall material layer and the third outer sidewall material layer on the outer surface of the first outer sidewall material layer. At the same time, remove the second outer sidewall material layer and the third outer sidewall material layer on the substrate surface of the peripheral logic area and the upper surface of the gate polysilicon layer, and retain the second outer sidewall material layer and the third outer sidewall material layer on the outer surface of the first outer sidewall material layer. Wherein, the remaining first outer sidewall material layer, the second outer sidewall material layer, and the third outer sidewall material layer in the storage area form the outer sidewall structure of the storage area, and the remaining first outer sidewall material layer, the second outer sidewall material layer, and the third outer sidewall material layer in the peripheral logic area form the sidewall structure of the peripheral logic area; Form source and drain in the substrate on both sides of the sidewall structure of the peripheral logic area respectively through an ion implantation process; Perform a second wet cleaning process on the semiconductor structure after forming the source and the drain, wherein the cleaning solution used in the second wet cleaning process does not contain hydrofluoric acid; Form a metal silicide blocking layer, and the metal silicide blocking layer covers the semiconductor structure after forming the source and the drain; 2. The manufacturing method of the flash memory device according to claim 1, characterized in that, During the process of removing the gate oxide layer on the substrate surface of the peripheral logic area by using the first wet cleaning process, the cleaning solution used at least includes: hydrofluoric acid; 3. The manufacturing method of the flash memory device according to claim 1, wherein The thickness of the gate oxide layer is 30 angstroms to 90 angstroms; 4. The method for manufacturing a flash memory device according to claim 1, characterized in that, The material of the first outer sidewall material layer is silicon nitride; 5. The manufacturing method of the flash memory device according to claim 1, characterized in that, The thickness of the first outer sidewall material layer is 130 angstroms to 150 angstroms; 6. The method for manufacturing a flash memory device according to claim 1, wherein The material of the second outer sidewall material layer is silicon dioxide; the material of the third outer sidewall material layer is silicon nitride; 7. The manufacturing method of the flash memory device according to claim 1, characterized in that, The thickness of the second outer sidewall material layer is 150 angstroms to 250 angstroms; 8. The method for manufacturing a flash memory device according to claim 1, wherein, The thickness of the third outer sidewall material layer is 80 angstroms to 120 angstroms; 9. The method for manufacturing a flash memory device according to claim 1, wherein, During the process of performing the second wet cleaning process on the semiconductor structure after forming the source and the drain, the cleaning solution used is SC1 solution;